Template mask and use thereof in lithographic fabrication

Abstract

The present disclosure relates to a stencil mask, a method of manufacturing the stencil mask, and use of the stencil mask in nanofabrication of nanoscale devices, including printing a deposition pattern on a substrate for nanoscale devices. One embodiment of the present disclosure relates to a template mask for fabricating at least one nanoscale device on a substrate, the template mask comprising: a film having a top surface and a bottom surface with a thickness between the top surface and the bottom surface of at least 500 nm; a predefined pattern of holes wherein the holes extend through the membrane, each hole having a width and a length in the top surface of the membrane wherein at least a width and / or length of one of said holes is less than 100 nm, each hole being defined by an inner sidewall extending between the top surface and the bottom surface of the membrane; and a set of partition nanostructures on the top surface of the film for separating the top surface of the film from the top surface of the substrate.

Description

Technical Field

[0001] The present disclosure relates to a stencil mask, a method of making the stencil mask, and the use of the stencil mask in nanofabrication of nanoscale devices, including printing a deposition pattern for a nanoscale device on a substrate. Background Art

[0002] The research fields of nanotechnology and nanofabrication are key to the development of quantum computing, leading to the realization and improved performance of today's quantum bit (qubit) prototypes. Previous leaps in solid-state qubit manufacturing were led by advances in nanofabrication tools. This allowed for cleaner, faster, and more precise nanofabrication processes to be performed, which improved the overall performance of the qubit.

[0003] Typically, the fabrication of qubit platforms for solid-state quantum computing requires extreme environments. Therefore, in order to deposit materials and fabricate qubits, ultra-high vacuum systems are used, in which both pressure and temperature are controlled with extreme precision. For example, the growth of semiconductors is usually carried out at temperatures of several hundred degrees Celsius, while the deposition of metals is carried out in the range of cryogenic temperatures to several hundred degrees Celsius. Template lithography is one of the techniques used to selectively fabricate nanoscale electronic and quantum devices. One of its advantages over traditional nanofabrication techniques is that it is a technique that does not require organic polymer resists, enabling devices to be fabricated in a cleaner way. Common device nanofabrication techniques mean coating a layer of organic resist on the device master substrate, which is usually exposed by electrons or photons to determine the device design before material deposition. Thereafter, the remaining resist is usually removed by wet chemical methods, with the risk of leaving undesirable contaminants on the substrate surface. Template mask lithography has the ability to deposit the desired material directly in a pattern that defines the device. This manufacturing technique ensures the cleanliness of the substrate throughout the manufacturing process.

[0004] Previously disclosed stencil lithography masks consist of a thin film with a thickness in the range of tens of nanometers, on which a defined pattern of openings is printed. By placing it above a substrate and evaporating the deposited material on it, only the material that passes through the hole pattern is deposited on the substrate, thereby generating a material pattern for one or more devices under the mask. However, using this method has some inconveniences. The membranes are usually very fragile, intended for single use, and due to their limited thickness, show relatively large dispersion of the deposition height. Summary of the invention

[0005] Therefore, there is a need to solve the problems of stencil lithography masks known in the prior art, as will be presented herein.

[0006] A solution to the previous limitations may be achieved by a stencil mask, such as a stencil mask for fabricating at least one nanoscale device on a substrate, the stencil mask comprising:

[0007] a film having a top surface and a bottom surface, preferably having a thickness between the top surface and the bottom surface of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, or even 1.5 or 2 μm,

[0008] - a predefined pattern of holes, wherein the holes extend through the membrane; each hole having a width and a length in the top surface of the membrane, preferably at least the width and / or the length of one of said holes is less than 500 nm, preferably less than 200 nm, most preferably less than 100 nm, possibly even less than 50 nm, each hole being defined by an inner side wall extending between the top and bottom surfaces of the membrane, and

[0009] Preferably, the mask further comprises one or more structural elements for separating the top surface of the film from the top surface of the substrate, for example, a set of separating nanostructures on the top surface of the film.

[0010] Typically, the template mask comprises a Si film, or a film of other materials compatible with the nanofabrication process. A major advantage of the template mask disclosed in the present invention is the thickness of the film, which can be at least one order of magnitude higher than the thickness of the film of the conventional template mask disclosed in the prior art, and can still be used to accurately define the holes extending through the film. Therefore, the aspect ratio between the obtainable hole and the film is very high. For example, the aspect ratio is defined as the ratio of the minimum dimension (such as width or length) of the hole in the plane of the film to the thickness of the film. Therefore, the aspect ratio of the hole relative to the mask thickness can be obtained by dividing the mask thickness by the hole width. The aspect ratio of the obtainable template mask disclosed in the present invention can be at least 2, preferably at least 5, more preferably at least 10, even more preferably at least 50, most preferably at least 100, and may be as high as 200 or even higher.

[0011] The present disclosure also relates to a method for manufacturing a template mask. Preferably, the template mask disclosed herein, also known as a hard template mask, can be manufactured by a Clean-Oxidize-Remove-Etch (CORE) nanofabrication process. The process allows etching of hole patterns in Si or SiN substrates / films with a thickness of >1μm. The CORE nanofabrication process is capable of etching holes with a width of less than 10nm, which means that the ultra-high aspect ratio between the hole width of the template mask disclosed herein and the thickness of the film is at least 5, preferably at least 10, more preferably at least 50, most preferably at least 100, and may be as high as 200 or more. It is the ability to define holes with ultra-high aspect ratios that makes the CORE process suitable for manufacturing hard template masks for lithography purposes.

[0012] The inner sidewalls of the apertures (e.g. defined by the CORE nanofabrication process) may have a line edge roughness of less than 10% relative to the (minimum) width of the aperture, preferably less than 5% or even less than 2%. That is, the inner sidewalls are substantially or completely smooth and scallop free. Furthermore, the inner sidewalls of the aperture pattern may be fabricated to be parallel to each other and perpendicular to the mask plane, parallel to each other but not parallel to the mask plane, and not parallel to each other.

[0013] The present disclosure also relates to a method for manufacturing at least one nanoscale device pattern on a substrate using a template mask of the present disclosure. In a preferred embodiment, the deposition material evaporates above the hard template mask to define a pattern on a substrate located below the mask. Due to the high aspect ratio of the hole, only materials whose evaporation angle is completely aligned with the longitudinal extension of at least one wall of the hole will be deposited on the surface of the underlying substrate. The present disclosure also relates to one or more nanoscale devices manufactured according to the method, such as quantum bits, semiconductor devices, superconductor devices, semiconductor-superconductor devices, any combination thereof, or other quantum and non-quantum devices for nanoelectronic experiments.

[0014] Therefore, through the template mask disclosed in this article, the problems of fragility, angular resolution and reusability of the prior art template masks can be overcome.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure will be described in more detail below with reference to the accompanying drawings:

[0017] FIG. 1 is a schematic diagram showing the steps of a process for manufacturing a mask (ie, a hard template mask) for template lithography.

[0018] FIG. 2 is a scanning electron micrograph of Al deposition on a substrate using a hard template mask, and a schematic diagram showing the direction in which the evaporated material is blocked by the walls of the hard template mask.

[0019] Figure 3 is a schematic diagram of a method for manufacturing a device using a stencil mask, comprising the steps of attaching and aligning a hard stencil mask to a substrate, evaporating a series of deposition materials, and peeling the mask off the substrate. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hard Template Mask

[0022] In a preferred embodiment, the template mask for manufacturing nanoscale devices disclosed in the present invention comprises a film having a top surface and a bottom surface, and a thickness between the top surface and the bottom surface of at least 200nm, preferably at least 500nm, more preferably at least 1μm, even 1.5 or 2μm; a predefined hole pattern, wherein the holes extend through the film, each hole has a width and a length in the top surface (and bottom surface) of the film, wherein at least one of the holes has a (minimum) width and / or (minimum) length of less than 200nm, preferably less than 100nm, more preferably less than 50nm. Each hole is defined by an inner sidewall extending between the top surface and the bottom surface of the film; and a set of separation nanostructures on the top surface of the film for separating the top surface of the film from the top surface of the substrate.

[0023] The spaced nanostructures may be arranged along the hard template mask surface to allow for uniform pressure, weight, and force distribution on the substrate.

[0024] In a preferred embodiment of the present invention, the material composition of the mask is selected from Si, SiN, SiGe and Ge. The cross-sectional shape of the holes in the top surface and / or bottom surface of the membrane can be any shape, such as circular, annular, elliptical, square, rectangular, triangular, pentagonal, etc. The width of the hole can be 10nm to 1μm, and may be up to 10μm. The length of the hole can be 10nm, or at least 500nm, and may be up to 1μm, or 10μm, or even up to 500μm.

[0025] The hole angle used in this article is defined as the angle formed between the plane formed by the extension of the inner side wall of the hole and the top surface of the film.At least one inner side wall of at least one hole can form an angle of 10 to 170 degrees with the top surface of the film, such as 90 degrees.At least two inner walls of at least one hole can be parallel to each other.Similarly, at least two inner walls of at least one hole are not parallel to each other.At least one hole can be substantially cylindrical.At least one hole can be conical.At least one hole can be limited to extend longitudinally through the film, and wherein the extension through the film is perpendicular to the top surface of the film (illustrated in Figures 1 and 2).At least one hole can be limited to extend longitudinally through the film, and wherein the extension through the film forms an angle of 10 to 90 with the top surface of the film.

[0026] The main advantage of the template mask disclosed in the present invention is that at least one (or all) of the inner side walls of at least one (or all) holes can be made smooth. For example, the surface roughness of at least one inner side wall of the hole can be less than 10nm, preferably less than 5nm, and most preferably less than 1nm. Surface roughness is understood here as the maximum extension of surface variation or the average extension of surface variation. Another way to characterize surface roughness is line edge roughness. The template mask disclosed in the present invention can achieve at least one pair of inner side walls with a line edge roughness of less than 20%, preferably less than 10%, most preferably less than 5%, even less than 2% or less than 1%. This can be achieved even for holes with a (minimum) width of less than 100nm. That is, at least one inner side wall of the hole can be substantially free of scallop shell texture. Scallop shell texture roughness is a known effect in the art, which may occur in a known dry etching process, in which the inner side wall of the defined hole forms a nano-sized inner protrusion toward the inner side of the substrate inside the hole. The stencil masks of the present disclosure can achieve holes with substantially no scalloping on the inner sidewalls, even for the narrower width ranges described previously.

[0027] In one embodiment, at least one inner sidewall of at least one hole is not parallel to each other, such as a positively tapered or negatively tapered sidewall, wherein the distance between the sidewalls at the start of the hole is greater or less than the distance between the sidewalls at the end of the hole, respectively. Thus, the hole size at the top surface of the membrane may be different from the size of the corresponding hole at the bottom surface of the membrane. Such sidewalls can be achieved by changing the manufacturing parameters accordingly during the CORE process.

[0028] The group of separation nanostructures can include a group of nanopillars, preferably uniformly arranged on the top surface of the template mask film. The separation nanostructure is preferably separated from any hole of the film by at least 1 μm. The material composition of the separation nanostructure can be selected from Si, SiN, SiGe and Ge, or other ultra-high vacuum, high vacuum or vacuum compatible materials. In addition, the separation nanostructure can be configured to separate the top surface of the film from the top surface of the substrate at a fixed distance. The distance may be 0nm (the top surface of the template mask film effectively contacts the substrate) to up to tens of μm, or even hundreds of μm.

[0029] Stencil mask manufacturing

[0030] One preferred nanofabrication method for the stencil mask disclosed herein is the Clean-Oxidation-Remove-Etch (CORE) nanofabrication process. This process allows nanofabrication of ultra-high aspect ratio features up to 200 in semiconductor substrates.

[0031] The manufacturing process of an embodiment of the template photolithography mask device disclosed in the present invention is shown in Figure 1. First, a blank silicon mask 100 without openings is provided, and the thickness is preferably 2 μm. The following detailed manufacturing steps are not limited to a specific thickness of the silicon mask, and the thickness can range from 100 nm to several μm.

[0032] The silicon mask has a set of nanopillars 101 evenly distributed around the surface. Such nanopillars can be composed of SiOx or other mechanically resistant materials (such as Si, SiGe, SiN or Ge). The height of the nanopillars (relative to the height level of the mask 103 where they are located) can be 0nm to several μm. The nanopillars are located on the substrate proximal surface 103 of the mask, which is the opposite surface of the distal surface 104 of the mask.

[0033] In nanofabrication of template masks, the CORE process is able to produce holes with smooth sidewalls in Si films, regardless of the hole width. This is especially important when defining hole patterns of small widths (e.g. <50nm), so that holes with smooth sidewalls and low or no line width roughness can be produced throughout the depth of the mask film. The advantage of the CORE nanofabrication process is that it can produce extremely thin holes (<50nm) in thick substrates of thickness such as 2μm or more, and these holes have smooth sidewalls without scallop texture.

[0034] like Figure 1B As shown, in the first manufacturing step of the template mask, two layers consisting of 10 nm of Cr 111 and 10 nm of Si 112 are deposited on the substrate proximal surface of the Si mask 110.

[0035] In the second manufacturing step, as Figure 1C As shown, an additional layer of ZEP520 organic resist 121 is spin coated on top of the previously deposited layer 120. The resist is exposed by standard electron lithography, exposing only the areas on the resist according to the predefined pattern. The exposed resist is developed, leaving a resist mask with a printed exposure pattern 122, located above the Si layer below.

[0036] In the next manufacturing step, as Figure 1D As shown, the deposited 10 nm Si layer is etched to expose the pattern 131 of the Cr layer deposited underneath. Figure 1E As shown, the top layer of zep520 organic resist is stripped, as shown in the template mask 140, and the Cr layer is etched to expose the underlying Si pattern 141, which includes the original mask.

[0037] In the final manufacturing step, a CORE process is performed on the template mask 150 using parameters comparable to those disclosed in the prior art. This creates a hole pattern 151 on the Si mask. The sidewalls of these holes are smooth compared to other dry etching techniques, meaning that the roughness and scallop shell texture size are less than 5nm and there is no scallop shell texture effect compared to the typical roughness and scallop shell texture size of other similar dry etching processes. Finally, the remaining Cr on the surface of the Si mask is removed, leaving a clean Si template mask with a hole pattern.

[0038] The sidewall configuration on each hole can be designed by adjusting the manufacturing parameters of the CORE process. In one embodiment, a pair of sidewalls defining the hole are parallel to each other. This means that the hole passes through the thickness of the Si mask perpendicular to the plane of the mask surface.

[0039] One of the characteristics of the CORE process compared to other manufacturing methods is the ability to generate patterns of thin pores (as small as 10 nm) with ultra-high aspect ratios in films with a thickness of at least >1 μm, while having smooth sidewalls. The thickness of typical films disclosed in the prior art means that the thickness is usually much less than 1 μm, however, those skilled in the art will understand that due to similarity, the embodiments disclosed herein use the above film definition, but this does not mean that the thickness is <1 μm.

[0040] Method for manufacturing a device

[0041] The present disclosure also relates to a method for manufacturing at least one nanoscale device pattern on a substrate. In one embodiment, the method includes the following steps: providing at least one template mask disclosed herein, attaching the top surface of the film of the template mask to the top surface of the substrate, and aligning it relative to the deposition material source on the top surface of the substrate; evaporating at least a first type of deposition material on the template mask so that at least a first nanoscale device pattern is generated on the top surface of the substrate according to at least a first portion of a predefined hole pattern in the film. Then optionally, evaporating at least a second type of deposition material on the template mask so that at least a second nanoscale device pattern is generated on the top surface of the substrate according to at least a second portion of a predefined hole pattern in the film. The first and second types of deposition materials can be the same or different materials. This deposition process can be repeated for different or the same materials until the desired nanoscale device pattern is obtained. That is, for one template mask, the evaporation step can be repeated multiple times.

[0042] The disclosed manufacturing method allows the fabrication of multiple layers of materials without breaking ultra-high vacuum during the process. For example, complementary steps such as oxidation, annealing, metallization or ion implantation can be performed between material deposition steps. Thus, complex material stacks can be fabricated using a single stencil mask and the deposition angle can be varied depending on the pattern being fabricated.

[0043] Another advantage of the stencil mask disclosed in the present invention is that the stencil mask can be reversibly attached to the substrate and evaporated deposited material can be removed from the stencil mask, making the stencil mask reusable. For example, evaporated deposited material on the mask can be removed by selective wet etching. The deposition of the material can be performed in a series of steps in a certain order so that the remaining material can be removed by etching techniques. The deposition of the material can be performed at a certain deposition rate, temperature and vacuum chamber pressure so that the remaining material can be removed by etching or thermal annealing processes.

[0044] The spatial positioning of at least one first and / or second deposition material source can be controlled to define a deposition material angle relative to the bottom surface of the film. In this regard, the deposition material angle can at least partially define at least one nanoscale device pattern deposited through the hole pattern in the film.

[0045] The angular dispersion of the evaporated deposited material on the top surface of the substrate can be determined by the aspect ratio between the thickness of the film of the template mask and the width of the hole in the pattern and the spacing distance between the top surface of the film and the top surface of the substrate. In addition, the angular dispersion of the evaporated deposited material can be determined by the height of the nanopillars located on the proximal surface of the substrate, where an increase in height will result in an increase in the angular dispersion of the deposited material. When the height of the nanopillars is equal to 0 nm, the angular dispersion is suppressed and the defined pattern is directly printed on the substrate surface.

[0046] exist Figure 2A In another preferred embodiment of the fabricated stencil mask 201 shown, due to the high aspect ratio of the fabricated holes 202, the evaporated deposition material may be blocked by the sidewalls of the holes if the evaporated material source is not aligned with the holes. Figure 2B An evaporation example 210 is shown, where the source, mask, and substrate are aligned. An evaporation source 211 evaporates at least one material onto the mask, and this evaporation process has a certain angular dispersion, which is defined by the maximum angle of the evaporated material 212 allowed to pass through the opening of the template mask 213. A deposit 216 is formed on the underlying substrate 214, and the deposit 216 is separated from the substrate 214 by a distance due to the presence of nanorods 215. Figure 2B The SEM images in the figure show the use of a template mask (according to Figure 2A As a result of material deposition using the mask shown, deposits 217, 218 and 219 are formed.

[0047] Figure 2CAn evaporation example 220 is shown where the source, mask, and substrate are not aligned. An evaporation source 221 evaporates at least one material onto the mask with an angular dispersion defined by the maximum angle of the evaporated material 212 allowed to pass through the openings of the stencil mask 223. In this case, due to the high aspect ratio of the apertures and the relative orientation of the evaporation source with respect to the stencil mask, material deposition at this angle is blocked by the stencil mask 223 and no material reaches the substrate 224. This example uses the same Figure 2B A template mask of nanorod spacing 225 is used for the same situation as shown in FIG. Figure 2C The SEM image in shows deposits 226 and 227 formed by material deposition using a stencil mask. Only the holes in the mask that produce deposits 226 and 227 are aligned with the material evaporation source.

[0048] and Figure 2B Compared with the situation shown, Figure 2C In the example, the center portion of the designed hole is not aligned with the mask, which results in the material being effectively blocked due to the misalignment of the mask with the evaporation source. A second source of material containing the same or different elements can be evaporated in a configuration aligned with the mask to produce additional deposits without having to change the mask.

[0049] In another preferred embodiment, the stencil mask can be mostly chemically stable to a wet etchant that is reactive with the material evaporated from the source. As material evaporates on the mask, the thinnest holes may become blocked, preventing any further material from being deposited through the mask. By immersing the mask in a wet etchant, the metal can be removed and the mask can be used for additional deposition processes.

[0050] Typical material deposition using the disclosed stencil masks may include insufficient amounts of evaporated material to plug the pores.

[0051] The disclosed stencil masks can be used to deposit a range of typical materials at different deposition rates, depending on the nature of the material to be evaporated, the desired crystalline quality of the deposited material layer, or the thickness of the holes in the stencil mask.

[0052] The disclosed stencil mask can be used to deposit a range of typical materials at different temperatures, depending on the nature of the material to be evaporated, the desired crystalline quality of the deposited material layer, or the thickness of the holes in the stencil mask.

[0053] The same stencil mask can be used to perform a series of depositions of different materials, with the evaporation source aligned differently with respect to the mask and substrate for each deposition, allowing different patterns to be printed within the same stencil mask and substrate system.

[0054] The pattern to be printed onto the substrate surface can be designed accordingly, taking into account the variables that affect its deposition. A series of deposition steps can be performed, each at different temperatures, pressures, mask orientations, and other parameters, until the desired complete material stack is fabricated.

[0055] Figure 3 A method 300 for manufacturing at least one nanoscale device on a substrate is shown, the method comprising the following steps: step 301, providing a template mask; step 302, attaching the mask to the top surface of the substrate and aligning it relative to a deposition material source on the top surface of the substrate; step 303, evaporating at least a first type of deposition material on the template mask so that at least a first nanoscale device pattern is generated on the top surface of the substrate according to at least a first portion of a predefined hole pattern in the film; step 304, optionally, evaporating at least a second type of deposition material on the template mask so that at least a second nanoscale device pattern is generated on the top surface of the substrate according to at least a second portion of a predefined hole pattern in the film, and peeling the mask off the substrate so that the nanoscale device pattern is exposed on the top surface of the substrate.

[0056] project

[0057] 1. A template mask for manufacturing at least one nanoscale device on a substrate, the template mask comprising:

[0058] a. a film having a top surface and a bottom surface, and a thickness between the top surface and the bottom surface of at least 200 nm, preferably at least 500 nm, more preferably at least 1 μm, or even 1.5 μm or 2 μm,

[0059] b. a predefined pattern of holes, wherein the holes extend through the membrane, each hole having a width and a length in the top surface of the membrane, wherein at least the width and / or the length of one of said holes is less than 100 nm, each hole being defined by an inner sidewall extending between the top and bottom surfaces of the membrane, and

[0060] c. A set of separation nanostructures located on the top surface of the film and used to separate the top surface of the film from the top surface of the substrate.

[0061] 2. The template mask according to item 1, wherein the material composition of the mask is selected from Si, SiN, SiGe and Ge.

[0062] 3. A stencil mask according to any of the preceding items, wherein the aspect ratio between the thickness of the film and the width of the pattern features is at least 2, preferably at least 5, more preferably at least 10, most preferably at least 50, and may be as high as 200.

[0063] 4. A stencil mask according to any of the preceding items, wherein the width of the holes is at least 10 nm and may be up to 10 μm.

[0064] 5. A stencil mask according to any of the preceding items, wherein the length of the holes is at least 10 nm, or at least 500 nm, possibly up to 500 μm.

[0065] 6. A stencil mask according to any of the preceding clauses, wherein the pores in the film are defined by a clean-oxidize-remove-etch nanofabrication process.

[0066] 7. The stencil mask according to any of the preceding clauses, wherein at least one inner sidewall of at least one hole defines an angle of 10 to 170 degrees with the top surface of the film.

[0067] 8. The stencil mask according to any of the preceding items, wherein at least two inner side walls of at least one hole are parallel to each other.

[0068] 9. The stencil mask according to any of the preceding items, wherein at least two inner side walls of at least one hole are not parallel to each other.

[0069] 10. The stencil mask according to any of the preceding items, wherein at least one hole is substantially cylindrical.

[0070] 11. The stencil mask according to any of the preceding items, wherein at least one hole is tapered.

[0071] 12. The stencil mask according to any of the preceding items, wherein at least one hole defines a longitudinal extension through the film, and wherein the extension through the film is perpendicular to the top surface of the film.

[0072] 13. The stencil mask according to any of the preceding items, wherein at least one hole defines a longitudinal extension through the film, and wherein the extension through the film forms an angle of 10 to 90 degrees with the top surface of the film.

[0073] 14. The stencil mask according to any of the preceding items, wherein at least one inner sidewall of the hole is smooth.

[0074] 15. The stencil mask according to any of the preceding items, wherein the surface roughness of at least one inner sidewall of the hole is lower than 5 nm.

[0075] 16. The stencil mask of any of the preceding items, wherein at least one inner sidewall of the aperture is substantially free of scalloped texture.

[0076] 17. The stencil mask according to any of the preceding items, wherein the line edge roughness of at least one pair of inner side walls of at least one hole is less than 20%, preferably less than 10%, most preferably less than 5%.

[0077] 18. The stencil mask according to any of the preceding items, wherein the line edge roughness of at least one pair of inner side walls of at least one hole having a width a less than 100 nm is less than 20%, preferably less than 10%, most preferably less than 5%.

[0078] 19. The stencil mask according to any of the preceding items, wherein the spaced nanostructures comprise a set of nanopillars, which are preferably uniformly arranged on the top surface of the film.

[0079] 20. A stencil mask according to any of the preceding items, wherein any holes separating the nanostructures from the membrane are at least 1 μm apart.

[0080] 21. The stencil mask according to any of the preceding items, wherein the material composition of the separated nanostructures is selected from Si, SiN, SiGe and Ge.

[0081] 22. The stencil mask according to any of the preceding items, wherein the separation nanostructures are configured to separate the film surface from the substrate surface by a fixed distance.

[0082] 23. A method for fabricating at least one nanoscale device pattern on a substrate, comprising the steps of:

[0083] a. Provide a template mask,

[0084] b. attaching a stencil mask to the top surface of the substrate and aligning it on the top surface of the substrate relative to a deposition material source,

[0085] c. evaporating at least a first type of deposition material on the template mask so that at least a first nanoscale device pattern is generated on the top surface of the substrate according to at least a first portion of the predefined hole pattern in the film,

[0086] d. Optionally, evaporating at least a second type of deposition material on the template mask so that at least a second nanoscale device pattern is generated on the top surface of the substrate according to at least a second portion of the predefined hole pattern in the film, and

[0087] e. The mask is peeled off from the substrate, exposing the nanoscale device pattern on the top surface of the substrate.

[0088] 24. The method of item 23, wherein the template mask is fabricated by a clean-oxidize-remove-etch (CORE) nanofabrication process.

[0089] 25. The method according to any one of items 23-24, further comprising the step of removing the evaporated deposition material from the stencil mask, so that the stencil mask can be reused.

[0090] 26. A method according to any of items 23-25, wherein the spatial positioning of at least one source of at least the first and / or second deposition material is controlled to define an angle of the deposition material relative to the bottom surface of the film.

[0091] 27. The method of clause 26, wherein the angle of deposited material at least partially defines at least one nanoscale device pattern deposited through the hole pattern in the film.

[0092] 28. A method according to any one of items 23-27, wherein the angular dispersion of the evaporated deposited material on the top surface of the substrate is determined by the aspect ratio between the thickness of the film of the template mask and the width of the holes in the pattern and the spacing distance between the top surface of the film and the top surface of the substrate.

[0093] 29. The method of any one of items 23-28, wherein the mask is reversibly attached to the substrate.

[0094] 30. The method according to any of items 25-29, wherein the evaporated deposited material on the mask is removed by selective wet etching.

[0095] 31. The method according to any of items 23 to 30, wherein the evaporation step is repeated more than once for one stencil mask.

[0096] 32. The method according to any one of items 23-31, wherein the template mask is a template mask according to any one of items 1-22.

Claims

1. A template mask for manufacturing at least one nanoscale device on a substrate, the template mask comprising: - a film having a top surface and a bottom surface and a thickness between the top surface and the bottom surface of at least 500 nm, - a predefined pattern of holes, wherein the holes extend through the membrane; each hole has a width and a length in the top surface of the membrane, wherein at least the width and / or the length of one of said holes is less than 100 nm, each hole being defined by an inner sidewall extending between the top and bottom surfaces of the membrane, and - a set of spacer nanostructures located on the top surface of the film and used to separate the top surface of the film from the top surface of the substrate. 2 . The template mask according to claim 1 , wherein the material composition of the mask is selected from Si, SiN, SiGe and Ge. 3 . The stencil mask according to claim 1 , wherein the aspect ratio between the thickness of the film and the width of at least one hole is at least 5. 4 .

4. The stencil mask according to any one of the preceding claims, wherein the thickness of the film is at least 500 nm, preferably at least 1 μm, more preferably at least 2 μm, or even more preferably at least 5 μm.

5. A stencil mask according to any one of the preceding claims, wherein the width of the holes is at least 10 nm, possibly up to 10 μm.

6. A stencil mask according to any preceding claim, wherein the holes have a length of at least 10 nm, or at least 500 nm, and possibly up to 500 μm.

7. A stencil mask according to any one of the preceding claims, wherein the pores in the film are defined by a clean-oxidize-remove-etch nanofabrication process.

8. The stencil mask of any one of the preceding claims, wherein at least one inner sidewall of at least one hole defines an angle of 10 to 170 degrees with the top surface of the film.

9. The stencil mask according to any one of the preceding claims, wherein at least two inner side walls of at least one hole are parallel to each other.

10. The stencil mask of any one of the preceding claims, wherein the inner sidewall of at least one hole is substantially smooth and free of scalloped texture.

11. The stencil mask according to any one of the preceding claims, wherein at least one inner sidewall of the hole has a surface roughness of 5 nm or less.

12. The stencil mask of any one of the preceding claims, wherein the set of spacer nanostructures is configured to separate the surface of the film from the surface of the substrate by a fixed distance.

13. The stencil mask according to any of the preceding claims, wherein the set of spaced nanostructures comprises a set of nanopillars, preferably uniformly arranged on the top surface of the film.

14. A stencil mask according to any preceding claim, wherein the set of spaced nanostructures are at least 1 μm apart from any pores of the membrane.

15. The stencil mask according to any one of the preceding claims, wherein the material composition of the separated nanostructures is selected from Si, SiO x , SiN, SiGe and Ge.

16. A method for fabricating at least one nanoscale device pattern on a substrate, comprising the steps of: a. Provide a template mask, b. attaching and aligning the mask on the top surface of the substrate relative to the deposition material source on the top surface of the substrate such that the separation nanostructures separate the top surface of the film of the mask from the top surface of the substrate, c. evaporating at least a first type of deposition material on the template mask so that at least a first nanoscale device pattern is generated on the top surface of the substrate according to at least a first portion of the predefined hole pattern in the film, d. Optionally, evaporating at least a second type of deposition material on the template mask so that at least a second nanoscale device pattern is generated on the top surface of the substrate according to at least a second portion of the predefined hole pattern in the film, and e. The mask is peeled off from the substrate, exposing the nanoscale device pattern on the top surface of the substrate.

17. The method of claim 16, further comprising the step of removing the evaporated deposition material from the stencil mask so that the stencil mask can be reused.

18. A method according to any one of claims 16-17, wherein the spatial positioning of at least one source of at least the first and / or second deposition material is controlled to define an angle of the deposited material relative to the bottom surface of the film.

19. The method of any one of claims 16-18, wherein the angular dispersion of the evaporated deposition material on the top surface of the substrate is determined by the aspect ratio between the thickness of the film of the template mask and the width of the holes in the pattern and the separation distance between the top surface of the film and the top surface of the substrate.

20. The method of any one of claims 16-19, wherein the mask is reversibly attached to the substrate.

Images