Semiconductor device

Abstract

A semiconductor device (100) has an insulating layer (4) and a first electrode pattern (1). The first electrode pattern (1) has a first main body section (21) and a first stepped section (31). The first main body section (21) has a first surface (11), a second surface (12), and a first side surface (41). The first surface (11) faces the insulating layer (4). The second surface (12) is on the opposite side of the first surface (11). The first stepped section (31) has a third surface (13) and a first stepped surface (25). The third surface (13) faces the insulating layer (4). The first stepped surface (25) is located on the opposite side of the third surface (13). The boundary between the second surface (12) and the first side surface (41) is a first boundary (91). The boundary between the first side surface (41) and the first stepped surface (25) is a second boundary (92). In a cross-section perpendicular to the second surface (12), the length of the first side surface (41) is longer than the length of a line segment connecting the first boundary (91) and the second boundary (92).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor elements that correspond to high voltage or large current are generally called power semiconductor elements. Usually, the power path of a power semiconductor element is in the thickness direction of the element. Power semiconductor elements refer to, for example, IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), bipolar transistors, diodes, etc. A device in which a power semiconductor element is mounted on an insulating substrate and encapsulated by a sealing component is called a semiconductor device.

[0003] Semiconductor devices are used in a wide range of fields such as industrial machinery, automobiles, and railways. In recent years, with the improvement in the performance of machines equipped with semiconductor devices, the rated voltage and rated current of semiconductor devices have increased, and the operating temperature range of semiconductor devices has expanded (higher and lower temperatures). In other words, the demand for higher performance and higher reliability of semiconductor devices has increased. In order to meet this demand, it is necessary to have higher heat dissipation and higher reliability of insulating substrates equipped with semiconductor elements.

[0004] Japanese Patent Application Laid-Open No. 2004-296619 (Patent Document 1) discloses a method for manufacturing an insulating substrate in which an electrode pattern having a stepped portion on a side surface is formed by milling at least a portion of a metal layer.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2004-296619 Summary of the invention

[0008] However, according to the insulating substrate manufactured using the manufacturing method disclosed in Patent Document 1, the shape of the side surface of the electrode pattern becomes a straight line. Therefore, when a thermal cycle is applied, the step portion can suppress the peeling between the electrode pattern and the insulating substrate, but there is a possibility that the peeling between the sealing component and the insulating substrate will occur. As a result, there is a possibility that the insulation performance of the semiconductor device will deteriorate.

[0009] The present disclosure has been made in view of the above, and an object of the present disclosure is to provide a semiconductor device capable of suppressing degradation of insulation performance due to a thermal cycle.

[0010] The semiconductor device disclosed in the present invention comprises an insulating substrate, a semiconductor element, a housing, and a sealing component. The insulating substrate comprises an insulating layer and a first electrode pattern. The first electrode pattern is arranged on the insulating layer. The semiconductor element is arranged on the first electrode pattern. The housing surrounds the insulating substrate. The sealing component covers each of the insulating substrate and the semiconductor element. The first electrode pattern comprises a first main body and a first step portion. The first step portion protrudes from the first main body. The first main body comprises a first surface, a second surface, and a first side surface. The first surface is opposite to the insulating layer. The second surface is on the opposite side of the first surface. The second surface is opposite to the semiconductor element. The first side surface is connected to the second surface. The first step portion comprises a third surface and a first step surface. The third surface is connected to the first surface. The third surface is opposite to the insulating layer. The first step surface is on the opposite side of the third surface. The first step surface is connected to the first side surface. In a section perpendicular to the second surface, the first side surface is curved. In the cross section perpendicular to the second surface, the boundary between the second surface and the first side surface is the first boundary. In the cross section perpendicular to the second surface, the boundary between the first side surface and the first step surface is the second boundary. The length of the line segment connecting the first boundary and the second boundary in the cross section perpendicular to the second surface is the first length. The length of the first side surface in the cross section perpendicular to the second surface is longer than the first length.

[0011] According to the present disclosure, the bonding force between the first electrode pattern and the insulating layer can be improved by the first step portion of the first electrode pattern, and the peeling between the sealing component and the insulating substrate can be suppressed by the anchoring effect between the first side surface and the sealing component. Thus, a semiconductor device capable of suppressing the degradation of insulation performance caused by thermal cycles can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0013] Figure 2 yes Figure 1 For ease of explanation, Figure 2 The sealing member is not shown in the figure.

[0014] Figure 3 It is an enlarged cross-sectional schematic diagram showing the process of bonding the metal plate to the insulating layer.

[0015] Figure 4 It is an enlarged cross-sectional schematic diagram showing the process of cutting a metal plate.

[0016] Figure 5 It is an enlarged cross-sectional schematic diagram showing the process of printing a resist on a metal plate.

[0017] Figure 6 It is an enlarged cross-sectional schematic diagram showing the structure of a semiconductor device according to a modification of the first embodiment.

[0018] Figure 7 It is a schematic cross-sectional view showing the structure of a semiconductor device according to the second embodiment.

[0019] Figure 8 It is a schematic cross-sectional view showing the structure of a semiconductor device according to the third embodiment.

[0020] Fig. 9 yes Figure 8 Schematic diagram of an enlarged cross section of region IX.

[0021] Fig.10 It is an enlarged cross-sectional schematic diagram showing the structure of a semiconductor device according to a modification of the third embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their description will not be repeated. Implementation method 1.

[0023] (Structure of semiconductor device)

[0024] use Figure 1 as well as Figure 2 , the structure of the semiconductor device 100 is described. Figure 1 As shown, the semiconductor device 100 mainly includes a base plate 5 , an insulating substrate 10 , a first bonding portion 51 , a semiconductor element 9 , a second bonding portion 52 , wirings 8 , terminals 7 , a housing 6 , a cover 70 , and a sealing member 60 .

[0025] The base plate 5 constitutes the bottom surface of the semiconductor device 100. In other words, the base plate 5 is the bottom plate of the semiconductor device 100. The insulating substrate 10 is located on the base plate 5. The insulating substrate 10 and the base plate 5 are bonded, for example, by a first bonding portion 51. The semiconductor element 9 is located on the insulating substrate 10. The semiconductor element 9 and the insulating substrate 10 are bonded, for example, by a second bonding portion 52. The housing 6 is combined with the base plate 5. The housing 6 constitutes the side surface of the semiconductor device 100. The terminal 7 is located on the housing 6. The cover 70 is located on the housing 6. The cover 70 and the housing 6 are bonded, for example, by an adhesive not shown in the figure. The sealing member 60 is filled in the area surrounded by the base plate 5, the housing 6 and the cover 70. The wiring 8 is a portion for electrically connecting the semiconductor element 9 and an external device (not shown) of the semiconductor device 100.

[0026] The base plate 5 is, for example, in the form of a flat plate. The base plate 5 has a seventh surface 17 and an eighth surface 18. The seventh surface 17 is the bottom surface of the semiconductor device 100. The eighth surface 18 is located on the opposite side of the seventh surface 17. The base plate 5 is, for example, made of copper. The insulating substrate 10 is opposite to the eighth surface 18 of the base plate 5. The insulating substrate 10 has an insulating layer 4, a first electrode pattern 1, a second electrode pattern 2, and a third electrode pattern 3.

[0027] The third electrode pattern 3 faces the eighth surface 18 of the base plate 5. The third electrode pattern 3 is made of copper, for example. The third electrode pattern 3 and the base plate 5 are joined, for example, by a first joining portion 51. The first joining portion 51 is, for example, solder. The first joining portion 51 may also be made of silver or a silver alloy, for example.

[0028] The insulating layer 4 is located on the third electrode pattern 3. The insulating layer 4 has a ninth surface 19 and a tenth surface 20. The ninth surface 19 is opposite to the third electrode pattern 3. The insulating layer 4 is in contact with the third electrode pattern 3 on the ninth surface 19. For example, the third electrode pattern 3 is provided on the ninth surface 19 of the insulating layer 4 using a direct bonding method, a solder bonding method, a molten metal bonding method, or a plating method. The tenth surface 20 is located on the opposite side of the ninth surface 19.

[0029] The insulating layer 4 insulates the semiconductor element 9 from the substrate 5. The insulating layer 4 preferably has heat dissipation properties. The insulating layer 4 is made of, for example, aluminum oxide (Al 2 O 3 ), silicon dioxide (SiO 2 ), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si 3 N 4 ) and other ceramics.

[0030] The first electrode pattern 1 is provided on the insulating layer 4. For example, the first electrode pattern 1 is provided on the insulating layer 4 using a direct bonding method, a solder bonding method, a molten metal bonding method, or a plating method. The first electrode pattern 1 faces the insulating layer 4. The first electrode pattern 1 is made of, for example, copper. The first electrode pattern 1 has a first surface 11 and a second surface 12.

[0031] The first surface 11 faces the insulating layer 4. On the first surface 11, the first electrode pattern 1 is in contact with the insulating layer 4, for example. On the first surface 11, the first electrode pattern 1 may be bonded to the insulating layer 4 via a bonding material (not shown). The second surface 12 is located on the opposite side of the first surface 11.

[0032] The second electrode pattern 2 is provided on the insulating layer 4. The second electrode pattern 2 faces the tenth surface 20 of the insulating layer 4. For example, the second electrode pattern 2 is provided on the insulating layer 4 using a direct bonding method, a solder bonding method, a molten metal bonding method, or a plating method. The second electrode pattern 2 is separated from the first electrode pattern 1. The second electrode pattern 2 is made of copper, for example. The second electrode pattern 2 has a fourth surface 14 and a fifth surface 15.

[0033] The fourth surface 14 is opposite to the insulating layer 4. On the fourth surface 14, the second electrode pattern 2 is in contact with the insulating layer 4, for example. On the fourth surface 14, the second electrode pattern 2 may also be bonded to the insulating layer 4 via a bonding material (not shown). The fifth surface 15 is located on the opposite side of the fourth surface 14. In addition, Figure 1 The cross section shown is a cross section perpendicular to the second surface 12. Specifically, Figure 1 The cross section shown is a cross section that is perpendicular to the second surface 12 and intersects the first electrode pattern 1 and the second electrode pattern 2 .

[0034] The semiconductor element 9 is provided on the first electrode pattern 1. The semiconductor element 9 is opposite to the second surface 12 of the first electrode pattern 1. The semiconductor element 9 and the first electrode pattern 1 are joined by the second joining portion 52. From another point of view, each of the semiconductor element 9 and the first electrode pattern 1 is in contact with the second joining portion 52. The second surface 12 is separated from the semiconductor element 9. The second joining portion 52 is, for example, solder. The second joining portion 52 may also be composed of, for example, silver or a silver alloy. The number of semiconductor elements 9 is, for example, two. The two semiconductor elements 9 are electrically connected to each other by the wiring 8.

[0035] The semiconductor element 9 is, for example, a wide bandgap semiconductor made of silicon carbide (SiC), gallium nitride (GaN)-based materials, or diamond. In addition, a wide bandgap semiconductor refers to a semiconductor with a larger bandgap than silicon (Si). The semiconductor element 9 is, for example, an electric power semiconductor element whose operating temperature reaches 150° C. or more. Specifically, the semiconductor element 9 is, for example, a semiconductor element for controlling large currents, such as a MOSFET. The semiconductor element 9 may also be a diode for reflux.

[0036] The shell 6 is annular in shape. The shell 6 surrounds the insulating substrate 10. The shell 6 is preferably made of a material that does not deform thermally within the operating temperature range of the semiconductor device 100. The shell 6 is preferably made of a material having insulating properties. Specifically, the shell 6 is preferably made of a resin material having a high thermal softening point. More specifically, the shell 6 is made of, for example, polyphenylene sulfide (PPS: PolyPhenylene Sulfide) resin.

[0037] The cover 70 isolates the inside of the semiconductor device 100 from the outside of the semiconductor device 100. The cover 70 is a part that prevents dust and the like from entering the inside of the semiconductor device 100. The terminal 7 is located between the cover 70 and the housing 6. The terminal 7 may be sandwiched between the housing 6 and the cover 70. A part of the terminal 7 is exposed outside the semiconductor device 100. The terminal 7 is made of copper, for example.

[0038] The wiring 8 electrically connects the terminal 7 and the semiconductor element 9. The wiring 8 electrically connects the semiconductor element 9 and the second electrode pattern 2. The wiring 8 electrically connects the second electrode pattern 2 and the terminal 7. The shape of the wiring 8 is linear. The cross section of the wiring 8 is, for example, circular. The wiring 8 is made of, for example, gold or aluminum.

[0039] The sealing member 60 covers each of the insulating substrate 10, the semiconductor element 9, and the wiring 8. The sealing member 60 insulates each of the insulating substrate 10, the semiconductor element 9, and the wiring 8. The sealing member 60 is in contact with each of the terminal 7, the housing 6, and the base plate 5. The sealing member 60 is separated from the cover 70. The sealing member 60 is made of a resin having a predetermined elastic modulus and heat resistance. Specifically, the sealing member 60 is made of, for example, epoxy resin. The sealing member 60 may also be made of a resin having insulation and adhesiveness. Specifically, the sealing member 60 may also be made of, for example, silicone resin.

[0040] like Figure 2 As shown, the first electrode pattern 1 includes a first main body portion 21 and a first step portion 31. The first step portion 31 protrudes from the first main body portion 21. Specifically, the first step portion 31 protrudes from the first main body portion 21 in a direction parallel to the first surface 11.

[0041] The first main body 21 constitutes each of the first surface 11 and the second surface 12 of the first electrode pattern 1. The first main body 21 has a first side surface 41. The first side surface 41 is connected to the second surface 12. The first side surface 41 is opposite to the second electrode pattern 2. The first side surface 41 is separated from the second electrode pattern 2. In a section perpendicular to the second surface 12, the first side surface 41 is curved. In a section perpendicular to the second surface 12, the first side surface 41 may also be arc-shaped. In a section perpendicular to the second surface 12, the first side surface 41 is, for example, recessed toward the inner side of the first main body 21.

[0042] The first step portion 31 has a third surface 13, a first step surface 25, and a first step side surface 43. The third surface 13 is connected to the first surface 11 of the first main body portion 21. The third surface 13 constitutes a part of the bottom surface of the first electrode pattern 1. The third surface 13 is opposite to the insulating layer 4. In the third surface 13, the first electrode pattern 1 is in contact with the insulating layer 4, for example. In the third surface 13, the first electrode pattern 1 may also be bonded to the insulating layer 4 via a bonding material (not shown). The third surface 13 extends in the direction in which the first surface 11 extends.

[0043] The first step surface 25 is located on the opposite side of the third surface 13. The first step surface 25 is connected to the first side surface 41. The first step surface 25 is, for example, a plane. The first step surface 25 extends, for example, in a direction parallel to the first surface 11. In a direction perpendicular to the second surface 12, the first step surface 25 is located between the first surface 11 and the second surface 12.

[0044] The first step side surface 43 is connected to each of the third surface 13 and the first step surface 25. The first step side surface 43 is opposite to the second electrode pattern 2. The first step side surface 43 is separated from the second electrode pattern 2. The first step side surface 43 is located outside the first electrode pattern 1 compared to the first side surface 41. In a cross section perpendicular to the second surface 12, the first step side surface 43 is, for example, curved. In a cross section perpendicular to the second surface 12, the first step side surface 43 may also be arc-shaped. In a cross section perpendicular to the second surface 12, the first step side surface 43 is, for example, recessed toward the inner side of the first main body 21.

[0045] like Figure 2 As shown, in the section perpendicular to the second surface 12, the boundary between the second surface 12 and the first side surface 41 is the first boundary 91. In the section perpendicular to the second surface 12, the boundary between the first side surface 41 and the first step surface 25 is the second boundary 92. In the section perpendicular to the second surface 12, the line segment connecting the first boundary 91 and the second boundary 92 is the first line segment 71. The first line segment 71 may also extend in a direction perpendicular to the second surface 12. The length of the first line segment 71 is the first length D1. The length of the first side surface 41 in the section perpendicular to the second surface 12 is longer than the first length D1. In addition, in the section perpendicular to the second surface 12, the length of the first side surface 41 refers to the distance from the first boundary 91 to the second boundary 92 along the first side surface 41.

[0046] The second electrode pattern 2 has a second main body portion 22 and a second step portion 32. The second step portion 32 protrudes from the second main body portion 22. Specifically, the second step portion 32 protrudes from the second main body portion 22 in a direction parallel to the fourth surface 14. Figure 1 as well as Figure 2 The cross section shown is a cross section that is perpendicular to the second surface 12 and intersects each of the first step portion 31 and the second step portion 32 .

[0047] The second main body portion 22 constitutes each of the fourth surface 14 and the fifth surface 15 of the second electrode pattern 2. The second main body portion 22 has a second side surface 42. The second side surface 42 is connected to the fifth surface 15. The second side surface 42 is opposite to the first side surface 41 of the first electrode pattern 1. The second side surface 42 is separated from the first side surface 41. In a section perpendicular to the second surface 12, the second side surface 42 is curved. In a section perpendicular to the second surface 12, the second side surface 42 may also be arc-shaped. In a section perpendicular to the second surface 12, the second side surface 42 is, for example, recessed toward the inner side of the second main body portion 22.

[0048] The second step portion 32 has a sixth surface 16, a second step surface 26, and a second step side surface 44. The sixth surface 16 is connected to the fourth surface 14 of the second main body portion 22. The sixth surface 16 constitutes a part of the bottom surface of the second electrode pattern 2. The sixth surface 16 is opposite to the insulating layer 4. On the sixth surface 16, the second electrode pattern 2 is in contact with the insulating layer 4, for example. On the sixth surface 16, the second electrode pattern 2 may also be bonded to the insulating layer 4 via a bonding material (not shown). The sixth surface 16 extends in the direction in which the fourth surface 14 extends.

[0049] The second step surface 26 is located on the opposite side of the sixth surface 16. The second step surface 26 is connected to the second side surface 42. The second step surface 26 is, for example, a plane. The second step surface 26 extends, for example, in a direction parallel to the fourth surface 14. In a direction perpendicular to the second surface 12, the second step surface 26 is located between the fourth surface 14 and the fifth surface 15.

[0050] The second step side surface 44 is connected to each of the sixth surface 16 and the second step surface 26. The second step side surface 44 is opposite to the first step side surface 43 of the first electrode pattern 1. The second step side surface 44 is separated from the first step side surface 43. The second step side surface 44 is located outside the second electrode pattern 2 compared to the second side surface 42. In a section perpendicular to the second surface 12, the second step side surface 44 is, for example, curved. In a section perpendicular to the second surface 12, the second step side surface 44 may also be arc-shaped. In a section perpendicular to the second surface 12, the second step side surface 44 is, for example, recessed toward the inner side of the second main body 22.

[0051] like Figure 2As shown, in the section perpendicular to the second surface 12, the boundary between the fifth surface 15 and the second side surface 42 is the third boundary 93. In the section perpendicular to the second surface 12, the boundary between the second side surface 42 and the second step surface 26 is the fourth boundary 94. In the section perpendicular to the second surface 12, the line segment connecting the third boundary 93 and the fourth boundary 94 is the fifth line segment 75. The fifth line segment 75 may also extend in a direction perpendicular to the second surface 12. The length of the fifth line segment 75 is the fifth length D5. The length of the second side surface 42 in the section perpendicular to the second surface 12 is longer than the fifth length D5. In addition, in the section perpendicular to the second surface 12, the length of the second side surface 42 refers to the distance along the second side surface 42 from the third boundary 93 to the fourth boundary 94.

[0052] like Figure 2 As shown, in the cross section perpendicular to the second surface 12, the line segment connecting the first boundary 91 and the third boundary 93 is the second line segment 72. The second line segment 72 extends, for example, along the direction in which the second surface 12 extends and from the first electrode pattern 1 toward the second electrode pattern 2. The length of the second line segment 72 is the second length D2.

[0053] In the cross section perpendicular to the second surface 12, the line segment connecting the second boundary 92 and the fourth boundary 94 is the third line segment 73. The third line segment 73 extends, for example, in a direction parallel to the second surface 12 and from the first electrode pattern 1 toward the second electrode pattern 2. The third line segment 73 may be substantially parallel to the second line segment 72. The length of the third line segment 73 is a third length D3. The third length D3 may be substantially the same as the second length D2. The third length D3 may be longer than the second length D2.

[0054] In the cross section perpendicular to the second surface 12, the midpoint of the first side surface 41 is the first midpoint 81. In the direction perpendicular to the second surface 12, the distance between the first boundary 91 and the first midpoint 81 is equal to the distance between the second boundary 92 and the first midpoint 81. In the cross section perpendicular to the second surface 12, the midpoint of the second side surface 42 is the second midpoint 82. In the direction perpendicular to the second surface 12, the distance between the third boundary 93 and the second midpoint 82 is equal to the distance between the fourth boundary 94 and the second midpoint 82.

[0055] In the cross section perpendicular to the second surface 12, the line segment connecting the first intermediate point 81 and the second intermediate point 82 is the fourth line segment 74. The fourth line segment 74 may be substantially parallel to the second line segment 72. In the direction perpendicular to the second surface 12, the fourth line segment 74 is between the second line segment 72 and the third line segment 73. The length of the fourth line segment 74 is the fourth length D4. The fourth length D4 is longer than each of the second length D2 and the third length D3.

[0056] like Figure 2As shown, the thickness of the first electrode pattern 1 in the direction perpendicular to the second surface 12 is the first thickness H1. The first thickness H1 is the distance between the first surface 11 and the second surface 12 in the direction perpendicular to the second surface 12. The first thickness H1 is, for example, greater than 0.3 mm and less than 5 mm. The first thickness H1 may also be, for example, greater than 0.5 mm.

[0057] The thickness of the second electrode pattern 2 in the direction perpendicular to the second surface 12 is the second thickness H2. The second thickness H2 is the distance between the fourth surface 14 and the fifth surface 15 in the direction perpendicular to the second surface 12. The second thickness H2 is, for example, greater than 0.3 mm and less than 5 mm. The second thickness H2 may also be, for example, greater than 0.5 mm. The second thickness H2 may also be substantially the same as the first thickness H1.

[0058] The thickness of the first step portion 31 in the direction perpendicular to the second surface 12 is the third thickness H3. The third thickness H3 is the distance between the third surface 13 and the first step surface 25 in the direction perpendicular to the second surface 12. The third thickness H3 is, for example, 0.2 mm. The third thickness H3 is smaller than the first thickness H1. The third thickness H3 is, for example, 0.1 times or more and 0.8 times or less of the first thickness H1.

[0059] The thickness of the second step portion 32 in the direction perpendicular to the second surface 12 is the fourth thickness H4. The fourth thickness H4 is the distance between the sixth surface 16 and the second step surface 26 in the direction perpendicular to the second surface 12. The fourth thickness H4 is, for example, 0.2 mm. The fourth thickness H4 is smaller than the second thickness H2. The fourth thickness H4 is, for example, 0.1 times or more and 0.8 times or less of the second thickness H2. The fourth thickness H4 may also be substantially the same as the third thickness H3.

[0060] The thickness of the insulating layer 4 in the direction perpendicular to the second surface 12 is the fifth thickness H5. The fifth thickness H5 is the distance between the ninth surface 19 and the tenth surface 20 in the direction perpendicular to the second surface 12. The fifth thickness H5 is, for example, 0.2 mm. The first thickness H1 is, for example, more than 4 times the fifth thickness H5. The lower limit of the first thickness H1 is not particularly limited, and for example, it may be more than 6 times the fifth thickness H5, or more than 8 times the fifth thickness H5. The upper limit of the first thickness H1 is not particularly limited, and for example, it may be less than 20 times the fifth thickness H5, or less than 10 times the fifth thickness H5.

[0061] The second thickness H2 is, for example, 4 times or more of the fifth thickness H5. The lower limit of the second thickness H2 is not particularly limited, and for example, it may be 6 times or more of the fifth thickness H5, or 8 times or more of the fifth thickness H5. The upper limit of the second thickness H2 is not particularly limited, and for example, it may be 20 times or less of the fifth thickness H5, or 10 times or less of the fifth thickness H5.

[0062] The third thickness H3 is, for example, more than half of the fifth thickness H5. The lower limit of the third thickness H3 is not particularly limited, and for example, it may be more than the fifth thickness H5, or more than twice the fifth thickness H5. The upper limit of the third thickness H3 is not particularly limited, and for example, it may be less than five times the fifth thickness H5, or less than four times the fifth thickness H5.

[0063] The fourth thickness H4 is, for example, more than half of the fifth thickness H5. The lower limit of the fourth thickness H4 is not particularly limited, and for example, it may be more than the fifth thickness H5, or more than twice the fifth thickness H5. The upper limit of the fourth thickness H4 is not particularly limited, and for example, it may be less than 5 times the fifth thickness H5, or less than 4 times the fifth thickness H5.

[0064] (Method for forming electrode pattern)

[0065] Next, use Figures 3 to 5 , a method for forming the first electrode pattern 1 and the second electrode pattern 2 of the semiconductor device 100 according to Embodiment 1 is described. In addition, hereinafter, the first electrode pattern 1 and the second electrode pattern 2 are collectively referred to as electrode patterns.

[0066] First, if Figure 3 As shown, for example, a metal plate 90 is bonded to the 10th surface 20 of the insulating layer 4 using a direct bonding method. The metal plate 90 has an 11th surface 86 and a 12th surface 87. The 11th surface 86 is in contact with the insulating layer 4, for example. The 12th surface 87 is located on the opposite side of the 11th surface 86.

[0067] Next, if Figure 4 As shown, for example, the metal plate 90 is cut by milling and sandblasting. Thus, a wall surface 98 and a bottom surface 97 are formed in the metal plate 90. The wall surface 98 is connected to the 12th surface 87. The wall surface 98 extends in a direction perpendicular to the 12th surface 87. The bottom surface 97 is connected to the wall surface 98. The wall surface 98 and the bottom surface 97 form a groove 99.

[0068] Next, if Figure 5 As shown, the resist 96 is printed on the metal plate 90. The resist 96 is printed on a part of the bottom surface 97 and each of the 12th surface 87. From another point of view, the 12th surface 87 is covered with the resist 96. A part of the bottom surface 97 is exposed from the resist 96. A part of the wall surface 98 is exposed from the resist 96.

[0069] The metal plate 90 is subjected to etching. As an etching liquid, for example, a ferric chloride solution is used. The bottom surface 97 and the wall surface 98 of the metal plate 90 are etched. A portion of the insulating layer 4 is exposed from the metal plate 90. As described above, the first electrode pattern 1 and the second electrode pattern 2 are formed (see Figure 1 as well as Figure 2 ).

[0070] In the case of forming the electrode pattern of the insulating substrate 10 using only etching, the time required to form the electrode pattern increases compared to the case of forming the electrode pattern using milling and etching. In particular, when the thickness of the metal plate 90 is, for example, 0.5 mm or more, the time required for etching becomes longer. Therefore, in the case where the etching solution is applied to the metal plate 90 in an uneven manner, the deviation of the size of the electrode pattern becomes larger. According to the method for forming the electrode pattern of the semiconductor device 100 involved in Embodiment 1, the electrode pattern is formed using milling and etching. Therefore, the deviation of the size of the electrode pattern can be reduced.

[0071] In addition, when the electrode pattern of the insulating substrate 10 is formed only by etching, the amount of the electrode pattern that is cut off by etching increases as the bottom surface of the electrode pattern approaches the top surface. In other words, as the bottom surface of the electrode pattern approaches the top surface, the side surface of the electrode pattern approaches the inner side of the electrode pattern. Therefore, compared with the case where the electrode pattern is formed by milling and etching, the second length D2 becomes longer. In other words, the ratio of the area of ​​the top surface to the area of ​​the bottom surface in the electrode pattern becomes smaller. According to the method for forming the electrode pattern of the semiconductor device 100 involved in embodiment 1, the ratio of the area of ​​the top surface to the area of ​​the bottom surface in the electrode pattern can be increased. In other words, the ratio of the area of ​​the top surface of the electrode pattern to the area of ​​the 10th surface 20 of the insulating layer 4 can be increased. Therefore, the insulating substrate 10 can be miniaturized without changing the number of semiconductor elements 9 in the semiconductor device 100. As a result, the semiconductor device 100 can be miniaturized.

[0072] When the electrode pattern is formed by only milling, the insulating layer 4 may be damaged when the electrode pattern near the insulating layer 4 is processed. As a result, the reliability of the insulating substrate 10 may be reduced. According to the method for forming the electrode pattern of the semiconductor device 100 according to the first embodiment, the electrode pattern near the insulating layer 4 is processed by etching. Therefore, the reliability of the insulating substrate 10 can be suppressed from being reduced.

[0073] Next, the operation and effects of the semiconductor device 100 according to the first embodiment will be described.

[0074] When the semiconductor device 100 is subjected to a heat cycle, there is a possibility that delamination occurs between components due to a difference in thermal expansion coefficients between components of the semiconductor device 100. Specifically, there is a possibility that the first electrode pattern 1 delaminates from the insulating layer 4 due to a difference in thermal expansion coefficients between the first electrode pattern 1 and the insulating layer 4.

[0075] According to the semiconductor device 100 involved in the first embodiment, the first electrode pattern 1 has the first main body portion 21 and the first step portion 31. The first step portion 31 protrudes from the first main body portion 21. The first step portion 31 has the third surface 13. The third surface 13 is opposite to the insulating layer 4. Therefore, the bonding area between the first electrode pattern 1 and the insulating layer 4 can be increased. In addition, compared with the case where the bonding area between the first electrode pattern 1 and the insulating layer 4 is increased by increasing the size of the first main body portion 21, the increase in thermal stress between the first electrode pattern 1 and the insulating layer 4 can be suppressed. Therefore, the peeling between the first electrode pattern 1 and the insulating layer 4 can be suppressed.

[0076] In addition, there is a possibility that the sealing component 60 is peeled off from the insulating substrate 10 due to the difference in thermal expansion coefficient between the sealing component 60 and the insulating substrate 10. According to the semiconductor device 100 involved in the first embodiment, the first main body 21 of the first electrode pattern 1 has a first side surface 41. In the cross section perpendicular to the second surface 12, the first side surface 41 is curved. In the cross section perpendicular to the second surface 12, the length of the first side surface 41 is longer than the length of the line segment connecting the first boundary 91 and the second boundary 92. Therefore, the sealing component 60 is arranged along the first side surface 41. As a result, an anchoring effect is exerted on the sealing component 60. The anchoring effect refers to, for example, the effect that the sealing component 60 enters the unevenness of the first side surface 41, so that the sealing component 60 sinks into the first side surface 41, and the bonding force between the sealing component 60 and the first electrode pattern 1 is improved.

[0077] Therefore, compared with the case where the shape of the first side surface 41 of the first electrode pattern 1 is a straight line, it is possible to suppress the peeling between the sealing member 60 and the insulating substrate 10. Therefore, the semiconductor device 100 according to the first embodiment can suppress the peeling between the first electrode pattern 1 and the insulating layer 4, and suppress the peeling between the sealing member 60 and the insulating substrate 10. As a result, it is possible to suppress the degradation of the insulation performance of the semiconductor device 100 due to the thermal cycle.

[0078] The semiconductor device 100 according to the first embodiment may also include a second electrode pattern 2. In the cross section perpendicular to the second surface 12, the length of the line segment connecting the first intermediate point 81 and the second intermediate point 82 (the fourth length D4) may be longer than the length of the line segment connecting the first boundary 91 and the third boundary 93 (the second length D2) and the length of the line segment connecting the second boundary 92 and the fourth boundary 94 (the third length D3). Therefore, the sealing member 60 is configured to be sunken between the first side surface 41 and the second side surface 42. As a result, the anchoring effect between the sealing member 60 and the first side surface 41 and the second side surface 42 is enhanced. As a result, it is possible to suppress the sealing member 60 from peeling off from the insulating substrate 10.

[0079] In order to improve the thermal diffusivity of the semiconductor device 100, the thickness of the electrode pattern is sometimes thickened. As the thickness of the electrode pattern increases, the thermal stress between the electrode pattern and the insulating layer 4 increases when a thermal cycle is applied. Therefore, the first electrode pattern 1 is easily peeled off. According to the semiconductor device 100 involved in embodiment 1, the thickness of the first electrode pattern 1 in the direction perpendicular to the second surface 12 can also be more than 4 times the thickness of the insulating layer 4. According to the semiconductor device 100 involved in embodiment 1, even in the insulating substrate 10 with a thick thickness of the first electrode pattern 1, it is possible to suppress the peeling between the insulating layer 4 and the first electrode pattern 1 and the peeling between the sealing component 60 and the insulating substrate 10 when a thermal cycle is applied. As a result, it is possible to suppress the degradation of the insulation performance of the semiconductor device 100.

[0080] When the thickness of the step portion of the electrode pattern is excessively thin, the proportion of the step portion contributing to the bonding force between the electrode pattern and the insulating layer 4 becomes small. Therefore, the effect of suppressing the peeling between the electrode pattern and the insulating layer 4 is reduced. According to the semiconductor device 100 involved in the first embodiment, the thickness of the first step portion 31 may be more than half of the thickness of the insulating layer 4. Therefore, the peeling between the first electrode pattern 1 and the insulating layer 4 can be suppressed more reliably.

[0081] When the thickness of the step portion of the electrode pattern is excessively thick, the thermal expansion amount in the step portion increases excessively. Therefore, there is a possibility that peeling occurs between the electrode pattern and the insulating layer 4. According to the semiconductor device 100 involved in the first embodiment, the thickness of the first step portion 31 may be less than 5 times the thickness of the insulating layer 4. Therefore, peeling between the first electrode pattern 1 and the insulating layer 4 can be suppressed.

[0082] In addition, when the ratio of the thickness of the step portion to the thickness of the electrode pattern is excessively large, the length of the side surface of the main body of the electrode pattern becomes excessively short, so the anchoring effect on the sealing member 60 becomes small. Therefore, there is a possibility that the sealing member 60 and the insulating substrate 10 are peeled off. According to the semiconductor device 100 involved in the first embodiment, the thickness of the first step portion 31 may be 0.8 times or less of the thickness of the first electrode pattern 1. Therefore, the peeling between the sealing member 60 and the insulating substrate 10 can be suppressed.

[0083] (Variation of Embodiment 1)

[0084] Next, use Figure 6 , a structure of a semiconductor device 100 according to a variation of the first embodiment will be described. Figure 6 The cross-sectional diagram shown is Figure 2 The cross-sectional diagram shown in FIG. Figure 6 As shown, the second length D2 may be greater than the third length D3. In the cross section perpendicular to the second surface 12, the first boundary 91 may be located inside the first electrode pattern 1 compared to the second boundary 92. In the cross section perpendicular to the second surface 12, the third boundary 93 may be located inside the second electrode pattern 2 compared to the fourth boundary 94.

[0085] The second length D2 may be greater than the fourth length D4. In the cross section perpendicular to the second surface 12, the first boundary 91 may be located inside the first electrode pattern 1 relative to the first midpoint 81. In the cross section perpendicular to the second surface 12, the third boundary 93 may be located inside the second electrode pattern 2 relative to the second midpoint 82.

[0086] In the above description, the insulating layer 4 is described as being made of ceramic. However, the structure of the semiconductor device 100 is not limited to the above structure. Specifically, the insulating layer 4 may be made of a resin cured product in which a powder is dispersed, such as Al 2 O 3 、SiO 2 、AlN、BN、Si 3 N 4 The powder can be made of ceramics such as diamond, silicon carbide or boron oxide (B 2 O 3 ) or a resin material such as silicone resin or acrylic resin. The shape of the powder is, for example, spherical. The shape of the powder can also be crushed, granular, scaly or agglomerated. The filling amount of the powder is an amount that obtains the required heat dissipation and insulation properties. The insulating layer 4 can also be composed of a resin cured product embedded in a ceramic plate.

[0087] The number of semiconductor elements 9 in the semiconductor device 100 is not limited to 2. The number of semiconductor elements 9 in the semiconductor device 100 may be a required number according to the application of the semiconductor device 100.

[0088] The materials of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5 and the terminal 7 are not particularly limited as long as they have the required heat dissipation characteristics. Specifically, the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5 and the terminal 7 can each be composed of, for example, a composite material of aluminum and iron, aluminum or iron. The first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5 and the terminal 7 can each be composed of a composite material such as copper / Invar alloy / copper clad material, and can also be composed of a composite material (AlSiC) of aluminum and silicon carbide. The first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the base plate 5 and the terminal 7 can each be composed of an alloy such as copper-molybdenum (CuMo).

[0089] The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the substrate 5, and the terminal 7 are each configured to supply the required current and voltage to the semiconductor element. Specifically, the surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the substrate 5, and the terminal 7 are each plated with nickel, for example. The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the substrate 5, and the terminal 7 may also be plated with gold or tin. The surfaces of the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the substrate 5, and the terminal 7 may also be provided with tiny concave and convex portions. Thus, the adhesion between the first electrode pattern 1, the second electrode pattern 2, the third electrode pattern 3, the substrate 5, and the terminal 7 and the sealing component 60 may be improved.

[0090] The wiring 8 may be, for example, a strip-shaped copper plate. In other words, the cross section of the wiring 8 may be, for example, a square. The number of wirings 8 is, for example, 4. The number of wirings 8 may be the number required according to the current density of the semiconductor element 9, etc.

[0091] The junction between the semiconductor element 9, the second electrode pattern 2, and each of the terminals 7 and the wiring 8 is a structure capable of supplying the required current and voltage to the semiconductor element 9. Specifically, for example, the semiconductor element 9, the second electrode pattern 2, and each of the terminals 7 and the wiring 8 can be joined using molten copper or tin, or can be joined using ultrasonic bonding. Implementation method 2.

[0092] Next, use Figure 7, the structure of the semiconductor device 100 involved in the second embodiment is described. The structure of the semiconductor device 100 involved in the second embodiment is mainly different from the structure of the semiconductor device 100 involved in the first embodiment in that the insulating layer 4 of the insulating substrate 10 is composed of an organic material. Regarding other points, the structure is substantially the same as the structure of the semiconductor device 100 involved in the first embodiment. The following description focuses on the points that are different from the structure of the semiconductor device 100 involved in the first embodiment. In addition, Figure 7 The cross-sectional diagram shown corresponds to Figure 1 Schematic cross-section shown.

[0093] like Figure 7 As shown, the insulating layer 4 of the insulating substrate 10 may also be bonded to the base plate 5. The 9th surface 19 of the insulating layer 4 is in contact with the 8th surface 18 of the base plate 5. For example, the insulating layer 4 and the base plate 5 are bonded using heat and pressure bonding (hot pressing). In other words, in the bonding between the insulating layer 4 and the base plate 5, for example, no bonding agent such as solder is used. The area of ​​the 9th surface 19 of the insulating layer 4 may be substantially the same as the area of ​​the 8th surface 18 of the base plate 5.

[0094] The insulating layer 4 is made of, for example, an organic material. Specifically, the insulating layer 4 may be made of, for example, epoxy resin. The insulating layer 4 may be made of a thermosetting resin such as polyimide resin, silicone resin, or acrylic resin. The insulating layer 4 may be made of, for example, an organic material made by filling ceramic powder into epoxy resin or the like.

[0095] Next, the operation and effects of the semiconductor device 100 according to the second embodiment will be described.

[0096] As the area of ​​the insulating layer 4 increases, the insulating layer 4 is easily affected by the warping of the semiconductor device 100 due to the load of the thermal cycle. Therefore, when the area of ​​the insulating layer 4 is excessively large, there is a possibility that cracks will occur in the insulating layer 4. According to the semiconductor device of the second embodiment, the insulating layer 4 is composed of an organic material. Generally, organic materials are softer than ceramics. Therefore, even when the area of ​​the insulating layer 4 is excessively large, cracks can be suppressed from occurring in the insulating layer 4.

[0097] When the insulating layer 4 is made of an organic material, the insulating layer 4 is more brittle and more susceptible to wear than when the insulating layer 4 is made of a ceramic material. Therefore, when the electrode pattern near the insulating layer 4 is processed by milling or the like, there is a possibility that the insulating layer 4 is worn. According to the semiconductor device involved in the present disclosure, etching is used when forming the electrode pattern near the insulating layer 4. Therefore, the wear of the insulating layer 4 can be suppressed. As a result, the reliability of the semiconductor device 100 can be suppressed from being reduced. Implementation method 3.

[0098] Next, use Figure 8 as well as Fig. 9 , the structure of the semiconductor device 100 involved in the third embodiment is described. The structure of the semiconductor device 100 involved in the third embodiment is mainly different from the structure of the semiconductor device 100 involved in the second embodiment in that the sealing component 60 has the first sealing portion 61 and the second sealing portion 62. Regarding other points, the structure is substantially the same as the structure of the semiconductor device 100 involved in the second embodiment. The following description will focus on the points that are different from the structure of the semiconductor device 100 involved in the second embodiment. In addition, Figure 8 The cross-sectional diagram shown corresponds to Figure 1 Schematic cross-section shown.

[0099] like Figure 8 as well as Fig. 9 As shown, the sealing member 60 includes a first sealing portion 61 and a second sealing portion 62. The first sealing portion 61 is located between the first electrode pattern 1 and the second electrode pattern 2. The first sealing portion 61 is in contact with each of the insulating layer 4, the first step portion 31, the second step portion 32, the first body portion 21, and the second body portion 22.

[0100] The thickness of the first sealing portion 61 in the direction perpendicular to the second surface 12 is a sixth thickness H6. The sixth thickness H6 is, for example, less than the first thickness H1. The first sealing portion 61 is, for example, made of epoxy resin. Alternatively, the first sealing portion 61 may be made of a thermosetting resin such as silicone resin or polyimide resin.

[0101] The second sealing portion 62 is located on the first sealing portion 61. The second sealing portion 62 is in contact with each of the insulating layer 4, the first sealing portion 61, the first step portion 31, the second step portion 32, the first main body portion 21, and the second main body portion 22. The second sealing portion 62 is made of, for example, silicone resin. The second sealing portion 62 may also be made of a thermosetting resin such as epoxy resin or polyimide resin. The adhesion of the material constituting the second sealing portion 62 may also be higher than the adhesion of the material constituting the first sealing portion 61.

[0102] The viscosity of the material constituting the first sealing portion 61 is lower than the viscosity of the material constituting the second sealing portion 62. In addition, the viscosity of the material constituting the first sealing portion 61 refers to the viscosity of the material constituting the first sealing portion 61 in a liquid state. Similarly, the viscosity of the material constituting the second sealing portion 62 refers to the viscosity of the material constituting the second sealing portion 62 in a liquid state.

[0103] In addition, in the above description, the structure in which the first sealing portion 61 is located between the first electrode pattern 1 and the second electrode pattern 2 is described, but the first sealing portion 61 may surround each of the first electrode pattern 1 and the second electrode pattern 2. From another point of view, the first sealing portion 61 may cover each of the first step portion 31 and the second step portion 32. The second sealing portion 62 may be separated from each of the first step portion 31 and the second step portion 32. The second sealing portion 62 may be separated from each of the first side surface 41 and the second side surface 42.

[0104] Next, the operation and effects of the semiconductor device 100 according to the third embodiment will be described.

[0105] When the thickness of the electrode pattern is excessively thick, there is a possibility that the sealing component 60 is not fully filled between the first electrode pattern 1 and the second electrode pattern 2, resulting in a gap. As a result, there is a possibility that the performance of the semiconductor device 100 is reduced. According to the semiconductor device 100 involved in embodiment 3, the sealing component 60 has a first sealing portion 61 and a second sealing portion 62. The first sealing portion 61 is in contact with each of the insulating layer 4, the first step portion 31, and the second step portion 32. The viscosity of the material constituting the first sealing portion 61 is lower than the viscosity of the material constituting the second sealing portion 62. Therefore, the first sealing portion 61 is also easy to fill in the narrow area between the electrode patterns. As a result, the occurrence of gaps between the sealing component 60 and the insulating substrate 10 can be suppressed. As a result, the insulation reliability of the semiconductor device 100 can be improved.

[0106] According to the semiconductor device 100 involved in the third embodiment, the first sealing portion 61 may also be composed of an epoxy resin. The second sealing portion 62 may also be composed of a silicone resin. Generally speaking, epoxy resin has a lower water permeability than silicone resin. Therefore, it is possible to suppress moisture absorption by the insulating layer 4. In addition, generally speaking, silicone resin has higher heat resistance than epoxy resin. Therefore, it is possible to improve the heat resistance of the second sealing portion 62. As a result, it is possible to improve the heat resistance of the semiconductor device 100.

[0107] When the insulating layer 4 is made of an organic material, it is more likely to absorb moisture than when the insulating layer 4 is made of ceramic. According to the semiconductor device 100 according to the third embodiment, even when the insulating layer 4 is made of an organic material, it is possible to suppress the insulating layer 4 from absorbing moisture.

[0108] (Variation of Embodiment 3)

[0109] Next, use Fig.10 The structure of a semiconductor device 100 according to a modification of the third embodiment will be described. Fig.10 The cross-sectional diagram shown corresponds to Fig. 9 Schematic cross-section shown.

[0110] like Fig.10 As shown, the sixth thickness H6 may be, for example, less than the third thickness H3. The upper limit of the sixth thickness H6 is not particularly limited, and may be, for example, less than 1 / 2 of the third thickness H3, or less than 1 / 4 of the third thickness H3. The lower limit of the sixth thickness H6 is not particularly limited, and may be, for example, more than 1 / 10 of the third thickness H3, or more than 1 / 8 of the third thickness H3.

[0111] The first seal portion 61 contacts a portion of each of the first step side surface 43 and the second step side surface 44. The first seal portion 61 is separated from each of the first body portion 21 and the second body portion 22. The first seal portion 61 is separated from each of the first step surface 25 and the second step surface 26.

[0112] A portion of the second sealing portion 62 is located between the first electrode pattern 1 and the second electrode pattern 2. The second sealing portion 62 is in contact with each of the first side surface 41, the second side surface 42, the first step surface 25, and the second step surface 26. The second sealing portion 62 is in contact with a portion of each of the first step side surface 43 and the second step side surface 44.

[0113] Next, the operation and effects of the semiconductor device 100 according to the modification of the third embodiment will be described.

[0114] According to the semiconductor device 100 involved in the modification of the third embodiment, the sixth thickness H6 may be, for example, less than the third thickness H3. Therefore, the second sealing portion 62 is filled between the electrode patterns. Thus, the anchoring effect generated by each of the first side surface 41 and the second side surface 42 is exerted on the second sealing portion 62. As a result, the peeling between the second sealing portion 62 and the insulating substrate 10 caused by the thermal cycle can be suppressed. Example

[0115] (Sample preparation)

[0116] Next, a test using the samples will be described. First, three semiconductor devices were prepared for each of samples 1 to 10. The semiconductor devices for samples 1 to 5 are comparative examples. The semiconductor devices 100 for samples 6 to 10 are examples.

[0117] The semiconductor device 100 associated with samples 1 to 10 corresponds to the semiconductor device 100 involved in Embodiment 2. In the semiconductor device 100 associated with samples 1 to 10, the size of the base plate 5 is 100 mm×150 mm. The size of the semiconductor element 9 is 10 mm×11 mm. The semiconductor element 9 and the insulating substrate 10 are bonded using solder. The diameter of the wiring 8 is 0.4 mm or 0.2 mm. The material of the wiring 8 is aluminum. The base plate 5 and the housing 6 are bonded using an adhesive.

[0118] According to the method for forming an electrode pattern of the semiconductor device 100 according to the first embodiment, the electrode patterns of the semiconductor devices 100 related to samples 1 to 10 were manufactured. The semiconductor devices 100 related to samples 1 to 5 did not have the first step portion 31 and the second step portion 32. The semiconductor devices 100 related to samples 6 to 10 had the first step portion 31 and the second step portion 32. The thickness of each of the first step portion 31 and the second step portion 32 of the semiconductor devices 100 related to samples 6 to 10 was 0.2 mm.

[0119] The electrode thickness (first thickness H1 and second thickness H2) of the semiconductor device related to Sample 1 and Sample 6 is 0.3 mm. The electrode thickness of the semiconductor device related to Sample 2 and Sample 7 is 0.5 mm. The electrode thickness of the semiconductor device related to Sample 3 and Sample 8 is 0.8 mm. The electrode thickness of the semiconductor device related to Sample 4 and Sample 9 is 1 mm. The electrode thickness of the semiconductor device related to Sample 5 and Sample 10 is 2 mm.

[0120] (Experimental Method)

[0121] A thermal cycle test was performed on the semiconductor devices 100 related to samples 1 to 10. First, before applying the thermal cycle, the insulation withstand voltage evaluation of the semiconductor devices 100 was performed. In the insulation withstand voltage evaluation, a voltage of an effective value of 4 kV was applied to the semiconductor devices 100. The number of semiconductor devices 100 that suffered insulation breakdown was confirmed among the three semiconductor devices 100.

[0122] Next, the semiconductor device 100 was placed in a temperature-controllable thermostatic bath, and the temperature of the thermostatic bath was repeatedly changed between -40°C and 180°C. The temperature of the thermostatic bath was maintained at -40°C for 30 minutes and then at 180°C for 30 minutes, and this was repeated 1000 times. The insulation withstand voltage of the semiconductor device 100 was evaluated every 250 cycles.

[0123] (Experimental results)

[0124]

Table 1

[0125] Table 1 shows the results of the insulation withstand voltage evaluation of the semiconductor devices 100 related to samples 1 to 10. In Table 1, A indicates that the number of semiconductor devices 100 that have undergone insulation breakdown is 0. B indicates that the number of semiconductor devices 100 that have undergone insulation breakdown is 1 or 2. C indicates that the number of semiconductor devices 100 that have undergone insulation breakdown is 3.

[0126] As shown in Table 1, in the semiconductor devices 100 related to samples 2 to 5, insulation breakdown was confirmed in the insulation withstand voltage evaluation after 1000 cycles. In other words, in the semiconductor device 100 of the comparative example, when the electrode thickness was 0.5 mm or more, the insulation performance was degraded by the thermal cycle test.

[0127] As shown in Table 1, in the semiconductor devices 100 related to samples 6 to 9, no semiconductor device 100 was confirmed to have insulation breakdown in the insulation withstand voltage evaluation after 1000 cycles. In other words, in the semiconductor device 100 of the embodiment, when the electrode thickness was 1 mm or less, the insulation performance was not degraded by the thermal cycle test.

[0128] As shown in Table 1, all semiconductor devices 100 related to sample 5 suffered insulation breakdown in the insulation withstand voltage evaluation after 1000 cycles. On the other hand, only one semiconductor device 100 related to sample 10 suffered insulation breakdown in the insulation withstand voltage evaluation after 1000 cycles.

[0129] From the above results, it was confirmed that the semiconductor device 100 of the embodiment can suppress the degradation of the insulation performance of the semiconductor device 100 when a heat cycle is applied, compared with the semiconductor device 100 of the comparative example.

[0130] The embodiments and examples disclosed herein are illustrative in all points and should not be construed as restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the scope and meaning equivalent to the claims.

[0131] (Explanation of symbols)

[0132] 1: 1st electrode pattern; 2: 2nd electrode pattern; 3: 3rd electrode pattern; 4: insulating layer; 5: base plate; 6: housing; 7: terminal; 8: wiring; 9: semiconductor element; 10: insulating substrate; 11: 1st surface; 12: 2nd surface; 13: 3rd surface; 14: 4th surface; 15: 5th surface; 16: 6th surface; 17: 7th surface; 18: 8th surface; 19: 9th surface; 20: 10th surface; 21: 1st main body; 22: 2nd main body; 25: 1st step surface; 26: 2nd step surface; 31: 1st step portion; 32: 2nd step portion; 41: 1st side surface; 42: 2nd side surface; 43: 1st step side surface; 44: 2nd step side surface; 51: 1st joint portion; 52: 2nd joint portion; 60: sealing component; 61: 1st sealing portion; 62: 2nd sealing portion; 70: cover; 71: 1st line segment; 72: 2nd line segment; 73: 3rd line segment; 74: 4th line segment; 75: 5th line segment; 81: 1st midpoint; 82: 2nd midpoint; 86: 11th surface; 87: 12th surface; 90: metal plate; 91: 1st boundary; 92: 2nd boundary; 93: 3rd boundary; 94: 4th boundary; 96: anti-etching agent; 97: bottom surface; 98: wall surface; 99: groove; 100: semiconductor device; D1: 1st length; D2: 2nd length; D3: 3rd length; D4: 4th length; D5: 5th length; H1: 1st thickness; H2: 2nd thickness; H3: 3rd thickness; H4: 4th thickness; H5: 5th thickness; H6: 6th thickness.

Claims

1. A semiconductor device comprising: An insulating substrate having an insulating layer and a first electrode pattern disposed on the insulating layer; A semiconductor element is disposed on the first electrode pattern; A shell, surrounding the insulating substrate; as well as a sealing member covering each of the insulating substrate and the semiconductor element, The first electrode pattern has a first main body portion and a first step portion protruding from the first main body portion. The first main body has: a first surface, opposite to the insulating layer; a second surface located on the opposite side of the first surface and facing the semiconductor element; and The first side surface is connected to the second side surface, The first step portion has: a third surface connected to the first surface and opposite to the insulating layer; as well as a first step surface, located on the opposite side of the third surface and connected to the first side surface, In a cross section perpendicular to the second surface, the first side surface is curved. In a cross section perpendicular to the second surface, When the boundary between the second surface and the first side surface is set as the first boundary, The boundary between the first side surface and the first step surface is set as the second boundary, When the length of the line segment connecting the first boundary and the second boundary is set to the first length, A length of the first side surface in a cross section perpendicular to the second surface is longer than the first length.

2. The semiconductor device according to claim 1, wherein The insulating substrate further includes a second electrode pattern disposed on the insulating layer and separated from the first electrode pattern. The second electrode pattern has a second main body portion and a second step portion protruding from the second main body portion. The second main body has: a fourth side, opposite to the insulating layer; a fifth surface, located on the opposite side of the fourth surface; and a second side surface connected to the fifth side surface and opposite to the first side surface, The second step portion has: a sixth surface connected to the fourth surface and opposite to the insulating layer; and a second step surface, located on the opposite side of the sixth surface and connected to the second side surface, In a cross section perpendicular to the second surface, When the boundary between the fifth surface and the second side surface is set as the third boundary, The boundary between the second side surface and the second step surface is set as the fourth boundary, The length of the line segment connecting the first boundary and the third boundary is set as the second length, The length of the line segment connecting the second boundary and the fourth boundary is set as a third length, When the length of the line segment connecting the midpoint of the first side surface and the midpoint of the second side surface is set to the fourth length, The fourth length is longer than each of the second length and the third length.

3. The semiconductor device according to claim 2, wherein: The sealing component has: a first sealing portion in contact with each of the insulating layer, the first step portion, and the second step portion; and The second sealing portion is located on the first sealing portion.

4. The semiconductor device according to claim 3, wherein: In a direction perpendicular to the second surface, a thickness of the first sealing portion is less than or equal to a thickness of the first step portion.

5. The semiconductor device according to claim 3 or 4, wherein: The viscosity of the material constituting the first sealing portion is lower than the viscosity of the material constituting the second sealing portion.

6. The semiconductor device according to claim 3 or 4, wherein: The first sealing portion is made of epoxy resin, The second sealing portion is made of silicone resin.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The insulating layer is made of an organic material.

8. The semiconductor device according to any one of claims 1 to 7, wherein: In a direction perpendicular to the second surface, a thickness of the first electrode pattern is four times or more the thickness of the insulating layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The thickness of the first step portion in a direction perpendicular to the second surface is equal to or greater than half of the thickness of the insulating layer.

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