Semiconductor package

Abstract

A semiconductor package according to an embodiment includes: an insulating layer including an upper surface and a lower surface; the protective layer is arranged on the upper surface of the insulating layer; a connecting member which is embedded in the insulating layer; and a wiring electrode embedded in the insulating layer and including an upper pad portion disposed between the insulating layer and the protective layer, a first via electrode disposed between the upper pad portion and the protective layer, a second via electrode disposed between the upper pad portion and the protective layer, and a bonding portion disposed between the first via electrode and the protective layer. And a first via electrode electrically connected to the connecting member by passing through a portion of the insulating layer from the upper pad portion and having a width narrower than a width of the upper pad portion, and a second via electrode embedded in the insulating layer and disposed closer to a lower surface of the insulating layer than the connecting member, and a bonding portion including a protruding portion disposed on the protective layer, and a through portion passing through the protective layer from the protruding portion and directly contacting the upper pad portion, the engaging portion includes a first engaging portion overlapping the connecting member in a vertical direction and a second engaging portion not overlapping the connecting member in the vertical direction. An inclination angle of each of a through portion of the first bonding portion and a through portion of the second bonding portion with respect to an upper surface of the insulating layer is closer to be perpendicular than an inclination angle of the second via electrode with respect to the upper surface of the insulating layer.

Description

Technical Field

[0001] Embodiments relate to semiconductor packaging. Background Art

[0002] As the performance of electrical / electronic products improves, technologies for arranging a large number of semiconductor devices on a semiconductor package substrate of limited size are being proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in achieving desired performance.

[0003] Therefore, a semiconductor package that uses a plurality of substrates to arrange a plurality of semiconductor devices has recently been provided. This semiconductor package has a structure in which a plurality of semiconductor devices on a substrate are connected to each other in a horizontal direction and / or a vertical direction. Therefore, the semiconductor package has the advantages of effectively using the mounting area of ​​the semiconductor device and transmitting a high-speed signal through a short signal transmission path between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products providing the Internet of Things (IoT), autonomous vehicles, and high-performance servers expand the concept to semiconductor chiplets as the number of semiconductor devices and / or the size of each semiconductor device increases or functional parts of semiconductor devices are divided according to the trend of high integration.

[0005] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets becomes important, and thus, there is a trend that an interposer is placed between the substrate of a semiconductor package and the semiconductor device.

[0006] The interposer may be used as a redistribution layer that gradually increases the width of a circuit pattern from the semiconductor device toward the semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chiplets, or interconnect the semiconductor device and the semiconductor package substrate. Thus, electrical signals may be smoothly transmitted between the semiconductor device and the semiconductor package substrate having a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.

[0007] At the same time, the packaging substrate and / or interposer applied to the semiconductor package may be equipped with a connecting member connected to the semiconductor device and / or the semiconductor chiplet. The connecting member is used to horizontally connect multiple semiconductor devices and / or semiconductor chips. Accordingly, the connecting member may be embedded in the packaging substrate and / or the interposer. At this time, the packaging substrate and / or the interposer may be provided with a plurality of bonding portions connected to the semiconductor device and / or the semiconductor chiplet. The bonding portion may include a first bonding portion that does not overlap with the connecting member in the vertical direction, and a second bonding portion that overlaps with the connecting member in the vertical direction and overlaps with the first bonding portion in the horizontal direction.

[0008] At this time, the first bonding portion and the second bonding portion may have different widths in the horizontal direction and / or different thicknesses in the vertical direction. That is, the width and / or thickness of the second bonding portion may depend on the width of the pad set in the connecting member and the height of the upper surface of the pad, but the width and height of the first bonding portion do not depend on the width and / or height of the pad set in the connecting member. That is, when the integration of the number of I / O (input and output) terminals of the connecting member increases, the current intensity generated during the plating of the first bonding portion and the second bonding portion may be different depending on the diameter and density of the through holes of the insulating layer and / or the protective layer set on the pad of the connecting member, and therefore, the height of the second bonding portion may be different from the height of the first bonding portion.

[0009] Therefore, the first bonding portion and the second bonding portion according to the prior art may have a height deviation due to a difference in width and / or thickness between the first bonding portion and the second bonding portion. In addition, when a height deviation occurs between the first bonding portion and the second bonding portion, a problem may occur that the semiconductor device and / or the semiconductor chiplet cannot be stably mounted on the first bonding portion and the second bonding portion. As a result, the operating characteristics, reliability, and yield of the semiconductor device and / or the semiconductor chiplet may deteriorate.

[0010] In addition, as the number of pads of the connecting member and the number of terminals of the semiconductor device increase, a fine pitch of two adjacent bonding parts in the first bonding part connected thereto is required. However, according to the prior art, the pitch between two adjacent bonding parts exceeds at least 60 μm. That is, the circuit board includes an electrode portion that passes through an insulating layer and is connected to the pad of the connecting member, and a bonding portion that passes through a protective layer and is arranged between the terminal of the semiconductor device and the electrode portion. At this time, the electrode portion includes a via electrode passing through the insulating layer and a pad electrode arranged on the via electrode. In addition, the bonding portion includes a through portion passing through the protective layer and a protruding portion arranged on the through portion. At this time, the pitch between the two adjacent bonding parts is determined by the width / interval of the via electrode, the width / interval of the pad electrode, the width / interval of the through portion, and the width / interval of the protruding portion. At this time, there is a limit to reducing the width of the via electrode and the width of the through portion, and as a result, the pitch between two adjacent bonding parts exceeds 60 μm. Therefore, there are limits to improving the circuit integration of the semiconductor package and miniaturizing the semiconductor package. Summary of the invention

[0011] [Technical issues]

[0012] The embodiment provides a semiconductor package having a novel structure.

[0013] In addition, the embodiment provides a semiconductor package capable of controlling height deviations between a plurality of bump portions connected to a semiconductor device.

[0014] In addition, the embodiment provides a semiconductor package capable of minimizing a pitch between a plurality of bumps.

[0015] The technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by technicians in the field to which the proposed embodiments belong from the following description.

[0016] [Technical solution]

[0017] A semiconductor package according to an embodiment includes: an insulating layer, the insulating layer including an upper surface and a lower surface; a protective layer, the protective layer being disposed on the upper surface of the insulating layer; a connecting member, the connecting member being embedded in the insulating layer; and a wiring electrode, the wiring electrode being embedded in the insulating layer and including: an upper pad portion, the upper pad portion being disposed between the insulating layer and the protective layer; a first via electrode, the first via electrode being electrically connected to the connecting member by passing through a portion of the insulating layer from the upper pad portion and having a width narrower than a width of the upper pad portion; and a second via electrode, the second via electrode being embedded in the insulating layer and is arranged to be closer to the lower surface of the insulating layer than the connecting member; and a joining portion, the joining portion including a protruding portion arranged on the protective layer and a through portion passing through the protective layer from the protruding portion and directly contacting the upper pad portion, wherein the joining portion includes a first joining portion overlapping with the connecting member in a vertical direction and a second joining portion not overlapping with the connecting member in a vertical direction, and each of the through portions of the first joining portion and the through portions of the second joining portion has an inclination angle relative to the upper surface of the insulating layer that is closer to vertical than the inclination angle of the second via electrode relative to the upper surface of the insulating layer.

[0018] In addition, the first bonding portion is provided as a plurality of first bonding portions, and the interval distance in the horizontal direction between two first bonding portions closest to each other among the plurality of first bonding portions is 26 μm or less.

[0019] In addition, each of the plurality of first engaging portions includes a plurality of first protruding portions, and a width of each of the plurality of first protruding portions in the horizontal direction is 29 μm to 34 μm.

[0020] In addition, the protective layer includes a plurality of first fillers, and the through portion of the first bonding portion does not contact the plurality of first fillers.

[0021] In addition, the first via electrode includes a first overlapping via electrode overlapping the connection member in a vertical direction, and an inclination angle of the first overlapping via electrode is the same as an inclination angle of the through portion of the first bonding portion.

[0022] In addition, the insulating layer includes a plurality of stacked insulating layers arranged between the upper surface of the insulating layer and the lower surface of the insulating layer, the plurality of stacked insulating layers include an upper insulating layer forming the upper surface of the insulating layer and a lower insulating layer forming the lower surface of the insulating layer, the wiring layer also includes a plurality of wiring electrodes respectively arranged in the plurality of stacked insulating layers, a plurality of via electrodes connecting the plurality of wiring electrodes, and a lower pad portion arranged on the lower surface of the insulating layer, the plurality of via electrodes also include a plurality of upper vias and a plurality of lower vias, the plurality of upper vias overlap with the connecting member in a horizontal direction, the plurality of lower vias are arranged between the plurality of upper vias and the lower surface of the insulating layer, and the inclination angle of the upper vias is symmetrical with the inclination angle of the lower vias.

[0023] In addition, the thickness of the upper insulating layer is thinner than that of the lower insulating layer.

[0024] In addition, the first through portion of the first bonding portion vertically overlaps at least a portion of the first overlapping via electrode.

[0025] In addition, the insulating layer includes a side surface located between the upper surface and the lower surface, the protective layer includes a lower surface facing the upper surface of the insulating layer, an upper surface corresponding to the lower surface, and a side surface located between the lower surface and the upper surface, the side surface of the protective layer includes an inner surface surrounding the first through portion and the second through portion, respectively, and an outer surface adjacent to the side surface of the insulating layer, and the length of the inner surface in the vertical direction is different from the length of the outer surface in the vertical direction.

[0026] In addition, the length of the inner surface in the vertical direction is greater than the length of the outer surface in the vertical direction.

[0027] [Beneficial Effects]

[0028] The embodiment includes a protective layer and a bonding portion that passes through a partial area of ​​the protective layer from the upper surface of the protective layer. At this time, the protective layer has a through hole corresponding to the bonding portion. The through hole of the protective layer is formed by a dry film pattern. That is, the through hole is formed corresponding to the width and pitch that the bonding portion provided in the semiconductor package should have. That is, the embodiment pre-forms a dry film pattern in consideration of the width and pitch of the bonding portion. Thus, the embodiment can minimize the pitch between multiple bonding portions. For example, the embodiment can arrange the horizontal distance between the centers of two adjacent bonding portions to be less than 40 μm. The embodiment can refine the pitch of the bonding portion to less than 40 μm, thereby, the embodiment can improve the circuit integration and miniaturize the circuit board and the semiconductor package. In addition, the embodiment can reduce the distance between multiple bonding portions, based on which the transmission distance of the signal transmitted through the corresponding bump portion can be minimized. Therefore, the embodiment can minimize the signal transmission loss that increases according to the signal transmission distance, thereby improving the electrical characteristics of the circuit board and the semiconductor package. In addition, the embodiment can allow the semiconductor device to be arranged on the circuit board to work stably, so that electronic products such as servers that apply semiconductor packages can work stably.

[0029] In addition, the embodiment has an electrode portion arranged between the connecting member and the joining portion. The electrode portion passes through at least a portion of the insulating layer. At this time, the insulating layer has a through hole corresponding to the via electrode of the electrode portion. In addition, a dry film is formed according to the width and pitch that the joining portion of the embodiment should have, and the through hole of the insulating layer is set by the dry film. Thus, the embodiment can form an electrode portion corresponding to the width and pitch that the joining portion should have. Therefore, the embodiment can make the joining portion have a target width and pitch. In addition, the embodiment can form the electrode portion at a position corresponding to the joining portion, thereby improving the positional alignment of the joining portion and the electrode portion, and further improving the electrical characteristics of the joining portion and the electrode portion.

[0030] In addition, the embodiment can minimize the height deviation between the plurality of joint parts. That is, the embodiment includes a first joint part overlapping with the connecting member in the vertical direction and a second joint part not overlapping with the connecting member in the vertical direction. At this time, the size of the first through-portion of the first joint part is the same as the size of the second through-portion of the second joint part. That is, the embodiment can use the dry film pattern to make the through-portions of the first joint part and the second joint part have the same size, thereby minimizing the height deviation between the first joint part and the second joint part caused by the size difference.

[0031] Therefore, the embodiment can minimize the height deviation of the first bonding portion and the second bonding portion, thereby allowing the semiconductor element to be stably arranged on the first bonding portion and the second bonding portion. Therefore, the embodiment can improve the reliability of the first semiconductor device and the second semiconductor device. In addition, the embodiment can allow the operation of the first semiconductor element and the second semiconductor element to be smoothly performed, thereby allowing the operation of the electronic product or server to be smoothly performed.

[0032] In addition, the embodiments allow the first bonding portion and the second bonding portion to have the same height, thereby preventing problems such as impedance changes or signal transmission loss caused by thickness changes of the first bonding portion and the second bonding portion, and problems such as the semiconductor device being set in a tilted state, thereby further improving electrical reliability.

[0033] In addition, the embodiment can relatively reduce the surface roughness of the interface between the through portion of each of the first bonding portion and the second bonding portion and the protective layer. Therefore, the embodiment can reduce the surface roughness of the through portion, thereby minimizing the signal transmission loss that increases in proportion to the surface roughness. Therefore, the embodiment can further improve the operating characteristics of the semiconductor device.

[0034] At the same time, the upper surface of the protective layer of the embodiment may have a concave portion and a convex portion through a process of thinning the thickness to increase the surface area of ​​the upper surface of the protective layer. The concave portion and the convex portion may improve the reliability of the circuit board in thermal cycles such as expansion and contraction of the circuit board caused by heat generated during the operation of the semiconductor chip or heat applied from the outside. For example, since the convex portion and the concave portion have different thicknesses, the volume deformed during thermal expansion may be different. That is, the thickness of the concave portion may be thinner than the thickness of the convex portion, and due to the difference in the thermal expansion coefficient of the convex portion and the thermal expansion coefficient of the concave portion, the overall thermal deformation of the semiconductor package may be suppressed. Therefore, the embodiment may prevent the semiconductor device coupled to the upper portion of the semiconductor package from being electrically separated during thermal expansion, thereby improving product reliability.

[0035] In addition, the via electrode located above the connecting member of the embodiment has a different width and / or tilt direction from the via electrode located below the connecting member. That is, the via electrode located above the connecting member has a more vertical side surface than the via electrode located below the connecting member. That is, by arranging the via electrode with a vertical side surface to be located above the connecting member, the embodiment can have the effect of improving the warping of the circuit board. In addition, when the pattern of the via electrode with a vertical side surface is finer than the pattern of the via electrode with an inclined side surface, the via electrode with a vertical side surface can be implemented to be located above the connecting member so as to reduce the stress applied to the via electrode, thereby improving the reliability of the electrical connection between the semiconductor chip and the circuit board.

[0036] In addition, the upper surface of the protective layer of the embodiment includes a first area adjacent to and including the through hole, and a second area other than the first area. The height of the first area of ​​the protective layer is greater than the height of the second area. The first area of ​​the protective layer includes a raised portion that bulges in an upward direction. Specifically, the upper surface of the protective layer includes a raised portion that bulges in an upward direction while being connected to the inner surface of the through hole. The raised portion can improve the process characteristics in the process of setting a connecting portion such as solder in the through hole of the protective layer. Specifically, the raised portion can be used as a barrier function to prevent the diffusion of the connecting portion without increasing the total thickness of the protective layer. Thus, the embodiment can prevent the diffusion of the connecting portion set in the through hole, and therefore, the width and pitch of the connecting portion can be refined. In addition, the embodiment can solve the problem of short-circuit connection with adjacent pads caused by the diffusion of the connecting portion. Thus, the physical reliability and electrical reliability of the circuit board and the semiconductor package can be improved.

[0037] In addition, the raised portion of the protective layer of the embodiment can have a closed loop shape, which surrounds the periphery of the through hole and is located adjacent to the through hole. Thus, the embodiment can more effectively prevent the diffusion of the connection portion disposed in the through hole, thereby improving product reliability.

[0038] In addition, the embodiment can form a connection portion having a width corresponding to the width of the opening region of the protective layer by using the protruding portion, while maintaining a distance between the upper surface of the connection portion and the upper surface of the protective layer equal to the POR. Thus, the embodiment can reduce welding defects that may occur during the welding bonding process.

[0039] In addition, the embodiment can remove the photoinitiator provided in the protective layer. At this time, the photoinitiator acts as a factor that deteriorates the physical and electrical properties of the semiconductor package. At this time, because the photoinitiator is not included in the protective layer, the embodiment can improve the physical and electrical properties of the circuit board. In addition, since the photoinitiator is not included in the protective layer, the embodiment can expand the types of insulating layers that can be used as the protective layer, and further reduce the unit cost required to develop the protective layer. In addition, compared with the control example, the embodiment can significantly reduce the tolerance between the center of the through hole of the protective layer and the center of the pad. Therefore, the embodiment can improve the installation reliability of the semiconductor device, thereby improving the physical reliability and electrical reliability of the circuit board and the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1a is a diagram showing a configuration of a circuit board according to an embodiment.

[0041] Figure 1b yes Figure 1a A plan view of the joining portion is shown.

[0042] Figure 1c yes Figure 1a An enlarged view of a partial area R1.

[0043] Figure 1d It is used to explain Figure 1c Cross-sectional view of the surface roughness of the first protective layer.

[0044] Figure 2a and Figure 2b is a cross-sectional view showing a joining portion according to the prior art.

[0045] Figure 3 yes Figure 1c An enlarged view of a modified example of .

[0046] Figure 4a is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0047] Figure 4b yes Figure 4a An enlarged view of a partial area R1.

[0048] Figure 4c is a cross-sectional view for explaining the surface roughness and structure of the first insulating layer according to the second embodiment.

[0049] Figure 5 According to the third embodiment Figure 4a An enlarged view of a partial region R1 of a semiconductor package.

[0050] Figure 6 According to the fourth embodiment Figure 4a An enlarged view of a partial region R1 of a semiconductor package.

[0051] Figure 7 is a diagram showing a semiconductor package according to a fifth embodiment.

[0052] Figures 8a to 8q It is described in the process sequence. Figure 4a sectional view of a method for manufacturing a circuit board according to a second embodiment.

[0053] Fig. 9 is a cross-sectional view showing a circuit board according to a comparative example.

[0054] Fig.10 is a sectional view showing a circuit board according to a sixth embodiment.

[0055] Fig.11 It is shown in detail Fig.10 A cross-sectional view of a first partial area of ​​a circuit board.

[0056] Fig.12 It is shown in detail Fig.11 A cross-sectional view of a second partial area of ​​the circuit board.

[0057] Fig.13 is a cross-sectional view of a partial area of ​​a circuit board for explaining a raised portion according to an embodiment.

[0058] Fig.14 is a plan view of a partial area of ​​a circuit board for explaining a raised portion according to an embodiment.

[0059] Fig.15 It is shown Fig.13 and Fig.14 A scanning electron microscope image of a portion of a circuit board.

[0060] Fig.16 It is shown Fig.12 Scanning electron microscope image of the upper surface of the first protective layer.

[0061] Fig.17 It is shown Fig.12 Scanning electron microscope image of the inner surface of the through-hole of the first protective layer.

[0062] Fig.18 A resist pattern for forming a through hole of a first protective layer according to an embodiment is shown.

[0063] Fig.19 is a plan view for explaining the tolerance (SRR: Solder Resist Registration) according to the comparative example.

[0064] Fig. 20 is a diagram for explaining tolerance according to the sixth embodiment.

[0065] Fig.21 is a sectional view showing a circuit board according to a seventh embodiment.

[0066] Fig. 22 is a sectional view showing a circuit board according to an eighth embodiment.

[0067] Fig.23 are diagrams showing various modified examples of the circuit board according to the embodiment.

[0068] Fig.24 is a cross-sectional view showing a semiconductor package according to another embodiment.

[0069] Fig.25 : is a graph showing the arrangement reliability of the first connection portion of the embodiment and the comparative example.

[0070] Figure 26a to Figure 26h It is described in the process sequence. Fig.10 A cross-sectional view of the circuit board method is shown.

[0071] Figures 27a to 27n are cross-sectional views describing a method of manufacturing a circuit board according to another embodiment in process order. DETAILED DESCRIPTION

[0072] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0073] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments and may be implemented in various other forms, and one or more elements of the embodiments may be selectively combined and rearranged within the spirit and scope of the present disclosure.

[0074] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present disclosure may be interpreted as having the same meaning as that generally understood by a person of ordinary skill in the art to which the present invention belongs, and such terms as those defined in commonly used dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant art. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0075] In the present specification, unless otherwise stated, a singular form may also include a plural form, and when described as "at least one (or more) of A (and), B, and C", at least one of all combinations of A, B, and C may be included. In addition, when describing elements of an embodiment of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0076] These terms are only used to distinguish an element from other elements, and these terms do not limit the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it can include not only the element being directly "connected", "coupled" or "in contact with" the other element, but also the element being "connected", "coupled" or "in contact with" another element between the element and the other element.

[0077] The terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "one", "said" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include", "contain", "comprise" and / or "have" specify the presence of stated features, integers, steps, operations, elements and / or parts when used herein, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their combinations.

[0078] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those commonly understood by ordinary technicians in the field to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and are not interpreted in an ideal or overly formal sense unless clearly defined in this application.

[0079] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, but the same or corresponding components will be given the same reference numerals regardless of the reference numerals, and redundant descriptions thereof will be omitted.

[0080] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. In addition, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor chip and the circuit board, a resin portion for filling the space between the semiconductor chip and the circuit board, and a molding portion for completely surrounding the semiconductor chip. Here, various semiconductor chips can be installed in the semiconductor package.

[0081] The semiconductor chip may include active devices and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC), in which hundreds or even millions of integrated circuits are integrated into a single chip. The semiconductor chip may be a logic chip, a memory chip, etc. The logic chip may be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application specific IC (ASIC), etc., or a chipset including a specific combination of the above.

[0082] The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or the like.

[0083] Meanwhile, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0084] In addition, the electronic device may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game console, a smart watch, a car, etc. However, the present invention is not limited thereto, and may be any other electronic device that processes data other than these.

[0085] Figure 1a is a diagram showing a configuration of a circuit board according to an embodiment, Figure 1b yes Figure 1a A plan view of the joint portion shown, Figure 1c yes Figure 1a An enlarged view of a partial area R1, Figure 1d It is used to explain Figure 1c A cross-sectional view of the surface roughness of the first protective layer, Figure 2a and Figure 2b is a cross-sectional view showing a joining portion according to the prior art, Figure 3 yes Figure 1c Hereinafter, reference will be made to Figures 1a to 3 A semiconductor package of an embodiment is described.

[0086] refer to Figure 1a , a semiconductor package according to an embodiment includes a circuit board 100 electrically connecting a main board of an electronic device with semiconductor chips 320 and 330, a plurality of semiconductor chips 320 and 330 mounted on the circuit board 100, and a connection portion 310 electrically connecting the plurality of semiconductor chips 320 and 330 with the circuit board 100.

[0087] In order to facilitate explanation of the embodiments, terms related to components included in a semiconductor package are explained, and each of the components involved will be explained later.

[0088] Figure 1a The circuit board 100 shown includes an insulating layer 110, an electrode portion 140, protective layers 120 and 130, and a connecting member 200. For example, the insulating layer 110 is provided with a structure in which first to fifth insulating layers 110b2, 110b1, 110a, 110c1, and 110c2 are sequentially stacked. The upper surface of the first insulating layer 110b2 is set as the upper surface of the insulating layer 110, and the lower surface of the fifth insulating layer 110c2 is set as the lower surface of the insulating layer 110. At this time, the first insulating layer 110b2 and the second insulating layer 110b1 can be referred to as upper insulating layers, and the fourth insulating layer 110c1 and the fifth insulating layer 110c2 can be referred to as lower insulating layers.

[0089] The first protection layer 120 is disposed on the upper surface of the insulating layer 110 , and the second protection layer 130 is disposed on the lower surface of the insulating layer 110 .

[0090] The electrode portion 140 includes a wiring electrode 140 a , a via electrode 140 b , and a bonding portion 150 .

[0091] The wiring electrode 140a includes a first wiring electrode 140a1 arranged on the upper surface of the first insulating layer 110b2, a second wiring electrode 140a2 arranged on the upper surface of the second insulating layer 110b1, a 3-1 wiring electrode 140a3 arranged on the upper surface of the third insulating layer 110a, a 3-2 wiring electrode 140a4 arranged on the lower surface of the third insulating layer 110a, a fourth wiring electrode 140a5 arranged on the lower surface of the fourth insulating layer 110c1, and a fifth wiring electrode 140a6 arranged on the lower surface of the fifth insulating layer 110c2. The via electrode 140b includes a first via electrode 140b1 connecting the first wiring electrode 140a1 and the second wiring electrode 140a2, a second via electrode 140b2 connecting the second wiring electrode 140a2 and the 3-1 wiring electrode 140a3, a third via electrode 140b3 connecting the 3-1 wiring electrode 140a3 and the 3-2 wiring electrode 140a4, a fourth via electrode 140b4 connecting the 3-2 wiring electrode 140a4 and the fourth wiring electrode 140a5, and a fifth via electrode 140b5 connecting the fourth wiring electrode 140a5 and the fifth wiring electrode 140a6.

[0092] In addition, each wiring electrode 140a includes a pad and / or a trace. The trace is used to transmit signals and / or power to the semiconductor device and can be referred to as a circuit pattern. The pad serves as a connecting portion that electrically connects the semiconductor device and the trace or connects the trace provided on each insulating layer. If the width of the trace is made large enough to directly connect the semiconductor device to the trace, the pad may be unnecessary. However, if the width of the trace is too large, there is a problem that the impedance may increase, and there is a problem that the trace cannot be integrated into a limited circuit board area. Therefore, the pad generally has the same conductive function as the trace, but is set to have a wider width than the trace so as to have an additional function of being able to contact the through-electrode or semiconductor device. In addition, Figure 1a A pad of each wiring electrode 140 a may be shown.

[0093] For example, the first wiring electrode 140a1 includes a first pad connected to the first via electrode 140b1 and / or the bonding portion 150. The second wiring electrode 140a2 includes a second pad connected to the first via electrode 140b1 and / or the second via electrode 140b2. The 3-1st wiring electrode 140a3 includes a 3-1st pad connected to the second via electrode 140b2 and / or the third via electrode 140b3 and a 3-2nd pad 140a31 connected to the connecting member 200. The 3-2nd wiring electrode 140a4 includes a 3-2nd pad connected to the third via electrode 140b3 and / or the fourth via electrode 140b4. The fourth wiring electrode 140a5 includes a fourth pad connected to the fourth via electrode 140b4 and / or the fifth via electrode 140b5. The fifth wiring electrode 140a6 includes a fifth pad connected to the fifth via electrode 140b5 and / or the main board of the electronic device.

[0094] In addition, the circuit board 100 includes a bonding portion 150 disposed on the first protective layer 120. The bonding portion 150 includes protruding portions 151b and 152b disposed on the first protective layer 120, and through portions 151a and 152a that pass through the first protective layer 120 and are connected to the pad of the first wiring electrode 140a1. The connecting member 200 may be embedded in the insulating layer 110. According to an embodiment, the connecting member 200 is disposed between the first insulating layer 110b1 and the second insulating layer 110b2, but the position where the connecting member is embedded is not limited thereto, and the connecting member may be embedded in an insulating layer other than the first insulating layer 110b1 and the second insulating layer 110b2.

[0095] The stacked first to fifth insulating layers 110b2, 110b1, 110a, 110c1, and 110c2 may be formed of an insulating material having a function of facilitating processing, reducing the loss of a signal transmitted through the electrode portion 140, or forming a fine interval between the electrode portions 140. In addition, the first to fifth insulating layers 110b2, 110b1, 110a, 110c1, and 110c2 may all be formed of the same insulating material, but are not limited thereto, and at least one insulating layer may be formed of an insulating material different from the other insulating layers. For example, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., may be used, and FR-4, BT (Bismaleimide Triazine), and PID (Photo Imaging Dielectric Resin) may be used.

[0096] For example, the third insulating layer 110a may include a reinforcing member including at least one of glass fiber and GCP (glass core primer). The reinforcing member may increase the rigidity of the insulating layer, thereby preventing the circuit board 100 and / or the semiconductor package from bending in a specific direction. If the insulating layer 110 is bent in a specific direction during the process of forming the circuit board 100, the position accuracy during the process of setting the electrode portion 140 may be reduced, but since the rigidity of the circuit board 100 is improved, this problem can be solved. In addition, even when the semiconductor chips 320 and 330 are mounted on the circuit board 100, problems such as electrical short circuit or open circuit of the semiconductor chips 320 and 330 caused by the warping of the circuit board 100 can be prevented. In addition, the warping problem caused by the thermal cycle occurring during the operation of the semiconductor package can be prevented, and therefore, products such as servers to which the semiconductor package of the embodiment is applied can operate stably, thereby improving the overall reliability of the product.

[0097] according to Figure 1a , the insulating member 110d is disposed in the third insulating layer 110a including the reinforcing member. The insulating member 110d passes through the third insulating layer 110a including the reinforcing member. The insulating member 110d may be provided with a hole-clogging ink, but is not limited thereto. The insulating member 110d is provided to be surrounded by the third via electrode 140b3 passing through the third insulating layer 110a. When the third insulating layer 110a is thicker, the problem that the third via electrode 140b3 passing through the third insulating layer 110a does not densely fill the through hole of the third insulating layer 110a may occur. This problem may cause the pad of each of the 3-1 wiring electrode 140a3 and / or the 3-2 wiring electrode 140a4 to not be plated flatly, or a gap is generated inside the third via electrode 140b3. Therefore, the arrangement of the insulating member 110d can solve the electrical reliability problem and / or mechanical reliability problem that may occur due to the through hole of the third insulating layer 110a not being completely filled. For example, the third insulating layer 110 a may have a thickness in the range of 0.4 T to 1.5 T in order to ensure ease of processing and rigidity.

[0098] For example, at least one of the first insulating layer 110b2, the second insulating layer 110b1, the fourth insulating layer 110c1, and the fifth insulating layer 110c2 may include a filler made of an inorganic material. The filler has a size and / or shape different from that of the reinforcing member included in the third insulating layer 110a. Considering the thermal expansion coefficient, stiffness, etc. of each of the first insulating layer 110b2, the second insulating layer 110b1, the fourth insulating layer 110c1, and the fifth insulating layer 110c2, and in order to solve problems such as light scattering during laser processing for densely arranging the electrode portion 140, the diameter and content of the filler may be adjusted. For example, in order to solve the above-mentioned problems, the diameter of the filler may be applied to 0.1 μm to 5.0 μm, and the content of the filler may be applied to 30 wt% to 40 wt% or 78 wt% to 85 wt%, but is not limited thereto. However, the embodiment is not limited thereto, and the first insulating layer 110 b 2 , the second insulating layer 110 b 1 , the fourth insulating layer 110 c 1 , and the fifth insulating layer 110 c 2 may include a reinforcement member including at least one of glass fiber and GCP (Glass Core Primer).

[0099] The circuit board 100 includes a first protective layer 120 disposed on the upper surface of the first insulating layer 110b2 and a second protective layer 130 disposed on the lower surface of the fifth insulating layer 110c2 to protect its surface. The first protective layer 120 and the second protective layer 130 may be provided with, for example, a photosensitive material and / or a solder resist so as to prevent a short circuit between the connection portion 310 (e.g., solder or wire) when the semiconductor chip is joined to the circuit board 100 and / or the main board is joined to the circuit board 100, while protecting the pad from external moisture or contaminants. In addition, for example, a photosensitive solder resist may be applied. According to the present embodiment, the semiconductor chips 320 and 330 and / or the main board of the electronic device, etc. may have a plurality of terminals for connecting to the circuit board 100 arranged at a high density. In addition, solder may be used when joining a plurality of terminals to the joining portion 150 of the circuit board 100. In this case, when solder is used, a solder short circuit problem may occur between the terminals having a high density. In order to solve this short circuit problem, a solder resist having poor wettability to the solder is provided to prevent the diffusion or movement of the solder, thereby preventing the solder short circuit problem between the terminals. Taking into account the warpage or thermal expansion coefficient of the circuit board 100, the first protective layer 120 and the second protective layer 130 may be provided with different thicknesses. This may vary according to the area and thickness of the circuit board 100, but according to the present embodiment, the thickness of the first protective layer 120 may have a portion that is thicker than the thickness of the second protective layer 130. Here, the portion refers to at least one area of ​​the upper surface of the first protective layer 120, which may mean that the thickness of the first protective layer 120 may be unevenly set, or the thickness of the first protective layer 120 may be uniformly set and thicker than the second protective layer 130.

[0100] Considering the impedance and bending of the circuit board 100 for transmitting signals and power between the semiconductor chips 320 and 330 and the main board of the electronic device, the traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 can be designed in various shapes. The traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 can be designed and arranged to have a width and interval of 2μm to 10μm so as to have high density while considering signals and impedance, and to ensure adhesion with each insulating layer 110 to prevent peeling problems. That is, the traces of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 can be set to have various widths and intervals, from a design in which the traces are set to have a width of 2μm and an interval of 2μm to a design in which the traces are set to have a width of 10μm and an interval of 10μm.

[0101] At this time, the width and spacing of the above-mentioned first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 are too small, and the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4 and 140b5 cannot be arranged to vertically connect the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6. Therefore, the width of the wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 is too narrow to ensure that the positions of the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4 and 140b5 are aligned or the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4 and 140b5 cannot be formed. Here, vertical means the direction in which the first to fifth insulating layers 110b2, 110b1, 110a, 110c1 and 110c2 are stacked, and vertical and perpendicular directions can be used in the same sense. In addition, the same definition applies to the vertical relationship of the components described below. Therefore, in order to ensure the position alignment and placement of the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4 and 140b5, the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 respectively include first to fifth pads. The width of each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, and 140a6 is greater than the width of each trace of the above-mentioned first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, and 140a6 so as to be connected to the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4, and 140b5. For example, each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5, and 140a6 may have a circular structure, and its diameter may be in the range of 30 μm to 100 μm. However, the embodiments are not limited thereto, and depending on technical limitations of the process used to set the first to fifth via electrodes 140b1, 140b2, 140b3, 140b4 and 140b5, the width of each pad of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6 may be the same as the width of each trace of the first to fifth wiring electrodes 140a1, 140a2, 140a3, 140a4, 140a5 and 140a6.

[0102] For example, in order to arrange the first via electrode 140b1, a through hole is processed in a partial area of ​​the first insulating layer 110b2 by laser. At this time, the size of the through hole corresponds to the beam size of the laser. Thereafter, by arranging the pads and traces of the first via electrode 140b1 and the first wiring electrode 140a1 together, productivity and yield can be improved. Therefore, the first via electrode 140b1 may have a lower surface located on the same plane as the upper surface of the pad of the second wiring electrode 140a2. That is, for example, the first via electrode 140b1 may be referred to as a protruding portion in which a portion of the pad of the first wiring electrode 140a1 protrudes toward the pad of the second wiring electrode 140a2. Here, the upper surface of the pad of the second wiring electrode 140a2 does not necessarily mean a flat surface, but should be understood to include a concave or convex surface that may appear according to various processes.

[0103] For example, the upper surface of the second wiring electrode 140a2 in contact with the lower surface of the first via electrode 140b1 has a concave surface. In the process of forming the first via electrode 140b1, if the pad of the second wiring electrode 140a2 is exposed to the air, the surface of the pad of the second wiring electrode 140a2 may be oxidized, or the bonding strength of the pad of the second wiring electrode 140a2 for contacting the surface of the first via electrode 140b1 may be reduced or the impedance may be increased due to the chemical reaction between the pad of the second wiring electrode 140a2 and the first insulating layer 110b2. Therefore, by removing a portion of the surface of the pad of the second wiring electrode 140a2 exposed to the through hole of the first insulating layer 110b2 before setting the first via electrode 140b1, and then setting the first via electrode 140b1, problems such as cracks, peeling, and increased impedance between the pads of the first via electrode 140b1 and the second wiring electrode 140a2 can be prevented. In addition, since the first via electrode 140b1 is integrally provided with the first wiring electrode 140a1, it can be said that it is located on the same plane as the lower surface of the pad of the first wiring electrode 140a1. Since the width of the first via electrode 140b1 is smaller than the width of the pad of the first wiring electrode 140a1, it can be referred to as the first via electrode 140b1 as described above in order to distinguish it from the pad of the first wiring electrode 140a1. The second to fifth via electrodes 140b2, 140b3, 140b4 and 140b5 can be referred to in the same manner as the first via electrode 140b1 described above.

[0104] The connection member 200 is used to electrically connect the plurality of semiconductor chips 320 and 330 to each other. Figure 1aIn the figure, two semiconductor chips 320 and 330 are shown as examples, but the present invention is not limited to this, and a larger number of semiconductor chips can be installed. In addition, the connecting member 200 is also shown as electrically connecting two chips, but it is not limited to this, and a larger number of semiconductor chips can be connected. In addition, the semiconductor chips 320 and 330 here can be logic chips such as memory, processor, GPU, etc., and can be small chips divided by the function of each logic chip.

[0105] according to Figure 1a , the connection member 200 includes a plurality of pads 210 and is embedded and disposed in the circuit board 100. The plurality of pads 210 of the connection member 200 are electrically connected to the electrode portion 140 of the circuit board 100, and the electrode portion 140 of the circuit board 100 connected to the plurality of pads 210 of the connection member 200 is electrically connected to the terminals 325 and 335 of the semiconductor chips 320 and 330 through the bonding portion 150, thereby performing a communication function between the semiconductor chips 320 and 330.

[0106] exist Figure 1a In the embodiment, the connection member 200 is shown as having a structure embedded and disposed in the circuit board 100, but is not limited thereto, and may also be disposed on the circuit board 100 without being embedded. That is, the connection member 200 may be embedded in the circuit board 100 to make the circuit board 100 thinner, but the connection member 200 may be placed so as not to be buried in the circuit board 100, so as to solve problems such as height deviation between the joint parts 150 of the circuit board 100 and errors in the process of arranging the connection member 200 in the correct position when burying the connection member. In this case, although not shown, a molding member (not shown) may be disposed on the circuit board 100, and the connection member 200 may be embedded in the molding member. The molding member (not shown) may be made of a resin such as EMC (epoxy molding compound), and in this case, the connection member 200 may be electrically connected to the semiconductor chips 320 and 330 by passing through electrodes of the molding member.

[0107] The connecting member 200 is composed of at least one material selected from the group consisting of silicon, organic substances and glass, and can be disposed on the circuit board 100 and can be used as an interposer. When the connecting member 200 is used as an interposer, the pitch of the connecting member is narrower than the pitch of the electrode portion 140 of the circuit board 100 to provide a finer pattern than the circuit board 100, and a buffering function of the pattern can be performed between the pattern of the semiconductor chips 320 and 330 and the pattern of the circuit board 100. Here, the pattern can refer to not only the shape of the wire or terminal for electrical connection (such as the terminal, wiring electrode and via electrode of the semiconductor package, including the electrode portion 140 of the circuit board 100, the terminals 325 and 335 of the semiconductor chips 320 and 330 and the pad 210 of the connecting member 200), but also the size, width and spacing of the wire or terminal for electrical connection. In addition, in Figure 1a In the embodiment, the connection member 200 is provided to have a width smaller than the sum of the widths of each of the semiconductor chips 320 and 330 in the horizontal direction, but is not limited thereto, and the connection member 200 may also have a wide width so that all the semiconductor chips 320 and 330 may be provided on the connection member 200. When the connection member 200 is made of silicon and has a wide width so that all the semiconductor chips 320 and 330 may be provided, the connection member 200 may be referred to as a silicon interposer.

[0108] according to Figure 1c , which is Figure 1a In an enlarged view of an area of ​​the circuit board 100, the bonding portion 150 is disposed on the first protective layer 120, and the bonding portion 150 includes protruding portions 151b and 152b disposed on the first protective layer 120 and through portions 151a and 152a that pass through the first protective layer 120 and directly contact the pads 141a and 142a of the first wiring electrode 140a1 disposed on the first insulating layer 110b2 of the circuit board 100. The bonding portion 150 includes the protruding portions 151b and 152b disposed on the first protective layer 120 to reduce the volume of solder and prevent electrical short circuits between two adjacent bonding portions 150 by using thermocompression bonding. In addition, the bonding portion 150 includes the through portions 151a and 152a that directly contact the pads 141a and 142a of the first wiring electrode 140a1 on the first insulating layer 110b2 to connect the above-mentioned protruding portions 151b and 152b with the circuit board 100.

[0109] At this time, the pads 141a and 142a of the first wiring electrode 140a1 on the first insulating layer 110b2 may be formed by forming a first via electrode 140b1 that passes through a portion of the first insulating layer 110b2 to have a fine pattern interval and then performing a polishing process. However, when the polishing process is performed, there may be a reduction in yield due to problems such as warping and wrinkling of the circuit board 100, and in particular, during the process of connecting the through portions 151a and 152a of the bonding portion 150 to the circuit board 100, there is a problem that it is difficult to ensure positional accuracy. Therefore, in the present invention, the technical concept and means are described by an embodiment within the scope of not performing a polishing process.

[0110] refer to Figure 1a , the bonding portion 150 may include a first bonding portion 151 vertically overlapping with the connection member 200 and a second bonding portion 152 that does not vertically overlap. As described above, since the connection member 200 has a finer electrode pattern than the electrode portion 140 of the circuit board 100, the first bonding portion 151 has a finer electrode pattern than the second bonding portion 152. Specifically, the first bonding portion 151 located between the connection member 200 and the semiconductor chips 320 and 330 in the bonding portion 150 has a finer electrode pattern than the second bonding portion 152. For example, referring to Figure 1a, the bonding portion 150 includes a first bonding portion 151 and a second bonding portion 152, and the first bonding portion 151 has a finer pattern than the second bonding portion 152. Similarly, the first wiring electrode 140a1 and the first via electrode 140b1 connected to the electrode portion 140 of the bonding portion 150 also include a first portion 141 and a second portion 142. For example, the first wiring electrode 140a1 includes a first portion 141a overlapping with the connection member 200 in the vertical direction and a second portion 142a not overlapping with the first portion 141a in the vertical direction, and the first portion 141a of the first wiring electrode 140a1 may have a finer pattern than the second portion 142a of the first wiring electrode 140a1. In addition, the first via electrode 140b1 may similarly include a first portion 141b and a second portion 142b, and the first portion 141b may have a finer pattern than the second portion 142b. Therefore, by performing a buffering function for electrically connecting the pattern of the circuit board 100 and the connection member 200, the reliability of electrical connection between the connection member 200, the circuit board 100, and the semiconductor chips 320 and 330 can be improved. In addition, according to the embodiment, the 3-1st wiring electrode 140a3, the 3-2nd wiring electrode 140a4, the fourth wiring electrode 140a5, the fifth wiring electrode 140a6, the second via electrode 140b2, the third via electrode 140b3, the fourth via electrode 140b4, and the fifth via electrode 140b5 are located under the connection member 200 (for example, under the pad of the connection member), and thus may not be connected to the fine pattern of the connection member 200. Therefore, each of the 3-1st wiring electrode 140a3, the 3-2nd wiring electrode 140a4, the fourth wiring electrode 140a5, the fifth wiring electrode 140a6, the second via electrode 140b2, the third via electrode 140b3, the fourth via electrode 140b4, and the fifth via electrode 140b5 may have the same pattern fineness regardless of whether they overlap the connection member 200 in the vertical direction. Hereinafter, the first portion 141 of the electrode portion 140 refers to the electrode portion 140 located between the connection member 200 and the semiconductor chips 320 and 330 and vertically overlaps the connection member 200. In addition, the second portion 142 of the electrode portion 140 refers to the electrode portion 140 located between the connection member 200 and the semiconductor chips 320 and 330 and does not vertically overlap the connection member 200 but horizontally overlaps the first portion 141.

[0111] refer to Figure 1a, the size of the first bonding portion 151 is depicted as being smaller than the size of the second bonding portion 152. This may be because the density of the first bonding portion 151 to be connected to the connection member 200 is higher than the density of the second bonding portion 152. Therefore, by setting the size of the first bonding portion 151 to be smaller than the size of the second bonding portion 152, the reliability of electrical connection between the connection member 200 and the semiconductor chips 320 and 330 can be improved. Figure 1b The upper surfaces of the first joint portion 151 and the second joint portion 152 of the circuit board 100 are shown. For example, Figure 1b An upper surface of the protruding portion 151 b of the first engaging portion 151 and an upper surface of the protruding portion 152 b of the second engaging portion 152 are shown.

[0112] like Figure 1b As shown, the size and interval of the first bonding portion 151 are smaller than the size and interval of the second bonding portion 152. The first bonding portion 151 connects the connection member 200 and the semiconductor chips 320 and 330 to each other. Therefore, the first bonding portion 151 is arranged with a smaller size and interval than the second bonding portion 152 of the bonding portion to correspond to the fine pattern of the pad 210 of the connection member 200 and the terminals 325 and 335 of the semiconductor chips 320 and 330 in the vertical overlap region. At this time, a part of the first bonding portion 151 is arranged between the first semiconductor chip 320 and the connection member 200, and the rest of the first bonding portion 151 is arranged between the second semiconductor chip 330 and the connection member 200. In addition, a part of the second bonding portion 152 overlaps with the first semiconductor chip 320 in the vertical direction, but does not overlap with the connection member 200 in the vertical direction, and the rest of the second bonding portion 152 overlaps with the second semiconductor chip 330 in the vertical direction, but does not overlap with the connection member 200 in the vertical direction.

[0113] refer to Figure 1a, the width of the through portions 151a and 152a of the bonding portion 150 gradually narrows toward the connecting member 200, and passes through the first protective layer 120 to contact the pads 141a and 142a of the first wiring electrode 140a1. The process of processing the first through hole 120a and the second through hole 120b in the first protective layer 120 is performed so as to arrange the first bonding portion 151 and the second bonding portion 152. Recently, in the trend of increasing the number of pads 210 of the connecting member 200, increasing the number of terminals 325 and 335 of the semiconductor chips 320 and 330, or increasing the number of semiconductor chips 320 and 330 to be connected, the first through hole 120a may be required to have a width of 20μm or less, and the second through hole 120b may be required to have a width greater than 30μm. At this time, the first protective layer 120 is formed of a photosensitive material, and therefore, in the conventional technology, the first protective layer 120 is exposed and developed to form a through hole. However, due to the limitation of the resolution of the exposure process, it is difficult to process the width of the first through hole 120a to be less than 20 μm. Therefore, in the conventional technology, the first through hole 120a is formed using a laser process. When both the first through hole 120a and the second through hole 120b are processed by the laser process, such as wrinkles on the surface of the circuit board 100 during processing due to the stress caused by the laser, the yield may be significantly reduced. Therefore, in the conventional technology, the first through hole 120a is processed by the laser process, and the second through hole 120b is formed by the exposure process. However, in this case, the width of the first through hole 120a and the width of the second through hole 120b differ, and therefore, in the plating process for setting the first bonding portion 151 and the second bonding portion 152, a plating deviation occurs due to the difference in the current intensity applied to the first through hole 120a and the second through hole 120b, so a height deviation occurs between the first bonding portion 151 and the second bonding portion 152.

[0114] In addition, when the first through hole 120a is formed using a laser process, since the laser beam has a Gaussian distribution, the inner wall of the first through hole 120a has a vertically extending portion and a curved portion whose width is narrowed in a portion adjacent to the pads 141a and 142a of the first wiring electrode 140a1. Figure 2aAs shown, in the conventional art, a through hole is formed in the protective layer 12 by a laser process so that the width of the bonding portion 20 is minimized. However, when the through hole is formed in the protective layer 12 by a laser process, since the laser beam has the characteristics of Gaussian distribution, the through hole includes a curved portion whose width is narrowed in a portion adjacent to the pad 40. Therefore, the through portion 21 of the bonding portion 20 provided in the through hole of the protective layer 12 has a curved portion 21a whose width is rapidly narrowed in a portion adjacent to the pad 40. At this time, since the width of the bonding portion that does not vertically overlap with the connecting member 200 is greater than the width of the bonding portion that vertically overlaps with the connecting member 200, even if it includes a curved portion, no major problem in terms of physical reliability and / or electrical reliability occurs. However, since the bonding portion overlapping the connection member 200 in the vertical direction has a relatively small width, due to the thermal cycle of the protective layer 12 caused by the heat generated during the operation of the semiconductor chips 320 and 330 or in the subsequent process, stress may be applied to the bent portion 21a, and therefore, cracks may occur at the interface between the through portion 21 of the bonding portion 20 and the pad 40, or a reliability problem that the through portion 21 of the bonding portion 20 is peeled off from the pad 40 may occur. In order to solve this problem, when the width of the bonding portion 20 is increased, it may be difficult to adjust the pitch between the plurality of bonding portions to be less than 40 μm, and therefore, the area of ​​the semiconductor package may increase, and therefore, it may be difficult to reduce the thickness. In addition, when a through hole is formed in the protective layer 12 by a laser process, the processing time may increase, which may reduce productivity. In addition, when a through hole having a relatively small width is formed by a laser process, it may be difficult to align the laser beam to an accurate position, and therefore, defects such as misalignment of the position of the through hole may occur, which may reduce product yield.

[0115] Here, the pitch refers to the distance between the center lines of each of the plurality of first bonding portions 151 of the bonding portion 150, and may be defined as Figure 1c The horizontal distance W6 is shown. A manufacturing method for achieving a fine pitch of the plurality of first bonding portions 151 of the bonding portion 150 and improving reliability according to an embodiment will be described below.

[0116] on the contrary, Figure 1a The embodiment shown is arranged so that the inner wall of the first through hole 120a is vertical. That is, the first through hole 120a of the embodiment has a width of 20 μm or less, and the inner wall of the first through hole 120a does not include a curved portion as in the conventional art. Thus, even if the width of the first through hole 120a is thinned, the embodiment can increase the width of the first through hole 120a in the area closest to the pads 141a and 142a to ensure the contact area between the pads 141a and 142a and the bonding portion 150, thereby improving adhesion, compared with the conventional art.

[0117] on the contrary, Figure 1a The embodiment shown in is arranged so that the inner wall of the first through hole 120a is vertical. Specifically, the inner wall of the first through hole 120a of the first protective layer 120 arranged on the pads 141a and 142a of the first wiring electrode 140a1 is arranged to be perpendicular to the upper surface of the pads 141a and 142a. A portion of the upper surface of the pads 141a and 142a may be in contact with the lower surface of the first protective layer 120, and the inner wall of the first through hole 120a may be arranged to be perpendicular to the portion of the upper surface of the pads 141a and 142a in contact with the lower surface of the above-mentioned first protective layer 120. Here, vertical not only means that the angle formed by the inner wall of the first through hole 120a and the above-mentioned portion of the upper surface of the pads 141a and 142a is 90° (degrees), and considering the process error, etc., the inclination angle within the range of 85° (degrees) to 90° (degrees) should be considered to be vertical. Thereby, it is possible to prevent a problem in which cracks occur at the interface between the first bonding portion 151 and the pads 141 a and 142 a .

[0118] refer to Figure 1c , the widths of the first through hole 120a and the second through hole 120b of the first protective layer 120 are formed to be the same. Thus, the same current intensity can be applied in the plating process, so that the height difference between the first protruding portion 151b of the first bonding portion 151 and the second protruding portion 152b of the second bonding portion 152 can be reduced, and when the semiconductor chips 320 and 330 are mounted in a subsequent process, the semiconductor chips 320 and 330 can be mounted with high reliability without tilting.

[0119] In addition, for example, the first protrusion portion 151b and the second protrusion portion 152b may have different widths. Figure 1c As shown, the size and interval of the second protruding portion 152b are larger than the size and interval of the first protruding portion 151b located in the area where the connecting member 200 is provided. Therefore, the allowable error of the position alignment can be ensured to improve the yield during the installation of the semiconductor chips 320 and 330, and the impedance can be reduced by setting the second protruding portion 152b to a large size. In addition, although not shown, a plurality of second through portions 152a connected to one second protruding portion 152b can be arranged at intervals in the horizontal direction to ensure a certain degree of uniformity in the density of the first through hole 120a and the second through hole 120b during the plating process of the first bonding portion 151 and the second bonding portion 152, and improve the impedance of the second bonding portion 152.

[0120] according to Figure 1cIn the embodiment shown, the width W1 of the first through portion 151a may be in the range of 12 μm to 20 μm. If the width W1 of the first through portion 151a is less than 12 μm, the allowable current of the signal transmitted through the first through portion 151a may be reduced. In addition, if the width W1 of the first through portion 151a is less than 12 μm, the impedance of the first through portion 151a may increase, and as the contact area with the pad 141a of the first wiring electrode 140a1 decreases, a mechanical reliability problem may occur in which the first bonding portion 151 is peeled off from the pad 141 of the first wiring electrode 140a1. In addition, if the width W1 of the first through portion 151a of the first bonding portion 151 is greater than 20 μm, it may be difficult to arrange all of the plurality of first through portions 151a vertically overlapping the connection member 200 in a limited space. That is, if the width W1 of the first through portion 151 a is greater than 20 μm, it may be difficult to adjust the pitch between the plurality of first bonding portions 151 to be 40 μm or less, and thus the circuit integration degree may be reduced.

[0121] Meanwhile, the width W2 of the second through-portion 152a may correspond to the width W1 of the first through-portion 151a. For example, the width W1 of the first through-portion 151a may be equal to the width W2 of the second through-portion 152a.

[0122] Each of the first through portion 151a and the second through portion 152a may have a maximum width and a minimum width. The maximum width may represent the width of the region with the maximum width in the entire region in the thickness direction of each of the first through portion 151a and the second through portion 152a. In addition, the minimum width may represent the width of the region with the minimum width in the entire region in the thickness direction of each of the first through portion 151a and the second through portion 152a. In addition, each maximum width may be implemented as less than 105% of the minimum width. Hereinafter, it is described that the maximum width is the upper surface width of each through portion, and the minimum width is the lower surface width of each through portion. However, the embodiment is not limited thereto, and each through portion may have a maximum width and a minimum width in another region between the upper surface and the lower surface.

[0123] The first through portion 151a may include an upper surface and a lower surface. The upper surface and the lower surface of the first through portion 151a may have corresponding widths or the same width. For example, the upper surface width of the first through portion 151a may correspond to or be the same as the lower surface width of the first through portion 151a. For example, the upper surface width of the first through portion 151a may be implemented as less than 105% of the lower surface width of the first through portion 151a. Similarly, the upper surface width of the second through portion 152a may be implemented as less than 105% of the lower surface width of the second through portion 152a.

[0124] In the embodiment, the first through portion 151a and the second through portion 152a of the first bonding portion 151 and the second bonding portion 152 are disposed in the first through hole 120a and the second through hole 120b of the first protective layer 120 formed using the dry film pattern. Therefore, according to the shape of the dry film pattern, as described above, the inner wall slope of the first through portion 151a and / or the second through portion 152a may be close to vertical. That is, the first through portion 151a may have an inner wall slope close to vertical while having a width of 20 μm or less, and the inner wall slope of the second through portion 151b may also be close to vertical.

[0125] The width W3 of the first protruding portion 151b may be in the range of 29 μm to 34 μm. If the width W3 of the first protruding portion 151b is less than 29 μm, when the semiconductor chips 320 and 330 are mounted, the alignment error of the position of the semiconductor chips 320 and 330 may be exceeded, so the semiconductor chips 320 and 330 may not be stably bonded to the first protruding portion 151b. For example, if the width W3 of the first protruding portion 151b is less than 29 μm, the semiconductor chips 320 and 330 may not be stably mounted on the first protruding portion 151b, so the problem of peeling from the first protruding portion 151b may occur. In addition, if the width W3 of the first protruding portion 151b exceeds 34 μm, it may be difficult to achieve a pitch of less than 40 μm between the plurality of first bonding portions 151. Thus, the number of the first protruding portions 151b may not be ensured, and a smooth electrical connection between the semiconductor chips 320 and 330 and the connecting member 200 may be difficult.

[0126] Therefore, the first protruding portion 151b can be arranged on the first through portion 151a with a predetermined width W4 along the circumferential direction of the first through portion 151a. That is, the first protruding portion 151b can be arranged on the first through portion 151a with a width W4 in the range of 5μm to 10μm along the circumferential direction of the first through portion 151a. If the predetermined width W4 of the first protruding portion 151b is less than 5μm, it may be difficult to ensure the alignment of the position in the patterning of placing the first bonding portion 151 on the first through hole 120a of the first protective layer 120. In addition, if the width W4 of the first protruding portion 151b exceeds 10μm, it may be difficult to achieve a pitch of 40μm or less between the plurality of first bonding portions 151 as described above. Thus, it may be difficult to ensure the number of first protruding portions 151b, and a smooth electrical connection between the semiconductor chips 320 and 330 and the connecting member 200 may be difficult.

[0127] The interval W5 between the protruding portions of two adjacent first bonding portions in the plurality of first bonding portions 151 of the embodiment may be 5 μm to 11 μm. If the interval W5 between the protruding portions of two adjacent first bonding portions is less than 5 μm, the problem of electrical short circuit of the adjacent first bonding portions due to process errors in the process of forming the first bonding portions 151 may occur. In addition, if the interval W5 between the protruding portions of two adjacent first bonding portions exceeds 11 μm, it may be difficult to achieve a pitch of less than 40 μm between the plurality of first bonding portions 151. Therefore, it may be difficult to ensure the number of first protruding portions 151b, and a smooth electrical connection between the semiconductor chips 320 and 330 and the connecting member 200 may be difficult.

[0128] Therefore, the horizontal distance W6 between the centers of the first through-parts 151a of two adjacent first bonding parts 151 of the multiple first bonding parts 151 of the embodiment may be 40 μm or less. At this time, the horizontal distance W6 may represent the pitch between the multiple first bonding parts 151 as described above, and may correspond to W1+W4+W5. The embodiment may make the mutual communication between the semiconductor chips 320 and 330 smoother by arranging a large number of multiple first bonding parts 151 in a limited space. Therefore, electronic products such as servers to which semiconductor packaging is applied can process a large amount of data, thereby realizing key technical interconnectivity with the above-mentioned electronic products.

[0129] In addition, according to Figure 1c In the embodiment shown, the first via electrode 140b1 includes a 1-1 via electrode 141b and a 1-2 via electrode 142b. The 1-1 via electrode 141b has a smaller width and a shorter vertical length than the 1-2 via electrode 142b. That is, since the upper surface of the connection member 200 is positioned higher than the second wiring electrode 140a2, the vertical length of the 1-1 via electrode 141b can be shortened, thereby shortening the signal transmission length and reducing the length impedance, thereby facilitating the electrical connection between the semiconductor devices 320 and 330 and the connection member 200.

[0130] According to an embodiment, the first through hole 120a is formed using a dry film pattern. In addition, the same method as the first through hole 120a can be applied to form the second through hole 120b. In addition, the embodiment can allow the first through hole 120a and the second through hole 120b to have the same width. Thereafter, the first bonding portion 151 and the second bonding portion 152 are formed by a plating process. At this time, by controlling the width and / or density of the first through hole 120a and the second through hole 120b, the height deviation of the first bonding portion 151 and the second bonding portion 152 can be reduced during the plating process. In addition, by forming the first through hole 120a and the second through hole 120b using a dry film pattern, the pitch of the first bonding portion 151 and the second bonding portion 152 can be finely realized.

[0131] refer to Figure 1d , the first protective layer 120 includes a filler. The filler may be provided as an inorganic particle, and may be provided as a silica filler as an example. When the first through hole 120a and the second through hole 120b are realized by a conventional laser process and / or an exposure process, the filler may be exposed to the first through hole 120a and the second through hole 120b. Therefore, when the first bonding portion 151 and the second bonding portion 152 are set by a subsequent plating process, the filler exposed in the first through hole 120a and the second through hole 120b contacts the first through portion 151a and the second through portion 152a. The first bonding portion 151 and the second bonding portion 152 including the first through portion 151a and the second through portion 152a are provided with a material capable of performing a conductive function. For example, a metal material may be provided, and specifically, copper metal may be used. Therefore, the filler exposed to the first through hole 120a and the second through hole 120b and the first through portion 151a and the second through portion 152a may not have good mutual adhesion, and may have the effect of partially reducing the width of the first through portion 151a and the second through portion 152a. In addition, problems such as peeling or cracking due to differences in thermal expansion coefficients (thermal expansion rate coefficients) may occur.

[0132] Therefore, according to the present embodiment, a dry film pattern is provided on the pads 141a and 142a of the first wiring electrode 140a1 to correspond to the pitch W6 of the plurality of first bonding portions 151 and the width of the first through portion 151a, and a first protective layer 120 is provided on the first insulating layer 110b2 to cover the dry film pattern. Thereafter, the first protective layer 120 is etched using chemical liquid and / or plasma to reduce the thickness of the first protective layer 120, thereby exposing the dry film pattern. Thereafter, by separating the dry film pattern, the first through hole 120a and the second through hole 120b are formed.

[0133] In the case of implementing the first through hole 120a and the second through hole 120b using a dry film pattern according to the present embodiment, since the dry film pattern is preferentially provided, the filler of the first protective layer 120 does not penetrate into the dry film pattern. Therefore, the filler of the first protective layer 120 is not exposed in the first through hole 120a and the second through hole 120b, and thus, the contact between the filler and the first through portion 151a and the second through portion 152a can be prevented, so that the electrical reliability and / or mechanical reliability can be significantly improved. In addition, since the filler of the first protective layer 120 is uniformly distributed, the thermal expansion coefficient of the first protective layer 120 can also be uniformly distributed. That is, since some areas of the first protrusion 151b and the second protrusion 152b overlap vertically with the filler of the first protective layer 120, and the filler of the first protective layer 120 vertically overlapped with some areas of the first protrusion 151b and the second protrusion 152b does not contact the first through-portion 151a and the second through-portion 152a, it is possible to suppress the occurrence of peeling and cracking between the first protrusion 151b and the second protrusion 152b and the first protective layer 120 due to the shrinkage and expansion caused by the thermal cycle of the first protective layer 120, and the electrical reliability and / or mechanical reliability can be greatly improved as described above. In addition, in order to further improve the above effect, the filler may include fillers having various different diameters, and the diameter of some fillers may be smaller than the predetermined width W4 of the first protrusion 151b provided on the first through-portion 151a in the circumferential direction of the first through-portion 151a.

[0134] In addition, in the process of etching and thinning the first protective layer 120, the surface roughness of the first protective layer 120 may increase. Therefore, in the subsequent process of setting the first bonding portion 151 and the second bonding portion 152, since the first protruding portion 151b and the second protruding portion 152b are in contact with the above-mentioned surface of the first protective layer 120, the contact area can be increased, thereby improving the bonding strength. Therefore, it is possible to prevent the first bonding portion 151 and the second bonding portion 152 from peeling or cracking due to the stress caused by the contraction and / or expansion of the first protective layer 120 through thermal cycles.

[0135] In addition, the surface roughness of the first protective layer 120 and the surface roughness of the first through hole 120a and the second through hole 120b may be different from each other. Specifically, through the above process, the inner surface of the first protective layer 120 forming the first through hole 120a and the second through hole 120b has the same roughness as the side surface roughness of the dry film pattern. During the subsequent process, the surface roughness of the first protective layer 120 increases due to etching the first protective layer 120 by chemical liquid and / or plasma, but the change in roughness does not occur on the inner surface of the first protective layer 120 forming the first through hole 120a and the second through hole 120b. Therefore, the surface roughness of the first protective layer 120 is different from the roughness of the first through hole 120a and the second through hole 120b. Therefore, the width of the first through portion 151a and the second through portion 152a can be uniformly provided, while improving the bonding strength between the first protruding portion 151b and the second protruding portion 152b and the first protective layer 120, and electrical adverse effects such as signal loss can be improved. Here, the roughness of the first through hole 120 a and the second through hole 120 b and the roughness of the inner surface of the first protective layer 120 refer to each other.

[0136] At this time, refer to Figure 2b In the conventional technology, a through hole is formed in the protective layer 20 through an exposure and development process, or a through hole is formed in the protective layer 20 through a laser process.

[0137] refer to Figure 2b (a), in the first conventional technology, a through hole is formed by exposing and developing the protective layer 12. However, due to the limitation of the resolution of the exposure process, the width W6 of the through hole passing through the first protective layer 12 exceeds 20 μm, and further exceeds 35 μm. Therefore, when a through hole is formed in the protective layer 12 using the exposure and development process, it is difficult to refine the width and interval of the bonding portion 20, and further, it is difficult to refine the pitch between a plurality of bonding portions disposed adjacent to each other.

[0138] In addition, refer to Figure 2b (b), in the second conventional technology, a through hole is formed through the protective layer 12 by a laser process, and therefore, the width W1 of the through hole is set to be less than 20 μm. However, in the second conventional technology, a through hole is provided in the protective layer 12 by a laser process and / or an exposure process, and the through portion 21 of the bonding portion 20 may be provided in the through hole. Therefore, since the through portion 21 in the second conventional technology includes a bottleneck portion (or a bent portion) having a width difference in the thickness direction, the bonding force between the through portion 21 at the bottleneck portion and the pad 40 may be reduced. In addition, due to various factors (e.g., thermal stress), cracks may occur in the lower region of the through portion 21. Therefore, according to Figure 2bIn the second conventional technology shown in (b), the through portion 21 may include a first metal layer 21-1 and a second metal layer 21-2 disposed on the first metal layer 21-1. At this time, the pad 40 may include a recessed portion 40C disposed on the upper surface so as to dispose the second metal layer 21-2, and the recessed portion may mean a crack. That is, since the contact area between the bonding portion 20 and the pad 40 at the bottleneck portion is reduced, the bonding force is reduced, and in order to compensate for this, the recessed portion 40C may be filled with the first metal layer 21-1 of the through portion 21. At this time, since the through portion 21 has a bottleneck portion, the through portion 21 must have a plurality of metal materials including different metal materials, so the manufacturing process may be complicated or the manufacturing cost may increase.

[0139] On the contrary, the embodiment may allow the first through portion 151a and the second through portion 152a to have a width of 20 μm or less, and the upper surface and the lower surface of each of the first through portion 151a and the second through portion 152a to have a width corresponding to each other. Therefore, even if the process of forming the concave portion 40C and the process of forming the first metal layer and the second metal layer are omitted, the embodiment may maintain the bonding strength of the first through portion 151a and the second through portion 152a, and thus the manufacturing cost may be reduced. However, the embodiment is not limited thereto.

[0140] refer to Figure 3 In order to further improve the bonding strength of the first through-portion 151a and the second through-portion 152a, a concave portion 40C may be implemented in the pads 141a and 142a, and each of the first through-portion 151a and the second through-portion 152a may be implemented to include first metal layers 151a1 and 152a1 filling the concave portion 40C. In addition, each of the first through-portion 151a and the second through-portion 152a may be implemented to include second metal layers 151a2 and 152a2 disposed on the first metal layers 151a1 and 152a1.

[0141] For example, the second metal layers 151a2 and 152a2 may be solid metals, and may specifically include first metal layers 151a1 and 152a1 containing nickel and second metal layers 151a2 and 152a2 containing a metal material other than nickel. In the process of disposing the first bonding portion 151 and the second bonding portion 152 on the pads 141a and 142a of the first wiring electrode 140a1, if the upper surface of the pads 141a and 142a of the first wiring electrode 140a1 is partially exposed from the first protective layer 120, oxidation may occur. As a result, the bonding strength between the pads 141a and 142a of the first wiring electrode 140a1 and the first bonding portion 151 and the second bonding portion 152 may be reduced, thereby causing cracks or peeling, or the electrical characteristics may be reduced due to the oxidized surfaces of the pads 141a and 142a. In addition, when the width of the first through portion 151a and the second through portion 152a is less than 30 μm, the problem of peeling between the pads 141a and 142a of the first wiring electrode 140a1 and the first bonding portion 151 and the second bonding portion 152 due to thermal stress such as contraction and / or expansion of the first protective layer 120 can be prevented.

[0142] Figure 4a is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 4b yes Figure 4a An enlarged view of a partial area R1, Figure 4c is a cross-sectional view for explaining the surface roughness and structure of the first insulating layer 110b2 according to the second embodiment.

[0143] In the following, reference will be made to Figures 4a to 4c A semiconductor package according to a second embodiment is described. In the semiconductor package of the second embodiment, components substantially the same as those of the semiconductor package of the first embodiment are given the same reference numerals.

[0144] refer to Figures 4a to 4c Compared with the circuit board 100 according to the first embodiment, the circuit board 1000 according to the second embodiment has a difference in the shape of the first via electrode 1140b. Figure 1aThe first via electrode 140b of the circuit board 100 has an inclined side surface structure, and its width gradually narrows from the upper surface to the lower surface of the circuit board 100, but the side surface of the first via electrode 1140b of the circuit board 1000 according to the second embodiment has a vertical side surface structure. That is, the inclination angle of the first through portion 151a and the second through portion 152a is set to be the same as the inclination angle of the first via electrode 1140b. Specifically, similar to the first bonding portion 151 and the second bonding portion 152, the first via electrode 1140b according to the present embodiment includes a 1-1 via electrode 1141b and a 1-2 via electrode 1142b vertically overlapped with the connecting member 200. As described above, the pad 210 of the connecting member 200 has a finer pitch than the pitch of the pad 143a of the second wiring electrode 140a2 for electrical connection between the semiconductor devices 320 and 330. Therefore, in the process for setting the pads 1141a and 1142a of the first wiring electrode, it is difficult to finely set the pitch of the pads 1141a and 1142a using processing by a conventional laser process. In addition, when the first insulating layer 110b2 is set as an insulating layer including an inorganic filler such as ABF and a through hole is formed in the first insulating layer 110b2 by a laser process, the inorganic filler included in the first insulating layer 110b2 is exposed in the through hole, so the side surface of the first via electrode 1141b and 1142b may have a concave portion corresponding to the exposed inorganic filler. Therefore, the bonding strength between the first via electrode 1141b and 1142b and the first insulating layer 110b2 is reduced, and there are electrical adverse effects such as signal loss, and problems such as difficulty in finely setting the pitch of the pads 1141a and 1142a. Therefore, according to the second embodiment, the above problem can be solved by setting the inclination angle of the first via electrodes 1141 b and 1142 b to have the same inclination angle as the side surfaces of the first through portion 151 a and the second through portion 152 a .

[0145] According to the present embodiment, the dry film pattern is disposed on the pad 143a of the second wiring electrode 140a2 and the pad 210 of the connecting member 200 to correspond to the pitch of the plurality of pads 1141a and 1142a of the first wiring electrode and the first via electrodes 1141b and 1142b. Thereafter, the first insulating layer 110b2 is disposed to cover the dry film pattern. Thereafter, the first insulating layer 110b2 is etched using a chemical liquid and / or plasma to reduce the thickness of the first insulating layer 110b2, thereby exposing the dry film pattern. Thereafter, by separating the dry film pattern, a through hole in which the first via electrodes 1141b and 1142b are disposed is formed in the first insulating layer 110b2, and thereafter, the first via electrodes 1141b and 1142b and the pads 1141a and 1142a are disposed at a desired pitch.

[0146] refer to Figure 4b , the width of the 1-1 via electrode 1141b may correspond to the width W1 of the first through portion 151a of the first bonding portion 151. In addition, the width of the 1-1 via electrode 1141b in the horizontal direction may be in the range of 12 μm to 20 μm. If the width of the 1-1 via electrode 1141b is less than 12 μm, the allowable current of the signal transmitted through the 1-1 via electrode 1141b may decrease or the impedance may increase. In addition, if the width W1 of the 1-1 via electrode 1141b is greater than 20 μm, it may be difficult to refine the pitch of the pad 1141a. In addition, the widths of the 1-1 via electrode 1141b and the 1-2 via electrode 1142b may be the same. That is, the pitch of the pads 1141a and 1142a may be more easily refined. In addition, although not shown, by providing a plurality of 1-2 th via electrodes 1142 b connected to one pad 1142 a so as to be spaced apart in the horizontal direction, impedance may be improved.

[0147] The width of the pad 1141a may be in the range of 29 μm to 34 μm. If the width of the pad 1141a is less than 29 μm, the contact area with the first through portion 151a of the first bonding portion 151 is reduced, and thus the bonding strength may be deteriorated. Therefore, peeling between the first bonding portion 151 and the pad 1141a may occur. In addition, due to process deviations in the process of forming the pad 1141a, at least a portion of the 1-1 via electrode 1141b may not overlap with the pad 1141a in the vertical direction, which may cause electrical reliability and / or mechanical reliability problems. In addition, if the width of the pad 1141a exceeds 34 μm, the effect of improving the position alignment with the first bonding portion 151 and more easily adjusting the pitch of the first bonding portion 151 to the target value may be insufficient.

[0148] In addition, refer to Figure 4b , the interval between the plurality of adjacent pads 1141a and 1142a may be 5 μm to 11 μm. Therefore, the horizontal distance W6 between the centers of the plurality of adjacent pads 1141a and 1142a may be 40 μm or less. Figure 4b In FIG. 1 , the horizontal distance W6 between the centers of the pads 1141a is defined, but it is not limited thereto and can also be understood as the horizontal distance between the centers of the pads 1142a and 1141a. Figure 4b , the 1-1 via electrode 1141a and the first through portion 151a are aligned with each other, and the 1-2 via electrode 1142a and the second through portion 152a are aligned with each other. This prevents voltage drop. However, due to process errors, there may be an alignment error of less than 10 μm between each center line.

[0149] refer to Figure 4c, roughness may be formed on the upper surface of the first insulating layer 110b2. As with the first protective layer 120, when the first insulating layer 110b2 is etched and thinned using a chemical solution and / or plasma, roughness may be formed on the surface of the first insulating layer 110b2. Thus, the bonding strength between the first protective layer 120 and the first insulating layer 110b2 may be improved. In addition, although not shown, due to the roughness formed on the upper surface of the first insulating layer 110b2, a concave portion may be formed on the upper surface of the first insulating layer 110b2, and the filler of the first protective layer 120 may fill the concave portion formed on the upper surface of the first insulating layer 110b2. Therefore, the bonding strength between the first protective layer 120 and the first insulating layer 110b2 may be further improved. In addition, the filler of the first protective layer 120 and the filler of the first insulating layer 110b2 may be provided with the same material and / or the same diameter, but are not limited thereto.

[0150] Figure 5 According to the third embodiment Figure 4a An enlarged view of region R1 of a semiconductor package.

[0151] refer to Figure 5 The semiconductor package according to the third embodiment may be different from the semiconductor package of the second embodiment in terms of the structure of the bonding portion. For ease of explanation, the following description will be based on the first bonding portion vertically overlapping the connection member 200.

[0152] The first electrode portion 2141 includes a first via electrode 2141b and a first wiring electrode 2141a which are provided on the connection member 200. In addition, a first bonding portion 2151 is provided on the first electrode portion 2141.

[0153] The first coupling portion 2151 includes a first through portion 2151 a passing through the first protective layer 120 and a first protruding portion 2151 b protruding on the first through portion 2151 a .

[0154] At this time, the first through portion and the first protruding portion in the previous embodiment are provided with different widths.

[0155] In contrast, according to the third embodiment, the first through portion 2151a may have the same width as the first protruding portion 2151b. In addition, each of the first through portion 2151a and the first protruding portion 2151b may have the same width as the first wiring electrode 2141a of the first electrode portion 2141.

[0156] The third embodiment can increase the volume of the first bonding portion 2151 without affecting the pitch of the first bonding portion 2151, thereby allowing the semiconductor device to be more stably disposed on the first bonding portion 2151. In addition, the embodiment can improve the rigidity of the semiconductor package by increasing the volume of the first bonding portion 2151, thereby preventing the semiconductor device from being greatly bent in a specific direction.

[0157] Figure 6 According to the fourth embodiment Figure 4a An enlarged view of region R1 of a semiconductor package.

[0158] refer to Figure 6 , the first through portion 3141 is disposed on the connection member 200. The first through portion 3141 may not have a width variation from an upper surface to a lower surface, and may pass through the first insulating layer 110b2.

[0159] The first protruding portion 3151 is disposed on the first through portion 3141. The first protruding portion 3151 may not have a width change from the upper surface to the lower surface, and may pass through the first protective layer 120. That is, after the first protruding portion 3151 and the first through portion 3141 are integrally disposed, the first protective layer 120 is etched using a chemical solution and / or plasma to reduce the thickness of the first protective layer 120, thereby exposing the first protruding portion 3151. Therefore, since the pitch of the first protruding portion 3151 can be implemented finer, mutual communication between the semiconductor chips 320 and 330 and the circuit board 100 can become smoother.

[0160] Figure 7 is a diagram showing a semiconductor package according to a fifth embodiment.

[0161] refer to Figure 7 , the semiconductor package according to the fifth embodiment includes a circuit board manufactured by an ETS (embedded trace substrate) method, and according to the above description, the circuit board according to the fifth embodiment can be classified as a coreless substrate.

[0162] refer to Figure 7 , the semiconductor package includes an insulating layer 4110, a first protective layer 4120, a second protective layer 4130, an electrode portion 4140, and a bonding portion 4150. The connecting member 200 is embedded in the insulating layer 4110. In addition, the contact member 220 may be provided between the connecting member 200 and the electrode portion 4140. Therefore, while the dry film pattern is provided on the wiring electrode 4140a of the uppermost electrode portion 4140 embedded in the insulating layer 4110, the laminated Figure 7The first protective layer 4120 is formed by laminating the first protective layer 4120, and thus, a through hole corresponding to the dry film pattern is provided in the first protective layer 4120. That is, in the fifth embodiment, in the process of manufacturing a circuit board using the ETS method, a process of providing a dry film pattern corresponding to the pitch that the bonding portion 4150 should have can be performed before laminating the first protective layer 4120. For example, the fifth embodiment can be manufactured by a process of forming a through hole in the first protective layer using a dry film pattern and a process of forming a bonding portion described in the first embodiment.

[0163] The embodiment includes a protective layer and a bonding portion that passes through a partial area of ​​the protective layer from the upper surface of the protective layer. At this time, the protective layer has a through hole corresponding to the bonding portion. The through hole of the protective layer is formed by a dry film pattern. That is, the formed through hole corresponds to the width and pitch that the bonding portion provided in the semiconductor package should have. That is, considering the width and pitch of the bonding portion, the embodiment pre-forms the dry film pattern. Thus, the embodiment can minimize the pitch between multiple bonding portions. For example, the embodiment can arrange the horizontal distance between the centers of two adjacent bonding portions to be less than 40 μm. The embodiment can refine the pitch of the bonding portion to less than 40 μm, thereby, the embodiment can improve the circuit integration and miniaturize the circuit board and the semiconductor package. In addition, the embodiment can reduce the distance between multiple bonding portions, based on which the transmission distance of the signal transmitted through the corresponding bump portion can be minimized. Therefore, the embodiment can minimize the signal transmission loss that increases according to the signal transmission distance, thereby improving the electrical characteristics of the circuit board and the semiconductor package. In addition, the embodiment can allow the semiconductor device to be arranged on the circuit board to work stably, so that electronic products such as servers that apply semiconductor packages can work stably.

[0164] In addition, the embodiment has an electrode portion disposed between the connecting member and the joining portion. The electrode portion passes through at least a portion of the insulating layer. At this time, the insulating layer has a through hole corresponding to the via electrode of the electrode portion. In addition, a dry film is formed according to the width and pitch that the joining portion of the embodiment should have, and the through hole of the insulating layer is set by the dry film. Thus, the embodiment can form an electrode portion corresponding to the width and pitch that the joining portion should have. Therefore, the embodiment can enable the joining portion to have a target width and pitch. In addition, the embodiment can form an electrode portion at a position corresponding to the joining portion, thereby improving the positional alignment of the joining portion and the electrode portion, and further improving the electrical characteristics of the joining portion and the electrode portion.

[0165] In addition, the embodiment can minimize the height deviation between the plurality of joint parts. That is, the embodiment includes a first joint part overlapping with the connecting member in the vertical direction and a second joint part not overlapping with the connecting member in the vertical direction. At this time, the size of the first through-portion of the first joint part is the same as the size of the second through-portion of the second joint part. That is, the embodiment can use the dry film pattern to make the through-portions of the first joint part and the second joint part have the same size, thereby minimizing the height deviation between the first joint part and the second joint part caused by the size difference.

[0166] Therefore, the embodiment can minimize the height deviation of the first bonding portion and the second bonding portion, thereby allowing the semiconductor element to be stably arranged on the first bonding portion and the second bonding portion. Therefore, the embodiment can improve the reliability of the first semiconductor device and the second semiconductor device. In addition, the embodiment can allow the operation of the first semiconductor element and the second semiconductor element to be smoothly performed, thereby enabling the operation of the electronic product or server to be smoothly performed.

[0167] In addition, the embodiments allow the first bonding portion and the second bonding portion to have the same height, thereby preventing problems such as impedance variation or signal transmission loss caused by thickness variations of the first bonding portion and the second bonding portion, and problems such as the semiconductor device being set in a tilted state, thereby further improving electrical reliability.

[0168] In addition, the embodiment can relatively reduce the surface roughness of the interface between the through portion of each of the first bonding portion and the second bonding portion and the protective layer. Therefore, the embodiment can reduce the surface roughness of the through portion, thereby minimizing the signal transmission loss that increases in proportion to the surface roughness. Therefore, the embodiment can further improve the operating characteristics of the semiconductor device.

[0169] At the same time, the upper surface of the protective layer of the embodiment may have a concave portion and a convex portion through a process of thinning the thickness to increase the surface area of ​​the upper surface of the protective layer. The concave portion and the convex portion may improve the reliability of the circuit board in thermal cycles such as expansion and contraction of the circuit board caused by heat generated during the operation of the semiconductor chip or heat applied from the outside. For example, since the convex portion and the concave portion have different thicknesses, the volume deformed during thermal expansion may be different. That is, the thickness of the concave portion may be thinner than the thickness of the convex portion, and due to the difference in the thermal expansion coefficient of the convex portion and the thermal expansion coefficient of the concave portion, the overall thermal deformation of the semiconductor package may be suppressed. Therefore, the embodiment may prevent the semiconductor device coupled to the upper portion of the semiconductor package from being electrically separated during thermal expansion, thereby improving product reliability.

[0170] With reference to the first to fifth embodiments, the via electrode located above the connection member 200 has a different width and / or tilt direction from the via electrode located below the connection member 200. That is, the via electrode located above the connection member 200 has a more vertical side surface than the via electrode located below the connection member 200. That is, the via electrode having a vertical side surface is located above the connection member 200, and therefore, the effect of improving the warpage of the circuit board 100 can be achieved. In addition, when the pattern of the via electrode having a vertical side surface is finer than the pattern of the via electrode having an inclined side surface, the stress applied to the via electrode can be alleviated, thereby improving the reliability of the electrical connection between the semiconductor chips 320 and 330 and the circuit board 100. Therefore, the via electrode having a vertical side surface can be implemented as being located above the connection member 200.

[0171] In addition, although the above description describes that a through hole is formed in the first protective layer 120 using a dry film, the width of the through hole is 20 μm or less and the pitch between two adjacent through holes is 40 μm or less, it is not limited thereto. For example, the embodiment may also form a through hole in the second protective layer 130 in the same manner as the process of forming a through hole in the first protective layer 120.

[0172] In addition, the first protective layer 120 is described as having a plurality of through holes, and the plurality of through holes are provided with the bonding portion 150 , but is not limited thereto.

[0173] For example, at least one of the through holes provided in the first protective layer 120 may not be provided with a bonding portion. In addition, the through hole not provided with the bonding portion may be filled with a molding member (not shown) for molding a semiconductor chip. Therefore, the embodiment can improve the bonding strength between the circuit board and the molding member. In addition, the embodiment can control the density of the first protective layer in the edge area of ​​the circuit board, or firmly bond the molding member and the circuit board to prevent the circuit board from bending in a specific direction, or firmly fix the circuit board to improve the rigidity when the circuit board bends in a specific direction.

[0174] Figures 8a to 8q It is described in the process sequence. Figure 4a sectional view of a method for manufacturing a circuit board according to a second embodiment.

[0175] refer to Figure 8a , the embodiment prepares the third insulating layer 110a. In addition, the embodiment may perform a process of forming an electrode portion in the third insulating layer 110a. For example, the embodiment may perform a process of forming a wiring electrode on the upper surface and the lower surface of the third insulating layer 110a and a process of forming a via electrode and an insulating member 110d passing through the third insulating layer 110a.

[0176] Next, the embodiment performs a process of stacking the second insulating layer 110b1 on the third insulating layer 110a. In addition, the embodiment performs a process of forming a via electrode passing through the second insulating layer 110b1 and a wiring electrode on the second insulating layer 110b1.

[0177] refer to Figure 8b , the embodiment performs a process of forming a cavity C in the second insulating layer 110b1. At this time, the dummy electrode 141a31 is disposed on the third insulating layer 110a, and the cavity C overlaps the dummy electrode 141a31 in a vertical direction.

[0178] Next, refer to Figure 8c , the embodiment performs a process of applying an adhesive material on the dummy electrode 141 a 31 , thereby attaching the connection member 200 to the cavity C. At this time, the connection member 200 is provided with the pad 210 , and the pad 210 is disposed to face upward.

[0179] Next, refer to Figure 8d , the embodiment performs a process of stacking the first dry film DF1 on the second insulating layer 110 b 1 and the connection member 200 .

[0180] Next, refer to Figure 8e , the embodiment performs a process of exposing and developing the first dry film DF1 to correspond to the width and pitch that the first bonding portion 151 and the second bonding portion 152 should have. Thus, a first dry film pattern DFP1-1 corresponding to the area where the first via electrode 141b of the first electrode portion 141 is to be provided is formed on the pad 210 of the connection member 200. In addition, a second dry film pattern DFP1-2 corresponding to the area where the second via electrode 142b of the second electrode portion 142 is to be provided is formed on the wiring electrode.

[0181] Next, refer to Figure 8f , the embodiment performs a process of stacking the first insulating layer 110b2. At this time, the first insulating layer 110b2 is provided to fill the cavity C in which the connection member 200 is embedded. In addition, the first insulating layer 110b2 is provided to have a height greater than the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2.

[0182] Next, refer to Figure 8g, the embodiment performs a process of thinning the thickness of the first insulating layer 110b2. Thus, the upper surface of the first insulating layer 110b2 is positioned lower than the upper surfaces of the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2. In addition, by the process of thinning the thickness of the first insulating layer 110b2, the filler disposed in the second layer 110b2 of the second insulating layer 110b may be detached or exposed through the upper surface of the first insulating layer 110b2. Therefore, the upper surface of the first insulating layer 110b2 may be provided with a concave portion and / or a convex portion corresponding to the filler disposed in the first insulating layer 110b2. In addition, at least a portion of the filler disposed in the first insulating layer 110b2 may be exposed through the upper surface of the first insulating layer 110b2.

[0183] Next, refer to Figure 8h , the embodiment performs a process of removing the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2. Thus, the first through hole TH1 and the second through hole TH2 corresponding to the space where the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2 are removed are formed in the second layer 110b2 of the second insulating layer 110b. In this case, the embodiment allows the first through hole TH1 and the second through hole TH2 to be formed using the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2. Therefore, the filler disposed in the first insulating layer 110b2 may not be detached through the first through hole TH1 and the second through hole TH2, and the filler disposed in the second layer 110b2 of the second insulating layer 110b may not be exposed through the first through hole TH1 and the second through hole TH2. In addition, in the embodiment, by forming the first through hole TH1 and the second through hole TH2 using the first dry film pattern DFP1-1 and the second dry film pattern DFP1-2, the upper surface of the pad 210 of the connection member 200 may not have a concave portion.

[0184] Next, refer to Figure 8i , the embodiment forms a second dry film DF2 on the first insulating layer 110b2. At this time, the second dry film DF2 has an opening opened in the area where the wiring electrode is to be set. Next, the embodiment performs a plating process to fill the first through hole TH1, the second through hole TH2, and the opening of the second dry film DF2 of the first insulating layer 110b2. Therefore, the embodiment can form an electrode portion 140 including a wiring electrode 140a and a via electrode 140b.

[0185] Next, refer to Figure 8j , the embodiment performs a process of stacking the third dry film DF3 on the first insulating layer 110 b 2 .

[0186] Next, refer to Figure 8k, the embodiment performs a process of exposing and developing the third dry film DF3 to correspond to the width and pitch that the first bonding portion 151 and the second bonding portion 152 should have. Thus, a third dry film pattern DFP3-1 corresponding to the first bonding portion 151 and a fourth dry film pattern DFP3-2 corresponding to the second bonding portion 152 are formed on the wiring electrode 140a.

[0187] Next, refer to Figure 8l The embodiment performs a process of stacking the first protection layer 120 on the first insulating layer 110b2. At this time, the height of the first protection layer 120 is set to be greater than the heights of the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2.

[0188] Next, refer to Figure 8m , the embodiment performs a process of thinning the thickness of the first protective layer 120. Thus, the upper surface of the first protective layer 120 is positioned lower than the upper surfaces of the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2. In addition, by the process of thinning the thickness of the first protective layer 120, the filler disposed in the first protective layer 120 may be detached or exposed to the outside. Therefore, the upper surface of the first protective layer 120 may be provided with a concave portion and / or a convex portion corresponding to the filler disposed in the first protective layer. In addition, at least a portion of the filler disposed in the first protective layer 120 may be exposed through the upper surface of the first protective layer 120.

[0189] Next, refer to Figure 8n , the embodiment performs a process of removing the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2. Thus, the first through hole 120a and the second through hole 120b are formed in the first protective layer 120. Therefore, in the embodiment, by forming the first through hole 120a and the second through hole 120b using the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2, the filler disposed in the first protective layer 120 may not be detached through the first through hole 120a and the second through hole 120b, and the filler disposed in the first protective layer 120 may not be exposed through the first through hole 120a and the second through hole 120b. In addition, in the embodiment, by forming the first through hole 120a and the second through hole 120b using the third dry film pattern DFP3-1 and the fourth dry film pattern DFP3-2, a concave portion may not be disposed on the upper surface of the wiring electrode 140a.

[0190] Next, refer to Figure 8o , the embodiment performs a plating process to fill the first and second through holes 120 a and 120 b , thereby forming the first and second bonding portions 151 and 152 .

[0191] Next, refer to Figure 8p, the embodiment performs a process of disposing the connection part 310 on the first bonding part 151 and the second bonding part 152 .

[0192] Meanwhile, a circuit board and a semiconductor package including the circuit board according to an additional embodiment are described below. The circuit board and the semiconductor package of the additional embodiment may be similar to those of the previous embodiment, because the circuit board and the semiconductor package include a protective layer, and a through hole is formed in the protective layer. However, hereinafter, while a through hole is formed in the protective layer using a dry film, a convex portion is provided on the surface of the protective layer.

[0193] Before describing the embodiment, the structure of a protective layer according to a conventional technology is described in comparison with the embodiment.

[0194] Fig. 9 is a cross-sectional view showing a circuit board according to a comparative example.

[0195] refer to Fig. 9 , the circuit board of the comparative example includes an insulating layer 10, a circuit pattern layer and a protective layer 30. The circuit pattern layer includes a first pad 21, a second pad 22 and a trace 23. The protective layer 30 includes a first through hole 31 vertically overlapping the first pad 21. The first through hole 31 partially opens the upper surface of the first pad 21. According to the exposure resolution (e.g., high resolution) of the protective layer 30, the width W1 of the first through hole 31 is at least more than 50μm. Specifically, according to the exposure resolution (e.g., normal resolution) of the protective layer 30, the width W1 of the first through hole 31 is at least more than 70μm. Therefore, the width of the first pad 21 vertically overlapping the first through hole 31 exceeds 70μm, which is greater than the width W1 of the first through hole 31. For example, the width of the first pad 21 exceeds 90μm, which is greater than the width W1 of the first through hole 31. This is in consideration of the process deviation in the process of forming the first through hole 31.

[0196] As described above, the width of the first through hole 31 is at least more than 50 μm or more than 70 μm, and therefore, the width of the first pad 21 is more than 70 μm or more than 90 μm. Therefore, the comparative example has a limitation in reducing the gap between the plurality of first pads. That is, the comparative example has a limitation in miniaturizing the width W1 of the first through hole 31, and also has a limitation in miniaturizing the width of the first pad 21.

[0197] The protective layer 30 includes a second through hole 32 vertically overlapping the second pad 22. The second through hole 32 opens the entire upper surface of the second pad 22. That is, the second through hole 32 is an NSMD type through hole. According to the exposure resolution of the protective layer 30, the width W2 of the second through hole 32 exceeds 50μm or 70μm. That is, the protective layer 30 has a limitation in miniaturizing the width W2 of the second through hole 32.

[0198] In addition, the protective layer 30 performs an exposure and curing process to form the first through hole 31 and the second through hole 32. At this time, there is a problem that the lower region of the protective layer 30 cannot be completely cured during the exposure and curing of the protective layer 30. In addition, in the case where the complete curing is not achieved, there is a problem that an undercut 33 is formed in the lower region of the side wall of the second through hole 32 during the formation of the second through hole 32.

[0199] At this time, the horizontal distance W3 of the undercut 33 of the comparative example exceeds 15 μm or exceeds 20 μm. The horizontal distance W3 of the undercut 33 indicates the horizontal distance from the innermost end to the outermost end in the lower region of the side wall of the second through hole 32 .

[0200] At this time, the circuit pattern layer includes a trace 23 disposed adjacent to the second pad 22. In addition, in the control example, when the trace 23 is disposed, the horizontal distance W3 of the undercut 33 must be considered. That is, in the control example, if the horizontal distance W3 of the undercut 33 is not considered, one side of the trace 23 may be exposed through the undercut 33. In this case, the solder ball disposed on the second pad 22 extends to the undercut 33, and therefore, contacts the trace 23 and a circuit short circuit problem occurs. Therefore, in the control example, the interval between the second pad 22 and the trace 23 is determined by considering the width W2 of the second through hole 32 and the horizontal distance W3 of the undercut 33. Therefore, in the control example, the interval increases, and thus there is a problem of reduced circuit integration.

[0201] In addition, with the recent improvement in the performance of electrical / electronic products, a technology for attaching a large number of semiconductor devices to a substrate of a limited size is being studied, and therefore, miniaturization of circuit patterns is required. In the case of a semiconductor package using the circuit board of the comparative example, the minimum width of the through hole that can be formed in the protective layer 30 and the limitation of the horizontal distance of the undercut must be considered, and therefore, there is a limitation in miniaturizing the circuit pattern.

[0202] In addition, the functions processed in a logic chip such as an application processor (AP) have recently increased. This makes it difficult to implement all functions in one logic chip. Therefore, a space for mounting multiple logic chips on a circuit board is required. However, it is difficult to mount multiple logic chips with different functions in a limited space using the circuit board of the comparative example.

[0203] In addition, the upper surface of the protective layer 30 of the comparative example is formed substantially in a flat surface. Therefore, in order to prevent diffusion of a connection portion such as solder provided in a through hole of the protective layer 30, the thickness of the protective layer 30 must be increased.

[0204] That is, the protective layer 30 of the comparative example does not include a barrier structure to prevent the diffusion of solder. Therefore, the comparative example has a problem that a solder short circuit occurs due to the diffusion of solder when the thickness of the protective layer 30 is reduced.

[0205] In addition, when the thickness of the protective layer 30 is increased, the comparative example has a problem that a designed distance may be exceeded when the epoxy mold compound is filled after chip mounting, and thus an unfilled area may occur.

[0206] Embodiments are intended to address these problems and provide a barrier structure capable of preventing solder from diffusing on the upper surface of a protective layer. That is, the protective layer of the embodiment includes a raised portion disposed adjacent to a through hole and surrounding an upper region of the through hole. In addition, the embodiment can improve the reliability of the solder disposed in the through hole by using the raised portion. In addition, compared to the control example, the embodiment can significantly reduce the width of the through hole that can be formed in the protective layer. In addition, the embodiment can minimize the horizontal distance of the undercut at the side wall of the through hole formed in the protective layer, or can eliminate the undercut. In addition, the embodiment can reduce the tolerance (SRR: solder resist registration) between the center of the through hole of the protective layer and the center of the pad. In addition, the embodiment can improve electrical and mechanical properties while improving the bonding strength with the molding layer.

[0207] Fig.10 is a sectional view showing a circuit board according to a sixth embodiment, Fig.11 It is shown in detail Fig.10 A cross-sectional view of a first partial area of ​​a circuit board, Fig.12 It is shown in detail Fig.11 A cross-sectional view of a second partial area of ​​the circuit board, Fig.13 is a cross-sectional view of a partial area of ​​a circuit board according to an embodiment for explaining a raised portion, Fig.14 is a plan view of a partial area of ​​a circuit board according to an embodiment for explaining a raised portion, Fig.15 It is shown Fig.13 and Fig.14 Scanning electron microscope image of a portion of a circuit board. Fig.16 It is shown Fig.12 Scanning electron microscope image of the upper surface of the first protective layer, Fig.17 It is shown Fig.12 Scanning electron microscope image of the inner surface of the through-hole of the first protective layer, Fig.18 A resist pattern for forming a through hole of a first protective layer according to an embodiment is shown.

[0208] In the following, reference will be made to Figures 10 to 18 A circuit board according to the sixth embodiment will be described in detail.

[0209] The circuit board 4100 of the sixth embodiment includes an insulating layer 4110, an upper wiring electrode 4120, and a lower wiring electrode 4130. The upper wiring electrode 4120 may refer to the upper wiring electrode 140a1 located at the uppermost portion of the insulating layer in the previous embodiment. In addition, the lower wiring electrode 4130 may refer to the fifth wiring electrode 140a6 located at the lowermost portion of the insulating layer in the previous embodiment.

[0210] The upper wiring electrode 4120 includes a first pad 4120-1, a second pad 4120-2, and a third pad 4120-3. The first pad 4120-1, the second pad 4120-2, and the third pad 4120-3 of the upper wiring electrode 4120 can be distinguished by their widths. For example, the width of the first pad 4120-1 can be greater than the width of the second pad 4120-2 and less than the width of the third pad 4120-3. For example, the width of the second pad 4120-2 can be less than the width of the first pad 4120-1 and the third pad 4120-3. For example, the width of the third pad 4120-3 can be greater than the width of the first pad 4120-1 and the second pad 4120-2.

[0211] It is necessary to miniaturize the upper wiring electrode 4120, and therefore, the intervals between the plurality of pads can be reduced. In addition, when the intervals between the plurality of pads are reduced due to miniaturization, the circuit integration can be improved, but solder short circuits may occur due to the diffusion of solder during the process of setting the solder. Therefore, the embodiment includes a barrier structure capable of preventing the solder from diffusing in the protective layer.

[0212] The upper wiring electrode 4120 and the lower wiring electrode 4130 may each have a multi-layer structure.

[0213] The upper wiring electrode 4120 may include a first metal layer 4121 and a second metal layer 4122. That is, each of the first pad 4120-1, the second pad 4120-2, and the third pad 4120-3 of the upper wiring electrode 4120 may include the first metal layer 4121 and the second metal layer 4122.

[0214] The first metal layer 4121 of the upper wiring electrode 4120 may protrude above the upper surface of the insulating layer 4110. The first metal layer 4121 of the upper wiring electrode 4120 may be a chemically plated metal layer. The thickness of the first metal layer 4121 of the upper wiring electrode 4120 may be in the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer 4121 of the upper wiring electrode 4120 may be in the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer 4121 of the upper wiring electrode 4120 may be in the range of 0.5 μm to 2.5 μm. If the thickness of the first metal layer 4121 of the upper wiring electrode 4120 is less than 0.2 μm, the first metal layer 4121 of the upper wiring electrode 4120 may not be used as a seed layer. If the thickness of the first metal layer 4121 of the upper wiring electrode 4120 is less than 0.2 μm, it may be difficult to form the first metal layer 4121 with a uniform thickness on the upper surface of the insulating layer 4110. If the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the processing time for forming the first metal layer 4121 of the upper wiring electrode 4120 may increase, and thus the yield may decrease. In addition, if the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the etching time of the first metal layer 4121 in the process of forming the upper wiring electrode 4120 may increase. In addition, if the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, when etching the first metal layer 4121 of the upper wiring electrode 4120, deformation of the second metal layer 4122 of the upper wiring electrode 4120 may occur. Here, the deformation of the second metal layer 4122 of the upper wiring electrode 4120 may mean that when etching the first metal layer 4121, since the side of the second metal layer 4122 is also etched, the difference between the width of the upper surface and the width of the lower surface of the second metal layer 4122 increases. For example, the deformation of the second metal layer 4122 of the upper wiring electrode 4120 may mean that the shape of the vertical cross section of the second metal layer 4122 changes from a square to a trapezoid. In addition, if the thickness of the first metal layer 4121 of the upper wiring electrode 4120 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer 4121 increases, and thus, the depth of the groove (e.g., undercut) formed at the side of the first metal layer 4121 and the side of the second metal layer 4122 may increase. For example, if the etching amount in the etching process of the first metal layer 4121 increases, the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 may increase. In addition, when the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 increases, the electrical characteristics may be deteriorated due to the increase in signal transmission loss.In addition, when the difference between the width of the first metal layer 4121 and the width of the second metal layer 4122 becomes large, dendrites may be formed by electromigration, thereby deteriorating the electrical characteristics and / or physical characteristics of the upper wiring electrode 4120. The second metal layer 4122 may be an electrolytic plating layer using the first metal layer 4121 as a seed layer. The second metal layer 4122 of the upper wiring electrode 4120 may be formed on the first metal layer 4121 with a certain thickness. The second metal layer 4122 of the upper wiring electrode 4120 may include the same metal as the first metal layer 4121 of the upper wiring electrode 4120, but is not limited thereto. For example, the first metal layer 4121 and the second metal layer 4122 of the upper wiring electrode 4120 may each include copper.

[0215] The thickness of the second metal layer 4122 of the upper wiring electrode 4120 may be greater than the thickness of the first metal layer 4121 of the upper wiring electrode 4120. The thickness of the second metal layer 4122 of the upper wiring electrode 4120 may be in the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer 4122 of the upper wiring electrode 4120 may be in the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer 4122 of the upper wiring electrode 4120 may be in the range of 4.5 μm to 22 μm. If the thickness of the second metal layer 4122 of the upper wiring electrode 4120 is less than 3.5 μm, the second metal layer 4122 may also be etched during the etching process of the first metal layer 4121. If the thickness of the second metal layer 4122 of the upper wiring electrode 4120 is less than 3.5 μm, the allowable current of the signal transmitted through the upper wiring electrode may be reduced, and thus the electrical characteristics may be deteriorated. If the thickness of the second metal layer 4122 of the upper wiring electrode 4120 exceeds 25 μm, it may be difficult to miniaturize the upper wiring electrode 4120. For example, if the thickness of the second metal layer 4122 of the upper wiring electrode 4120 exceeds 25 μm, the width and interval of the pattern constituting the upper wiring electrode 4120 may not meet the required conditions. Therefore, the circuit integration may be reduced, or the volume of the circuit board and the semiconductor package may be increased.

[0216] The lower wiring electrode 4130 may include a first metal layer 4131 and a second metal layer 4132 corresponding to the upper wiring electrode 4120 .

[0217] The circuit board 4100 may include a via electrode 4140. The via electrode 4140 may pass through the insulating layer 4110. Preferably, the via electrode 4140 may pass through the insulating layer 4110 to be electrically connected between the upper wiring electrode 4120 and the lower wiring electrode 4130. At this time, when the insulating layer 4110 has a multi-layer structure, the via electrode 4140 may be spaced apart in a vertical direction and electrically connected between adjacent wiring electrodes.

[0218] In addition, the via electrode 4140 includes a first metal layer 4141 and a second metal layer 4142 corresponding to the upper wiring electrode and the lower wiring electrode.

[0219] A first protective layer 4150 may be included on the insulating layer 4110. For example, the circuit board 4100 may include a second protective layer 4160 disposed below the insulating layer 4110.

[0220] The first protective layer 4150 includes at least one through hole. In addition, the second protective layer 4160 includes at least one through hole. Figure 1a to Figure 1d The illustrated bonding portion 150 may be disposed in a through hole of the first protective layer 4150 .

[0221] In addition, the first protective layer 4150 and the second protective layer 4160 may include raised portions 4150P and 4160P. The raised portions 4150P and 4160P may be disposed on the surfaces of the first protective layer 4150 and the second protective layer 4160. In addition, the raised portion 4150P of the first protective layer 4150 may be disposed to surround the through portion of the bonding portion 150. That is, the raised portion 4150P of the first protective layer 4150 may be disposed on the surface of the first protective layer 4150 and the second protective layer 4160. Figure 1a to Figure 1d On the first protective layer 120 shown, thus, the engaging portion 150 may include a portion surrounded by the raised portion 4150 of the first protective layer 4150 .

[0222] That is, the insulating layer 4100 includes a side surface located between the upper surface and the lower surface. In addition, the first protective layer 4150 includes a lower surface facing the upper surface of the insulating layer 4100, an upper surface corresponding to the lower surface of the first protective layer 4150, and a side surface between the upper surface and the lower surface of the first protective layer 4150. At this time, the side surface of the first protective layer 4150 includes an inner surface of the through portion surrounding the bonding portion 150 and an outer surface adjacent to the side surface of the insulating layer 4110. In addition, the length of the inner surface of the first protective layer 4150 in the vertical direction is different from the length of the outer surface of the first protective layer 4150 in the vertical direction. For example, the length of the inner surface of the first protective layer 4150 in the vertical direction is greater than the length of the outer surface in the vertical direction. Thus, the embodiment can allow the bonding portion 150 to be more stably supported by the first protective layer 4150, thereby improving the physical reliability and / or electrical reliability of the bonding portion 150.

[0223] That is, the first protective layer 4150 includes the convex portion 4150P. In addition, the second protective layer 4160 includes the convex portion 4160P.

[0224] The convex portion 4150P of the first protective layer 4150 may convex in an upward direction at an upper surface of the first protective layer 4150. Preferably, the convex portion 4150P of the first protective layer 4150 may protrude upward at an upper surface of the first protective layer 4150 adjacent to the through hole.

[0225] Specifically, the first protective layer 4150 may be divided into a plurality of regions in the horizontal direction. For example, the first protective layer 4150 includes a through hole and a first region R1 adjacent to the through hole. In addition, the first protective layer 4150 includes a second region R2 other than the first region R1. In addition, the first region R1 of the first protective layer 4150 may have a first height. In this case, the first height may represent a vertical distance from the upper surface of the insulating layer 4110 to the upper surface of the first region R1 of the first protective layer 4150. In addition, the second region R2 of the first protective layer 4150 may have a second height different from the first height. The second height may represent a vertical distance from the upper surface of the insulating layer 4110 to the upper surface of the second region R2 of the first protective layer 4150. In addition, the first height may be greater than the second height. That is, the upper surface of the first protective layer 4150 of the embodiment may include a region whose height increases as it approaches the through hole. For example, a convex portion 4150P may be formed in the first region R1 of the first protective layer 4150 , the convex portion 4150P being positioned higher than the second region R2 of the first protective layer 4150 and convex in an upward direction.

[0226] The raised portion 4160P of the second protective layer 4160 may be raised in a downward direction from the lower surface of the second protective layer 4160. Preferably, the raised portion 4160P of the second protective layer 4160 may protrude downward from the lower surface of the second protective layer 4160 adjacent to the through hole. In addition, the second protective layer 4160 may further include a first region and a second region corresponding to the first protective layer 4150. In addition, the first height of the first region of the second protective layer 4160 may be greater than the second height of the second region of the second protective layer 4160. At this time, the first height of the first region of the second protective layer 4160 may represent a vertical distance from the lower surface of the insulating layer 4110 to the lower surface of the first region of the second protective layer 4160. In addition, the second height of the second region of the second protective layer 4160 may represent a vertical distance from the lower surface of the insulating layer 4110 to the lower surface of the second region of the second protective layer 4160.

[0227] The first protective layer 4150 includes a first through hole 4151. For example, the first protective layer 4150 may include the first through hole 4151 vertically overlapping the first pad 4120-1 of the upper wiring electrode 4120.

[0228] The first through hole 4151 of the first protective layer 4150 may vertically overlap with the upper surface portion of the first pad 4120-1. The width W1 of the first through hole 4151 of the first protective layer 4150 may be less than the width of the upper surface of the first pad 4120-1. For example, the first protective layer 4150 may include the first through hole 4151 covering at least a portion of the upper surface of the first pad 4120-1 and exposing the rest of the upper surface of the first pad 4120-1.

[0229] The width W1 of the first through hole 4151 of the first protective layer 4150 may be in the range of 10 μm to 20 μm. Preferably, the width W1 of the first through hole 4151 of the first protective layer 4150 may be in the range of 12 μm to 20 μm. More preferably, the width W1 of the first through hole 4151 of the first protective layer 4150 may be in the range of 13 μm to 20 μm.

[0230] At this time, when the first through hole 4151 of the first protective layer 4150 has a width variation in the thickness direction, the width W1 of the first through hole 4151 may represent a width of a region having a maximum width among the entire region.

[0231] If the width W1 of the first through hole 4151 of the first protective layer 4150 is less than 10 μm, the amount of solder applied to the connection portion (such as a solder ball) provided in the first through hole 4151 may be reduced, thereby reducing the bonding strength with the semiconductor device. If the width W1 of the first through hole 4151 of the first protective layer 4150 exceeds 20 μm, the width of the first pad 4120-1 increases accordingly, and thus the circuit integration may be reduced.

[0232] The width of the first through hole 4151 of the first protective layer 4150 may hardly change from the area adjacent to the upper surface of the first protective layer 4150 to the area adjacent to the lower surface of the first protective layer 4150. Here, the fact that the width does not change may mean that the slope of the first inner surface 4151S of the first protective layer 4150 constituting the first through hole 4151 is close to vertical. For example, the fact that the width does not change may mean that the width difference between the area with the maximum width and the area with the minimum width in the entire area in the thickness direction of the first through hole 4151 is 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, or 0.5 μm or less. The first through hole 4151 of the first protective layer 4150 is formed using the resist pattern as described in the previous embodiment.

[0233] The upper surface 4150T of the first protective layer 4150 may have a surface roughness different from the surface roughness of the first inner surface 4151S of the first through hole 4151 .

[0234] That is, the upper surface 4150T of the first protective layer 4150 may have an inner surface (4150S, see Fig.17 The inner surface 4150S of the through hole may include a first inner surface 4151S of the first through hole 4151 and a second inner surface 4152S of the second through hole 4152. The surface roughness of the upper surface 4150T of the first protective layer 4150 may be greater than the surface roughness of the inner surface of the through hole of the first protective layer 4150.

[0235] refer to Fig.16 , the first protective layer 4150 includes a resin and a filler 4150F dispersed in the resin. At this time, when the first protective layer 4150 is etched using a chemical solution and / or plasma, etc., the filler 4150F provided in the first protective layer 4150 may be exposed to the upper surface 4150T of the first protective layer 4150. Alternatively, the filler 4150F may not be exposed through the inner surface 4150S of the through hole of the first protective layer 4150, or the amount of the filler exposed through the inner surface 4150S of the through hole of the first protective layer 4150 may be less than the amount of the filler exposed to the upper surface 4150T of the first protective layer 4150. Therefore, due to the filler 4150F, the upper surface 4150T of the first protective layer 4150 may have a greater surface roughness than the inner surface of the through hole of the first protective layer 4150.

[0236] Due to the filler 4150F exposed through the upper surface 4150T of the first protective layer 4150, the surface roughness of the upper surface 4150T of the first protective layer 4150 can be increased. Thus, the embodiment can increase the bonding area between the first protective layer 4150 and the molding layer in the molding process after mounting the semiconductor device on the circuit board, thereby improving the bonding strength.

[0237] The first protective layer 4150 includes a second through hole 4152. For example, the first protective layer 4150 may include the second through hole 4152 vertically overlapping the second pad 4120-2 of the upper wiring electrode 4120.

[0238] At this time, the second through hole 4152 of the first protective layer 4150 may overlap vertically with the upper surface of the entire second pad 4120-2. That is, the width W2 of the second through hole 4152 of the first protective layer 4150 may be greater than the width of the upper surface of the second pad 4120-2. For example, the first protective layer 4150 may completely expose the upper surface and inner surface of the second pad 4120-2. For example, the second inner surface 4152S of the second through hole 4152 of the first protective layer 4150 may be spaced apart from the second pad 4120-2 and not in contact. For example, the second pad 4120-2 may not be in contact with the first protective layer 4150.

[0239] At this time, the embodiment forms a resist pattern by exposing and developing a photosensitive film capable of realizing a relatively fine pattern, rather than exposing and developing the protective layer itself (such as solder resist). In addition, the embodiment uses the resist pattern to form a through hole in the first protective layer 4150. Therefore, compared with the control example, the embodiment can reduce the size of the through hole formed in the first protective layer 4150, thereby improving the circuit integration.

[0240] At this time, since the embodiment does not expose and develop the first protective layer 4150, the first protective layer 4150 does not need to contain a photoinitiator. For example, a general solder resist contains a photoinitiator for exposure and development. At this time, the photoinitiator acts as a factor that deteriorates the physical and electrical properties of the circuit board.

[0241] Here, since the embodiment does not expose and develop the first protective layer 4150, the first protective layer 4150 does not include a photoinitiator. Therefore, since the first protective layer 4150 does not include a photoinitiator, the embodiment can improve physical and electrical characteristics of the circuit board.

[0242] Furthermore, since the first protective layer 4150 does not include a photoinitiator, embodiments may expand the types of insulating layers that may be used as the first protective layer 4150 and further reduce the unit cost required to develop the protective layer.

[0243] For example, the first protective layer 4150 of the embodiment may be a solder resist without a photoinitiator. In contrast, the first protective layer 4150 of the embodiment may use an insulating layer in which an inorganic filler of silicon dioxide or aluminum oxide is provided in a thermosetting resin or a thermoplastic resin without including glass fiber. For example, the first protective layer 4150 may use ABF (Ajinomoto stacked film), FR-4, BT (bismaleimide triazine), PID (photo-imaging dielectric resin), etc.

[0244] However, according to an embodiment, the first protective layer 4150 and the second protective layer 4160 of the present invention may be implemented using a solder resist used in a general circuit board. For example, according to an embodiment, the first protective layer 4150 and the second protective layer 4160 may contain a photoinitiator.

[0245] The upper surface 4150T of the first protective layer 4150 is provided with a convex portion 4150P.

[0246] For example, due to the convex portion 4150P, a first height of the first protective layer 4150 in the first region R1 may be greater than a second height in the second region R2.

[0247] The first region R1 of the first protective layer 4150 is a region adjacent to the through hole formed in the first protective layer 4150. For example, the convex portion 4150P may convex in an upward direction and may be formed in the first region R1 of the first protective layer 4150.

[0248] At this time, the convex portion 4150P may be formed adjacent to the through hole of the upper surface of the first protective layer 4150. For example, the convex portion 4150P may be convex in an upper region of the through hole of the first protective layer 4150. For example, the convex portion 4150P may be convex in an upward direction while being connected to the through hole of the first protective layer 4150.

[0249] Preferably, the protrusion 4150P may be formed to surround the inner edge of the through hole of the first protective layer 4150. The protrusion 4150P is connected to the through hole of the first protective layer 4150. Therefore, the inner area of ​​the protrusion 4150P connected to the through hole may also be referred to as a part of the through hole.

[0250] At this time, the raised portion 4150P does not follow the surface contour of the upper wiring electrode 4120 set on the upper surface of the insulating layer 4110. For example, a general protective layer is formed along the contour of the wiring electrode. For example, a general protective layer has a large height in an area vertically overlapping with the wiring electrode, and has a small height in an area that does not overlap with the wiring electrode. This is a structural feature that occurs due to the difference in surface height during the formation of the protective layer. That is, the area in the protective layer that overlaps with the wiring electrode has a greater height than the area that does not overlap with the wiring electrode, and therefore, this area can also be referred to as a raised portion. However, this is different from the structural feature of the raised portion 4150P of the present invention.

[0251] That is, the general protective layer formed along the contour of the wiring electrode 1) protrudes in the entire region overlapping with the wiring electrode, and 2) does not protrude in the entire region not overlapping with the wiring electrode.

[0252] On the contrary, the first protective layer 4150 of the present invention in which the raised portion 4150P is formed based on the through hole, 1) is raised in the area adjacent to the through hole, 2) at this time, the raised area includes not only the area vertically overlapping with the wiring electrode, but also the area not vertically overlapping, and 3) among the area vertically overlapping with the wiring electrode, the area separated from the through hole is not raised.

[0253] At this time, the filler 4150F is exposed on the upper surface 4150T of the first region R1 and the second region R2 of the first protective layer 4150. That is, the convex portion 4150P of the present invention is not a structure naturally formed by the outline of the wiring electrode, but a structural feature provided in the process of forming the through hole of the first protective layer 4150 of the present invention. In addition, the convex portion 4150P of the embodiment can be used as a barrier structure to prevent the diffusion of the connection portion such as the solder ball in the packaging process.

[0254] refer to Fig.11 , Fig.14 (a) and Fig.15 , the first protective layer 4150 includes a first convex portion 4151P. The first convex portion 4151P may be formed in an area adjacent to the first through hole 4151 on the upper surface of the first protective layer 4150. For example, the first convex portion 4151P may be formed in a first region R1 adjacent to the first through hole 4151 of the first protective layer 4150. The first convex portion 4151P may be disposed around the inner edge of the upper surface of the first through hole 4151. The first convex portion 4151P is positioned adjacent to the first through hole 4151. At this time, the first inner surface 4151S of the first through hole 4151 vertically overlaps the first pad 4120-1. In addition, the first convex portion 4151P is connected to the first inner surface 4151S of the first through hole 4151. Therefore, the first convex portion 4151P may vertically overlap the first pad 4120-1. At this time, the upper surface 4150T of the first protective layer 4150 adjacent to the first convex portion 4151P and vertically overlapping the first pad 4120-1 may be flat instead of convex. At this time, flatness may mean that the height deviation in the entire area of ​​the upper surface is 1 μm or less, 0.8 μm or less, 0.5 μm or less, or 0.2 μm or less. At this time, the height deviation may be divided into a height deviation in a portion exposed by the filler 4150F and a height deviation in a portion not exposed by the filler 4150F.

[0255] The first protruding portion 4151P of the first through hole 4151 may partially overlap vertically with the first pad 4120-1. This may mean that the first region R1 of the first protective layer 4150 adjacent to the first through hole 4151 partially overlaps vertically with the first pad 4120-1. For example, the second region R2 of the first protective layer 4150 may not overlap vertically with the first pad 4120-1. The first protruding portion 4151P or the first region R1 may include an overlapping region that vertically overlaps with the first pad 4120-1 and a non-overlapping region that does not vertically overlap with the first pad 4120-1.

[0256] refer to Fig.11 and Fig.14(b), the first protective layer 4150 includes a second convex portion 4152P. The second convex portion 4152P may be formed in a first region R1 of the first protective layer 4150 adjacent to the second through hole 4152 in the upper surface of the first protective layer 4150. Preferably, the second convex portion 4152P may be arranged to surround the inner edge of the upper surface of the second through hole 4152. At this time, the second inner surface 4152S of the second through hole 4152 does not overlap vertically with the second pad 4120-2. In addition, the second convex portion 4152P is connected to the second inner surface 4152S of the second through hole 4152. Therefore, the second convex portion 4152P may not overlap vertically with the second pad 4120-2. That is, unlike the first convex portion 4151P, the second convex portion 4152P positioned adjacent to the second through hole 4152 may not overlap vertically with the upper wiring electrode 4120.

[0257] That is, the first region R1 of the first protective layer 4150 adjacent to the second convex portion 4152P or the second through hole 4152 may not vertically overlap the upper wiring electrode 4120 including the second pad 4120 - 2 .

[0258] In addition, refer to Fig.12 , the first protection layer 4150 may include a third convex portion. The first protection layer 4150 may include a third through hole 4153 vertically overlapping the third pad 4120-3 of the upper wiring electrode 4120. At this time, the third through hole 4153 may be divided into a plurality of sub-through holes. The third pad 4120-3 may be a ground pad. For example, the third pad 4120-3 may be a large area pad.

[0259] Therefore, the first protective layer 4150 includes a third through hole 4153, and the third through hole 4153 includes a plurality of sub-through holes partially exposing the third pad 4120-3. The third through hole 4153 may include a first sub-through hole 4153-1 partially exposing the third pad 4120-3. In addition, the third through hole 4153 may include a second sub-through hole 4153-2 that is spaced apart from the first sub-through hole 4153-1 and partially exposes the third pad 4120-3.

[0260] The first protection layer 4150 may include a third raised portion adjacent to the third through hole 4153. For example, the third raised portion of the first protection layer 4150 includes a 3-1 raised portion 4153-1P surrounding an upper portion of the first sub-through hole 4153-1 of the third through hole 4153. In addition, the third raised portion of the first protection layer 4150 includes a 3-2 raised portion 4153-2P surrounding an upper portion of the second sub-through hole 4153-2 of the third through hole 4153. At this time, in the upper surface of the first protection layer 4150, an upper surface 4153F between the 3-1 raised portion 4153-1P and the 3-2 raised portion 4153-2P may be non-raised and flat while vertically overlapping the third pad 4120-3. That is, the upper surface 4153F between the 3-1st convex portion 4153-1P and the 3-2nd convex portion 4153-2P may be positioned lower than the 3-1st convex portion 4153-1P and the 3-2nd convex portion 4153-2P.

[0261] The first convex portion 4151P will be described in detail. In addition, the second convex portion 4152P and the third convex portion 4153P may have a structure corresponding to the first convex portion 4151P described below.

[0262] refer to Figure 5 , the first convex portion 4151P may be disposed to surround an upper region of the first through hole 4151 in a closed loop shape. That is, the first region R1 of the first protective layer 4150 may be disposed in an upper region of the first through hole 4151 and surround the first through hole 4151 .

[0263] The first convex portion 4151P may have a shape in which the width decreases or remains unchanged from the lower surface to the upper surface. The width of the first convex portion 4151P may represent the distance of the first convex portion 4151P in the horizontal direction. For example, the height of the first region R1 of the first protective layer 4150 including the first convex portion 4151P may decrease toward the second region R2. The vertical cross-sectional shape of the first convex portion 4151P may be a triangle, but is not limited thereto. For example, the vertical cross-sectional shape of the first convex portion 4151P may be set to various shapes, such as a step shape, a fan shape, a polygonal shape, etc.

[0264] At this time, the first convex portion 4151P may be formed in the process of etching the first protective layer 4150 using the resist pattern DFR1-F. That is, when the first protective layer 4150 is etched using the resist pattern DFR1-F, the first convex portion 4151P may be formed by controlling the etching conditions in the region adjacent to the resist pattern DFR1-F. In addition, the shape, width, thickness, and outer slope of the first convex portion 4151P may be controlled by controlling the etching conditions.

[0265] The first convex portion 4151P includes an inner surface 4151PS1 and an outer surface 4151PS2. The inner surface 4151PS1 of the first convex portion 4151P is connected to the first inner surface 4151S of the first through hole 4151. Therefore, the inner surface 4151PS1 of the first convex portion 4151P may also be referred to as a part of the first inner surface 4151S of the first through hole 4151. The inner surface 4151PS1 of the first convex portion 4151P may have a predetermined slope. For example, the inner surface 4151PS1 of the first convex portion 4151P may have a slope corresponding to the slope of the first inner surface 4151S of the first through hole 4151.

[0266] The inner surface 4151PS1 of the first convex portion 4151P may have a predetermined height. For example, the inner surface 4151PS1 of the first convex portion 4151P may have a vertical length T1 corresponding to the thickness of the first convex portion 4151P. The vertical length T1 may represent any one of the vertical length of the inner surface 4151PS1 of the first convex portion 4151P, the vertical length of the outer surface 4151PS2 of the first convex portion 4151P, and the thickness of the first convex portion 4151P. In addition, the vertical length T1 may represent the difference between the first height of the first region R1 of the first protective layer 4150 and the second height of the second region R2.

[0267] The vertical length T1 or thickness of the first convex portion 4151P may be in the range of 1.0 μm to 4.0 μm. Preferably, the thickness or vertical length T1 of the first convex portion 4151P may be in the range of 1.2 μm to 3.8 μm. The thickness or vertical length T1 of the first convex portion 4151P may be in the range of 1.5 μm to 3.5 μm. If the thickness or vertical length T1 of the first convex portion 4151P is less than 1.0 μm, the effect exhibited by the first convex portion 4151P may not be significant. For example, if the thickness or vertical length T1 of the first convex portion 4151P is less than 1.0 μm, the solder diffusion prevention effect or the solder short circuit prevention effect may not be significant. If the thickness or vertical length T1 of the first convex portion 4151P exceeds 4.0 μm, the distance between the first pad 4120-1 and the semiconductor device at the position where the first convex portion 4151P is provided increases, and thus, due to the increase in the signal transmission distance, the signal transmission loss may increase. In addition, if the thickness or vertical length T1 of the first convex portion 4151P exceeds 4.0 μm, the width of the first convex portion 4151P must be increased so that the first convex portion 4151P maintains a certain strength, and thus, an unfilled area may occur during the formation of the mold layer.

[0268] The width W3 of the first convex portion 4151P may be in the range of 0.5 μm to 2.5 μm. Preferably, the width W3 of the first convex portion 4151P may be in the range of 0.7 μm to 2.3 μm. More preferably, the width W3 of the first convex portion 4151P may be in the range of 0.9 μm to 2.0 μm. The width W3 of the first convex portion 4151P may represent the maximum width in the entire area in the thickness direction of the first convex portion 4151P. For example, the width W3 of the first convex portion 4151P may represent the width of the first region R1 of the first protective layer 4150 adjacent to the first through hole 4151. If the width W3 of the first convex portion 4151P is less than 0.5 μm, the rigidity of the first convex portion 4151P may be reduced. In addition, if the width W3 of the first convex portion 4151P is less than 0.5 μm, a problem may occur in which the first convex portion 4151P collapses due to pressure applied during a process of disposing a connection portion such as a solder ball in the first through hole 4151. In addition, if the width W3 of the first convex portion 4151P exceeds 2.5 μm, filling of the molding layer in the corresponding region may not occur, and thus, a physical reliability problem and / or an electrical reliability problem may occur because molding is not performed.

[0269] The outer surface 4151PS2 of the first convex portion 4151P may have a predetermined inclination angle θ. The inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may represent the slope of an imaginary straight line connecting the uppermost end and the lowermost end of the outer surface 4151PS2 of the first convex portion 4151P. Specifically, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may represent the inner angle formed by the outer surface 4151PS2 of the first convex portion 4151P and the lower surface of the first convex portion 4151P. For example, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may represent the inclination angle of the upper surface of the first region R1 of the first protective layer 4150. For example, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may represent the inner angle between the upper surface of the first region R1 of the first protective layer 4150 and the lower surface of the first region R1. The inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may be in the range between 50 degrees and 75 degrees. Preferably, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may be in the range between 52 degrees and 73 degrees. More preferably, the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P may be in the range between 55 degrees and 70 degrees. If the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P is less than 50 degrees, the width W3 of the first convex portion 4151P may increase, and thus reliability problems may occur during the filling process of the molding layer. In addition, if the inclination angle θ of the outer surface 4151PS2 of the first convex portion 4151P exceeds 75 degrees, the rigidity of the first convex portion 4151P may decrease, or the vertical length T1 of the first convex portion 4151P may increase.

[0270] Fig.19 is a plan view for explaining the tolerance (SRR: Solder Resist Registration) according to the comparative example, Fig. 20 is a diagram for explaining tolerance according to the sixth embodiment.

[0271] refer to Fig.19(a), in the control example, the first pad 21 includes a first portion 21a exposed by the first through hole 31 of the protective layer 30 and a second portion 21b covered with the protective layer 30. At this time, in the control example, the protective layer 30 is exposed and developed to form the first through hole 31. At this time, the protective layer 30 has an exposure resolution much lower than the DFR. Therefore, in the control example, it can be confirmed that the center 21C of the first pad 21 is not aligned with the center 31C of the first through hole 31 by a first tolerance d1. Specifically, in the control example, the first tolerance d1 between the center 21C of the first pad 21 and the center 31C of the first through hole 31 exceeds 12.5μm, or exceeds 14μm, or exceeds 15μm. Therefore, in the control example, an alignment reliability problem in which at least a portion of the first through hole 31 does not overlap vertically with the first pad 21 may occur.

[0272] refer to Fig.19 (b), in the control example, the second pad 22 is completely exposed through the second through hole 32 of the protective layer 30. At this time, in the control example, the protective layer 30 is exposed and developed to form the second through hole 32. At this time, the protective layer 30 has an exposure resolution much lower than the DFR. Therefore, in the control example, it can be confirmed that the center 22C of the second pad 22 is not aligned with the center 32C of the second through hole 32 by a second tolerance d2. Specifically, in the control example, the second tolerance d2 between the center 22C of the second pad 22 and the center 32C of the second through hole 32 exceeds 12.5μm, or exceeds 14μm, or exceeds 15μm. Therefore, in the control example, an alignment reliability problem may occur in which at least a portion of the upper surface of the second pad 22 is covered by the protective layer 30.

[0273] In contrast, the embodiment can significantly reduce the tolerance compared to the control example.

[0274] For example, refer to Fig. 20(a), in the case of the embodiment, the first pad 4120-1 includes a first portion 4120-1a exposed by the first through hole 4151 of the first protective layer 4150 and a second portion 4120-1b covered by the first protective layer 4150. At this time, in the embodiment, in order to form the first through hole 4151, a resist pattern DFR1-F formed by DFR is used instead of exposing and developing the first protective layer 4150. Therefore, in the embodiment, it can be confirmed that the center 4120-1C of the first pad 4120-1 and the center 4151C of the first through hole 4151 are misaligned by a third tolerance D1, which is significantly reduced compared to the first tolerance d1 of the control example. Specifically, the third tolerance D1 between the center 4120-1C of the first pad 4120-1 of the embodiment and the center 4151C of the first through hole 4151 is less than 10μm, or less than 9μm, or less than 8μm. Therefore, the embodiment can improve the alignment accuracy between the first through hole 4151 and the first pad 4120-1. Thus, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board.

[0275] In addition, refer to Fig. 20 (b), in the case of the embodiment, the second pad 4120-2 is completely exposed through the second through hole 4152 of the first protective layer 4150. At this time, in the embodiment, in order to form the second through hole 4152, a resist pattern DFR1-F formed by DFR is used instead of exposing and developing the first protective layer 4150. Therefore, in the embodiment, it can be confirmed that the center 4120-2C of the second pad 4120-2 is misaligned with the center 4152C of the second through hole 4152 by a fourth tolerance D2, which is significantly reduced compared to the second tolerance d2 of the control example. Specifically, the fourth tolerance D2 between the center 4120-2C of the second pad 4120-2 of the embodiment and the center 4152C of the second through hole 4152 is less than 10 μm, or less than 9 μm, or less than 8 μm. Therefore, the embodiment can improve the alignment accuracy between the second through hole 4152 and the second pad 4120-2. Thus, embodiments may further improve the electrical reliability and / or physical reliability of a circuit board.

[0276] Fig.21 is a sectional view showing a circuit board according to a seventh embodiment.

[0277] refer to Fig.21The circuit board according to the seventh embodiment includes an insulating layer 4210, an upper wiring electrode 4220, a lower wiring electrode 4230, a via electrode 4240, a first protective layer 4250, and a second protective layer 4260. The upper wiring electrode 4220, the lower wiring electrode 4230, and the via electrode 4240 include first metal layers 4221, 4231, 4241 and second metal layers 4222, 4232, and 4242, respectively.

[0278] At this time, the inner surface of the through hole in the sixth embodiment has a substantially vertical slope relative to the upper surface of the insulating layer. Differently, the inner surface of the through hole in the seventh embodiment may have an inclined surface relative to the upper surface of the insulating layer.

[0279] For example, the upper wiring electrode 4220 includes a first pad 4220-1 and a second pad 4220-2. In addition, the first protection layer 4250 includes a first through hole 4251 vertically overlapping the first pad 4220-1. In addition, the first protection layer 4250 includes a second through hole 4252 vertically overlapping the second pad 4220-2.

[0280] At this time, the basic structure of the first through hole 4251 and the second through hole 4252 is the same as that of the sixth embodiment, and a detailed description thereof is omitted.

[0281] The width of the first through hole 4251 may vary from the upper surface to the lower surface of the first protective layer 4250. For example, the first inner surface 4251S of the first protective layer 4250 may have a slope whose width decreases toward the downward direction. That is, in the seventh embodiment, the photosensitive film used to form the first through hole 4251 is a negative type, and the resist pattern DFR1-F may be formed using the negative photosensitive film. Therefore, the resist pattern DFR1-F may have a shape whose width decreases toward the downward direction. In addition, the first inner surface 4251S of the first through hole 4251 of the first protective layer 4250 formed by the resist pattern DFR1-F may have a slope whose width decreases toward the downward direction. The negative photosensitive film has the characteristic that the unexposed portion is developed and removed when exposed and developed.

[0282] Accordingly, the second inner surface 4252S of the second through hole 4252 of the first protection layer 4250 may also have a slope whose width decreases toward the downward direction.

[0283] At this time, the embodiment does not include undercuts in the first inner surface 4251S and the second inner surface 4252S. Therefore, each of the first inner surface 4251S and the second inner surface 4252S has a slope in which the width decreases from the upper end to the lower end. At this time, the first through hole 4251 and the second through hole 4252 only include a slope in which the width decreases from the upper end to the lower end of the first inner surface 4251S and the second inner surface 4252S, respectively, without including a slope that keeps the width unchanged or a slope that increases the width. That is, a slope that keeps the width unchanged or a slope that increases the width may mean an undercut. In addition, since the embodiment does not include an undercut, each of the first inner surface 4251S and the second inner surface 4252S of the first through hole 4251 and the second through hole 4252 may only include a slope that decreases the width, and may not include a slope that keeps the width unchanged or increases the width. At this time, the embodiment forms a through hole in the first protective layer 4250 using a negative photosensitive film as described above. Thus, the embodiment can ensure smooth removal of the resist pattern DFR1-F during removal of the resist pattern DFR1-F after forming a through hole in the first protective layer 4250. Thus, the embodiment can solve the problem of separation of the first protective layer 4250 from the insulating layer 4210 during removal of the resist pattern DFR1-F.

[0284] The first protective layer 4250 includes a first convex portion 4251P surrounding an upper portion of the first through hole 4251. In addition, the inclined surface of the inner surface of the first convex portion 4251P may have a slope corresponding to the slope of the first inner surface 4251S of the first through hole 4251. In addition, the inclined surface of the inner surface of the first convex portion 4251P may indicate a portion horizontally overlapped with the first convex portion 4251P, and the first inner surface 4251S of the first through hole 4251 may indicate an area horizontally overlapped with the second region R2 of the first protective layer 4250.

[0285] The first protection layer 4250 includes a second convex portion 4252P surrounding an upper portion of the second through hole 4252. In addition, an inner surface of the second convex portion 4252P may have a slope corresponding to a slope of the second inner surface 4252S of the second through hole 4252.

[0286] Fig. 22 is a sectional view showing a circuit board according to an eighth embodiment.

[0287] refer to Fig. 22 The circuit board of the eighth embodiment includes an insulating layer 4310, an upper wiring electrode 4320, a lower wiring electrode 4330, a via electrode 4340, a first protective layer 4350, and a second protective layer 4360. The upper wiring electrode 4320, the lower wiring electrode 4330, and the via electrode 4340 include first metal layers 4321, 4331, and 4341 and second metal layers 4322, 4332, and 4342, respectively.

[0288] At this time, the inner surface of the through hole in the sixth embodiment has a substantially vertical slope relative to the upper surface of the insulating layer, and the inner surface of the through hole in the seventh embodiment has a slope whose width decreases in the downward direction. In addition, the inner surface of the through hole of the eighth embodiment may have a slope whose width increases in the downward direction.

[0289] For example, the upper wiring electrode 4320 includes a first pad 4320-1 and a second pad 4320-2. In addition, the first protection layer 4350 includes a first through hole 4351 vertically overlapping the first pad 4320-1. In addition, the first protection layer 4350 includes a second through hole 4352 vertically overlapping the second pad 4320-2.

[0290] The width of the first through hole 4351 may change from the upper surface to the lower surface of the first protective layer 4350. For example, the first inner surface 4351S of the first protective layer 4350 may have a slope whose width increases toward the downward direction. That is, in the eighth embodiment, the photosensitive film used to form the first through hole 4351 is a positive type, and the resist pattern DFR1-F may be formed using the positive type photosensitive film. Thus, the resist pattern DFR1-F may have a shape whose width increases toward the downward direction. In addition, the first inner surface 4351S of the first through hole 4351 of the first protective layer 4350 formed by the resist pattern DFR1-F may have a slope whose width increases toward the downward direction. The positive type photosensitive film has the characteristic that the portion that has received light during exposure and development is developed and removed.

[0291] Accordingly, the second inner surface 4352S of the second through hole 4352 of the first protective layer 4350 may have a slope with a width increasing toward the downward direction. At this time, in the eighth embodiment, since the width of the through hole increases toward the downward direction, when a connection portion such as a solder ball is provided in the through hole, the through hole may be used as an anchor. Thus, the embodiment may improve the bonding performance with the connection portion.

[0292] In addition, the first protective layer 4350 includes a first convex portion 4351P surrounding an upper portion of the first through hole 4351. In addition, an inner surface of the first convex portion 4351P may have a slope corresponding to a slope of the first inner surface 4351S of the first through hole 4351.

[0293] In addition, the first protection layer 4350 includes a second convex portion 4352P surrounding an upper portion of the second through hole 4352. In addition, an inner surface of the second convex portion 4352P may have a slope corresponding to a slope of the second inner surface 4352S of the second through hole 4352.

[0294] Fig.23 are diagrams showing various modified examples of the circuit board according to the embodiment.

[0295] In the circuit board of the sixth embodiment, the first convex portion 4151P formed in the first region R1 of the first protective layer 4150 partially overlaps the first pad 4120 - 1 in the vertical direction.

[0296] On the contrary, reference Fig.23 (a), the entire area of ​​the first convex portion 4151P1 formed in the first region R1 of the first protective layer 4150 may vertically overlap the first pad 4120-1. For example, the boundary between the first region R1 and the second region R2 of the first protective layer 4150 may vertically overlap the first pad 4120-1.

[0297] In addition, refer to Fig.23 (b), the first convex portion 4151P2 formed in the first region R1 of the first protective layer 4150 may have a sub-convex portion 4151PC formed in a region vertically overlapping an edge region of the first pad 4120-1. The sub-convex portion 4151PC may be a portion protruding due to the height of the first pad 4120-1 during the application of the first protective layer 4150.

[0298] Meanwhile, the convex portion in the previous embodiment has an inclined surface with a certain slope. For example, the convex portion in the previous embodiment has a shape in which the width changes from the upper side to the lower side. For example, the height of the first region R1 of the first protective layer 4150 gradually decreases toward the second region R2.

[0299] In contrast, reference Fig.23 (c), the first convex portion 4151P3 formed in the first region R1 of the first protective layer 4150 may have a shape whose width does not change. For example, the upper surface of the first region R1 of the first protective layer 4150 may not have a height change. For example, the vertical cross-sectional shape of the first convex portion 4151P3 may have a rectangular shape.

[0300] At the same time, despite Fig.23 The modified example of the first convex portion is described, but the second convex portion and the third convex portion in the sixth embodiment may also be modified to have the same structure.

[0301] Fig.24 is a cross-sectional view showing a semiconductor package according to another embodiment, Fig.25 : is a graph showing the arrangement reliability of the first connection portion of the embodiment and the comparative example.

[0302] refer to Fig.24 and Fig.25 , the semiconductor package of another embodiment may have a POP (Package on Package) structure.

[0303] The first connection portion 4410 is provided on the circuit board. In addition, the semiconductor chip 4420 is mounted on the first connection portion 4410. The terminal 4425 of the semiconductor chip 4420 is connected to the wiring electrode of the circuit board through the first connection portion 4410.

[0304] At this time, refer to Fig.25 (a), in the first comparative example, a through hole is formed in the protective layer 30 having the same thickness T2 as the thickness of the first protective layer of the present invention, and a certain amount of solder balls SB are set in the through hole. At this time, in the first comparative example, since the thickness T2 of the protective layer is relatively small, the diffusion of the solder balls SB cannot be effectively prevented. Therefore, in the first comparative example, the diffusion degree of the solder balls SB is large, and therefore, the width W4 of the solder balls SB is relatively large. In addition, as the diffusion of the solder balls SB in the first comparative example increases, the thickness T3 of the solder balls SB also appears to be relatively low.

[0305] In addition, refer to Fig.25 (b), in the second control example, a through hole is formed in the protective layer 30 having a thickness T2-1 greater than the thickness of the first protective layer of the present invention and the protective layer 30 of the first control example, and a certain amount of solder balls SB are set in the through hole. At this time, in the second control example, the thickness T2-1 of the protective layer is greater than the thickness T2 of the protective layer of the first control example, and therefore, the diffusion of the solder balls SB can be prevented to a certain extent. However, even if the thickness T2-1 of the protective layer 30 is increased as in the second control example, it can be confirmed that the diffusion of the solder balls SB occurs, and therefore, it can be confirmed that the width W4-1 caused by the diffusion of the solder balls SB is greater than the through hole of the protective layer 30. Therefore, it can be confirmed that the thickness T3-1 of the solder balls SB of the second control example increases compared to the first control example, but does not have the target thickness. In addition, in the second control example, since the entire area of ​​the protective layer 30 has the thickness T2-1, the fluidity of the EMC may be reduced during the EMC filling for forming the molding layer, and therefore, an area where the EMC is not filled may appear.

[0306] On the contrary, reference Fig.25 (c) The protective layer 4150 of the embodiment forms a protruding portion 4150P adjacent to the through hole on the upper surface to have a thickness T2 of the protective layer 30 of the first comparative example.

[0307] Therefore, the embodiment can confirm that the width W4-2 of the first connection portion 4410 corresponds to the width of the through hole due to the protrusion portion 4150P. Thus, the embodiment can effectively reduce the pitch between the plurality of first connection portions.

[0308] In addition, the embodiment can confirm that the height of the first connection portion 4410 is maintained by the convex portion 4150P. Thus, it is confirmed that the first connection portion 4410 is set to a greater thickness T3-2 than the first and second comparative examples even when the same amount of solder is applied.

[0309] In addition, the semiconductor package may include an underfill 4430. The underfill 4430 may be provided to cover the periphery of the semiconductor chip 4420 on the circuit board. However, the underfill 4430 may be optionally omitted. For example, when the underfill 4430 is omitted, the semiconductor package may perform the function of the underfill 4430 in the molding layer 4450.

[0310] The semiconductor package may include a second connection portion 4440. The second connection portion 4440 is disposed on a wiring electrode of a circuit board. The second connection portion 4440 may be a bump. As an example, the second connection portion 4440 may be a solder bump, but is not limited thereto. For example, the second connection portion 4440 may be a column bump. For example, the second connection portion 4440 may include a copper column and a solder bump disposed on the copper column. The upper surface of the second connection portion 4440 may be positioned higher than the upper surface of the semiconductor chip 4420. This may prevent the semiconductor device 4420 from being damaged during the process of bonding the external substrate 4500 disposed on the second connection portion 4440.

[0311] The semiconductor package may include a molding layer 4450. The molding layer 4450 may mold a component disposed on the circuit board. The molding layer 4450 may include an opening. For example, the molding layer 4450 may include an opening that overlaps with an upper surface of the second connection portion 4440 in a vertical direction.

[0312] The semiconductor package includes a third connection portion 4460 .

[0313] The third connection portion 4460 may be disposed under the wiring electrode disposed at the lowermost side of the circuit board. The third connection portion 4460 may be solder for connecting the semiconductor package of the embodiment to a separate external substrate (eg, a main board of an electronic device), but is not limited thereto.

[0314] The semiconductor package includes an external substrate 4500. The external substrate 4500 may represent a separate substrate coupled to the circuit board of the embodiment. For example, the semiconductor chip 4420 provided on the circuit board may be a logic chip such as a CPU or a GPU, and the external substrate 4500 may represent a memory substrate where a memory chip connected to the logic chip is located. The external substrate 4500 may be an interposer connected between the memory substrate and the circuit board, and a semiconductor chip 4420 corresponding to the memory chip is provided on the memory substrate.

[0315] The external substrate 4500 may include an insulating layer 4510, a circuit layer 4520, a through electrode 4530, an upper protective layer 4540, and a lower protective layer 4550. In addition, the external substrate 4500 may include a fourth connection portion 4560. The fourth connection portion 4560 may be disposed between the external substrate 4500 and the third connection portion 4440.

[0316] In addition, the semiconductor package may include a fifth connection portion 4570 . The fifth connection portion 4570 may be provided on the external substrate 4500 .

[0317] The semiconductor package may include a semiconductor chip 4580 . The semiconductor chip 4580 may be mounted on the external substrate 4500 through the fifth connection portion 4570 .

[0318] Figure 26a to Figure 26h It is described in the process sequence. Fig.10 A cross-sectional view of the circuit board method is shown.

[0319] refer to Fig.26a In an embodiment, an insulating layer 4110 is prepared. Thereafter, an embodiment forms a through hole VH passing through the upper and lower surfaces of the insulating layer 4110 .

[0320] Next, refer to Figure 26b , embodiments may form a via electrode 4140 filling the through hole VH on the insulating layer 4110. In addition, embodiments may form an upper wiring electrode 4120 including a first pad 4120-1 and a second pad 4120-2 on the upper surface of the insulating layer 4110. In addition, embodiments may form a lower wiring electrode 4130 on the lower surface of the insulating layer 4110.

[0321] Afterwards, refer to Fig.26c , the embodiment forms a first dry film DFR1 on the insulating layer 4110. At this time, the first dry film DFR1 may be provided to completely cover the upper wiring electrode 4120. In addition, the embodiment forms a second dry film DFR2 under the insulating layer 4110. At this time, the second dry film DFR2 may be provided to completely cover the lower wiring electrode 4130.

[0322] Next, refer to Fig.26d, the embodiment may perform a process of forming the first exposure pattern ER1 by exposing and curing the first dry film DFR1. At this time, the first dry film DFR1 may be a negative type. Therefore, the unexposed portion may be removed by subsequent development, and the exposed first exposure pattern ER1 may not be removed. In addition, the embodiment may perform a process of forming the second exposure pattern ER2 by exposing and curing the second dry film DFR2. At this time, the second dry film DFR2 may be a negative type. Therefore, the unexposed portion may be removed by subsequent development, and the exposed second exposure pattern ER2 may not be removed.

[0323] Next, refer to Fig.26e , the embodiment may perform a process of forming a first resist pattern DFR1-F by removing an area of ​​the first dry film DFR1 except the first exposure pattern ER1. At this time, the first resist pattern DFR1-F may be formed on the insulating layer 4110 to correspond to an area where a through hole of the first protective layer 4150 is to be formed. In addition, the embodiment may perform a process of forming a second resist pattern DFR2-F by removing an area of ​​the second dry film DFR2 except the second exposure pattern ER2. At this time, the second resist pattern DFR2-F may be formed on the insulating layer 4110 to correspond to an area where a through hole of the second protective layer 4160 is to be formed.

[0324] Next, refer to Figure 26f , embodiments may form a first protective layer 4150R covering the first resist pattern DFR1-F on the insulating layer 4110. In addition, embodiments may form a second protective layer 4160R covering the second resist pattern DFR2-F under the insulating layer 4110.

[0325] Next, refer to Figure 26g , embodiments may perform a process of reducing the thickness of the first protective layer 4150R to a target thickness by removing the first protective layer 4150R by etching.

[0326] The etching process may be performed using an organic alkaline compound including tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0327] In addition, the embodiment can perform a process of reducing the thickness of the second protective layer 4160R to a target thickness by etching away the second protective layer 4160R. At this time, the embodiment controls the etching conditions in the region adjacent to the first resist pattern DFR1-F and the region adjacent to the second resist pattern DFR2-F. For example, the embodiment controls the etching degree of the first protective layer 4150R in the region adjacent to the first resist pattern DFR1-F. Thus, the first protective layer 4150R may include a raised portion 4150P formed adjacent to the first resist pattern DFR1-F. Accordingly, the embodiment controls the etching degree of the second protective layer 4160R in the region adjacent to the second resist pattern DFR2-F. Thus, the second protective layer 4160R may include a raised portion 4160P formed adjacent to the second resist pattern DFR2-F.

[0328] Next, refer to Figure 26h , the embodiment may perform a process of removing the first resist pattern DFR1-F and the second resist pattern DFR2-F. Therefore, the embodiment may form a through hole and a convex portion corresponding to the first resist pattern DFR1-F and the second resist pattern DFR2-F in the first protective layer 4150 and the second protective layer 4160, respectively.

[0329] Hereinafter, a method of manufacturing a semiconductor package according to another embodiment is described.

[0330] Figures 27a to 27n is a cross-sectional view of a method for manufacturing a circuit board according to another embodiment in a process sequence. The embodiment described below is similar to Figure 1a However, the position of the cavity C and the number of insulating layers in the circuit board described below may be different from Figure 1a The circuit board shown in is different.

[0331] refer to Fig.27a , the embodiment prepares an insulating layer 5110. An insulating layer 5110 may correspond to Figure 1a The third insulating layer 110a of the first embodiment.

[0332] Thereafter, the embodiment may perform a process of forming an electrode portion on the one-layer insulating layer 5110. For example, the embodiment may perform a process of forming a wiring electrode 5140a on each of the upper surface and the lower surface of the one-layer insulating layer 5110, a process of forming a via electrode 5140b passing through the one-layer insulating layer 5110, and a process of forming an insulating member 5110d surrounded by the via electrode 5140b.

[0333] refer to Figure 27b , embodiments may perform a process of forming a cavity C through a layer of insulating layer 5110. For example, Figure 1a The cavity C in the first embodiment is disposed in the second insulating layer 110b1. In contrast, the cavity C in another embodiment may be disposed in an insulating layer 5110, which is a third insulating layer disposed in the center. Figure 27b 51 is shown as being disposed to pass through a layer of the insulating layer 5110 , but the embodiment is not limited thereto, and the cavity C may have a groove shape that does not pass through the insulating layer 5110 .

[0334] refer to Fig.27c , embodiments may perform a process of attaching a carrier film CB to a lower portion of the insulating layer 5110. The carrier film CB may be provided to cover a lower portion of the cavity C of the insulating layer 5110.

[0335] refer to Fig.27d , embodiments may perform a process of attaching the connection member 5200 on the carrier film CB vertically overlapping the cavity C.

[0336] refer to Fig.27e , embodiments may stack a stacked insulating layer (eg, an upper insulating layer) filling the cavity C on the insulating layer 5110 .

[0337] refer to Figure 27f , embodiments may perform a process of removing the carrier film CB.

[0338] refer to Figure 27g , the embodiment may stack an additional stacked insulating layer below the insulating layer 5110. For example, the embodiment may perform a process of stacking a lower insulating layer. In this case, the number of layers of the upper insulating layer and the lower insulating layer may be different. For example, Figure 27h As shown in , the number of layers of the upper insulating layer may be smaller than the number of layers of the lower insulating layer.

[0339] refer to Figure 27h , the embodiment may perform a process of forming a wiring electrode and a via electrode in the upper insulating layer and the lower insulating layer, respectively. At this time, a first electrode portion 5141 and a second electrode portion 5142 may be formed in the upper insulating layer, the first electrode portion 5141 including a first pad 5141a and a first via electrode 5141b overlapping the connection member 5200 in a vertical direction, and the second electrode portion 5142 including a second pad 5142a and a second via electrode 5142b that do not overlap the connection member 5200 in a vertical direction.

[0340] refer to Fig.27i , embodiments may perform a process of forming a dry film DF1 covering the first pad 5141a and the second pad 5142a on the upper insulating layer of the insulating layer 5110.

[0341] refer to Figure 27j, the embodiment may perform a process of exposing and developing the dry film DF1 to form an exposure pattern at a position in the protective layer corresponding to the position where the first through hole and the second through hole are to be formed. At this time, the upper surface of the exposure pattern and the lower surface of the exposure pattern may have substantially the same width, and further, the width of the upper surface of the exposure pattern and the lower surface of the exposure pattern may be less than 20 μm, respectively.

[0342] refer to Figure 27k , embodiments may perform a process of forming a first protective layer 5120 covering the exposure pattern on the upper insulating layer.

[0343] refer to Figure 27l , embodiments may perform a process of removing the first protective layer 5120 by etching, thereby allowing an upper surface of the first protective layer 5120 to have a height lower than an upper surface of the exposure pattern.

[0344] refer to Figure 27m , the embodiment may perform a process of removing the exposure pattern. Therefore, the embodiment may form a through hole TH in the first protective layer 5120 corresponding to the position where the exposure pattern is removed.

[0345] refer to Figure 27n , embodiments may perform a process of forming a first bonding portion 5151 and a second bonding portion 5152 in the through hole of the first protective layer 5120. For example, embodiments may form a first bonding portion 5151 including a first through portion 5151a and a first protruding portion 5151b that overlap with the connection member 5200 in a vertical direction. In addition, embodiments may form a second bonding portion 5152 including a second through portion 5152a and a second protruding portion 5152b that do not overlap with the connection member 5200 in a vertical direction.

[0346] On the other hand, when the circuit board having the above-mentioned features of the present invention is used for IT equipment or household appliances (such as smart phones, server computers, TVs, etc.), functions such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present invention performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or pollutants, or alternatively, it can solve the problems of leakage current, electrical short circuit and electrical open circuit of the terminals provided to the semiconductor chip. In addition, when the signal transmission function is dominant, the noise problem can be solved. Thus, the circuit board having the above-mentioned features of the present invention can maintain the stable function of IT equipment or household appliances, so that the entire product and the circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0347] When the circuit board having the above-mentioned features of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or alternatively, the safety of the transportation device can be further improved by safely protecting the semiconductor chip controlling the transportation device from external influences and solving the problem of leakage current or electrical short circuit between terminals provided to the semiconductor chip or electrical open circuit of the terminals. Therefore, the transportation device and the circuit board to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0348] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, a person skilled in the art to which the embodiments belong may even combine or modify the characteristics, structures and effects shown in each embodiment relative to other embodiments. Therefore, it should be understood that the contents related to such combination and such modification are included within the scope of the embodiments.

[0349] The above description has focused on the embodiments, but it is merely illustrative and does not limit the embodiments. It will be appreciated by those skilled in the art that various modifications and applications not shown above are possible without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A semiconductor package, comprising: an insulating layer, the insulating layer comprising an upper surface and a lower surface; A protective layer, the protective layer being arranged on an upper surface of the insulating layer; a connecting member, wherein the connecting member is embedded in the insulating layer; as well as a wiring electrode embedded in the insulating layer and comprising: an upper pad portion, the upper pad portion being disposed between the insulating layer and the protective layer; a first via electrode electrically connected to the connection member by passing through a portion of the insulating layer from the upper pad portion and having a width narrower than a width of the upper pad portion; a second via electrode embedded in the insulating layer and disposed closer to a lower surface of the insulating layer than the connecting member; and a bonding portion, the bonding portion including a protruding portion provided on the protective layer and a through portion passing through the protective layer from the protruding portion and directly contacting the upper pad portion, wherein the engaging portion includes a first engaging portion overlapping with the connecting member in a vertical direction and a second engaging portion not overlapping with the connecting member in the vertical direction, The inclination angle of each of the through portion of the first joint portion and the through portion of the second joint portion relative to the upper surface of the insulating layer is closer to vertical than the inclination angle of the second via electrode relative to the upper surface of the insulating layer.

2. The semiconductor package according to claim 1, wherein The first engaging portion is provided as a plurality of first engaging portions, The horizontal distance between two first bonding portions closest to each other among the plurality of first bonding portions is less than 26 μm.

3. The semiconductor package according to claim 2, wherein: Each of the plurality of first engaging portions includes a plurality of first protruding portions, Here, each of the plurality of first protrusions has a width in a horizontal direction of 29 μm to 34 μm.

4. The semiconductor package according to claim 1, wherein: The protective layer includes a plurality of first fillers, The through portion of the first joint portion does not contact the plurality of first fillers.

5. The semiconductor package according to claim 1, wherein The first via electrode includes a first overlapping via electrode overlapping the connecting member in a vertical direction, The inclination angle of the first overlapping via electrode is the same as the inclination angle of the through portion of the first bonding portion.

6. The semiconductor package according to claim 1, wherein The insulating layer includes a plurality of stacked insulating layers disposed between an upper surface of the insulating layer and a lower surface of the insulating layer, wherein the plurality of stacked insulating layers include an upper insulating layer forming an upper surface of the insulating layer and a lower insulating layer forming a lower surface of the insulating layer, The wiring layer further includes a plurality of wiring electrodes respectively arranged in the plurality of stacked insulating layers, a plurality of via electrodes connecting the plurality of wiring electrodes, and a lower pad portion arranged on the lower surface of the insulating layer. The plurality of via electrodes further include a plurality of upper vias and a plurality of lower vias, the plurality of upper vias overlap with the connecting member in a horizontal direction, and the plurality of lower vias are arranged between the plurality of upper vias and the lower surface of the insulating layer. Wherein, the inclination angle of the upper via hole is symmetrical with the inclination angle of the lower via hole.

7. The semiconductor package according to claim 6, wherein: The thickness of the upper insulating layer is thinner than that of the lower insulating layer.

8. The semiconductor package according to claim 7, wherein: The first through portion of the first bonding portion vertically overlaps at least a portion of the first overlapping via electrode.

9. The semiconductor package according to claim 1, wherein: The insulating layer includes a side surface between an upper surface and a lower surface, The protective layer includes a lower surface facing the upper surface of the insulating layer, an upper surface corresponding to the lower surface, and a side surface located between the lower surface and the upper surface. The side surface of the protective layer includes an inner surface surrounding the first through portion and the second through portion respectively and an outer surface adjacent to the side surface of the insulating layer. Wherein, the length of the inner surface in the vertical direction is different from the length of the outer surface in the vertical direction.

10. The semiconductor package according to claim 9, wherein The length of the inner surface in the vertical direction is greater than the length of the outer surface in the vertical direction.

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