Wiring board and mounting structure using wiring board

Abstract

A wiring board according to the present disclosure includes: a first insulating layer having a first surface; and a conductor layer located on the first surface. The first insulating layer includes an insulating resin and a plurality of insulating particles dispersed in the insulating resin. The plurality of insulating particles include first insulating particles having, on the first surface, a first region exposed from the insulating resin and a second region other than the first region in a plan view of the first surface. The conductor layer is located on the surface of the first region and the surface of the insulating resin, and is not located below the first region and between the second region and the insulating resin.

Description

Technical Field

[0001] The present invention relates to a wiring substrate and a mounting structure using the wiring substrate. Background Art

[0002] Conventionally, for the purpose of reducing the thermal expansion coefficient of the insulating layer, inorganic fillers (insulating particles) such as silicon dioxide and aluminum oxide are dispersed in the insulating layer included in the wiring substrate, as described in Patent Document 1. As shown in Patent Document 1, a part of the inorganic filler is sometimes exposed from the surface of the insulating layer.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-30289 Summary of the invention

[0006] -Methods for solving problems-

[0007] The wiring substrate involved in the present disclosure comprises: a first insulating layer having a first surface; and a conductor layer located on the first surface. The first insulating layer comprises an insulating resin and a plurality of insulating particles dispersed in the insulating resin. The plurality of insulating particles include first insulating particles, and when the first surface is viewed from above, the first insulating particles have a first region exposed from the insulating resin and a second region other than the first region on the first surface. The conductor layer is located on the surface of the first region and the surface of the insulating resin, and is not located below the first region and between the second region and the insulating resin.

[0008] Furthermore, a mounting structure according to the present disclosure includes the above-mentioned wiring substrate and an electronic component located in a mounting region of the wiring substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view showing a wiring substrate according to one embodiment of the present disclosure.

[0010] Figure 2 It is used to illustrate Figure 1 An enlarged cross-sectional view of region X (main part).

[0011] Figure 3 It is an enlarged cross-sectional view for explaining other main parts of the wiring substrate involved in one embodiment of the present disclosure.

[0012] Figure 4 This is an explanatory diagram for explaining one embodiment of a method for forming a conductor layer on a first surface of a first insulating layer in a wiring substrate according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0013] Usually, the conductor layer is located on the surface of the insulating layer. When there is an inorganic filler exposed from the surface of the insulating layer, as shown in Patent Document 1, the conductor layer also exists in the gap between the portion of the exposed inorganic filler in which the insulating layer is buried and the insulating layer. When the inorganic filler and the conductor layer are weakly bonded, when the conductor layer exists on the inorganic filler, expansion and peeling of the conductor layer may occur sometimes. Therefore, it is required that the insulating layer and the conductor layer have excellent adhesion on the surface of the insulating layer where insulating particles are dispersed.

[0014] The wiring board according to the present disclosure has the structure described in the section of means for solving the above-mentioned problems, so that the insulating layer and the conductor layer have excellent adhesion on the surface of the insulating layer in which the insulating particles are dispersed.

[0015] based on Figure 1 to Figure 3 The wiring substrate according to one embodiment of the present disclosure will be described. Figure 1 As shown, a wiring board 1 according to one embodiment includes a first insulating layer 11 , a second insulating layer 13 , and a conductive layer 12 . Figure 1 It is a cross-sectional view showing a wiring board 1 according to one embodiment.

[0016] In a wiring substrate 1 according to an embodiment, Figure 1 As shown in FIG. 1 , the first insulating layer 11 corresponds to the insulating layer for build-up. Figure 2 As shown, the first insulating layer 11 has a structure in which insulating particles 14 are dispersed. Figure 2 It is used to illustrate Figure 1 The first insulating layer 11 is not particularly limited as long as it is an insulating resin 111. Examples of the insulating resin 111 include epoxy resins, bismaleimide-triazine resins, polyimide resins, polyphenylene ether resins, and liquid crystal polymers. The insulating resin 111 may be used alone or in combination of two or more.

[0017] Although not shown, the first insulating layer 11 may further include a reinforcing material. Examples of the reinforcing material include insulating fabrics such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. The thickness of the first insulating layer 11 is not particularly limited, and is, for example, 2 μm or more and 100 μm or less.

[0018] The plurality of insulating particles 14 dispersed in the first insulating layer 11 have the function of reducing the thermal expansion coefficient of the first insulating layer 11. The insulating particles 14 are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. The insulating particles 14 may be used alone or in combination of two or more.

[0019] The average particle size of the insulating particles 14 is not limited. The insulating particles 14 may have an average particle size of, for example, 0.1 μm or more and 2 μm or less, or 1 μm or less. The filling rate of the insulating particles 14 in the first insulating layer 11 is not limited. In order to make the thermal expansion coefficient of the first insulating layer 11 sufficiently small, the filling rate of the insulating particles 14 in the first insulating layer 11 may be 50 volume % or more and 90 volume % or less.

[0020] If the filling rate of the insulating particles 14 is 50% by volume or more and 90% by volume or less, the contact portion between the conductor layer 12 (seed layer 121) and the insulating particles 14 (second insulating particles 14b) described later increases. As a result, the portion having the amorphous structure 16 described later increases, and the conductor layer 12 (seed layer 121) and the insulating particles 14 can be more firmly in contact. The average particle size of the insulating particles 14 can also be calculated by processing an electron microscope-based camera image of the insulating particles 14 within a given range, for example. The filling rate can also be detected by energy dispersive X-ray analysis.

[0021] Some of the insulating particles 14 are first insulating particles 14a. Figure 2 As shown, the first insulating particle 14 a has a first region 141 exposed from the insulating resin 111 and a second region 142 excluding the first region 141 on the first surface 11 a of the first insulating layer 11 .

[0022] The top of the first region 141 is located farther from the second insulating layer 13 than the insulating resin 111 closest to the first region 141. The first surface 11a of the first insulating layer 11 corresponds to a main surface farther from the center portion in the thickness direction of the wiring substrate 1. Figure 1 In the figure, the first surface 11 a of the first insulating layer 11 corresponds to a main surface which is away from a second insulating layer 13 which will be described later.

[0023] like Figure 1 As shown in FIG. 1 , the conductor layer 12 is located on the first surface 11a of the first insulating layer 11. Figure 2 As shown, on the first surface 11 a of the first insulating layer 11 , the conductive layer 12 is located on the first region 141 of the first insulating particles 14 a and on the surface of the insulating resin 111 .

[0024] The conductor layer 12 is not limited as long as it is a conductor. Examples of the conductor include metals such as copper. The conductor layer 12 is specifically formed by metal plating such as copper plating. The thickness of the conductor layer 12 is not particularly limited, and for example, the thickest part is 2 μm or more and 50 μm or less.

[0025] like Figure 2As shown in FIG. 1 , the conductor layer 12 may also include a seed layer 121, which covers the first region 141 of the first insulating particle 14a and the surface of the insulating resin 111. The seed layer 121 is formed for the purpose of improving the adhesion of the conductor layer 12 or as a base metal for conduction when the conductor layer 12 is formed on an insulator by electrolytic plating. The seed layer 121 is formed of, for example, a transition metal of the 4th, 5th, 6th, and 10th groups of the periodic table such as titanium, nickel, and chromium, or an alloy containing these transition metals such as nickel-chromium. The thickness of the seed layer 121 is not particularly limited, and is, for example, not less than 1 nm and not more than 100 nm.

[0026] In order to electrically connect the upper and lower portions of the stacked first insulating layer 11, a via conductor 12V is provided. The via conductor 12V is located in a via hole that penetrates the upper and lower surfaces of the first insulating layer 11. The via conductor 12V is not limited as long as it is made of a metal (conductor) such as copper. The via conductor 12V can be made of any material. Figure 1 The via hole conductor 12V is filled in the via hole as shown, or may be formed only on the inner wall surface of the via hole. The via hole conductor 12V is connected to the conductor layer 12 located on the surface of the first insulating layer 11 .

[0027] In the wiring board 1 according to one embodiment, the conductor layer 12 is not located below the first region 141 of the first insulating particle 14a and between the second region 142 of the first insulating particle 14a and the insulating resin 111. The conductor layer 12 is not located below the first region 141 of the first insulating particle 14a. In other words, the conductor layer 12 does not exist at a position overlapping with the first region 141 in a plan view except for a region where the conductor layer 12 and the first region 141 are in direct contact. That is, the conductor layer 12 is not located below the first insulating particle 14a (on the central portion side in the thickness direction of the wiring board 1).

[0028] When the conductor layer 12 is located below the first region 141 of the first insulating particle 14a, for example, under high temperature conditions, the conductor layer 12 may thermally expand and push up the conductor layer 12 above the first insulating particle 14a via the first insulating particle 14a to cause expansion. When the conductor layer 12 is located between the second region 142 of the first insulating particle 14a and the insulating resin 111, the first insulating particle 14a is easily detached from the insulating resin 111. Therefore, expansion and peeling of the conductor layer 12 may occur. Therefore, in the wiring substrate 1 according to an embodiment in which the conductor layer 12 is not located below the first region 141 of the first insulating particle 14a and between the second region 142 of the first insulating particle 14a and the insulating resin 111, the first insulating layer 11 and the conductor layer 12 have excellent adhesion.

[0029] like Figure 1As shown in FIG. 1 , in the wiring substrate 1 according to one embodiment, the second insulating layer 13 is located substantially in the center in the thickness direction of the wiring substrate 1. Figure 1 As shown, the second insulating layer 13 corresponds to the core insulating layer. Specifically, in the wiring board 1 according to one embodiment, the first insulating layer 11 is located on two second surfaces 13a of the second insulating layer 13. The second surface 13a of the second insulating layer 13 corresponds to the main surface of the second insulating layer 13.

[0030] The second insulating layer 13 is also the same as the first insulating layer 11, and is not particularly limited as long as it is an insulating resin 111. Examples of the insulating resin 111 include epoxy resins, bismaleimide-triazine resins, polyimide resins, polyphenylene ether resins, and liquid crystal polymers. The insulating resin 111 may be used alone or in combination of two or more. The insulating resin 111 included in the second insulating layer 13 may be the same as or different from the insulating resin 111 included in the first insulating layer 11. The thickness of the second insulating layer 13 is not particularly limited, and is, for example, not less than 0.04 mm and not more than 3 mm.

[0031] Although not shown in the figure, the second insulating layer 13 may further include a reinforcing material, insulating particles 14, and the like. Examples of the reinforcing material include insulating fabrics such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more reinforcing materials may be used in combination. Examples of the insulating particles 14 include inorganic insulating fillers such as silicon dioxide, aluminum oxide, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide, as described above. The insulating particles 14 may be used alone or in combination of two or more.

[0032] In order to electrically connect the upper and lower surfaces of the second insulating layer 13, a through-hole conductor 12T is disposed in the second insulating layer 13. The through-hole conductor 12T is located in a through hole that penetrates the upper and lower surfaces of the second insulating layer 13. The through-hole conductor 12T is not limited as long as it is made of a metal (conductor) such as copper. The through-hole conductor 12T can be Figure 1 Although it is shown as being formed only on the inner wall surface of the through hole, it may be filled in the through hole. The through hole conductor 12T is connected to the conductor layer 12 located on the upper and lower surfaces of the second insulating layer 13 .

[0033] In a wiring substrate 1 according to an embodiment, Figure 3 As shown, the conductor layer 12 may include a protrusion 12A protruding toward the insulating resin 111. That is, the protrusion 12A is located in the direction from the first surface 11a to the second insulating layer 13 side. Figure 31 is an enlarged cross-sectional view of another main part of the wiring substrate 1 according to one embodiment. When the conductor layer 12 includes the protrusion 12A, the contact area between the conductor layer 12 and the insulating resin 111 increases, so that the conductor layer 12 is difficult to be peeled off from the first insulating layer 11. The depth of the protrusion 12A from the first surface 11a is not limited, for example, the deepest part is 30nm or more and 1μm or less, and may be 50nm or more and 500nm or less. The protrusion 12A with a smaller depth is advantageous in forming fine wiring.

[0034] like Figure 3 As shown, the protrusion 12A may also include pores 15. By including the pores 15 in the protrusion 12A, a buffering effect can be imparted. As a result, the stress generated in the conductor layer 12 can be relieved. The proportion of the pores 15 may also be, for example, 10% by volume or more and 60% by volume or less relative to the volume of the protrusion 12A. The proportion of the pores 15 can be calculated by performing image processing of cross-section observation from multiple directions in an electron microscope. In particular, since the pores 15 are fine, it can be calculated based on a photograph taken with a transmission electron microscope.

[0035] like Figure 3 As shown, in the wiring substrate 1 according to one embodiment, the contact portion between the conductor layer 12 (seed layer 121) and the insulating particles 14 may have an amorphous structure 16. The amorphous structure 16 is a structure that does not have a regular arrangement structure like a crystal. Specifically, in the contact portion between the conductor layer 12 (seed layer 121) and the insulating particles 14, the amorphous of the conductor layer 12 (seed layer 121) and the amorphous of the insulating particles 14 are mixed with each other. Due to the presence of such an amorphous structure 16, the conductor layer 12 (seed layer 121) and the insulating particles 14 are more firmly bonded.

[0036] like Figure 3 As shown, in the wiring substrate 1 according to one embodiment, when the first surface 11a is cross-sectionally viewed, the plurality of insulating particles 14 may include second insulating particles 14b, and the second insulating particles 14b have a third region 143 in contact with the conductor layer 12 (seed layer 121) and a fourth region 144 in contact with the protrusion 12A (seed layer 121) on the first surface 11a. In the case of having such a structure, the third region 143 and the fourth region 144 of the second insulating particles 14b may be covered with the insulating resin 111. When the third region 143 and the fourth region 144 are covered with the insulating resin 111, the insulating resin 111 can alleviate the thermal stress generated by the difference between the thermal expansion coefficient of the conductor layer 12 and the thermal expansion coefficient of the second insulating particles 14b. As a result, the adhesion between the conductor layer 12 and the second insulating particles 14b is further improved.

[0037] Next, based on Figure 4 One embodiment of a method of forming the conductive layer 12 on the first surface 11 a of the first insulating layer 11 will be described with reference to FIGS. Figure 4 A to E are explanatory diagrams for explaining an embodiment of a method for forming the conductor layer 12 on the first surface 11a of the first insulating layer 11 in the wiring substrate 1 according to the embodiment. Figure 4 In A to E of FIG. 1 , a method of forming the conductive layer 12 on the first surface 11 a of the first insulating layer 11 located on the upper surface (second surface 13 a ) of the second insulating layer 13 is described as an example. Figure 4 In A to E of FIG. 1 , the portion where the conductive layer 12 does not exist on the second surface 13 a of the second insulating layer 13 is described as an example, but the conductive layer 12 is also located on the second surface 13 a of the second insulating layer 13 .

[0038] First, if Figure 4 As shown in A, an insulating sheet 111P including an insulating resin 111 in which a plurality of insulating particles 14 are dispersed is stacked on the second surface 13a of the second insulating layer 13. The stacking method may be, for example, to thermally press-bond the insulating sheet 111P to the second surface 13a under vacuum. At this time, the insulating particles 14 are biased toward the second insulating layer 13 side, and a portion (layer) with a high proportion of the insulating resin 111 is formed near the surface on the opposite side. The thickness of the portion with a high proportion of the insulating resin 111 is, for example, about 10 nm or more and 100 μm or less.

[0039] Next, if Figure 4 As shown in B, the obtained laminate is subjected to plasma treatment, and the thickness of the portion with a higher proportion of insulating resin 111 is reduced. Specifically, the plasma treatment is performed so that the thickness is about 100 nm. After the thickness of the portion with a higher proportion of insulating resin 111 is reduced, a permanganate solution treatment is performed. The permanganate solution treatment can be performed at a temperature of, for example, 40°C to 60°C for 30 seconds to 10 minutes. Figure 4 As shown in C, a portion of the insulating particle 14 is exposed from the surface of the insulating resin 111. The insulating particle 14 partially exposed from the surface of the insulating resin 111 corresponds to the first insulating particle 14a. In the first insulating particle 14a, the portion exposed from the surface of the insulating resin 111 corresponds to the first region 141.

[0040] After the permanganate solution treatment, the plasma treatment is performed again. The second plasma treatment is performed to roughen the surface of the insulating resin 111 exposed between the first insulating particles 14a. By performing the second plasma treatment, the adhesion of the seed layer 121 can be improved. The second plasma treatment is performed, for example, in a manner that removes the resin to a depth of about 100 nm or more and about 300 nm or less from the surface of the insulating resin 111 exposed between the first insulating particles 14a.

[0041] Next, if Figure 4 As shown in D, a seed layer 121 is formed on the surface of the first region 141 of the first insulating particle 14a and the surface of the insulating resin 111. The seed layer 121 is formed, for example, by a transition metal of the 4th, 5th, 6th and 10th groups of the periodic table such as titanium, nickel, chromium or an alloy containing these transition metals such as nickel-chromium as described above. The method for forming the seed layer 121 is not limited, and for example, a sputtering method or a vapor deposition method can be cited.

[0042] In the case of the sputtering method, the metal forming the seed layer 121 collides with the first region 141 of the first insulating particle 14a and the third region 143 and the fourth region 144 of the second insulating particle 14b exposed from the surface of the insulating resin 111, thereby generating thermal energy. Due to the generated thermal energy, the atomic arrangement changes or shifts on the surfaces of the first region 141, the third region 143, and the fourth region 144. As a result, a portion of the surface of the first region 141, the third region 143, and the fourth region 144 becomes amorphous, and an amorphous layer of the insulating particle 14 is formed.

[0043] In parallel with the formation of the amorphous layer of the insulating particles 14, the seed layer 121 is formed on the surface of the insulating resin 111 and the surfaces of the first region 141, the third region 143, and the fourth region 144. At this time, since the insulating particles 14 are amorphous, a portion of the seed layer 121 (the contact surface with the surfaces of the first region 141, the third region 143, and the fourth region 144) becomes amorphous, forming an amorphous layer of the metal. By forming the amorphous layer of the metal, the conductor layer 12 is reduced from entering between the insulating resin 111 and the insulating particles 14.

[0044] Next, if Figure 4 As shown in FIG. 1E, the conductor layer 12 is formed on the surface of the seed layer 121. Specifically, the conductor layer 12 is formed by depositing a metal such as copper by electrolytic plating. The thickness of the conductor layer 12 is as described above, and detailed description thereof is omitted.

[0045] Furthermore, another insulating sheet 111P including insulating resin 111 in which a plurality of insulating particles 14 are dispersed is laminated on the upper surface, and the same steps are repeated to obtain wiring board 1 laminated a desired number of layers.

[0046] The mounting structure involved in the present disclosure includes the wiring substrate involved in the present disclosure, and an electronic component located in the mounting area of ​​the wiring substrate. As the electronic component, for example, a semiconductor integrated circuit element, an optoelectronic element, etc. can be listed. The electronic component is connected to the mounting area of ​​the wiring substrate via solder. The electronic component can be located on both sides of the wiring substrate, or the component can be located on one surface, such as a motherboard, etc., which is located on the other surface.

[0047] The wiring substrate disclosed in the present invention is not limited to the above-mentioned one embodiment. For example, the above-mentioned wiring substrate 1 includes a second insulating layer 13 corresponding to the core insulating layer. However, in the wiring substrate disclosed in the present invention, the second insulating layer 13 is not a necessary component but an arbitrary component. Therefore, the wiring substrate disclosed in the present invention may also be in the form of a so-called coreless substrate in which the second insulating layer 13 does not exist.

[0048] Furthermore, in the above-mentioned wiring substrate 1, the amorphous structure 16 is only shown in Figure 3 However, in the wiring substrate 1 of the present disclosure, the amorphous structure 16 can be formed as long as it is the contact part between the conductor layer 12 (seed layer 121) and the insulating particles 14. Therefore, Figure 2 As shown, the amorphous structure 16 can also be formed in at least a portion of the contact portion between the first region 141 of the first insulating particle 14 a and the conductive layer 12 (seed layer 121 ).

[0049] The embodiments of the present disclosure have been described above. However, the invention according to the present disclosure is not limited to the above-described embodiments, and various changes and improvements can be made within the scope of the present disclosure as shown in the following (1) and (8).

[0050] (1) The wiring substrate of the present disclosure comprises: a first insulating layer having a first surface; and a conductor layer located on the first surface. The first insulating layer comprises an insulating resin and a plurality of insulating particles dispersed in the insulating resin. The plurality of insulating particles include first insulating particles, and when the first surface is viewed from above, the first insulating particles have a first region exposed from the insulating resin and a second region other than the first region on the first surface. The conductor layer is located on the surface of the first region and on the surface of the insulating resin, and is not located below the first region or between the second region and the insulating resin.

[0051] Regarding the embodiment of the present disclosure, the following embodiments (2) to (7) are further disclosed.

[0052] (2) In the wiring substrate described in (1) above,

[0053] The substrate further includes a second insulating layer having a second surface, and at least one first insulating layer is located on the second surface.

[0054] (3) In the wiring substrate described in (1) or (2) above,

[0055] The conductor layer includes a protrusion protruding toward the insulating resin.

[0056] (4) In the wiring substrate described in (3) above,

[0057] The protrusion includes a void.

[0058] (5) In the wiring substrate described in any one of (1) to (4) above,

[0059] The contact portion between the conductive layer and the insulating particles has an amorphous structure.

[0060] (6) In the wiring substrate described in any one of (3) to (5) above,

[0061] In cross-section through the first surface, the plurality of insulating particles include second insulating particles having a third region in contact with the conductor layer and a fourth region in contact with the protrusion on the first surface, and the insulating resin covers a portion between the third region and the fourth region of the second insulating particles.

[0062] (7) In the wiring substrate described in any one of (1) to (6) above,

[0063] The filling rate of the insulating particles is 50 volume % or more and 90 volume % or less.

[0064] (8) The mounting structure according to the present disclosure includes the wiring substrate according to any one of (1) to (7) above, and an electronic component located in a mounting region of the wiring substrate.

[0065] -Explanation of symbols-

[0066] 1 Wiring board

[0067] 11. First insulation layer

[0068] 11a Page 1

[0069] 111 Insulating resin

[0070] 12 Conductor layer

[0071] 12A Protrusion

[0072] 12T Through-hole conductor

[0073] 12V via conductor

[0074] 121 seed layer (conductor layer)

[0075] 13 Second insulation layer

[0076] 13a Page 2

[0077] 14 Insulating particles

[0078] 14a The first insulating particle

[0079] 14b Second insulating particle

[0080] 141 Area 1

[0081] 142 Area 2

[0082] 143 Area 3

[0083] 144 Area 4

[0084] 15 Porosity

[0085] 16 Amorphous structure.

Claims

1. A wiring substrate, comprising: a first insulating layer having a first surface; and The conductor layer is located on the first surface. The first insulating layer comprises an insulating resin and a plurality of insulating particles dispersed in the insulating resin. The plurality of insulating particles include first insulating particles, wherein the first insulating particles have a first region exposed from the insulating resin and a second region other than the first region on the first surface when the first surface is viewed from above. The conductor layer is located on the surface of the first region and the surface of the insulating resin, and is not located below the first region or between the second region and the insulating resin.

2. The wiring substrate according to claim 1, wherein: The wiring substrate further includes a second insulating layer having a second surface. At least one first insulating layer is located on the second surface.

3. The wiring substrate according to claim 1 or 2, wherein: The conductor layer includes a protrusion protruding toward the insulating resin.

4. The wiring substrate according to claim 3, wherein: The protrusion includes an aperture.

5. The wiring substrate according to any one of claims 1 to 4, wherein: A contact portion between the conductive layer and the insulating particles has an amorphous structure.

6. The wiring substrate according to any one of claims 3 to 5, wherein: In a cross-sectional view through the first surface, The plurality of insulating particles include second insulating particles, the second insulating particles having a third region in contact with the conductive layer and a fourth region in contact with the protrusion on the first surface, A portion between the third region and the fourth region of the second insulating particle is covered with the insulating resin.

7. The wiring substrate according to any one of claims 1 to 6, wherein: The filling rate of the insulating particles is 50 volume % or more and 90 volume % or less.

8. A mounting structure, comprising: The wiring substrate according to any one of claims 1 to 7; and An electronic component is located in a mounting area of ​​the wiring substrate.

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