Power semiconductor device

Abstract

The present disclosure relates to a power semiconductor device in which a main current flows in a thickness direction of a semiconductor substrate. The semiconductor substrate includes: a first active region which is provided in a central portion of the semiconductor substrate and through which the main current flows; and a second active region provided on the outside of the first active region. The power semiconductor device includes: a first main electrode provided on the first and second active regions; and a second main electrode provided on the opposite side of the first main electrode, and the second active region has first two sides facing each other in a first direction and second two sides facing each other in a second direction orthogonal to the first direction. The distance from the center of the semiconductor substrate is set to be less than 1 / 4 of the shorter length if a first length between the first two sides of the second active region and a second length between the second two sides of the second active region exist, and the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of the shorter length if the length does not exist, and the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of any one of the lengths if the length does not exist. The first energization capability of the first active region is set to be lower than the second energization capability of the second active region.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device capable of reducing the maximum junction temperature of a semiconductor substrate. Background Art

[0002] In power semiconductor devices such as power IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and power diodes, reducing the maximum junction temperature (TjMAX) of the semiconductor substrate becomes a problem. For example, Patent Document 1 discloses a technique in which the current carrying capacity of a cell structure in the center of a semiconductor substrate is made smaller than that of a cell structure in the periphery, thereby suppressing TjMAX.

[0003] This technology suppresses TjMAX by reducing the heat generated in the center of the semiconductor substrate, which has low heat dissipation properties. However, if the area with low current carrying capacity is too wide, energy loss increases and TjMAX may increase instead. Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2010-4003 Summary of the invention Technical problem to be solved by the invention

[0005] In the prior art disclosed in Patent Document 1, in order to reduce TjMAX, the current carrying capacity of the unit structure in the central part of the semiconductor substrate with lower heat dissipation is made smaller than that of the unit structure in the peripheral part. However, if the area of ​​the unit structure with smaller current carrying capacity becomes too large, the energy loss increases. Therefore, certain conditions need to be set, but this is not fully disclosed in Patent Document 1.

[0006] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a power semiconductor device capable of reliably suppressing TjMAX. Technical means for solving technical problems

[0007] The power semiconductor device involved in the present disclosure is a power semiconductor device in which a main current flows in the thickness direction of a semiconductor substrate, the semiconductor substrate comprising: a first active region arranged in the central portion of the semiconductor substrate and through which the main current flows; and a second active region arranged outside the first active region, the power semiconductor device comprising: a first main electrode arranged on the first active region and the second active region; and a second main electrode arranged on a main surface of the semiconductor substrate on the opposite side of the first main electrode, the second active region having a first direction relative to the first active region. The first two sides and the second two sides opposite to each other in a second direction orthogonal to the first direction, in the first active region, when there is a difference between the first length between the first two sides and the second length between the second two sides in the second active region, the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of the length of the shorter one, and when there is no difference between the first length and the second length between the second two sides, the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of either length, and the first current carrying capacity of the first active region is set to be lower than the second current carrying capacity of the second active region. Effects of the Invention

[0008] According to the power semiconductor device according to the present disclosure, heat generation in the central portion of the semiconductor substrate can be suppressed, and the maximum junction temperature can be reliably suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic cross-sectional view of the power semiconductor device according to the first embodiment of the present disclosure. Figure 2 It is a top view of the semiconductor substrate of the power semiconductor device according to the first embodiment of the present disclosure. Figure 3 This is a diagram showing the dependency of the maximum junction temperature of the semiconductor substrate of the power semiconductor device according to the first embodiment of the present disclosure on the area of ​​the active region. Figure 4 This is a partial cross-sectional view showing the structure of a power semiconductor device according to Embodiment 2 of the present disclosure. Figure 5 This is a partial cross-sectional view showing the structure of a power semiconductor device according to Embodiment 3 of the present disclosure. Figure 6 This is a partial cross-sectional view showing the structure of a power semiconductor device according to a fourth embodiment of the present disclosure. Figure 7 This is a partial cross-sectional view showing the structure of a power semiconductor device according to Embodiment 5 of the present disclosure. DETAILED DESCRIPTION

[0010] <Introduction> Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, the accompanying drawings are schematically shown, and the horizontal and vertical dimensions of the structural elements in the drawings cannot accurately represent the actual dimensions, and the dimension ratios are not accurate. In addition, in the following description, the same structural elements are marked with the same reference numerals for illustration, and their names and functions are also set to be the same. Therefore, their detailed description is sometimes omitted.

[0011] In addition, in the following description, terms such as "upper", "lower", "side", "surface" or "back" are sometimes used to indicate specific positions and directions, but these terms are used to facilitate understanding of the contents of the implementation method and have nothing to do with the direction during actual implementation.

[0012] In addition, hereinafter, “outside” refers to a direction toward the outer periphery of the semiconductor substrate, and “inside” refers to a direction opposite to “outside”.

[0013] In addition, n and p represent the conductivity type of the semiconductor. In the present disclosure, the first conductivity type is set to n-type and the second conductivity type is set to p-type for explanation, but the first conductivity type may be set to p-type and the second conductivity type may be set to n-type. In addition, n-type represents a concentration lower than that of n-type, and n+ type represents a concentration higher than that of n-type. Similarly, p-type represents a concentration lower than that of p-type, and p+ type represents a concentration higher than that of p-type.

[0014] <Implementation method 1> Figure 1 1 is a schematic cross-sectional view of a power semiconductor device according to Embodiment 1 of the present disclosure. The power semiconductor device may be any of a power IGBT, a power MOSFET, and a power diode, but a power IGBT 100 will be described as an example.

[0015] like Figure 1 As shown, in the power IGBT100, the semiconductor substrate 11 is bonded to the heat sink 132 via a conductive bonding layer 12b (second bonding layer) such as a solder layer. The lower surface (second main surface) of the semiconductor substrate 11 is provided with a collector electrode (not shown), and the heat sink 132 is directly bonded to the collector electrode via the bonding layer 12b. In addition, an insulating sheet 14 is provided on the lower surface of the heat sink 132.

[0016] Then, the conductor plate 131 is bonded to the upper surface (first main surface) of the semiconductor substrate 11 via a conductive bonding layer 12a (first bonding layer) such as a solder layer. An emitter electrode (not shown) is provided on the upper surface of the semiconductor substrate 11, and the conductor plate 131 is directly bonded to the emitter electrode via the bonding layer 12b. The semiconductor substrate 11 has an active region 11b (first active region) provided in the central portion of the substrate, an active region 11a (second active region) surrounding the active region 11b, and a terminal region 11c further outside the active region 11a as an active region through which the main current flows. The active region 11b is an active region that makes the current carrying capacity (collector current) per unit area lower than that of the active region 11a.

[0017] in addition, Figure 1 Although not shown in the figure, the power IGBT 100 is housed in a resin case, and the insulating sheet 14 on the lower surface of the heat sink 132 is exposed from the bottom surface of the resin case, and the resin case is filled with a sealing resin (not shown). The power IGBT 100 sealed in the resin case in this way can be mounted on a heat sink or other heat dissipation member to improve the cooling capacity. In addition, a conductor plate can be provided under the insulating sheet 14, and the conductor plate can be exposed from the bottom surface of the resin case.

[0018] The bonding layer 12a is provided only on the region other than the region where the structure for inputting gate signals such as gate wiring and gate pads (not shown) is provided, that is, on the emitter electrode (not shown), and the bonding layer 12b is provided on the entire surface of the collector electrode (not shown) provided on the entire surface of the lower surface (second main surface) of the semiconductor substrate 11. Therefore, the heat dissipation of the semiconductor substrate 11 can be ensured.

[0019] Figure 2 Observe when looking down Figure 1 In the top view of the semiconductor substrate 11, the bonding layer 12a and the conductor portion 131 are omitted for convenience.

[0020] Figure 2 In FIG. 1 , the active region 11 b is set as a circular region, and its radius is represented by “d.” In addition, the radius d of the active region 11 b is set to d≤X / 4. Figure 2 In the figure, X is the length between the two long sides, which can be said to be the first length between the first two sides opposite to each other in the first direction. In addition, Y is the length between the two short sides, which can be said to be the second length between the second two sides opposite to each other in the second direction orthogonal to the first direction.

[0021] In addition, the plan view shape of the active region 11b is not limited to a circle. Figure 2 In the case of , the plan view shape can be set to a quadrilateral as long as it is within a range smaller than 1 / 4 of the length X of the active region 11 a in the vertical direction. Figure 2In the plan view, the active region 11a is a rectangular shape in which the relationship between the horizontal length Y and the vertical length X in the plan view satisfies X<Y. However, X≤Y is sufficient and the plan view shape may be a square.

[0022] also, Figure 2 In the embodiment, the gate pad 4 is provided at the center of one side of the lower side of the semiconductor substrate 11, but the position of the gate pad 4 is not limited thereto. In addition, a gate wiring (not shown) is connected to the gate pad 4, but the gate wiring may be provided along the periphery of the active region 11a.

[0023] Figure 3 It is shown in Figure 1 A graph showing the dependence of the maximum junction temperature (TjMAX) of the semiconductor substrate 11 on the area of ​​the active region 11b when the total current of the entire semiconductor substrate 11 is always set to a constant in the power IGT100 and the current-carrying capacity ratio of the active region 11b to the active region 11a is set to 1 (straight line), 0.9 (■ block), 0.8 (□ block), 0.7 (▲ block) and 0.6 (△ block).

[0024] Figure 3 In FIG. 1 , the horizontal axis represents the distance (d) from the center of the semiconductor substrate corresponding to the radius d of the active region 11 b , and the vertical axis represents TjMAX (° C.).

[0025] exist Figure 3 When the current carrying capacity of the active region 11b is 1, that is, when the current carrying capacity of the active region 11a and the active region 11b are the same, TjMAX is constant at about 112.6°C and has nothing to do with the radius d from the center of the semiconductor substrate. However, if the current carrying capacity of the active region 11b is smaller than that of the active region 11a, it can be seen that TjMAX varies according to the radius d from the center of the semiconductor substrate, that is, the area of ​​the active region 11b.

[0026] For example, when the current carrying capacity ratio of the active region 11 b is 0.8, TjMAX becomes 112° C. near the radius d of X / 4, and then TjMAX increases rapidly as the radius d approaches X / 4.

[0027] This characteristic is the same at other current carrying capacity ratios, and has a characteristic of being the minimum value at a temperature close to 112°C. Therefore, if the current carrying capacity ratio of the active region 11b is set to be less than 1, and the radius d of the active region 11b from the center of the semiconductor substrate 11 is set to be less than 1 / 4 of the length X of the side in the vertical direction of the active region 11a of the semiconductor substrate 11, TjMAX can be reduced compared to when the current carrying capacity ratio of the active region 11b is 1. In addition, if the radius d is too small, TjMAX increases, so it is desirable that the radius d is not less than X / 8.

[0028] In addition to the structure of the power IGBT 100 dissipating heat to the bonding layer 12b on the back side, the effect can be improved by the structure of dissipating heat through the bonding layer 12a on the surface side. That is, this is because in the power IGBT 100, the conductor plate 131 is directly bonded to the semiconductor substrate 11 through the bonding layer 12a by DLB (Direct Lead Bonding), so that heat can be dissipated to a metal frame with higher heat dissipation performance through the bonding layer 12a on the surface side and the conductor plate 131.

[0029] On the other hand, it is found that if the active region 11 b is made too wide, such as by setting the radius d of the active region 11 b from the center of the semiconductor substrate 11 to be equal to or larger than X / 4, TjMAX increases instead.

[0030] In addition, if the radius d from the center of the semiconductor substrate in the direction parallel to one side of the vertical direction of the active region 11a and the direction parallel to one side of the horizontal direction of the active region 11a becomes X / 4 or more, both become active regions 11a with large current carrying capacity, and therefore, under the condition of X≤Y, it is not related to the length of Y. Therefore, by reducing the current carrying capacity within the range where the radius d from the center of the semiconductor substrate is less than X / 4, TjMAX can be reliably suppressed.

[0031] <Implementation method 2> Figure 4 2 is a cross-sectional view showing the structure of the power IGBT 200 according to the second embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b. Figure 1 The power IGBT 100 shown is the same, and the same reference numerals are given to the same structures, and duplicate descriptions are omitted.

[0032] Figure 4 The cross-sectional structure of the unit structure of the power IGBT 200 is shown. Figure 2 The semiconductor substrate 11 is shown in a cross-sectional view taken along line AA in a plan view.

[0033] Figure 4 In the figure, a p+ type collector region (first semiconductor region) is provided on the back side of the semiconductor substrate 11, an n- type drift region 34 (second semiconductor region) is provided on the collector region 38, and a p type body region (third semiconductor region) is provided on the drift region 34.

[0034] A plurality of n+ type source (emitter) regions 37a and 37b (fourth semiconductor region) are selectively provided in the upper layer of the body region 33. In addition, a plurality of trenches 35 are provided which penetrate the body region 33 from the outermost surface of the body region 33 and reach the drift region 34. The arrangement interval 31a and the arrangement interval 31b of the trenches 35 in the active region 11a and the active region 11b are the same interval.

[0035] The inner wall of the trench 35 is covered with a gate insulating film 36, and the gate electrode 39 is filled in the gate insulating film 36. The gate electrodes 39 are respectively covered with insulating films 32, and the upper surface of the semiconductor substrate 11 including the insulating film 32 is covered with the emitter electrode 31. In addition, the collector electrode is provided on the side opposite to the emitter electrode 31 across the semiconductor substrate 11, but is omitted for convenience.

[0036] One side surface of each of the source regions 37 a and 37 b is provided so as to be in contact with a side surface of the trench 35 , that is, a side surface of the gate insulating film 36 .

[0037] Figure 4 In the embodiment, the source region 37b is provided in the active region 11b, and the source region 37a is provided in the active region 11a, but the impurity concentration of the n-type impurity in the source region 37b is set lower than the impurity concentration of the n-type impurity in the source region 37a. By setting in this way, the amount of carriers in the active region 11b decreases, and the current carrying capacity of the active region 11b is lower than the current carrying capacity of the active region 11a.

[0038] In order to make the current carrying capacity of the active region 11b lower than that of the active region 11a, the impurity concentration of the source region 37b can be lower than that of the source region 37a. For example, if the impurity concentration of the source region 37b is 50% lower than that of the source region 37a, the current carrying capacity can be reduced by 12%.

[0039] The separation of the source regions 37 a and 37 b can be achieved by performing two impurity implantation steps in the manufacturing process using an impurity implantation mask for forming the source region 37 a and an impurity implantation mask for forming the source region 37 b .

[0040] <Implementation method 3> Figure 5 2 is a cross-sectional view showing the structure of a power IGBT 300 according to Embodiment 3 of the present disclosure, and is a partial cross-sectional view of a semiconductor substrate 11 near a boundary region between an active region 11a and an active region 11b. Figure 5 For use with Figure 4 The same components as the power IGBT 200 described herein are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0041] Figure 5In the figure, the source region 37b is provided in the active region 11b, and the source region 37a is provided in the active region 11a. Although not shown in the figure, the region width of the source region 37b, that is, the length of the source region 37b in the direction along the extension direction of the gate electrode 39 is formed to be shorter than the region width of the source region 37a, that is, the length of the source region 37a in the direction along the extension direction of the gate electrode 39. By forming in this way, the amount of carriers in the active region 11b is reduced, and the current carrying capacity of the active region 11b is lower than the current carrying capacity of the active region 11a.

[0042] In order to make the current carrying capacity of the active region 11b lower than that of the active region 11a, the width of the source region 37b can be made shorter than that of the source region 37a. For example, if the width of the source region 37b is 50% shorter than that of the source region 37a, the current carrying capacity can be reduced by 10%.

[0043] The separation of the source regions 37a and 37b can be achieved in a single impurity implantation step by using an impurity implantation mask having different lengths of respective implantation openings for forming the source regions 37a and 37b in the manufacturing process.

[0044] <Implementation method 4> Figure 6 1 is a cross-sectional view showing the structure of a power IGBT 400 according to the fourth embodiment of the present disclosure, and is a partial cross-sectional view of the semiconductor substrate 11 near the boundary region between the active region 11a and the active region 11b. Figure 6 For use with Figure 4 The same components as the power IGBT 200 described herein are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0045] Figure 6 In the active region 11b, the spacing 31b of the trenches 35 is set wider than the spacing 31a of the trenches 35 in the active region 11a. By forming in this way, the carrier accumulation effect in the active region 11b is reduced, and the current carrying capacity of the active region 11b is lower than that of the active region 11a.

[0046] The carrier accumulation effect is an effect of reducing on-resistance and suppressing on-voltage by accumulating carriers in the drift region 34 , but by widening the arrangement interval 31 b of the trenches 35 in the active region 11 b , the ability to accumulate carriers is reduced, and the current carrying capacity is reduced.

[0047] In order to make the current carrying capacity of the active region 11b lower than that of the active region 11a, the configuration interval 31b of the groove 35 in the active region 11b can be made wider than the configuration interval 31a of the groove 35 in the active region 11a. For example, if the configuration interval 31b is made 50% wider than the configuration interval 31a, the current carrying capacity can be reduced by 3%.

[0048] The separation of the arrangement intervals 31 a and 31 b of the trenches 35 can be achieved by etching using an etching mask for forming the trenches 35 in a manufacturing process in which the arrangement intervals of the openings in the active regions 11 a and 11 b are different.

[0049] <Implementation method 5> Figure 7 1 is a cross-sectional view showing the structure of a power IGBT 500 according to Embodiment 5 of the present disclosure, and is a partial cross-sectional view of a semiconductor substrate 11 near a boundary region between an active region 11a and an active region 11b. Figure 7 For use with Figure 4 The same components as the power IGBT 200 described herein are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0050] Figure 7 In the embodiment, the collector region is formed with different impurity concentrations in the active region 11a and the active region 11b. The active region 11a is set as the collector region 38a, and the active region 11b is set as the collector region 38b.

[0051] In the power IGBT 500, the p+ type impurity concentration of the collector region 38b of the active region 11b is set lower than the impurity concentration of the collector region 38a of the active region 11a. By setting this, the number of carriers in the active region 11b decreases, and the current carrying capacity of the active region 11b is lower than that of the active region 11a.

[0052] In order to make the current-carrying capacity of the active region 11b lower than that of the active region 11a, the impurity concentration of the collector region 38b can be lower than that of the collector region 38a. For example, if the impurity concentration of the collector region 38b is 50% lower than that of the collector region 38a, the current-carrying capacity can be reduced by 26%.

[0053] The separation of the collector regions 38 a and 38 b can be achieved by performing two impurity implantation steps in the manufacturing process using an impurity implantation mask for forming the collector region 38 a and an impurity implantation mask for forming the collector region 38 b .

[0054] In order to Figure 3The current carrying capacity ratio of the active region 11b shown relative to the active region 11a is adjusted to 0.9, 0.8, 0.7, and 0.6, which can also be achieved by combining multiple parameters. For example, if the region width of the source region 37b is made about 50% shorter than that of the source region 37a, the current carrying capacity ratio can be adjusted to about 0.9. In addition, if the region width of the source region 37b is made about 50% shorter than that of the source region 37a, and the impurity concentration of the source region 37b is made about 50% lower than that of the source region 37a, the current carrying capacity ratio can be adjusted to about 0.8. In addition, if the configuration interval of the groove 35 in the active region 11b is made about 50% wider than the configuration interval 31a of the groove 35 in the active region 11a, and the impurity concentration of the collector region 38b is made about 50% lower than that of the collector region 38a, the current carrying capacity ratio can be adjusted to about 0.7. In addition, if the region width of source region 37b is made about 50% shorter than that of source region 37a, the impurity concentration of source region 37b is made about 50% lower than that of source region 37a, and the impurity concentration of collector region 38b is made about 50% lower than that of collector region 38a, the current carrying capacity ratio can be adjusted to about 0.6.

[0055] The present disclosure has been described in detail, but the above description is only an example in all aspects and the present disclosure is not limited thereto. Numerous modifications not shown by way of example are conceivable without departing from the scope of the present disclosure.

[0056] In addition, the present invention can freely combine the various embodiments within the scope of the invention, or can appropriately modify or omit the various embodiments.

Claims

1. A power semiconductor device, The main current flows in the thickness direction of the semiconductor substrate, and the power semiconductor device is characterized in that: The semiconductor substrate comprises: a first active region provided in a central portion of the semiconductor substrate and through which the main current flows; as well as a second active region disposed outside the first active region, The power semiconductor device comprises: a first main electrode disposed on the first active region and the second active region; as well as a second main electrode provided on a main surface of the semiconductor substrate on the opposite side to the first main electrode, The second active region has two first sides that are opposite to each other in a first direction and two second sides that are opposite to each other in a second direction that is orthogonal to the first direction. In the first active region, when there is a difference between the first length between the first two sides and the second length between the second two sides of the second active region, the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of the shorter length, and when there is no difference between the first length and the second length between the second two sides, the distance from the center of the semiconductor substrate is set to be less than 1 / 4 of either length. A first current carrying capacity of the first active region is set lower than a second current carrying capacity of the second active region.

2. The power semiconductor device according to claim 1, wherein: include: a conductor plate directly bonded to the first main electrode via a first bonding layer; as well as A heat sink plate is directly bonded to the second main electrode via a second bonding layer.

3. The power semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate comprises: a first semiconductor region of a second conductivity type disposed on the second main electrode; a second semiconductor region of the first conductivity type disposed on the first semiconductor region; a third semiconductor region of the second conductivity type disposed on the second semiconductor region; a plurality of fourth semiconductor regions of the first conductivity type selectively provided on an upper layer portion of the third semiconductor region; a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region; a gate insulating film respectively disposed on inner walls of the plurality of trenches; and The gate electrodes are respectively filled into the interior of the gate insulating film, One side surface of each of the plurality of fourth semiconductor regions is arranged to be in contact with a side surface of each of the plurality of trenches. The impurity concentration of the plurality of fourth semiconductor regions in the first active region is set lower than the impurity concentration of the plurality of fourth semiconductor regions in the second active region.

4. The power semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate comprises: a first semiconductor region of a second conductivity type disposed on the second main electrode; a second semiconductor region of the first conductivity type disposed on the first semiconductor region; a third semiconductor region of the second conductivity type disposed on the second semiconductor region; a plurality of fourth semiconductor regions of the first conductivity type selectively provided on an upper layer portion of the third semiconductor region; a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region; a gate insulating film respectively disposed on inner walls of the plurality of trenches; and The gate electrodes are respectively filled into the interior of the gate insulating film, One side surface of each of the plurality of fourth semiconductor regions is arranged to be in contact with a side surface of each of the plurality of trenches. A region width of the plurality of fourth semiconductor regions in the first active region along an extending direction of the gate electrode is formed to be shorter than a region width of the plurality of fourth semiconductor regions in the second active region.

5. The power semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate comprises: a first semiconductor region of a second conductivity type disposed on the second main electrode; a second semiconductor region of the first conductivity type disposed on the first semiconductor region; a third semiconductor region of the second conductivity type disposed on the second semiconductor region; a plurality of fourth semiconductor regions of the first conductivity type selectively provided on an upper layer portion of the third semiconductor region; a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region; a gate insulating film respectively disposed on inner walls of the plurality of trenches; and The gate electrodes are respectively filled into the interior of the gate insulating film, One side surface of each of the plurality of fourth semiconductor regions is arranged to be in contact with a side surface of each of the plurality of trenches. The arrangement interval of the plurality of trenches in the first active region is formed to be wider than the arrangement interval of the plurality of trenches in the second active region.

6. The power semiconductor device according to claim 1 or 2, wherein: The semiconductor substrate comprises: a first semiconductor region of a second conductivity type disposed on the second main electrode; a second semiconductor region of the first conductivity type disposed on the first semiconductor region; a third semiconductor region of the second conductivity type disposed on the second semiconductor region; a plurality of fourth semiconductor regions of the first conductivity type selectively provided on an upper layer portion of the third semiconductor region; a plurality of trenches penetrating the third semiconductor region and reaching the second semiconductor region; a gate insulating film respectively disposed on inner walls of the plurality of trenches; and The gate electrodes are respectively filled into the interior of the gate insulating film, One side surface of each of the plurality of fourth semiconductor regions is arranged to be in contact with a side surface of each of the plurality of trenches. The impurity concentration of the first semiconductor region in the first active region is set lower than the impurity concentration of the first semiconductor region in the second active region.

7. The power semiconductor device according to claim 2, wherein: The second main electrode is provided across the entire surface of the main surface of the semiconductor substrate. The second bonding layer is provided across the entire main surface of the second main electrode.

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