Preparation method of porous microelectrode array

Abstract

The present invention relates to a method for preparing a porous microelectrode array, comprising: S100: depositing a sacrificial layer on a substrate, the substrate comprising a first part and a second part, the sacrificial layer being deposited on the first part; S200: depositing a first encapsulation layer on the second part of the substrate and the sacrificial layer, wherein the first encapsulation layer located on the sacrificial layer has a plurality of first through holes; S300: depositing a first metal layer on the first encapsulation layer; S400: depositing a second metal layer on the first encapsulation layer located above the second part of the substrate, wherein the second metal layer covers a portion of the first metal layer; S500: depositing a second encapsulation layer, wherein the second encapsulation layer has a plurality of second through holes, and each second through hole of the second encapsulation layer is aligned one by one with each first through hole of the first encapsulation layer; S600: etching off the sacrificial layer, and cutting off the first part of the substrate. The method for preparing a porous microelectrode array of the present invention has a simpler process than the existing preparation method.

Description

Technical Field

[0001] The invention relates to the technical field of microelectrode arrays, and more particularly to a method for preparing a porous microelectrode array for nerve cell detection and electrical stimulation. Background Art

[0002] With the development of microfabrication technology, microelectrode arrays (MEA) have been widely used in fields such as neuroscience, cardiology, and drug testing. MEA allows researchers to perform long-term and stable recording and analysis of the electrical activity of single cells or cell networks under in vitro culture conditions. The advantage is that it has high spatial resolution and can record a large number of neurons at the same time, achieving high-throughput detection.

[0003] However, the packaging layer of the existing microelectrode array is made of polyimide (PI) material, which has a high hardness. In order to form a specific shape, the PI packaging layer needs to be etched using an etching process, which is a complicated process. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a porous microelectrode array, using SU-8 photoresist instead of polyimide as a packaging layer to make the porous microelectrode array flexible and simplify the process.

[0005] Based on the above purpose, the present invention provides a method for preparing a porous microelectrode array, comprising the following steps:

[0006] S100: depositing a sacrificial layer on a substrate, wherein the substrate comprises a first portion and a second portion, and the sacrificial layer is deposited on the first portion of the substrate;

[0007] S200: depositing a first packaging layer on the second portion of the substrate and the sacrificial layer, wherein the first packaging layer located on the sacrificial layer has a plurality of first through holes;

[0008] S300: depositing a first metal layer on the first packaging layer;

[0009] S400: depositing a second metal layer on the first encapsulation layer located above the second portion of the substrate, wherein the second metal layer covers a portion of the first metal layer;

[0010] S500: depositing a second encapsulation layer, wherein the second encapsulation layer has a plurality of second through holes, each second through hole of the second encapsulation layer is aligned one by one with each first through hole of the first encapsulation layer, and the second encapsulation layer covers a portion of the second metal layer and the first metal layer located above the second portion of the substrate, and covers a portion of the first metal layer located above the first portion of the substrate;

[0011] S600: etching away the sacrificial layer and removing the first portion of the substrate.

[0012] Furthermore, the method further comprises the steps of:

[0013] S700: electroplating a conductive polymer on a portion of the first metal layer not covered by the second packaging layer.

[0014] Furthermore, step S100 specifically includes the following steps:

[0015] S110: coating LOR-5B and LC-100A photoresists on the substrate;

[0016] S120: Expose and develop LOR-5B and LC-100A photoresists;

[0017] S130: depositing the sacrificial layer on the developed substrate;

[0018] S140: Stripping of unexposed LOR-5B and LC-100A photoresists.

[0019] Further, the first encapsulation layer is formed by SU-8 2005 photoresist, and step S200 specifically includes the following steps:

[0020] S210: spin coating SU-8 2005 photoresist on the second portion of the substrate and the sacrificial layer;

[0021] S220: exposing and developing the SU-8 2005 photoresist so that the SU-8 2005 photoresist located above the sacrificial layer has a plurality of first through holes.

[0022] Furthermore, step S300 specifically includes the following steps:

[0023] S310: spin coating nlof-2020 photoresist on the first encapsulation layer;

[0024] S320: Expose and develop nlof-2020 photoresist;

[0025] S330: sequentially depositing chromium, gold, and chromium metals on the developed first encapsulation layer to form a first metal layer;

[0026] S340: Stripping the unexposed nlof-2020 photoresist.

[0027] Furthermore, step S400 specifically includes the following steps:

[0028] S410: spin-coating LOR-5B and LC-100A photoresists on the first packaging layer and the first metal layer in sequence;

[0029] S420: Expose and develop LOR-5B and LC-100A photoresists;

[0030] S430: sequentially depositing chromium, nickel and gold on the developed first encapsulation layer and the first metal layer to form a second metal layer;

[0031] S440: Stripping unexposed LOR-5B and LC-100A photoresists.

[0032] Further, the second encapsulation layer is formed by SU-8 2005 photoresist, and step S500 specifically includes the following steps:

[0033] S510: coating SU-8 2005 photoresist on the first packaging layer, the first metal layer and the second metal layer;

[0034] S520: sequentially exposing and developing the SU-8 2005 photoresist so that a plurality of second through holes are formed on the SU-8 2005 photoresist.

[0035] Furthermore, the sacrificial layer is aluminum.

[0036] Furthermore, in step S600, the sacrificial layer is corroded by using a hydrofluoric acid solution.

[0037] Further, the portion of the first metal layer not covered by the second packaging layer is formed as an electrode site of the porous microelectrode array, and the portion of the second metal layer not covered by the second packaging layer is formed as a pad.

[0038] In the method for preparing the porous microelectrode array of the present invention, the first encapsulation layer and the second encapsulation layer are both formed of SU-8 2005 photoresist, which can be removed by exposure and development without etching by etching process, so the process is simpler. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A flowchart of a method for preparing a porous microelectrode array according to an embodiment of the present invention;

[0040] Figure 2 1 is a cross-sectional view of a porous microelectrode array at different steps in the preparation process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The preferred embodiments of the present invention are given below in conjunction with the accompanying drawings and described in detail.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing a porous microelectrode array, which includes the following steps S100-S600:

[0043] S100 : depositing a sacrificial layer 20 on a substrate 10 , wherein the substrate 10 includes a first portion and a second portion, and the sacrificial layer 20 is deposited on the first portion of the substrate 10 .

[0044] like Figure 2 As shown, the sacrificial layer 20 only covers the right part of the substrate 10 , while the left part of the substrate 10 is not covered by the sacrificial layer 20 . With the sacrificial layer 20 as the boundary, the right part is the first part, and the left part is the second part.

[0045] In some embodiments, substrate 10 is silicon.

[0046] In some embodiments, step S100 specifically includes the following steps:

[0047] S110: coating a photoresist on the substrate 10;

[0048] S120: exposing and developing the photoresist to obtain a preset pattern of the sacrificial layer 20;

[0049] S130: depositing a sacrificial layer 20 on the developed substrate 10, for example, by using a high vacuum thermal evaporation coating machine to deposit the sacrificial layer 20;

[0050] S140: Stripping unexposed photoresist.

[0051] In some embodiments, the sacrificial layer 20 may be aluminum with a thickness of 200 nanometers.

[0052] In step S110, the photoresist may use LOR-5B and LC-100A photoresists. For example, LOR-5B photoresist may be uniformly coated on the upper surface of the substrate. LOR-5B photoresist has good bottom layer protection and is easy to strip. Then, LC-100A photoresist is coated on the LOR-5B photoresist. As a top layer of glue, LC-100A photoresist has high resolution and good pattern transfer capability. In step S140, acetone may be used to strip the unexposed LC-100A photoresist, and a positive photolithography developer may be used to strip the unexposed LOR-5B photoresist.

[0053] In step S120, the photoresist can be exposed using a photolithography mask with a specific pattern and a UV photolithography machine. The exposure time can be 7-10 seconds to ensure that the photoresist is fully photosensitized. The development time is 120 seconds. During the development process, the exposed part of the photoresist will be dissolved to form the desired pattern.

[0054] S200 : depositing a first encapsulation layer 30 on the second portion of the substrate 10 and the sacrificial layer 20 , wherein the first encapsulation layer 30 located above the sacrificial layer 20 has a plurality of first through holes 31 .

[0055] In some embodiments, the first encapsulation layer 30 is formed of SU8-2005 photoresist, which is softer than polyimide and can make the porous microelectrode array flexible. SU8-2005 photoresist can be removed by exposure and development without etching, so the process is simpler. The thickness of the first encapsulation layer 30 can be 4.5-5 microns.

[0056] Specifically, step S200 includes:

[0057] S210: spin coating SU-8 2005 photoresist on the second portion of the substrate 10 and the sacrificial layer 20;

[0058] S220 : sequentially exposing and developing the SU8-2005 photoresist so that the SU-82005 photoresist located above the sacrificial layer 20 has a plurality of first through holes 31 .

[0059] S300 : depositing a first metal layer 40 on the first encapsulation layer 30 .

[0060] In some embodiments, the first metal layer 40 is formed by sequentially depositing chromium, gold, and chromium. The first metal layer 40 includes a plurality of metal wires, which are used as electrode sites for detecting action potentials of nerve cells and conductors for transmitting potential signals. The specific pattern of the first metal layer 40 can be designed as needed.

[0061] In some embodiments, step S300 specifically includes the following steps:

[0062] S310: spin coating nlof-2020 photoresist on the first encapsulation layer 30;

[0063] S320: Expose and develop nlof-2020 photoresist;

[0064] S330: depositing chromium, gold, and chromium metals in sequence on the developed first encapsulation layer 30, wherein the thicknesses of chromium, gold, and chromium are 3 nanometers, 120 nanometers, and 3 nanometers, respectively;

[0065] S340: using acetone to strip off the unexposed nlof-2020 photoresist, so as to strip off the first metal layer on the unexposed nlof-2020 photoresist.

[0066] S400 : depositing a second metal layer 50 on the first encapsulation layer 30 located above the second portion of the substrate 10 , wherein the second metal layer 50 covers a portion of the first metal layer 40 .

[0067] In some embodiments, the second metal layer 50 is formed by sequentially depositing chromium, nickel, and gold. The second metal layer 50 is only formed on the second portion of the substrate 10 , and the second metal layer 50 is not deposited on the sacrificial layer 20 .

[0068] In some embodiments, step S400 specifically includes the following steps:

[0069] S410: Spin-coating LOR-5B and LC-100A photoresists on the first packaging layer 30 and the first metal layer 40 in sequence;

[0070] S420: exposing and developing LOR-5B and LC-100A photoresists to obtain a preset pattern;

[0071] S430: depositing chromium, nickel and gold in sequence on the developed first encapsulation layer 30 and the first metal layer 40, wherein the thicknesses of the chromium, nickel and gold are 5 nanometers, 150 nanometers and 100 nanometers, respectively;

[0072] S440: Use acetone to strip the unexposed LC-100A photoresist, and use developer to strip the LOR-5B photoresist.

[0073] S500: Depositing a second packaging layer 60, wherein the second packaging layer 60 has a plurality of second through holes 61, each second through hole 61 is aligned one by one with each first through hole 31, and is formed into a through hole of a porous microelectrode array, the second packaging layer 60 covers a portion of the second metal layer 50 and the first metal layer 40 located above the second portion of the substrate 10, and covers a portion of the first metal layer 40 located above the first portion of the substrate 10.

[0074] In some embodiments, the second encapsulation layer 60 is formed of SU-8 2005 photoresist to make the porous microelectrode array flexible.

[0075] In some embodiments, step S500 specifically includes the following steps:

[0076] S510: coating SU-8 2005 photoresist on the first packaging layer 30, the first metal layer 40 and the second metal layer 50;

[0077] S520: sequentially exposing and developing the SU-8 2005 photoresist to obtain a second encapsulation layer 60 with a preset pattern.

[0078] The portion of the first metal layer 40 not covered by the second packaging layer 60 is formed as an electrode site of the porous microelectrode array, and the portion of the second metal layer 50 not covered by the second packaging layer 60 is formed as a pad for connecting to a signal acquisition device to transmit the potential signal to the signal acquisition device.

[0079] S600: etching away the sacrificial layer 20 and removing the first portion of the substrate 10.

[0080] In some embodiments, the porous microelectrode array can be immersed in hydrofluoric acid to etch the sacrificial layer 20. After the sacrificial layer 20 is etched away, a certain gap exists between the first portion of the substrate 10 and the first encapsulation layer 30. Since the first encapsulation layer 30 and the second encapsulation layer 60 are both flexible, the area above the first portion of the substrate 10 can be bent, forming a flexible portion (i.e., Figure 2 In order to prevent the flexible portion from being interfered by the first portion of the substrate 10 when being bent, the first portion of the substrate 10 can be cut off. Since the flexible portion can be bent and formed into a curved structure, its contact surface with the nerve tissue is larger, which can improve the signal-to-noise ratio of the collected signal.

[0081] In some embodiments, the method for preparing the porous microelectrode array further comprises the following steps:

[0082] S700 : electroplating a conductive polymer PEDOT:pss (poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid)) on the portion of the first metal layer 40 not covered by the second encapsulation layer 60 to reduce impedance.

[0083] In order to detect the action potential of nerve cells in vitro, a porous microelectrode array is usually formed as a part of a microfluidic device for use. The microfluidic device includes a microfluidic layer, a porous microelectrode array and a cell culture layer. The microfluidic layer is provided with a first blind hole, a second blind hole and a microfluidic channel. The two ends of the microfluidic channel are respectively connected to the two blind holes. The cell culture layer is provided with a third through hole and a fourth through hole. The third through hole is aligned with the first blind hole. The flexible portion of the porous microelectrode array is sandwiched between the microfluidic layer and the cell culture layer and covers the third through hole and the first blind hole. The third through hole and the first blind hole are connected by The through holes of the porous microelectrode array are interconnected, and the fourth through hole is aligned with and connected to the second blind hole, so that a channel for the flow of cell culture fluid can be formed; during detection, the neural cell culture fluid can be injected from the third through hole, and negative pressure is applied at the fourth through hole, so that the neural cell culture fluid enters the third through hole under the action of negative pressure, and passes through the through holes of the porous microelectrode array, the first blind hole, the microfluidic channel, and the second blind hole in sequence, and then flows out from the fourth through hole. Under the action of negative pressure, the neural tissue will fit closely with the electrode sites of the porous microelectrode array, thereby improving the signal-to-noise ratio of signal detection.

[0084] In some implementations, the sizes of the through holes of the porous microelectrode array can be all the same, for example, all approximately equal to the size of the electrode site, or the sizes of the through holes can be partially the same, or the sizes of the through holes can be different. The through holes can be evenly arranged around the electrode sites so that the neural tissue can be better attached to the electrode sites.

[0085] In the method for preparing the porous microelectrode array according to the embodiment of the present invention, the first encapsulation layer 30 and the second encapsulation layer 60 are both formed of SU-8 2005 photoresist, which can be removed by exposure and development without etching by an etching process, so the process is simpler.

[0086] The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The above embodiment of the present invention can also be modified in various ways. That is, all simple, equivalent changes and modifications made according to the claims and the description of the present invention fall within the scope of protection of the claims of the present invention. The contents not described in detail in the present invention are all conventional technical contents.

Claims

1. A method for preparing a porous microelectrode array, characterized in that: The following steps are involved: S100: depositing a sacrificial layer on a substrate, wherein the substrate comprises a first portion and a second portion, and the sacrificial layer is deposited on the first portion of the substrate; S200: depositing a first packaging layer on the second portion of the substrate and the sacrificial layer, wherein the first packaging layer located on the sacrificial layer has a plurality of first through holes; The first encapsulation layer is formed of SU-8 2005 photoresist; S300: depositing a first metal layer on the first packaging layer; S400: depositing a second metal layer on the first encapsulation layer located above the second portion of the substrate, wherein the second metal layer covers a portion of the first metal layer; S500: depositing a second encapsulation layer, wherein the second encapsulation layer has a plurality of second through holes, each second through hole of the second encapsulation layer is aligned one by one with each first through hole of the first encapsulation layer, and the second encapsulation layer covers a portion of the second metal layer and the first metal layer located above the second portion of the substrate, and covers a portion of the first metal layer located above the first portion of the substrate; The second encapsulation layer is formed of SU-8 2005 photoresist; S600: etching away the sacrificial layer and removing the first portion of the substrate.

2. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Also includes the steps: S700: electroplating a conductive polymer on a portion of the first metal layer not covered by the second packaging layer.

3. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Step S100 specifically includes the following steps: S110: coating LOR-5B and LC-100A photoresists on the substrate; S120: Expose and develop LOR-5B and LC-100A photoresists; S130: depositing the sacrificial layer on the developed substrate; S140: Stripping of unexposed LOR-5B and LC-100A photoresists.

4. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Step S200 specifically includes the following steps: S210: spin coating SU-8 2005 photoresist on the second portion of the substrate and the sacrificial layer; S220: exposing and developing the SU-8 2005 photoresist so that the SU-8 2005 photoresist located above the sacrificial layer has a plurality of first through holes.

5. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Step S300 specifically includes the following steps: S310: spin coating nlof-2020 photoresist on the first encapsulation layer; S320: Expose and develop nlof-2020 photoresist; S330: sequentially depositing chromium, gold, and chromium metals on the developed first encapsulation layer to form a first metal layer; S340: Stripping the unexposed nlof-2020 photoresist.

6. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Step S400 specifically includes the following steps: S410: spin-coating LOR-5B and LC-100A photoresists on the first packaging layer and the first metal layer in sequence; S420: Expose and develop LOR-5B and LC-100A photoresists; S430: sequentially depositing chromium, nickel and gold on the developed first encapsulation layer and the first metal layer to form a second metal layer; S440: Stripping unexposed LOR-5B and LC-100A photoresists.

7. The method for preparing a porous microelectrode array according to claim 1, characterized in that: Step S500 specifically includes the following steps: S510: coating SU-8 2005 photoresist on the first packaging layer, the first metal layer and the second metal layer; S520: sequentially exposing and developing the SU-8 2005 photoresist so that a plurality of second through holes are formed on the SU-8 2005 photoresist.

8. The method for preparing a porous microelectrode array according to claim 1, characterized in that: The sacrificial layer is aluminum.

9. The method for preparing a porous microelectrode array according to claim 1, characterized in that: In step S600, the sacrificial layer is etched using a hydrofluoric acid solution.

10. The method for preparing a porous microelectrode array according to claim 1, characterized in that: The portion of the first metal layer not covered by the second packaging layer is formed as an electrode site of the porous microelectrode array, and the portion of the second metal layer not covered by the second packaging layer is formed as a pad.

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