Current detection circuit and method adopting digital counting, and DC-DC circuit

Abstract

The invention provides a current detection circuit and method adopting digital counting and a DC-DC circuit, and the current detection circuit comprises the steps that a first trigger assembly responds to a condition that a power tube in a circuit to be detected is in a conduction state, and determines the number of first rising edges corresponding to a conduction inversion signal; the second trigger component determines the number of second rising edges corresponding to the first clock control signal output by the first output end of the first trigger component so as to determine a first output signal output by the output end of the second trigger component according to the number of the second rising edges; and the third trigger component responds to the timer component reaching the set time, and determines the working mode of the to-be-detected circuit based on the first output signal, a second clock control signal output by the third output end of the first trigger component and a timing signal output by the second output end of the timer component. The overall circuit design is smaller in occupied area and lower in power consumption, so that the actual requirements of more low-power-consumption products can be met.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic technology, and in particular to a current detection circuit and method using digital counting, and a DC-DC circuit. Background Art

[0002] At present, multi-mode inductive DC-to-DC converter (DC-DC) circuits all need to detect their own output current to determine the working mode of the DC-DC circuit. On the premise of determining the working mode of the DC-DC circuit, the working mode of the electronic device used in the circuit can be further determined. It can be seen that the role of the current detection circuit is crucial.

[0003] Traditional current detection circuits use amplifiers to sample and amplify current, and then use comparators to compare the amplified voltage signal with a reference voltage to determine the optimal operating mode of the circuit.

[0004] However, in order to achieve sampling and amplification of current signals, the amplifier requires a large bandwidth, which means large current, which is very unfriendly to low-power design. In addition, the use of amplifiers often requires frequency compensation (such as compensation by using compensation capacitors, etc.), which has certain disadvantages. Summary of the invention

[0005] The embodiments of the present disclosure at least provide a current detection circuit and method using digital counting, as well as a DC-DC circuit, so as to realize current detection for the DC-DC circuit by digital counting. The circuit design occupies a smaller area, has lower power consumption, and is more in line with the actual needs of low-power design.

[0006] In a first aspect, an embodiment of the present disclosure provides a current detection circuit using digital counting, comprising: a first trigger component, a second trigger component, a third trigger component and a timer component; the first output end and the second output end of the first trigger component are respectively connected to the first input end and the second input end of the second trigger component, and the third output end of the first trigger component is connected to the first input end of the third trigger component; the output end of the third trigger component is connected to the first input end of the timer component, the first output end of the timer component is connected to the third input end of the second trigger component, and the second output end of the timer component is connected to the second input end of the third trigger component; the output end of the second trigger component is connected to the third input end of the third trigger component;

[0007] The first trigger component is used for determining the number of first rising edges corresponding to the conduction inverted signal in response to the power tube in the circuit to be detected being in the conduction state, so as to determine the first clock control signal and the second clock control signal respectively outputted by the first output terminal and the third output terminal of the first trigger component according to the first rising edge number;

[0008] The second trigger component is used to determine the number of second rising edges corresponding to the first clock control signal to determine a first output signal output by the output end of the second trigger component according to the second rising edge number;

[0009] The third trigger component is used to determine the working mode of the circuit to be detected based on the first output signal, the second clock control signal and the timing signal output by the second output terminal of the timer component in response to the timer component reaching a set time.

[0010] In a possible implementation manner, the first trigger component includes a plurality of first triggers, the plurality of first triggers are connected in series, and the input ends of the other first triggers except the first first trigger are connected to the output end of the previous first trigger;

[0011] The reset terminal of the first trigger is used to generate a first reset signal based on the standby signal output by the control logic unit of the circuit to be detected to trigger a reset function;

[0012] The clock terminal of the first trigger is used to receive the conduction inverted signal output by the control logic unit of the circuit to be detected to trigger the first rising edge counting function.

[0013] In a possible implementation manner, the plurality of first flip-flops are composed of five D flip-flops;

[0014] The output terminals of the second D flip-flop, the fourth D flip-flop and the fifth D flip-flop are respectively set as the first output terminal, the second output terminal and the third output terminal of the first flip-flop component.

[0015] In a possible implementation manner, the first trigger component further includes a first NOR gate, and an output end of the first NOR gate is connected to a reset end of each of the first triggers;

[0016] The first NOR gate is used to receive a standby signal output by a control logic unit of the circuit to be detected, and determine the first reset signal based on a NOR operation between a determined enable inverted signal and the standby signal.

[0017] In a possible implementation manner, the second trigger component includes a first OR gate and a plurality of second triggers, the plurality of second triggers are connected in series, the input ends of the second triggers other than the first second trigger are connected to the output end of the previous second trigger, and the output end of the last second trigger and the second output end of the first trigger component are respectively connected to the two input ends of the first OR gate;

[0018] The reset terminal of the second trigger is used to receive the second reset signal output by the first output terminal of the timer component to trigger the reset function;

[0019] The clock terminal of the second trigger is used to receive the first clock control signal output by the first output terminal of the first trigger component to trigger a second rising edge counting function.

[0020] In a possible implementation manner, the plurality of second flip-flops are composed of three D flip-flops;

[0021] The first OR gate is used to respectively receive the second output signal output from the second output terminal of the first trigger component and the third output signal output from the output terminal of the third D trigger, and determine the first output signal output from the output terminal of the second trigger component based on the OR operation between the second output signal and the third output signal.

[0022] In a possible implementation manner, the timer component includes a timer unit and a delay unit, and the output end of the timer unit is respectively connected to the input end of the delay unit, the input end of the timer unit, and the second input end of the third trigger component;

[0023] The output end of the delay unit serves as the first output end of the timer component, and is used to maintain the output duration of the first output signal.

[0024] In a possible implementation manner, the timer unit includes an inverter, a second OR gate, and a timer connected in sequence, the output end of the inverter is connected to the first input end of the second OR gate, and the output end of the timer is connected to the second input end of the second OR gate;

[0025] The second OR gate is used to receive the enable inverted signal output from the output terminal of the inverter and the timing signal output from the output terminal of the timer, and determine the third reset signal input to the timer based on the OR operation between the enable inverted signal and the timing signal;

[0026] The timer is used to adjust the timing time of the timer based on the mode status signal output by the output end of the third trigger component when the timer is synchronously reset based on the third reset signal, and generate an adjusted timing signal.

[0027] In a possible implementation manner, the delay unit includes a second NOR gate and a delay circuit, the output end of the timer is connected to the input end of the second NOR gate, the output end of the second NOR gate is connected to the input end of the delay circuit, and the output end of the delay circuit is connected to the third input end of the second trigger component;

[0028] The second NOR gate is used to receive the timing signal output from the output terminal of the timer, and determine the delay signal input to the delay circuit based on the determined enable inversion signal and the timing signal.

[0029] In a possible implementation manner, the third trigger component includes a third trigger and a third OR gate, the output end of the third OR gate is connected to the clock end of the third trigger, and the output end of the second trigger component is connected to the input end of the third trigger;

[0030] The third OR gate is used to receive the second clock control signal output by the third output terminal of the first flip-flop component and the timing signal output by the second output terminal of the timer component, and determine the third clock control signal input to the third flip-flop based on the second clock control signal and the timing signal;

[0031] The third trigger is used to determine a mode state signal for characterizing the working mode of the circuit to be detected based on the first output signal outputted from the output terminal of the second trigger component and the third clock control signal.

[0032] In a second aspect, the present disclosure further provides a DC-DC circuit, comprising: a current detection circuit using digital counting as described in any one of the first aspect and various embodiments thereof, further comprising a control logic unit, the current detection circuit being connected to the control logic unit;

[0033] The control logic unit is used to generate a conduction inversion signal for reversely conducting a power tube in a DC-DC circuit and a standby signal for reversely controlling a gate of the power tube;

[0034] The current detection circuit is used to determine the operation mode of the DC-DC circuit in response to input of the conduction inverting signal and the standby signal.

[0035] In a possible implementation manner, it further includes a charge-discharge function unit provided with a charge-discharge component and at least one power tube, and the charge-discharge function unit is connected to the control logic unit;

[0036] The control logic unit is used to determine a conduction signal for conducting control of at least one power tube based on the output voltage in the current detection state, and to determine the charge and discharge state of the charge and discharge component based on the conduction signal to adjust the conduction signal according to the charge and discharge state, and repeat this process.

[0037] In a third aspect, the present disclosure further provides a current detection method using digital counting, which is applied to the current detection circuit using digital counting described in any one of the first aspect and various embodiments thereof, and the method includes:

[0038] In response to the first current value output by the circuit to be detected gradually increasing, the timer component starts timing when the power tube in the circuit to be detected is turned on;

[0039] Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component changes from low to high, and that a second clock control signal outputted from a third output terminal of the first trigger component remains low;

[0040] Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component changes from low to high according to the second number of rising edges;

[0041] In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component changes from low to high, thereby determining that the circuit to be detected gradually transitions from the low power consumption operating mode to the normal operating mode.

[0042] In a fourth aspect, the present disclosure further provides a current detection method using digital counting, which is applied to the current detection circuit using digital counting described in any one of the first aspect and various embodiments thereof, and the method includes:

[0043] In response to the second current value output by the circuit to be detected gradually decreasing, the timer component starts timing when the power tube in the circuit to be detected is turned on;

[0044] Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component remains low, and a second clock control signal outputted from a third output terminal of the first trigger component remains low;

[0045] Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component remains low according to the second number of rising edges;

[0046] In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component changes from high to low, thereby determining that the circuit to be detected gradually transitions from the normal working mode to the low power consumption working mode.

[0047] In a fifth aspect, the present disclosure further provides a current detection method using digital counting, which is applied to the current detection circuit using digital counting described in any one of the first aspect and various embodiments thereof, and the method includes:

[0048] In response to the third current value output by the circuit to be detected increasing rapidly, the timer component starts timing when the power tube in the circuit to be detected is turned on;

[0049] Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component changes from low to high, and a second clock control signal outputted from a third output terminal of the first trigger component changes from low to high;

[0050] Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component quickly becomes high according to the second number of rising edges;

[0051] In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component quickly becomes high, determining that the circuit to be detected directly enters the normal working mode from the low power consumption working mode.

[0052] In a sixth aspect, the present disclosure further provides a current detection method using digital counting, which is applied to the current detection circuit using digital counting described in any one of the first aspect and various embodiments thereof, and the method includes:

[0053] In response to the fourth current value output by the circuit to be detected decreasing rapidly, the timer component starts timing when the power tube in the circuit to be detected is turned on;

[0054] Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component remains low, and a second clock control signal outputted from a third output terminal of the first trigger component remains low;

[0055] Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component remains low according to the second number of rising edges;

[0056] In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component quickly becomes low, determining that the circuit to be detected directly enters the low power consumption working mode from the normal working mode.

[0057] The above-mentioned current detection circuit and method using digital counting, and the DC-DC circuit are adopted, and the first trigger component in the current detection circuit is used to determine the number of first rising edges corresponding to the turned-on inverted signal in response to the power tube in the circuit to be detected being in the on state, so as to determine the first clock control signal and the second clock control signal respectively output by the first output end and the third output end of the first trigger component according to the first rising edge number; the second trigger component is used to determine the number of second rising edges corresponding to the first clock control signal so as to determine the first output signal output by the output end of the second trigger component according to the second rising edge number; the third trigger component is used to determine the working mode of the circuit to be detected based on the first output signal, the second clock control signal and the timing signal output by the second output end of the timer component in response to the timer component reaching the set time. The working mode of the circuit to be detected is realized based on digital circuits such as a trigger component including several triggers. This is mainly because the output current of the circuit to be detected is proportional to the number of pulses of the power tube being turned on within a certain period of time. Therefore, a timer component and each trigger component are combined to count the number of pulses of the power tube being turned on, so that the determined working mode is more reliable. The overall circuit design occupies a smaller area and consumes lower power, thereby meeting the actual needs of more low-power products.

[0058] Other advantages of the present disclosure will be explained in more detail in conjunction with the following description and drawings.

[0059] It should be understood that the above description is only an overview of the technical solution of the present disclosure, so that the technical means of the present disclosure can be generally understood and then implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are specifically described below with examples. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope of protection. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work. Moreover, the same reference numerals are used to represent the same components throughout the drawings. In the drawings:

[0061] Figure 1 A schematic diagram of the structure of a current detection circuit using digital counting provided by an embodiment of the present disclosure is shown;

[0062] Figure 2 A circuit diagram of a current detection circuit using digital counting provided by an embodiment of the present disclosure is shown;

[0063] Figure 3 A timing diagram under a gradual transition detection strategy in a current detection circuit using digital counting provided by an embodiment of the present disclosure is shown;

[0064] Figure 4 A timing diagram under a jump change detection strategy in a current detection circuit using digital counting provided by an embodiment of the present disclosure is shown;

[0065] Figure 5 A schematic diagram of the structure of a DC-DC circuit provided by an embodiment of the present disclosure is shown;

[0066] Figure 6 A circuit diagram of a DC-DC circuit provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0067] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0068] In the description of the embodiments of the present disclosure, it should be understood that terms such as "including" or "having" are intended to indicate the presence of the disclosed features, numbers, steps, behaviors, components, parts, or a combination thereof in the specification, and do not exclude the possibility of the presence of one or more other features, numbers, steps, behaviors, components, parts, or a combination thereof.

[0069] Unless otherwise specified, “ / ” means or. For example, A / B can mean A or B. The “and / or” in this article is merely a way to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0070] The terms "first", "second", etc. are used only to distinguish the same or similar technical features for the convenience of description, and should not be understood as indicating or implying the relative importance or quantity of these technical features. Thus, the features defined by "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the term "plurality" means two or more than two.

[0071] According to research, electronic products generally have multiple working modes. In the normal working mode (mode 1), almost all functional modules are turned on, consuming a large current; in the standby working mode (mode 2), some functional modules are turned off, consuming a medium current; in the sleep working mode (mode 3), most functional modules are turned off, consuming the least current. These electronic products are generally powered by inductive DC-DC circuits. The DC-DC circuit as a power supply also needs to have a corresponding working mode to match the working mode of the subsequent circuit and reduce the total power consumption of the entire system.

[0072] In order to determine the working mode of the load circuit connected to the output, the DC-DC circuit requires a current detection circuit to detect its own output current, thereby determining the working mode of its own circuit according to the working mode of the output load.

[0073] Traditional current detection circuits use amplifiers to sample and amplify current to achieve current detection. In order to achieve sampling and amplification of current signals, operational amplifiers are required, and fast current detection requires the amplifier to have a large bandwidth. Large bandwidth means large current, which is very unfriendly to low-power design and is contrary to low-power design. Moreover, the use of amplifiers often requires frequency compensation, and compensation capacitors are also a considerable expense.

[0074] In order to at least partially solve one or more of the above-mentioned problems and other potential problems, the present disclosure provides at least one current detection scheme using digital counting, which uses digital circuits such as D flip-flops and logic gates, combined with low-power timing circuits, and determines the working mode of the DC-DC circuit by counting the number of power tube conduction pulses. The use of digital methods can achieve lower power consumption and lower area, and can significantly reduce circuit costs.

[0075] To facilitate understanding of this embodiment, a current detection circuit using digital counting disclosed in the embodiment of the present disclosure is first introduced in detail. Figure 1 , which shows a schematic diagram of the structure of a current detection circuit 10 provided in an embodiment of the present disclosure, the current detection circuit 10 includes: a first trigger component 11, a second trigger component 12, a third trigger component 13 and a timer component 14; the first output terminal 11a and the second output terminal 11b of the first trigger component 11 are respectively connected to the first input terminal 12a' and the second input terminal 12b' of the second trigger component 12, and the third output terminal 11c of the first trigger component 11 is connected to the first input terminal 13a' of the third trigger component 13; the output terminal 13a of the third trigger component 13 is connected to the first input terminal 14a' of the timer component 14, the first output terminal 14a of the timer component 14 is connected to the third input terminal 12c' of the second trigger component 12, and the second output terminal 14b of the timer component 14 is connected to the second input terminal 13b' of the third trigger component 13; the output terminal 12a of the second trigger component 12 is connected to the third input terminal 13c' of the third trigger component 13;

[0076] The first trigger component 11 is used for determining the number of first rising edges corresponding to the conduction inverted signal in response to the power tube in the circuit to be detected being in the conduction state, so as to determine the first clock control signal and the second clock control signal respectively outputted by the first output terminal 11a and the third output terminal 11c of the first trigger component 11 according to the number of the first rising edges;

[0077] The second trigger component 12 is used to determine the number of second rising edges corresponding to the first clock control signal to determine the first output signal output by the output terminal 12a of the second trigger component 12 according to the second rising edge number;

[0078] The third trigger component 13 is used to determine the working mode of the circuit to be detected based on the first output signal, the second clock control signal and the timing signal output by the second output terminal 14b of the timer component 14 in response to the timer component 14 reaching the set time.

[0079] The circuit to be detected here can be, for example, a DC-DC circuit, or other circuits that require current detection, wherein the DC-DC circuit can adopt a buck topology, a boost topology, a buck-boost topology, etc., and the specific type of the circuit to be detected is not specifically limited here. Considering the wide application of DC-DC buck circuits, the following examples are mostly DC-DC buck circuits.

[0080] Considering that the output current of the DC-DC circuit is proportional to the number of pulses of the power tube being turned on within a certain period of time, for example, as the output current increases, the number of pulses of the power tube being turned on will increase; conversely, if the output current decreases, the number of pulses of being turned on will decrease. Therefore, a combination of a multi-trigger component and a timer component 14 can be used here to realize current detection of the DC-DC circuit.

[0081] Here, the different current sizes detected will correspond to different working modes. For example, when in the normal working mode, the current consumed will be larger. For another example, when in the low power working mode, the current consumed will be smaller. Among them, the sleep working mode is one of the low power working modes. Most functional modules are turned off and the current consumption is minimized. The standby working mode is another low power working mode and will also consume a certain amount of current.

[0082] Based on this, the present disclosure provides a current detection circuit 10 based on pulse digital counting, and the current detection circuit 10 includes three trigger components (i.e., a first trigger component 11, a second trigger component 12, and a third trigger component 13). The first trigger component 11 can determine the number of first rising edges corresponding to the conduction inverted signal, the second trigger component 12 can determine the number of second rising edges corresponding to the first clock control signal output from the first output terminal 11a of the first trigger component 11, and the third trigger component 13 can determine the working mode of the circuit to be detected based on the first output signal output from the output terminal 12a of the second trigger component 12, the second clock control signal output from the third output terminal 11c of the first trigger component 11, and the timing signal output from the second output terminal 14b of the timer component 14.

[0083] In practical applications, a DC-DC circuit is used as an example of a circuit to be detected. When the load connected to the output of the DC-DC circuit gradually transitions from the sleep mode to the standby mode, and then to the normal working mode, the output current of the DC-DC circuit will gradually increase, the DC-DC circuit itself will gradually transition from the low power mode to the normal working mode, and the number of pulses of the on-phase reverse signal will gradually increase. Conversely, when the load connected to the output of the DC-DC circuit gradually transitions from the normal working mode to the standby mode, and then to the sleep mode, the output current of the DC-DC circuit will gradually decrease, the DC-DC circuit itself will gradually transition from the normal working mode to the low power mode, and the number of pulses of the on-phase reverse signal will gradually decrease.

[0084] Taking into account the corresponding relationship between the output current of the circuit to be detected and its own working mode, and the number of pulses of the power tube being turned on in the circuit to be detected within a certain period of time, the embodiment of the present disclosure provides a current detection circuit 10 that combines three trigger components (i.e., a first trigger component 11, a second trigger component 12, and a third trigger component 13) and a timer component 14 for digital counting.

[0085] The first trigger component 11 in the above-mentioned current detection circuit 10 may include one or more first triggers, and the corresponding number of first triggers can count the corresponding number of rising edges of the on-phase inversion signal. For example, five first triggers can correspond to recording five pulses of the on-phase inversion signal; similarly, the second trigger component 12 may include one or more second triggers, and the corresponding number of second triggers can count the corresponding number of rising edges of the first clock control signal. For example, three second triggers can correspond to recording three pulses of the first clock control signal; similarly, the third trigger component 13 may also include one or more third triggers to determine the working mode of the circuit to be detected.

[0086] It should be noted that the trigger component in the embodiment of the present disclosure may include not only corresponding triggers but also matching logic gates, and no specific restrictions are made here; in addition, no matter which trigger component it is, the various triggers included therein may adopt D triggers, or other types of triggers, and no specific restrictions are made here. The following will use D triggers as examples.

[0087] In order to facilitate further understanding of the current detection circuit 10 provided in the embodiment of the present disclosure, the three trigger components mentioned above will be described in detail below.

[0088] The first trigger component 11 in the embodiment of the present disclosure includes a plurality of first triggers, the plurality of first triggers are connected in series, and the input ends of the other first triggers except the first first trigger are connected to the output end of the previous first trigger; wherein:

[0089] A reset terminal of the first trigger, used to generate a first reset signal based on a standby signal output by a control logic unit of the circuit to be detected to trigger a reset function;

[0090] The clock end of the first trigger is used to receive the conduction inverted signal output by the control logic unit of the circuit to be detected to trigger the first rising edge counting function.

[0091] It can be known that the reset terminal and clock terminal of the first trigger are respectively triggered by the standby signal and the on-phase inversion signal output by the control logic unit. Through the serial connection of each first trigger, the pulse counting of the on-phase inversion signal can be realized (corresponding to the first rising edge counting function).

[0092] In practical applications, the multiple first triggers in the embodiment of the present disclosure are composed of five D triggers, among which the output ends of the second D trigger, the fourth D trigger and the fifth D trigger are respectively set to the first output end 11a, the second output end 11b and the third output end 11c of the first trigger component 11, so as to support the subsequent second trigger component 12, the third trigger component 13 and the timer component 14 to realize corresponding functions.

[0093] like Figure 2 As shown, it is a circuit diagram of a current detection circuit 10 of an example embodiment of the present disclosure, the five D flip-flops included in the first flip-flop component 11 are respectively denoted as DFF1~DFF5, wherein the output end of DFF2 can be used as the first output end 11a of the first flip-flop component 11, outputting the first clock control signal (CK1), the output end of DFF4 can be used as the second output end 11b of the first flip-flop component 11, and the output end of DFF5 can be used as the third output end 11c of the first flip-flop component 11, outputting the second clock control signal (CK2).

[0094] It should be noted that the number of first triggers includes but is not limited to the 5 D triggers in the above example. In practical applications, the number of first triggers can be increased or decreased to change the number of rising edge detections and achieve detection of smaller currents or larger currents. There are no specific restrictions on the number, type, etc. of first triggers.

[0095] In order to better realize the reset function of each first trigger included in the first trigger component 11, the first trigger component 11 here can also include a first NOR gate, such as Figure 2 As shown, the output terminal of the first NOR gate (NOR1) is connected to the reset terminal (R) of each first trigger; wherein:

[0096] The first NOR gate is used to receive a standby signal (standyMode) output by a control logic unit of the circuit to be detected, and based on a determined NOR operation between an enable inverting signal (ENB) and the standby signal, determine a first reset signal (RESET1), and transmit the first reset signal to a reset terminal of each first trigger.

[0097] The second trigger component 12 in the embodiment of the present disclosure includes a first OR gate and a plurality of second triggers, the plurality of second triggers are connected in series, the input ends of the second triggers other than the first second trigger are connected to the output ends of the previous second trigger, and the output end of the last second trigger and the second output end 11b of the first trigger component 11 are respectively connected to the two input ends of the first OR gate; wherein:

[0098] A reset terminal of the second trigger, used to receive a second reset signal output by the first output terminal 14a of the timer component 14 to trigger a reset function;

[0099] The clock terminal of the second trigger is used to receive the first clock control signal output by the first output terminal 11 a of the first trigger component 11 to trigger the second rising edge counting function.

[0100] It can be known that the reset end and the clock end of the second trigger are respectively triggered by the second reset signal output by the first output end 14a of the timer component 14 and the first clock control signal output by the first output end 11a of the first trigger component 11. Through the serial connection of each second trigger, the pulse counting of the first clock control signal (corresponding to the second rising edge counting function) can be realized.

[0101] In practical applications, the plurality of second triggers included in the second trigger component 12 in the embodiment of the present disclosure may be composed of three D triggers, such as Figure 2 As shown, the three D flip-flops are respectively denoted as DFF6~DFF8, and the clock terminals (CK) of DFF6~DFF8 are all triggered by the first clock control signal (CK1) output by DFF2, and the reset terminals (R) of DFF6~DFF8 are all triggered by the second reset signal (RESET2) output by the first output terminal 14a of the timer component 14.

[0102] It should be noted that the number of second triggers includes but is not limited to the three D triggers in the above example. In practical applications, the number of second triggers can be increased or decreased to change the number of rising edge detections and achieve detection of smaller currents or larger currents. There are no specific restrictions on the number and type of second triggers.

[0103] like Figure 2As shown, the first OR gate here can be recorded as OR1. The first OR gate (OR1) can respectively receive the second output signal (DATA2) output by the second output terminal 11b of the first trigger component 11 and the third output signal (DATA3) output by the output terminal of DFF8, and determine the first output signal (DATA1) output by the output terminal 12a (i.e., the output terminal of the first OR gate) of the second trigger component 12 based on the OR operation between the second output signal and the third output signal, so that the third trigger component 13 determines the working mode of the circuit to be detected based on the capture of the first output signal.

[0104] The third trigger component 13 in the embodiment of the present disclosure includes a third trigger and a third OR gate, the output end of the third OR gate is connected to the clock end of the third trigger, and the output end 12a of the second trigger component 12 is connected to the input end of the third trigger; wherein:

[0105] A third OR gate, configured to receive the second clock control signal outputted by the third output terminal 11c of the first flip-flop component 11 and the timing signal outputted by the second output terminal 14b of the timer component 14, and determine a third clock control signal inputted to the third flip-flop based on the second clock control signal and the timing signal;

[0106] The third trigger is used to determine a mode state signal for characterizing the working mode of the circuit to be detected based on the first output signal outputted from the output terminal 12a of the second trigger component 12 and the third clock control signal.

[0107] It can be seen that the clock end of the third trigger here is triggered based on the third clock control signal output by the third OR gate, and can be combined with the first output signal captured from the first OR gate to determine the output mode state signal, which can characterize the working mode of the circuit to be detected.

[0108] like Figure 2 As shown, the third flip-flop included in the third flip-flop component 13 can be recorded as DFF9, and the first output signal (DATA1) output by DFF9 through the first OR gate (OR1) can determine the mode state signal.

[0109] In the above process of implementing working mode detection, the support of the timer component 14 is required, that is, it needs to participate in the actual timing work to make real-time timing adjustments according to the current detection status. The working principle of the timer component 14 will be explained in detail below.

[0110] The timer component 14 in the embodiment of the present disclosure includes a timer unit and a delay unit, and the output end of the timer unit is respectively connected to the input end of the delay unit, the input end of the timer unit and the second input end 13b' of the third trigger component 13;

[0111] The output end of the delay unit serves as the first output end 14a of the timer component 14, and is used to maintain the output duration of the first output signal.

[0112] The delay design is added here to ensure that the first output signal output by the first OR gate has sufficient holding time so that the third trigger can acquire the correct state of the first output signal based on the input third clock control signal.

[0113] The timer unit in the embodiment of the present disclosure includes an inverter, a second OR gate and a timer connected in sequence, the output end of the inverter is connected to the first input end of the second OR gate, and the output end of the timer is connected to the second input end of the second OR gate; wherein:

[0114] a second OR gate, configured to receive an enable inverted signal output from an output terminal of the inverter and a timing signal output from an output terminal of the timer, and determine a third reset signal input to the timer based on an OR operation between the enable inverted signal and the timing signal;

[0115] The timer is used to adjust the timing time of the timer based on the mode state signal output by the output terminal 13a of the third trigger component 13 when the timer is synchronously reset based on the third reset signal, and generate an adjusted timing signal.

[0116] In practical applications, in addition to achieving more comprehensive current detection by increasing or decreasing the number of triggers, the embodiments of the present disclosure can also change the number of rising edge detections by increasing or decreasing the setting time of the timer, thereby achieving detection of smaller currents or larger currents.

[0117] The delay unit here includes a second NOR gate and a delay circuit, the output end of the timer is connected to the input end of the second NOR gate, the output end of the second NOR gate is connected to the input end of the delay circuit, and the output end of the delay circuit is connected to the third input end 12c' of the second trigger component 12; wherein:

[0118] The second NOR gate is used to receive the timing signal output from the output terminal of the timer, and determine the delay signal input to the delay circuit based on the determined enable inversion signal and the timing signal.

[0119] To facilitate the explanation of the working principle of the timer component 14, Figure 2 Provide an example.

[0120] like Figure 2As shown, the enable signal (EN) outputs an enable inverted signal (ENB) through the action of the inverter (INV1), and the second OR gate (OR2) receives the enable inverted signal on the one hand, and receives the timing signal (TCN) output by the output end of the timer on the other hand, and determines the third reset signal (Tp) input to the timer (Timer) based on the OR operation between the enable inverted signal and the timing signal. The timer adjusts the timing time of the timer based on the mode state signal (MODE_SEL) output by the output end of the third trigger (i.e., the output end 13a of the third trigger component 13) when the timer is synchronously reset based on the third reset signal, and then performs the next round of timing.

[0121] The current detection circuit 10 provided in the embodiment of the present disclosure can realize continuous operating mode detection (which can correspond to different mode detection strategies), such as detection of gradual transition from low-power operating mode to normal operating mode, detection of gradual transition from normal operating mode to low-power operating mode, detection of direct entry from low-power operating mode to normal operating mode, detection of direct entry from normal operating mode to low-power operating mode, and so on.

[0122] The low-power working mode here may correspond to a power-saving working mode including standby and sleep modes of the load connected to the DC-DC circuit output. In the actual detection process, the gradual transition of the mode may be, for example, sleep mode→standby mode→normal mode or normal mode→standby mode→sleep mode, or other transition forms, which are not specifically limited here; the sudden change of the mode may include, for example, sleep mode→normal mode or normal mode→sleep mode, or other sudden changes, which are not specifically limited here.

[0123] In order to further understand the gradual transition detection strategy provided by the embodiment of the present disclosure, the following can be combined with Figure 3 The gradual transition timing diagram shown is Figure 2 The working process of the current detection circuit diagram shown is further explained.

[0124] Here, when the load connected to the DC-DC circuit output switches sequentially between its operating modes (such as sleep mode → standby mode → normal mode), the current detected by the current detection circuit 10 provided in the embodiment of the present disclosure will gradually transition between the low power consumption operating mode and the normal operating mode.

[0125] First, when the output current of the circuit to be detected gradually increases from the low power operation mode:

[0126] 1) Before the power tube starts to turn on, the standby signal (standbyMode) and the enable inverting signal (ENB) are both 0, the output of the first NOR gate (NOR1) is high, and the first trigger DFF1~DFF5 counts the number of rising edges of the power tube's turn-on inverting signal ( / DRV_SP).

[0127] In each standbyMode working cycle, when the second pulse appears, the first clock control signal (CK1) output by the first flip-flop DFF2 will become high; while the standbyMode is 0, the timer (Timer) starts timing internally.

[0128] 2) The second flip-flops DFF6 to DFF8 count the number of rising edges of CK1. When three CK1 pulses appear in succession, the third output signal (DATA3) output by the second flip-flop DFF8 and the first output signal (DATA1) output by the first OR gate (OR1) will become high. The second output signal (DATA2) output by the first flip-flop DFF4 and the second clock control signal (CK2) output by the first flip-flop DFF5 will remain low due to the reset of the standby signal.

[0129] 3) When the timer reaches the set time, the timing signal (TCN) it outputs and the third clock control signal (CK3) output by the third OR gate (OR3) generate a narrow pulse clock signal to capture the input signal of the third flip-flop DFF9, then the mode status signal (MODEL_SEL) output by the third flip-flop DFF9 changes from low to high, and the circuit enters the normal mode.

[0130] At this time, MODEL_SEL increases the timing time of the Timer, and the third reset signal (Tp) output by TCN through the second OR gate (OR2) resets the Timer synchronously, preparing for the next timing. This process will be repeated to achieve real-time monitoring of current changes.

[0131] 4) The enable signal (EN) passes through the inverter (INV1) to obtain ENB. ENB and the output signal TCN of the timer pass through OR2 to generate a narrow pulse Tp to reset the timer. The TCN and ENB output by the timer pass through the second NOR gate (NOR2) and the delay circuit (Delay) to generate the reset signal (RESET2) of the second flip-flop DFF6~DFF8.

[0132] Second, when the output current of the circuit to be detected gradually decreases from the normal working mode:

[0133] 1) Similarly, before the power tube starts to turn on, the standby signal (standbyMode) and the enable inverting signal (ENB) are 0, the output of the first NOR gate (NOR1) is high, and the first trigger DFF1~DFF5 counts the number of rising edges of the power tube's turn-on inverting signal ( / DRV_SP).

[0134] If the output current is very small, no more than two pulses will appear in each standbyMode working cycle, and the first clock control signal (CK1) output by the first flip-flop DFF2 will always be low.

[0135] 2) Due to the small current and the small number of on-pulses, the third output signal (DATA3) output by the second flip-flop DFF8, the second output signal (DATA2) output by the first flip-flop DFF4, and the first output signal (DATA1) output by the first OR gate (OR1) are all low. When the timer (Timer) reaches the set time, the timing signal (TCN) output by the Timer and the third clock control signal (CK3) output by the third OR gate (OR3) generate a narrow pulse clock signal.

[0136] Since the input of the input terminal (D) of the third flip-flop DFF9 is low, the mode state signal (MODEL_SEL) output by DFF9 will change from high to low, and the circuit will enter the low power mode. At this time, MODEL_SEL reduces the timing time of the Timer, and the signal TCN resets the Timer synchronously through the third reset signal (Tp) output by OR2, preparing for the next timing. This process will be repeated to achieve real-time monitoring of current changes.

[0137] 3) The enable signal (EN) passes through the inverter (INV1) to obtain ENB. ENB and the output signal TCN of the timer pass through OR2 to generate a narrow pulse Tp to reset the timer. The TCN and ENB output by the timer pass through the second NOR gate (NOR2) and the delay circuit (Delay) to generate the reset signal (RESET2) of the second flip-flop DFF6~DFF8.

[0138] In order to further understand the jump transformation detection strategy provided by the embodiment of the present disclosure, the following can be combined with Figure 4 The jump transition timing diagram shown is Figure 2 The working process of the current detection circuit 10 shown in FIG. 1 is further explained.

[0139] When the load connected to the DC-DC circuit output jumps between operating modes (such as sleep mode→normal mode), the current detected by the current detection circuit 10 provided in the embodiment of the present disclosure will suddenly switch between the low power consumption operating mode and the normal operating mode.

[0140] First, when the output current of the circuit to be detected suddenly enters the normal working mode from the low power working mode:

[0141] 1) Before the power tube starts to turn on, the standby signal (standbyMode) and the enable inverting signal (ENB) are 0, the output of the first NOR gate (NOR1) is high, and the first trigger DFF1~DFF5 counts the number of rising edges of the power tube's conduction pulse ( / DRV_SP).

[0142] Since the current is normal, the circuit will have more than 5 pulses continuously, and the second clock control signal (CK2) output by the first flip-flop DFF5 will become high. When the standbyMode is 0, the timer (Timer) starts timing internally.

[0143] 2) The second flip-flops DFF6 to DFF8 also count the number of rising edges of the first clock control signal (CK1) output by the first flip-flop DFF2. However, since the second output signal (DATA2) output by the first flip-flop DFF4 is generated before the third output signal (DATA3) output by the second flip-flop DFF8, the first output signal (DATA1) output by the first OR gate (OR1) quickly changes to high. Similarly, the second clock control signal (CK2) of the first flip-flop DFF5 takes precedence over the timing signal (TCN) output by the Timer. The third clock control signal (CK3) output by the third OR gate (OR3) quickly generates a narrow pulse clock signal, which captures the high level of DATA1 input by the third flip-flop DFF9. The mode state signal (MODEL_SEL) output by the third flip-flop DFF9 changes from low to high, and the circuit quickly enters the normal mode.

[0144] At this time, MODEL_SEL increases the timing time of the Timer, and the signal TCN resets the Timer synchronously through the output Tp of OR2 to prepare for the next timing.

[0145] 3) The enable signal (EN) passes through the inverter (INV1) to obtain ENB. ENB and the output signal TCN of the timer pass through OR2 to generate a narrow pulse Tp to reset the timer. The TCN and ENB output by the timer pass through the second NOR gate (NOR2) and the delay circuit (Delay) to generate the reset signal (RESET2) of the second flip-flop DFF6~DFF8.

[0146] Secondly, when the output current of the circuit to be detected suddenly enters the low power mode from the normal working mode, its operation is similar to the previous situation where the current gradually enters the low power mode from the normal working mode, and its working principle will not be repeated here.

[0147] After determining that a state change occurs based on the received mode switching signal (MODE_SEL), the timer (Timer) adjusts the set time to prevent MODE_SEL from changing repeatedly.

[0148] It should be noted that the gradual transition detection strategy and jump change detection strategy in the above-mentioned examples of the embodiments of the present disclosure are example detection strategies. In practical applications, more detection strategies can be implemented by increasing the various combinations of logic signals brought about by the number of triggers and combinational circuits, and no specific restrictions are made here.

[0149] Compared with the current detection circuit in the prior art, the current detection circuit 10 using digital counting provided in the embodiment of the present disclosure mainly has the following technical advantages:

[0150] 1) Using digital counting to detect current size and avoid using amplifiers can reduce circuit current consumption and extend battery life.

[0151] 2) Using digital methods can avoid complex analog circuits, eliminate the need for capacitor frequency compensation, and reduce circuit costs.

[0152] 3) The use of digital methods adapts to the process of technological evolution, and can easily move the circuit to a more advanced process, speeding up the circuit development process.

[0153] 4) The various combinations of logic signals brought about by increasing the number of triggers and combinational circuits can realize the detection of more working modes.

[0154] Based on the current detection circuit 10 using digital counting, the embodiment of the present disclosure further provides a DC-DC circuit, such as Figure 5 As shown, the DC-DC circuit mainly includes a current detection circuit 10 and a control logic unit 20, and the current detection circuit 10 is connected to the control logic unit 20; wherein:

[0155] The control logic unit 20 is used to generate a conduction inversion signal for reversely conducting the power tube in the DC-DC circuit and a standby signal for reversely controlling the gate of the power tube;

[0156] The current detection circuit 10 is used to determine the operation mode of the DC-DC circuit in response to the input of the conduction inverting signal and the standby signal.

[0157] The DC-DC circuit provided in the embodiment of the present disclosure further includes a charge-discharge function unit 30 provided with a charge-discharge component and at least one power tube, and the charge-discharge function unit 30 is connected to the control logic unit 20; wherein:

[0158] The control logic unit 20 is used to determine a conduction signal for conducting control of at least one power tube based on the output voltage in the current detection state, and determine the charge and discharge state of the charge and discharge component based on the conduction signal to adjust the conduction signal according to the charge and discharge state, and so on.

[0159] The charging and discharging components here may include, for example, inductors, capacitors and other devices.

[0160] In order to further understand the working principle of the above DC-DC circuit, we can combine Figure 6 A specific DC-DC buck circuit shown is described in detail.

[0161] When the circuit starts working, the output voltage (VOUT) is less than the reference voltage (VREF1) after the divided voltage (VFB) of feedback resistor 1 (RFA) and feedback resistor 2 (RFB), the output signal 1 (VCOM) of comparator 1 (CMP1) is low, and the adaptive conduction module (Ton) starts working, generating a high-level signal with a width of Ton.

[0162] After receiving the Ton high-level signal, the control logic unit 20 generates a low-level gate control signal 1 (DRV_SP) and a low-level gate control signal 2 (DRV_SN) with a width of Ton, turns on the power tube 1 (MP), turns off the power tube 2 (MN), and charges the inductor (L) and the output capacitor (CL). / DRV_SP is the inverted signal of DRV_SP, that is, the conduction inverted signal.

[0163] After the Ton time is over, under the action of the control logic unit 20, DRV_SP and DRV_SN become high, MP is turned off, MN is turned on, and L is discharged to charge CL.

[0164] At this time, the inductor current gradually decreases. When the inductor current is less than a certain set value, the output signal 2 (ZCD) of the comparator 2 (CMP2) changes from low to high. After being processed by the control logic unit 20, DRV_SN changes from high to low, the standby signal (standbyMode) changes from low to high, MP and MN are both cut off, and the circuit is in standby mode. When VFB is less than VREF1, the circuit repeats the above operation.

[0165] Due to the delay in the circuit, in order to avoid the backflow of the inductor current, the DC-DC circuit provided in the embodiment of the present disclosure introduces an offset voltage (VOS) at the positive end of CMP2. At a certain value before the inductor current is discharged to zero, the output ZCD of CMP2 becomes high in advance. After the delay of the logic circuit, the control signal DRV_SN of MN can become low in time to turn off MN.

[0166] In order to prevent MP and MN from being turned on at the same time, which would cause a large current to flow from the power supply to the ground, a dead time needs to be set between the gate control signals DRV_SP and DRV_SN.

[0167] In order to prevent high-frequency oscillation in the circuit, CMP1 needs to set hysteresis. The minimum off module (Toff_min) can set a minimum off time to prevent MP from repeatedly turning on.

[0168] It can be seen that when MP is turned on or off, the charging and discharging functions of the inductor and capacitor included in the charging and discharging components will be triggered, and then the conduction signal will be adjusted, thereby changing the signal output result of the corresponding trigger and related logic gate in the corresponding current detection circuit 10, and realizing current detection in a digital counting mode, so that the working mode of the DC-DC circuit and the electronic device to which it is applied can be better determined, and the power consumption of the entire current detection circuit 10 is lower, which is more in line with the low power consumption requirements of actual electronic equipment.

[0169] Based on the above-mentioned current detection circuit 10 using digital counting, the embodiment of the present disclosure also provides several current detection methods, which will be described in detail in the following aspects.

[0170] First aspect: When the output current of the circuit to be detected gradually increases from the low power operation mode, the current detection can be performed according to the following steps:

[0171] Step 1: In response to the first current value output by the circuit to be detected gradually increasing, the timer component 14 starts timing when the power tube in the circuit to be detected is turned on;

[0172] Step 2: using the first trigger component 11 to determine the number of first rising edges corresponding to the conduction inverted signal, and determining that the first clock control signal outputted from the first output terminal 11a of the first trigger component 11 changes from low to high, and the second clock control signal outputted from the third output terminal 11c remains low according to the number of the first rising edges;

[0173] Step 3: using the second trigger component 12 to determine the number of second rising edges corresponding to the first clock control signal, and determining that the first output signal outputted by the output terminal 12a of the second trigger component 12 changes from low to high according to the number of second rising edges;

[0174] Step 4, in response to the timer component 14 reaching the set time, the third trigger component 13 is used to determine the mode state signal based on the first output signal output by the output terminal 12a of the second trigger component 12, the second clock control signal output by the third output terminal 11c of the first trigger component 11, and the timing signal output by the second output terminal 14b of the timer component 14, which changes from low to high, to determine that the circuit to be detected gradually transitions from the low power consumption working mode to the normal working mode.

[0175] For the specific implementation of the detection strategy for gradually transitioning from the low-power working mode to the normal working mode, please refer to the relevant description content, which will not be repeated here.

[0176] Second aspect: When the output current of the circuit to be detected gradually decreases from the normal working mode, the current detection can be performed according to the following steps:

[0177] Step 1: In response to the second current value output by the circuit to be detected gradually decreasing, the timer component 14 starts timing when the power tube in the circuit to be detected is turned on;

[0178] Step 2: using the first trigger component 11 to determine the number of first rising edges corresponding to the conduction inverted signal, and determining that the first clock control signal outputted by the first output terminal 11a of the first trigger component 11 remains low and the second clock control signal outputted by the third output terminal 11c remains low according to the number of the first rising edges;

[0179] Step 3: using the second trigger component 12 to determine the number of second rising edges corresponding to the first clock control signal, and determining that the first output signal outputted by the output terminal 12a of the second trigger component 12 is kept low according to the number of second rising edges;

[0180] Step 4. In response to the timer component 14 reaching the set time, the third trigger component 13 is used to determine that the mode state signal based on the first output signal output by the output terminal 12a of the second trigger component 12, the second clock control signal output by the third output terminal 11c of the first trigger component 11, and the timing signal output by the second output terminal 14b of the timer component 14 changes from high to low, thereby determining that the circuit to be detected gradually transitions from the normal working mode to the low power consumption working mode.

[0181] For the specific implementation of the detection strategy for gradually transitioning from the normal working mode to the low power working mode, please refer to the relevant description content, which will not be repeated here.

[0182] Third aspect: When the output current of the circuit to be detected suddenly enters the normal working mode from the low power working mode, the current detection can be implemented according to the following steps:

[0183] Step 1: In response to the third current value output by the circuit to be detected increasing rapidly, the timer component 14 starts timing when the power tube in the circuit to be detected is turned on;

[0184] Step 2: using the first trigger component 11 to determine the number of first rising edges corresponding to the conduction inverted signal, and determining that the first clock control signal outputted from the first output terminal 11a of the first trigger component 11 changes from low to high, and the second clock control signal outputted from the third output terminal 11c changes from low to high according to the number of the first rising edges;

[0185] Step 3: using the second trigger component 12 to determine the number of second rising edges corresponding to the first clock control signal, and determining that the first output signal outputted by the output terminal 12a of the second trigger component 12 quickly becomes high according to the number of second rising edges;

[0186] Step 4, in response to the timer component 14 reaching the set time, the mode state signal determined by the third trigger component 13 based on the first output signal output by the output terminal 12a of the second trigger component 12, the second clock control signal output by the third output terminal 11c of the first trigger component 11, and the timing signal output by the second output terminal 14b of the timer component 14 quickly becomes high, determining that the circuit to be detected directly enters the normal working mode from the low power working mode.

[0187] For the specific implementation of the detection strategy for directly entering the normal working mode from the low power working mode, please refer to the relevant description content, which will not be repeated here.

[0188] Fourth aspect: When the output current of the circuit to be detected suddenly enters the low-power working mode from the normal working mode, the current detection can be achieved according to the following steps:

[0189] Step 1: In response to the fourth current value output by the circuit to be detected decreasing rapidly, the timer component 14 starts timing when the power tube in the circuit to be detected is turned on;

[0190] Step 2: using the first trigger component 11 to determine the number of first rising edges corresponding to the conduction inverted signal, and determining that the first clock control signal outputted by the first output terminal 11a of the first trigger component 11 remains low and the second clock control signal outputted by the third output terminal 11c remains low according to the number of the first rising edges;

[0191] Step 3: using the second trigger component 12 to determine the number of second rising edges corresponding to the first clock control signal, and determining that the first output signal outputted by the output terminal 12a of the second trigger component 12 is kept low according to the number of second rising edges;

[0192] Step 4, in response to the timer component 14 reaching the set time, the mode state signal determined by the third trigger component 13 based on the first output signal output by the output terminal 12a of the second trigger component 12, the second clock control signal output by the third output terminal 11c of the first trigger component 11, and the timing signal output by the second output terminal 14b of the timer component 14 quickly becomes low, determining that the circuit to be detected directly enters the low power consumption working mode from the normal working mode.

[0193] For the specific implementation of the detection strategy for directly entering the low power consumption working mode from the normal working mode, please refer to the relevant description content, which will not be repeated here.

[0194] In the description of this specification, the description with reference to the terms "some possible embodiments", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure, and the above terms do not necessarily represent the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0195] Those skilled in the art will appreciate that, in the method described in the above specific implementation, the writing order of each step does not mean a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0196] Although the spirit and principle of the present disclosure have been described above with reference to several specific embodiments, it should be understood that the present disclosure is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined. The present disclosure is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached claims.

Claims

1. A current detection circuit using digital counting, characterized in that: include: A first trigger component, a second trigger component, a third trigger component and a timer component; The first output terminal and the second output terminal of the first trigger component are connected to the first input terminal and the second input terminal of the second trigger component respectively, and the third output terminal of the first trigger component is connected to the first input terminal of the third trigger component; the output terminal of the third trigger component is connected to the first input terminal of the timer component, the first output terminal of the timer component is connected to the third input terminal of the second trigger component, and the second output terminal of the timer component is connected to the second input terminal of the third trigger component; The output terminal of the second trigger component is connected to the third input terminal of the third trigger component; The first trigger component is used for determining the number of first rising edges corresponding to the conduction inverted signal in response to the power tube in the circuit to be detected being in the conduction state, so as to determine the first clock control signal and the second clock control signal respectively outputted by the first output terminal and the third output terminal of the first trigger component according to the first rising edge number; The second trigger component is used to determine the number of second rising edges corresponding to the first clock control signal to determine a first output signal output by the output end of the second trigger component according to the second rising edge number; The third trigger component is used to determine the working mode of the circuit to be detected based on the first output signal, the second clock control signal and the timing signal output by the second output terminal of the timer component in response to the timer component reaching a set time.

2. The current detection circuit using digital counting according to claim 1, characterized in that: The first trigger component includes a plurality of first triggers, the plurality of first triggers are connected in series, and the input ends of the other first triggers except the first first trigger are connected to the output end of the previous first trigger; The reset terminal of the first trigger is used to generate a first reset signal based on the standby signal output by the control logic unit of the circuit to be detected to trigger a reset function; The clock terminal of the first trigger is used to receive the conduction inverted signal output by the control logic unit of the circuit to be detected to trigger the first rising edge counting function.

3. The current detection circuit using digital counting according to claim 2, characterized in that: The plurality of first flip-flops are composed of five D flip-flops; The output terminals of the second D flip-flop, the fourth D flip-flop and the fifth D flip-flop are respectively set as the first output terminal, the second output terminal and the third output terminal of the first flip-flop component.

4. The current detection circuit using digital counting according to claim 2, characterized in that: The first trigger component further includes a first NOR gate, wherein an output terminal of the first NOR gate is connected to a reset terminal of each of the first triggers; The first NOR gate is used to receive a standby signal output by a control logic unit of the circuit to be detected, and determine the first reset signal based on a NOR operation between a determined enable inverted signal and the standby signal.

5. The current detection circuit using digital counting according to claim 1, characterized in that: The second trigger component includes a first OR gate and a plurality of second triggers, the plurality of second triggers are connected in series, the input ends of the second triggers other than the first second trigger are connected to the output end of the previous second trigger, and the output end of the last second trigger and the second output end of the first trigger component are respectively connected to the two input ends of the first OR gate; The reset terminal of the second trigger is used to receive the second reset signal output by the first output terminal of the timer component to trigger the reset function; The clock terminal of the second trigger is used to receive the first clock control signal output by the first output terminal of the first trigger component to trigger a second rising edge counting function.

6. The current detection circuit using digital counting according to claim 5, characterized in that: The plurality of second flip-flops are composed of three D flip-flops; The first OR gate is used to respectively receive the second output signal output from the second output terminal of the first trigger component and the third output signal output from the output terminal of the third D trigger, and determine the first output signal output from the output terminal of the second trigger component based on the OR operation between the second output signal and the third output signal.

7. The current detection circuit using digital counting according to claim 1, characterized in that: The timer component comprises a timer unit and a delay unit, and the output end of the timer unit is respectively connected to the input end of the delay unit, the input end of the timer unit and the second input end of the third trigger component; The output end of the delay unit serves as the first output end of the timer component, and is used to maintain the output duration of the first output signal.

8. The current detection circuit using digital counting according to claim 7, characterized in that: The timer unit comprises an inverter, a second OR gate and a timer connected in sequence, the output end of the inverter is connected to the first input end of the second OR gate, and the output end of the timer is connected to the second input end of the second OR gate; The second OR gate is used to receive the enable inverted signal output from the output terminal of the inverter and the timing signal output from the output terminal of the timer, and determine the third reset signal input to the timer based on the OR operation between the enable inverted signal and the timing signal; The timer is used to adjust the timing time of the timer based on the mode status signal output by the output end of the third trigger component when the timer is synchronously reset based on the third reset signal, and generate an adjusted timing signal.

9. The current detection circuit using digital counting according to claim 8, characterized in that: The delay unit includes a second NOR gate and a delay circuit, the output end of the timer is connected to the input end of the second NOR gate, the output end of the second NOR gate is connected to the input end of the delay circuit, and the output end of the delay circuit is connected to the third input end of the second trigger component; The second NOR gate is used to receive the timing signal output from the output terminal of the timer, and determine the delay signal input to the delay circuit based on the determined enable inversion signal and the timing signal.

10. The current detection circuit using digital counting according to claim 1, characterized in that: The third trigger component includes a third trigger and a third OR gate, the output end of the third OR gate is connected to the clock end of the third trigger, and the output end of the second trigger component is connected to the input end of the third trigger; The third OR gate is used to receive the second clock control signal output by the third output terminal of the first flip-flop component and the timing signal output by the second output terminal of the timer component, and determine the third clock control signal input to the third flip-flop based on the second clock control signal and the timing signal; The third trigger is used to determine a mode state signal for characterizing the working mode of the circuit to be detected based on the first output signal outputted from the output terminal of the second trigger component and the third clock control signal.

11. A DC-DC circuit, characterized in that: include: The current detection circuit using digital counting according to any one of claims 1 to 10, further comprising a control logic unit, wherein the current detection circuit is connected to the control logic unit; The control logic unit is used to generate a conduction inversion signal for reversely conducting a power tube in a DC-DC circuit and a standby signal for reversely controlling a gate of the power tube; The current detection circuit is used to determine the operation mode of the DC-DC circuit in response to input of the conduction inverting signal and the standby signal.

12. The DC-DC circuit according to claim 11, characterized in that: It also includes a charge and discharge functional unit provided with a charge and discharge assembly and at least one power tube, and the charge and discharge functional unit is connected to the control logic unit; The control logic unit is used to determine a conduction signal for conducting control of at least one power tube based on the output voltage in the current detection state, and to determine the charge and discharge state of the charge and discharge component based on the conduction signal to adjust the conduction signal according to the charge and discharge state, and repeat this process.

13. A current detection method using digital counting, characterized in that: The current detection circuit using digital counting as applied to any one of claims 1 to 10, the method comprising: In response to the first current value output by the circuit to be detected gradually increasing, the timer component starts timing when the power tube in the circuit to be detected is turned on; Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component changes from low to high, and that a second clock control signal outputted from a third output terminal of the first trigger component remains low; Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component changes from low to high according to the second number of rising edges; In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component changes from low to high, thereby determining that the circuit to be detected gradually transitions from the low power consumption operating mode to the normal operating mode.

14. A current detection method using digital counting, characterized in that: The current detection circuit using digital counting as applied to any one of claims 1 to 10, the method comprising: In response to the second current value output by the circuit to be detected gradually decreasing, the timer component starts timing when the power tube in the circuit to be detected is turned on; Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component remains low, and a second clock control signal outputted from a third output terminal of the first trigger component remains low; Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component remains low according to the second number of rising edges; In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component changes from high to low, thereby determining that the circuit to be detected gradually transitions from the normal working mode to the low power consumption working mode.

15. A current detection method using digital counting, characterized in that: The current detection circuit using digital counting as applied to any one of claims 1 to 10, the method comprising: In response to the third current value output by the circuit to be detected increasing rapidly, the timer component starts timing when the power tube in the circuit to be detected is turned on; Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and determining that a first clock control signal outputted from a first output terminal of the first trigger component changes from low to high, and a second clock control signal outputted from a third output terminal of the first trigger component changes from low to high according to the first rising edge number; Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component quickly becomes high according to the second number of rising edges; In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component quickly becomes high, determining that the circuit to be detected directly enters the normal working mode from the low power consumption working mode.

16. A current detection method using digital counting, characterized in that: The current detection circuit using digital counting as applied to any one of claims 1 to 10, the method comprising: In response to the fourth current value output by the circuit to be detected decreasing rapidly, the timer component starts timing when the power tube in the circuit to be detected is turned on; Using a first trigger component to determine the number of first rising edges corresponding to the turned-on inverted signal, and according to the first number of rising edges, determining that a first clock control signal outputted from a first output terminal of the first trigger component remains low, and a second clock control signal outputted from a third output terminal of the first trigger component remains low; Using a second trigger component to determine the number of second rising edges corresponding to the first clock control signal, and determining that a first output signal outputted from an output terminal of the second trigger component remains low according to the second number of rising edges; In response to the timer component reaching the set time, the mode state signal determined by the third trigger component based on the first output signal output from the output end of the second trigger component, the second clock control signal output from the third output end of the first trigger component, and the timing signal output from the second output end of the timer component quickly becomes low, determining that the circuit to be detected directly enters the low power consumption working mode from the normal working mode.

Images