Display substrate, preparation method thereof and display panel

Abstract

The invention provides a display substrate which comprises a substrate body, a plurality of grid lines and a plurality of data lines, the grid lines and the data lines are arranged on the substrate body, and the grid lines and the data lines are arranged in a crossed mode to define a plurality of pixel units. Each pixel unit comprises a thin film transistor and a pixel electrode electrically connected with a drain electrode of the thin film transistor; the display substrate further comprises a touch signal line arranged on the side, away from the substrate, of the layer where the data lines are located, and the touch signal line is located between every two adjacent columns of pixel units.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a preparation method thereof, and a display panel. Background Art

[0002] With the development of information technology society, people's demand for display devices has increased significantly. Liquid crystal display technology has obvious advantages in display quality, manufacturing cost and promotion strength, and has become the mainstream technology type in the current display market. Liquid crystal display panels are the mainstream flat-panel displays in the current market. They are used in various display fields ranging from small sizes such as instruments and mobile phones to medium and large sizes such as monitors and ultra-large televisions. In the prior art, the touch signal line TL in the liquid crystal display panel is set in the pixel unit P, which is not conducive to achieving a high pixel aperture ratio. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, comprising a base substrate, a plurality of gate lines and a plurality of data lines arranged on the base substrate, wherein the plurality of gate lines and the plurality of data lines are arranged to cross to define a plurality of pixel units; the pixel unit comprises a thin film transistor and a pixel electrode electrically connected to the drain of the thin film transistor; wherein,

[0004] The display substrate further comprises a touch signal line arranged on a side of the layer where the data line is located away from the base substrate, and the touch signal line is located between two adjacent columns of the pixel units.

[0005] In some embodiments, for the data line and the touch signal line located between two adjacent columns of the pixel units, their orthographic projections on the substrate at least partially overlap.

[0006] In some embodiments, the source and drain of the thin film transistor are arranged in the same layer as the data line, and an interlayer insulating layer is provided on the side of the layer where the data line is located away from the base substrate, and the pixel electrode is connected to the drain of the thin film transistor through a first via hole penetrating the interlayer insulating layer; the interlayer insulating layer also includes a first accommodating portion partially penetrating along its thickness direction, and the touch signal line is located in the first accommodating portion.

[0007] In some embodiments, the touch signal line includes a first substructure and a second substructure which are sequentially arranged in a direction away from the base substrate; the second substructure is arranged in the same layer as the pixel electrode and is made of the same material.

[0008] In some embodiments, the pixel electrode is connected to the drain of the thin film transistor via a first connecting electrode, and the first connecting electrode is disposed in the same layer as the first substructure and is made of the same material.

[0009] In some embodiments, the interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer arranged in sequence along a direction away from the base substrate; a common electrode is arranged between the second sub-insulating layer and the third sub-insulating layer; and the first accommodating portion passes through the second sub-insulating layer and the third sub-insulating layer.

[0010] In some embodiments, a first auxiliary electrode is disposed on a side of the touch signal line close to the base substrate, the first auxiliary electrode is disposed on the same layer as the common electrode, and the orthographic projection of the first auxiliary electrode on the base substrate covers the orthographic projection of the first accommodating portion on the base substrate.

[0011] In some embodiments, the source and drain of the thin film transistor are arranged in the same layer as the data line, an interlayer insulating layer is arranged on the side of the layer where the data line is located away from the base substrate, and the pixel electrode is connected to the drain of the thin film transistor through a first via hole penetrating the interlayer insulating layer.

[0012] In some embodiments, the touch signal line includes a first substructure and a second substructure which are sequentially arranged in a direction away from the base substrate; the first substructure is arranged in the same layer as the pixel electrode and is made of the same material.

[0013] In some embodiments, the interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer arranged in sequence along a direction away from the base substrate; a common electrode is arranged between the second sub-insulating layer and the third sub-insulating layer; the common electrode at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

[0014] The present disclosure also provides a method for preparing a display substrate, comprising:

[0015] Providing a base substrate; forming a plurality of gate lines and a plurality of data lines on the base substrate, and pixel units located at intersections of the gate lines and the data lines;

[0016] Forming the pixel unit includes: forming a thin film transistor on the substrate, and a pixel electrode electrically connected to the drain of the thin film transistor;

[0017] Wherein, the method for preparing the display substrate further comprises:

[0018] A touch signal line is formed on a side of the layer where the data line is located away from the base substrate; the touch signal line is located between two adjacent columns of the pixel units.

[0019] In some embodiments, the data line and the source and drain of each of the thin film transistors are formed in one patterning process;

[0020] The preparation method also includes forming an interlayer insulating layer on the side of the layer where the data line is located away from the base substrate before forming the touch signal line; the interlayer insulating layer includes a first via hole penetrating along its thickness direction, and a first accommodating portion partially penetrating along its thickness direction; the pixel electrode is electrically connected to the drain of the thin film transistor through the first via hole, and the touch signal line is located in the first accommodating portion.

[0021] In some embodiments, the interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer sequentially arranged in a direction away from the substrate; the step of forming the interlayer insulating layer includes:

[0022] Forming a first sub-insulating layer on a side of the layer where the data line is located away from the base substrate;

[0023] The second sub-insulating layer is formed on a side of the first sub-insulating layer away from the base substrate; the second sub-insulating layer has a first sub-hole of the first via hole penetrating the first sub-insulating layer and the second sub-insulating layer along the thickness direction thereof, and a second sub-hole penetrating the first receiving portion of the second sub-insulating layer;

[0024] The third sub-insulating layer is formed on a side of the second sub-insulating layer away from the base substrate; the third sub-insulating layer has a third sub-hole of the first via hole penetrating along the thickness direction thereof, and a fourth sub-hole penetrating the first accommodation portion of the third sub-insulating layer;

[0025] The first sub-hole and the third sub-hole constitute the first via hole, and the second sub-hole and the fourth sub-hole constitute the first accommodation portion.

[0026] In some embodiments, the step of forming the touch signal line includes sequentially forming a first substructure and a second substructure along a direction away from the base substrate; the second substructure and the pixel electrode are formed in one patterning process.

[0027] In some embodiments, the step of forming the touch signal line includes forming a first substructure and a second substructure in sequence along a direction away from the base substrate; while forming the first substructure, a first connecting electrode is also formed; the first connecting electrode is located in the first via hole, and the first connecting electrode is used to electrically connect the pixel electrode to the drain of the thin film transistor.

[0028] In some embodiments, before forming the second sub-insulating layer and the third sub-insulating layer, the steps of forming a common electrode and forming a first auxiliary electrode covering the second sub-hole are further included.

[0029] In some embodiments, the interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer, and a third sub-insulating layer sequentially arranged in a direction away from the substrate; the step of forming the interlayer insulating layer includes:

[0030] Forming a first sub-insulating layer on a side of the layer where the data line is located away from the base substrate;

[0031] The second sub-insulating layer is formed at a portion of the first sub-insulating layer away from the base substrate; the second sub-insulating layer has a first sub-hole of a first via hole penetrating through the first sub-insulating layer and the second sub-insulating layer along a thickness direction thereof;

[0032] The third sub-insulating layer is formed on a side of the second sub-insulating layer away from the base substrate; the third sub-insulating layer has a third sub-hole of the first via hole penetrating along a thickness direction thereof;

[0033] The first sub-hole and the third sub-hole constitute the first via hole.

[0034] In some embodiments, the step of forming the touch signal line includes sequentially forming a first substructure and a second substructure along a direction away from the base substrate; the first substructure and the pixel electrode are formed in one patterning process.

[0035] In some embodiments, between forming the second sub-insulating layer and the third sub-insulating layer, a step of forming a common electrode is also included.

[0036] The present disclosure also provides a display panel, comprising the display substrate in the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A top view of a display substrate provided in an embodiment of the present disclosure.

[0038] Figure 2a A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure.

[0039] Figure 2b for Figure 2a A partial enlarged view of the substrate is shown in FIG.

[0040] Figure 2c It is a longitudinal cross-sectional view of a sub-hole in an embodiment of the present disclosure.

[0041] Figure 3a A schematic structural diagram of step S1 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0042] Figure 3b A schematic structural diagram of step S2 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0043] Figure 3c This is a schematic structural diagram of step S3 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0044] Figure 3d-1 The present invention is a schematic structural diagram of step S4 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0045] Figure 3d-2 This is a structural schematic diagram of step S41 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0046] Figure 3d-3 This is a schematic structural diagram of step S42 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0047] Figure 3d-4 This is a structural schematic diagram of step S43 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0048] Figure 3d-5 This is a structural schematic diagram of step S44 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0049] Figure 3e This is a schematic structural diagram of step S5 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0050] Figure 4 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure.

[0051] Figure 5a This is a schematic structural diagram of step P1 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0052] Figure 5b This is a schematic structural diagram of step P2 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0053] Figure 5c This is a schematic structural diagram of step P3 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0054] Figure 5d This is a schematic structural diagram of step P4 in a method for preparing a display substrate provided in an embodiment of the present disclosure.

[0055] Figure 5e This is a schematic structural diagram of step P5 in a method for preparing a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0057] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0058] The present disclosure provides a display substrate, referring to Figures 1 to 2a, which includes a substrate SUB, and a plurality of gate lines GL and a plurality of data lines DL arranged on the substrate SUB, the gate lines GL and the data lines DL are arranged crosswise and define a pixel unit array including a plurality of pixel units P. Each gate line GL extends along a first direction and is arranged at intervals along a second direction; each data line DL extends along a second direction and is arranged at intervals along the first direction. Exemplarily, the first direction is a row direction, and the second direction is a column direction. For the pixel unit P array, each pixel unit P located in the same row is connected to the same gate line GL, which is provided with a gate G driving signal by the gate line GL, and each pixel unit P located in the same column is connected to the same data line DL, which is provided with a data signal by the data line DL. Each pixel unit P specifically includes an electrically connected thin film transistor TFT and a pixel electrode PX, and a common electrode CX arranged corresponding to the pixel electrode PX, and a common voltage ELVSS is loaded on the common electrode CX. The thin film transistor TFT includes a gate G, a source S, a drain D and an active layer, and the active layer includes a source contact area, a drain contact area and a channel area sandwiched therebetween. The source electrode S of the thin film transistor TFT is connected to the source contact area, and the drain electrode D is connected to the drain contact area. Optionally, the thin film transistor TFT can be a top gate structure, a bottom gate structure or a double gate structure. In the present disclosure, only the bottom gate transistor is used as an example for explanation. Furthermore, the gate G of the thin film transistor TFT is connected to the corresponding gate line GL, the source electrode S is connected to the corresponding data line DL, the drain electrode D is connected to the pixel electrode PX, and the thin film transistor TFT is configured to respond to the gate drive signal on the gate line GL, and transmit the data signal from the source electrode S to the drain electrode D, and further to the pixel electrode PX. By applying different data signals to the pixel electrode PX, the electromagnetic field between the pixel electrode PX and the common electrode CX can be changed, thereby controlling the liquid crystal molecules in the electromagnetic field to deflect at different angles to achieve screen refresh. It should be noted that in order to reduce the number of signal lines crossing layers and simplify the process, the above-mentioned electrically connected structures can be set on the same layer. For example, the gate G and the gate line GL of the thin film transistor TFT are set on the same layer and formed through a one-time composition process. For another example, the source S and the drain D of the thin film transistor TFT are set on the same layer and the data line DL are formed through a one-time composition process.

[0059] In particular, the display substrate of the present disclosure further includes a touch signal line TL disposed on the side of the layer where the data line DL is located away from the base substrate SUB. The touch signal line TL is connected to a touch sensor. When the touch sensor detects a touch, a touch signal is generated. The physical parameters of the touch signal represent the specific information of the touch. For example, the amplitude of the touch signal can reflect the area of ​​the touch or the pressure of the touch. For another example, the phase of the touch signal can reflect the position of the touch and the change of the touch position. After that, the touch signal is transmitted to the timing controller TCON through the touch signal line TL. The timing controller TCON can identify the user's operation according to the physical parameters of the touch signal, such as tapping, sliding, rotating, etc., and then the timing controller TCON sends a signal instruction to control the display panel to refresh the screen. In some examples, the touch sensor can be a capacitive touch sensor. In this example, a conductive film layer is disposed on the side of the touch signal line TL and the touch sensor away from the base substrate SUB. When the user touches the screen, due to the conductivity of the human body, the capacitance of the touch area will change. The capacitive touch sensor can detect this change and generate a touch signal. In other examples, the touch sensor may be a resistive touch sensor, in which two conductive film layers are provided on the side of the touch signal line TL and the touch sensor away from the substrate SUB. When the user touches the screen, the two conductive film layers come into contact, and the resistance of the two conductive film layers changes. The resistive touch sensor detects this change and generates a touch signal. Compared with the resistive touch screen, the capacitive touch screen has a faster response speed and a higher touch sensitivity, but the resistive touch screen is more sensitive to touches with less pressure, and can be selected according to needs.

[0060] Reference Figure 1 , the touch signal line TL of the present disclosure is located between two adjacent columns of pixel units P. In this case, the extension direction of the touch signal line TL can be designed to be the same as that of the data line DL, that is, to extend along the column direction. This arrangement can avoid the touch signal line TL from blocking the pixel unit P and will not affect the pixel aperture ratio. In some examples, the orthographic projections of the touch signal line TL and the data line DL on the substrate SUB at least partially overlap. Preferably, the orthographic projections of the touch signal line TL and the data line DL on the substrate SUB completely overlap, that is, the touch signal line TL and the data line DL are arranged at the same position on different layers of the display substrate, which can further improve space utilization.

[0061] In one example, a column of pixel units P is correspondingly provided with a touch signal line TL. In this case, a column of pixel units P is provided between two adjacent touch signal lines TL. Such a setting is conducive to accurately determining the touch position, reducing the response time, and improving the touch experience. In another example, a touch signal line is provided corresponding to multiple columns of pixel units P. For example, two adjacent columns of pixel units constitute a pixel unit group, and each pixel unit group is correspondingly provided with a touch signal line TL. For each pixel unit group, the touch signal line TL can be provided between two columns of pixel units, or on the same side of the two columns of pixel units. In this case, two columns of pixel units P are provided between two adjacent touch signal lines TL. Compared with the previous example, the setting method of this example can reduce the number of touch signal lines TL, reduce the signal interference between the touch signal line TL and other lines, and improve the accuracy and stability of the touch operation.

[0062] Each pixel unit P includes a pixel electrode PX and a common electrode CX located on a side of the pixel electrode PX close to the substrate SUB. An interlayer insulating layer ILD is also provided between the layer where the data line DL is located and the layer where the touch signal line TL is located. The interlayer insulating layer ILD may be a multi-layer structure. In one example, refer to Figure 2a The interlayer insulating layer ILD includes a first sub-insulating layer ILD1, a second sub-insulating layer ILD2 and a third sub-insulating layer ILD3 which are stacked away from the substrate SUB, and a common electrode CX is arranged between the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3. Among them, the first sub-insulating layer ILD1 is used to isolate the data line DL and the touch signal line TL, and the third sub-insulating layer ILD3 is used to isolate the common electrode CX and the pixel electrode PX. The first sub-insulating layer ILD1 and the third sub-insulating layer ILD3 may include inorganic insulating materials, such as mica, asbestos, marble, porcelain, glass, sulfur, etc., which have excellent insulation properties and high temperature resistance. The materials of the first sub-insulating layer ILD1 and the third sub-insulating layer ILD3 may be the same or different. The second sub-insulating layer ILD2 is set to be relatively thick, which is used to achieve surface flattening of the device. The second sub-insulating layer ILD2 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For another example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU) and the like.

[0063] In one example, referring to Figure 2a-2bThe interlayer insulating layer ILD further includes a first via hole VIA penetrating along the thickness direction thereof and a first accommodation portion LG penetrating the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3 along the thickness direction thereof. The pixel electrode PX is electrically connected to the drain electrode D of the thin film transistor TFT through the first via hole VIA, and the touch signal line TL is arranged in the first accommodation portion LG. Specifically, the second sub-insulating layer ILD2 has a first sub-hole VIA1 penetrating the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along the thickness direction thereof, and a second sub-hole VIA2 penetrating the second sub-insulating layer ILD2; the orthographic projection of the first sub-hole VIA1 on the base substrate SUB at least partially overlaps with the orthographic projection of the drain electrode D of the thin film transistor TFT on the base substrate SUB, and the orthographic projection of the second sub-hole VIA2 on the base substrate SUB at least partially overlaps with the orthographic projection of the data line DL on the base substrate SUB. The third sub-insulating layer ILD3 has a third sub-hole VIA3 and a fourth sub-hole VIA4 penetrating along the thickness direction thereof; the orthographic projection of the third sub-hole VIA3 on the substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the substrate SUB, and the first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA; the orthographic projection of the fourth sub-hole VIA4 on the substrate SUB covers the orthographic projection of the second sub-hole VIA2 on the substrate SUB, and the second sub-hole VIA2 and the fourth sub-hole VIA4 constitute a first accommodation portion LG. It should be noted that, referring to Figure 2c The longitudinal section of each sub-hole VIAX along the thickness direction of the display substrate includes a first side W1 and a second side W2 that are arranged opposite to each other. The first angle α1 formed by the first side W1 and the horizontal plane is 30° to 70°, and / or the second angle α2 formed by the second side W2 and the horizontal plane is 30° to 70°. Preferably, the first angle α1 and the second angle α2 are both 60°.

[0064] Continue to refer to Figure 2a The touch signal line TL includes a first substructure TL1 and a second substructure TL2 sequentially arranged in a direction away from the substrate SUB. The first substructure TL1 and the second substructure TL2 both include conductive materials, such as metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Figure 2a The second substructure TL2 can be arranged in the same layer as the pixel electrode PX and formed by a one-time patterning process. Setting the touch signal line TL into a two-layer structure can improve the integrity of the signal, reduce signal interference and electromagnetic radiation, and reduce the transmission resistance of the touch signal line TL, which is conducive to realizing high-speed signal transmission.

[0065] For the common electrode CX in the pixel unit P, continue to refer to Figure 2aIt can be arranged between the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3, and the common electrode CX and the positive projection of the pixel electrode PX on the base substrate SUB at least partially overlap, and the overlapping part constitutes a capacitor. By controlling the voltage applied to the pixel electrode PX and the common electrode CX, the electric field can be adjusted, thereby controlling the deflection angle of the liquid crystal molecules and realizing the display of different gray scales.

[0066] In one example, continue to refer to Figure 2a The display substrate includes not only the above structure, but also a first auxiliary electrode FX formed in the same layer as the common electrode CX through a one-time patterning process, and the first auxiliary electrode FX covers the second sub-hole VIA2. Here, on the one hand, the first auxiliary electrode FX can be used as a shielding layer to shield the data line DL and the touch signal line TL to prevent the two from forming parasitic capacitance and affecting signal stability. On the other hand, the first auxiliary electrode FX is in direct contact with the touch signal line TL, so the resistance of the touch signal line TL can be reduced, reducing transmission loss.

[0067] In one example, continue to refer to Figure 2a The display substrate further includes a first connection electrode EX disposed in the first via hole VIA and electrically connecting the drain electrode D of the thin film transistor TFT and the pixel electrode PX. The first connection electrode EX is disposed in the same layer as the touch signal line TL in the first accommodation portion LG and is completed by a one-time patterning process. After the first connection electrode EX is prepared, the pixel electrode PX is prepared, which can reduce the climbing height of the pixel electrode PX, avoid electrode breakage, and extend the service life.

[0068] In another example, referring to Figure 4, the interlayer insulating layer ILD only includes a first via hole VIA penetrating along the thickness direction thereof, and the pixel electrode PX is connected to the drain electrode D of the thin film transistor TFT through the first via hole VIA. Specifically, the second sub-insulating layer ILD2 has a first sub-hole VIA1 penetrating the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along the thickness direction thereof, and the orthographic projection of the first sub-hole VIA1 on the base substrate SUB at least partially overlaps with the orthographic projection of the drain electrode D of the thin film transistor TFT on the base substrate SUB, and the third sub-insulating layer ILD3 has a third sub-hole VIA3 penetrating along the thickness direction thereof, and the orthographic projection of the third sub-hole VIA3 on the base substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the base substrate SUB, and the first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA. In this embodiment, a thicker film layer is arranged between the touch signal line TL and the data line DL, that is, a first sub-insulating layer ILD1, a second sub-insulating layer ILD2 and a third sub-insulating layer ILD3 are arranged between the touch signal line TL and the data line DL, so that the distance between the touch signal line TL and the data line DL can be increased, and the mutual induction between the two to form parasitic capacitance can be prevented, thereby avoiding the problems of signal distortion and poor circuit stability.

[0069] Continue to refer to Figure 4 In this embodiment, the touch signal line TL includes a first substructure TL1 and a second substructure TL2 sequentially arranged in a direction away from the substrate USB, and the first substructure TL1 and the second substructure TL2 both include conductive materials, such as metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Among them, the first substructure TL1 can be arranged in the same layer as the pixel electrode PX and formed by a one-time patterning process. Setting the touch signal line TL into a two-layer structure can improve the integrity of the signal, reduce signal interference and electromagnetic radiation, and reduce the transmission resistance of the touch signal line TL, which is conducive to the high-speed transmission of the signal.

[0070] For the common electrode CX in the pixel unit P, continue to refer to Figure 4 , which is arranged between the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3, the common electrode CX and the positive projection of the pixel electrode PX on the base substrate SUB at least partially overlap, and the overlapping part constitutes a capacitor. By controlling the voltage applied to the pixel electrode PX and the common electrode, the electric field is adjusted to control the deflection angle of the liquid crystal molecules to achieve display of different grayscales.

[0071] The display substrate of the present disclosure is described below in conjunction with specific embodiments.

[0072] The first example: Reference Figure 2a to 2cThe display substrate includes a base substrate SUB, and a gate electrode layer, a gate insulating layer GI, a semiconductor layer, a source-drain electrode layer, a first sub-insulating layer ILD1, a second sub-insulating layer ILD2, a common electrode layer, a third sub-insulating layer ILD3, a touch electrode layer and a pixel electrode layer sequentially arranged on the base substrate SUB. Among them, the gate electrode layer includes a gate G of a thin film transistor TFT in each pixel unit P and a correspondingly connected gate line GL. The gate insulating layer GI covers the gate electrode layer to insulate the gate electrode layer from the semiconductor layer. The semiconductor layer includes an active layer of each thin film transistor TFT. The source-drain electrode layer includes a source electrode S and a drain electrode D of each thin film transistor TFT, and a data line DL correspondingly connected to the source electrode S. The first sub-insulating layer ILD1 covers the source-drain electrode layer, the second sub-insulating layer ILD2 covers the first sub-insulating layer ILD1, and the second sub-insulating layer ILD2 includes a first sub-hole VIA1 that penetrates the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along its thickness direction, the first sub-hole VIA1 exposes at least part of the drain electrode D of the thin film transistor TFT, the second sub-insulating layer ILD2 also includes a second sub-hole VIA2 that penetrates along its thickness direction, and the second sub-hole VIA2 at least partially overlaps with the orthographic projection of the data line DL on the base substrate SUB. The common electrode layer includes a common electrode CX and a first auxiliary electrode FX, the common electrode CX covers part of the second sub-insulating layer ILD2, and the first auxiliary electrode FX covers the second sub-hole VIA2. The third sub-insulating layer ILD3 covers the common electrode layer, and the third sub-insulating layer ILD3 includes a third sub-hole VIA3 and a fourth sub-hole VIA4 penetrating along the thickness direction thereof, the orthographic projection of the third sub-hole VIA3 on the substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the substrate SUB, the orthographic projection of the fourth sub-hole VIA4 on the substrate SUB covers the orthographic projection of the second sub-hole VIA2 on the substrate SUB, the first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA, and the second sub-hole VIA2 and the fourth sub-hole VIA4 constitute a first accommodation portion LG. The touch electrode layer includes a touch signal line TL and a first connection electrode EX, the touch signal line TL is arranged in the first accommodation portion LG, and the first connection electrode EX is arranged in the first via hole VIA. The touch signal line TL includes a first sub-structure TL1 and a second sub-structure TL2 arranged in sequence along a direction away from the substrate SUB. The pixel electrode layer includes a pixel electrode PX of each pixel unit P. The pixel electrode PX is disposed in the same layer as the second substructure TL2 of the touch signal line TL and is formed by a one-time patterning process.

[0073] The following is a method for preparing the display substrate in this embodiment, the preparation method comprising: providing a base substrate SUB; forming a plurality of gate lines GL and a plurality of data lines DL on the base substrate SUB, and a pixel unit P located at the intersection of the gate lines GL and the data lines DL. The step of forming the pixel unit P comprises: forming a thin film transistor TFT on the base substrate SUB, and a pixel electrode PX electrically connected to the drain electrode D of the thin film transistor TFT. The preparation method of the display substrate further comprises forming a touch signal line TL on the side of the data line DL away from the base substrate SUB, and the touch signal line TL is located between two adjacent columns of pixel units P. In combination with the first example, refer to Figure 3a to 3e The preparation method may specifically include the following steps S1 to S5.

[0074] S1. Provide a substrate SUB, such as Figure 3a shown.

[0075] Step S1 may specifically include: cleaning the substrate SUB by a standard cleaning process. The cleaning method of the substrate SUB may include: alkaline cleaning, soaking the substrate SUB in a solution containing sodium hydroxide or ammonium hydroxide, the common solution concentration is 5% to 10%, which can clean the organic matter and metal ions on the surface of the substrate SUB; acid cleaning, soaking the substrate SUB in a solution containing hydrofluoric acid or hydrochloric acid, the common solution concentration is 10% to 30%, which can clean the oxide and silica impurities on the surface of the substrate SUB; oxidation cleaning, soaking the substrate SUB in a solution containing potassium hydroxide or hydrogen peroxide, the common solution concentration is 5% to 10%, which can clean the carbon and metal elements on the surface of the substrate SUB; ultrapure water cleaning, soaking or spraying the substrate SUB in ultrapure water, which can clean the tiny particles on the surface of the substrate SUB.

[0076] S2. Forming each gate line GL and data line DL, as well as thin film transistors TFT of each pixel unit P on the substrate SUB, Figure 3b shown.

[0077] Step S2 may specifically include: forming a gate electrode layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer on the substrate SUB in sequence. The step of forming the gate electrode layer includes: depositing a conductive film layer on the substrate SUB and performing patterning to form a pattern including the gate G and each gate line GL of each thin film transistor TFT (the gate line GL is not shown in the figure due to the angle of the cross section). The step of forming the gate insulating layer includes: depositing an insulating layer as the gate insulating layer GL on the side of the gate electrode layer away from the substrate SUB, and the gate insulating layer GI covers the gate electrode layer. The step of forming the semiconductor layer includes: depositing a semiconductor material layer on the side of the gate insulating layer away from the substrate SUB and performing patterning to form a pattern including the active layer of each thin film transistor TFT. The step of forming the source-drain electrode layer includes: forming a conductive film layer on the side of the semiconductor layer away from the substrate SUB and performing patterning to form a pattern including the source S, drain D and each data line DL connected to the source S of each thin film transistor TFT (due to the angle, the data line DL is blocked by the source S).

[0078] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD).

[0079] In some examples, the gate electrode layer may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode layer may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode may have a single layer or multiple layers.

[0080] In some examples, the gate insulating layer GI may include, for example, a silicon compound, a metal oxide. For example, the second gate insulating layer may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI may be formed as a single layer or multiple layers.

[0081] In some examples, the active layer may include, for example, an inorganic semiconductor material (e.g., polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, an oxide semiconductor material. The source contact region and the drain contact region in the active layer may each include an impurity with a higher impurity concentration than the channel region. The impurity may include an N-type impurity or a P-type impurity.

[0082] In some examples, the source-drain electrode layer may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the source-drain electrode layer is a single layer or multiple layers of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0083] S3. Reference Figure 3c An interlayer insulating layer ILD and a common electrode layer are formed on the side of the source and drain electrode layer away from the base substrate SUB. The interlayer insulating layer ILD specifically includes a first sub-insulating layer ILD1, a second sub-insulating layer ILD2 and a third sub-insulating layer ILD3 arranged in sequence along a direction away from the base substrate SUB. The common electrode layer is located between the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3. Among them, the second sub-insulating layer ILD2 includes a first sub-hole VIA1 penetrating the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along the thickness direction thereof and a second sub-hole VIA2 penetrating the second interlayer insulating layer ILD along the thickness direction thereof. The third sub-insulating layer ILD3 includes a third sub-hole VIA3 and a fourth sub-hole VIA4 penetrating along the thickness direction thereof. The first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA, and the second sub-hole VIA2 and the fourth sub-hole VIA4 constitute a first accommodation portion LG.

[0084] The step of forming the first sub-insulating layer ILD1 includes: depositing an inorganic material layer on the side of the source-drain electrode layer away from the base substrate SUB and etching it to form a first part of the first sub-hole VIA1. The first part exposes at least a part of the drain electrode D of the thin film transistor TFT. The step of forming the second sub-insulating layer ILD2 includes: depositing an organic material layer on the side of the first sub-insulating layer ILD1 away from the base substrate SUB and etching it to form a second part of the first sub-hole VIA1 and a second sub-hole VIA2, wherein the orthographic projection of the second part of the first sub-hole VIA1 on the base substrate SUB covers the orthographic projection of the first part of the first sub-hole VIA1 on the base substrate SUB. The orthographic projection of the second sub-hole VIA2 on the base substrate SUB is located between two adjacent columns of pixel units P, and the orthographic projection of the second sub-hole VIA2 on the base substrate SUB at least partially overlaps with the orthographic projection of the data line DL on the base substrate SUB. The step of forming the common electrode layer includes: forming a conductive film layer on the side of the second sub-insulating layer ILD2 away from the base substrate SUB and performing patterning to form a pattern including a first auxiliary electrode FX and a common electrode CX. The first auxiliary electrode covers the second sub-hole VIA2, and the common electrode CX covers part of the second sub-insulating layer ILD2. The step of forming the third sub-insulating layer ILD3 includes: forming an inorganic material layer on the side of the common electrode layer away from the base substrate SUB and etching it to form a third sub-hole VIA3 and a fourth sub-hole VIA4, wherein the orthographic projection of the third sub-hole VIA3 on the base substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the base substrate SUB, and the orthographic projection of the fourth sub-hole VIA4 on the base substrate SUB covers the orthographic projection of the second sub-hole VIA2 on the base substrate SUB.

[0085] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD).

[0086] Exemplarily, the etching process used in the above steps can be dry etching or wet etching. Among them, dry etching is to expose the surface of the film layer to be etched to the plasma generated in the gaseous state, and the plasma reacts physically or chemically with the film layer to be etched through the window opened in the photoresist, thereby removing the exposed surface material. Dry etching can specifically include: ion milling etching, plasma etching and reactive ion etching. Wet etching is to immerse the film layer to be etched in a certain chemical reagent or reagent solution, so that the part of the film surface that is not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern.

[0087] In some examples, the first sub-insulating layer ILD1 and the third sub-insulating layer ILD3 may include an inorganic insulating material, such as mica, asbestos, marble, porcelain, glass, sulfur, etc. The second sub-insulating layer ILD2 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials, etc. The common electrode layer may include a transparent conductive material, such as indium tin oxide, etc.

[0088] S4. A first substructure TL1 of the touch signal line TL located in the first accommodation portion LG and a first connection electrode EX located in the first via hole VIA are formed by a one-time patterning process. Figure 3d-1 shown.

[0089] Reference Figure 3d-2~3d-5 Step S4 specifically includes: S41. Depositing a conductive film layer on the side of the third sub-insulating layer ILD3 away from the substrate SUB, the conductive film layer covers the first accommodation portion LG and the first via hole VIA, such as Figure 3d-2 S42. Form a layer of photoresist with a preset thickness on the side of the conductive film layer away from the substrate SUB, so that the photoresist overflows and fills the first receiving portion LG and the first via hole VIA, as shown. Figure 3d-3 S43. Develop and expose the photoresist to remove the photoresist portion located in the exposure area, as shown. Figure 3d-4 S44. Etch the exposed display substrate to remove the remaining photoresist and at least part of the conductive film layer to form a pattern including the first substructure TL1 and the first connection electrode EX, as shown in FIG. Figure 3d-5 shown.

[0090] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD). The materials constituting the first substructure TL1 and the first connecting electrode may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0091] S5. The second substructure TL2 located in the first receiving portion LG and the pixel electrode PX located in the first via hole VIA are formed by a one-time patterning process. Figure 3e shown.

[0092] Step S5 specifically includes: depositing a conductive film layer on the light-emitting surface of the display substrate after step S4 and patterning it to form a pattern including the second substructure TL2 and the pixel electrode PX. The pixel electrode PX and the common electrode CX at least partially overlap in their orthographic projections on the base substrate SUB.

[0093] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD). The material constituting the second substructure TL2 and the pixel electrode PX may include a transparent conductive material, such as indium tin oxide.

[0094] Second example: Reference Figure 4 The display substrate includes a base substrate SUB, and a gate electrode layer, a gate insulating layer GI, a semiconductor layer, a source-drain electrode layer, a first sub-insulating layer ILD1, a second sub-insulating layer ILD2, a common electrode layer, a third sub-insulating layer ILD3, a pixel electrode layer and a touch electrode layer sequentially arranged on the base substrate SUB. The gate electrode layer includes a gate G of a thin film transistor TFT in each pixel unit P and a correspondingly connected gate line GL. The gate insulating layer covers the gate electrode layer to insulate the gate electrode layer from the semiconductor layer. The semiconductor layer includes an active layer of each thin film transistor TFT. The source-drain electrode layer includes a source electrode S and a drain electrode D of each thin film transistor TFT, and a data line DL correspondingly connected to the source electrode S. The first sub-insulating layer ILD1 covers the source-drain electrode layer, the second sub-insulating layer ILD2 covers the first sub-insulating layer ILD1, and the second sub-insulating layer ILD2 includes a first sub-hole VIA1 penetrating the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along its thickness direction, and the first sub-hole VIA1 exposes at least part of the drain electrode D of the thin film transistor TFT. The common electrode layer includes a common electrode CX, which covers a portion of the second sub-insulating layer ILD2. The third sub-insulating layer ILD3 covers the common electrode layer, and the third sub-insulating layer ILD3 includes a third sub-hole VIA3 that penetrates along its thickness direction, and the orthographic projection of the third sub-hole VIA3 on the substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the substrate SUB, and the first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA. The pixel electrode PX layer includes the pixel electrode PX of each unit. The touch electrode layer includes a touch signal line TL, and the touch signal line TL includes a first sub-structure TL1 and a second sub-structure TL2 arranged in a direction away from the substrate SUB, and the first sub-structure TL1 is arranged in the same layer as the pixel electrode PX and is formed by a one-time patterning process.

[0095] The following is a method for preparing the display substrate in this embodiment, the preparation method comprising: providing a base substrate SUB; forming a plurality of gate lines GL and a plurality of data lines DL on the base substrate SUB, and a pixel unit P located at the intersection of the gate line GL and the data line DL. The step of forming the pixel unit P comprises: forming a thin film transistor TFT on the base substrate SUB, and a pixel electrode PX electrically connected to the drain electrode D of the thin film transistor TFT. The preparation method of the display substrate further comprises forming a touch signal line TL on the side of the data line DL away from the base substrate SUB, and the touch signal line TL is located between two adjacent columns of pixel units P. In combination with the second example, refer to Figures 5a to 5e The preparation method may specifically include the following steps P1 to P5.

[0096] P1. Provide a substrate SUB, such as Figure 5a shown.

[0097] Step P1 may specifically include: cleaning the substrate SUB by a standard cleaning process. The cleaning method of the substrate SUB may include: alkaline cleaning, soaking the substrate SUB in a solution containing sodium hydroxide or ammonium hydroxide, the concentration of which is usually 5% to 10%, which can clean the organic matter and metal ions on the surface of the substrate SUB; acid cleaning, soaking the substrate SUB in a solution containing hydrofluoric acid or hydrochloric acid, the concentration of which is usually 10% to 30%, which can clean the oxide and silica impurities on the surface of the substrate SUB; oxidation cleaning, soaking the substrate SUB in a solution containing potassium hydroxide or hydrogen peroxide, the concentration of which is usually 5% to 10%, which can clean the carbon and metal elements on the surface of the substrate SUB; ultrapure water cleaning, soaking or spraying the substrate SUB in ultrapure water, which can clean the tiny particles on the surface of the substrate SUB.

[0098] P2. Forming each gate line GL and data line DL, as well as a thin film transistor TFT of each pixel unit P on the substrate SUB, Figure 5b shown.

[0099] Step S2 may specifically include: forming a gate electrode layer, a gate insulating layer GI, a semiconductor layer and a source-drain electrode layer on the substrate SUB in sequence. The step of forming the gate electrode layer includes: depositing a conductive film layer on the substrate SUB and performing patterning to form a pattern including the gate G and each gate line GL of each thin film transistor TFT (the gate line GL is not shown in the figure due to the angle of the cross section). The step of forming the gate insulating layer GI includes: depositing an insulating layer as the gate insulating layer GI on the side of the gate electrode layer away from the substrate SUB, and the gate insulating layer GI covers the gate electrode layer. The step of forming the semiconductor layer includes: depositing a semiconductor material layer on the side of the gate insulating layer GI away from the substrate SUB and performing patterning to form a pattern including the active layer of each thin film transistor TFT. The step of forming the source-drain electrode layer includes: forming a conductive film layer on the side of the semiconductor layer away from the substrate SUB and performing patterning to form a pattern including the source S, drain D and each data line DL connected to the source S of each thin film transistor TFT (due to the angle problem, the data line DL is blocked by the source S).

[0100] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD).

[0101] In some examples, the gate electrode layer may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode layer may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The gate electrode may have a single layer or multiple layers.

[0102] In some examples, the gate insulating layer GI may include, for example, a silicon compound, a metal oxide. For example, the second gate insulating layer may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The gate insulating layer GI may be formed as a single layer or multiple layers.

[0103] In some examples, the active layer may include, for example, an inorganic semiconductor material (e.g., polycrystalline silicon, amorphous silicon, etc.), an organic semiconductor material, an oxide semiconductor material. The source contact region and the drain contact region in the active layer may each include an impurity with a higher impurity concentration than the channel region. The impurity may include an N-type impurity or a P-type impurity.

[0104] In some examples, the source-drain electrode layer may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the source-drain electrode layer is a single layer or multiple layers of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0105] P3. An interlayer insulating layer ILD and a common electrode layer are formed on the side of the source and drain electrode layer away from the substrate SUB. The interlayer insulating layer ILD specifically includes a first sub-insulating layer ILD1, a second sub-insulating layer ILD2 and a third sub-insulating layer ILD3 arranged in sequence along a direction away from the substrate SUB. The common electrode layer is located between the second sub-insulating layer ILD2 and the third sub-insulating layer ILD3. The second sub-insulating layer ILD2 includes a first sub-hole VIA1 penetrating the first sub-insulating layer ILD1 and the second sub-insulating layer ILD2 along its thickness direction, the third sub-insulating layer ILD3 includes a third sub-hole VIA3 penetrating along its thickness direction, and the first sub-hole VIA1 and the third sub-hole VIA3 constitute a first via hole VIA, such as Figure 5c shown.

[0106] The step of forming the first sub-insulating layer ILD1 includes: depositing an inorganic material layer on the side of the source-drain electrode layer away from the base substrate SUB and etching it to form the first part of the first sub-hole VIA1. The first part exposes at least part of the drain electrode D of the thin film transistor TFT. The step of forming the second sub-insulating layer ILD2 includes: depositing an organic material layer on the side of the first sub-insulating layer ILD1 away from the base substrate SUB and etching it to form the second part of the first sub-hole VIA1, and the orthographic projection of the second part of the first sub-hole VIA1 on the base substrate SUB covers the orthographic projection of the first part of the first sub-hole VIA1 on the base substrate SUB. The step of forming the common electrode layer includes: forming a conductive film layer on the side of the second sub-insulating layer ILD2 away from the base substrate SUB and performing patterning to form a pattern including the common electrode CX. The common electrode CX covers part of the second sub-insulating layer ILD2. The step of forming the third sub-insulating layer ILD3 includes: forming an inorganic material layer on the side of the common electrode layer away from the base substrate SUB and etching it to form a third sub-hole VIA3, the orthographic projection of the third sub-hole VIA3 on the base substrate SUB covers the orthographic projection of the first sub-hole VIA1 on the base substrate SUB.

[0107] Exemplarily, the above-mentioned film layer can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD).

[0108] Exemplarily, the etching process used in the above steps can be dry etching or wet etching. Among them, dry etching is to expose the surface of the film layer to be etched to the plasma generated in the gaseous state, and the plasma reacts physically or chemically with the film layer to be etched through the window opened in the photoresist, thereby removing the exposed surface material. Dry etching can specifically include: ion milling etching, plasma etching and reactive ion etching. Wet etching is to immerse the film layer to be etched in a certain chemical reagent or reagent solution, so that the part of the film surface that is not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern.

[0109] In some examples, the first sub-insulating layer ILD1 and the third sub-insulating layer ILD3 may include an inorganic insulating material, such as mica, asbestos, marble, porcelain, glass, sulfur, etc. The second sub-insulating layer ILD2 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials, etc. The common electrode layer may include a transparent conductive material, such as indium tin oxide, etc.

[0110] P4. The first substructure TL1 located in the first receiving portion LG and the pixel electrode PX located in the first via hole VIA are formed by a one-time patterning process. Figure 5d shown.

[0111] Step P4 specifically includes: depositing a conductive film layer on the light-emitting surface of the display substrate after step P3 and patterning it to form a pattern including the first substructure TL1 and the pixel electrode PX. The pixel electrode PX and the common electrode CX at least partially overlap in their orthographic projections on the base substrate SUB.

[0112] Exemplarily, the conductive film layer may be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD). The material constituting the first substructure TL1 and the pixel electrode PX may include a transparent conductive material, such as indium tin oxide.

[0113] P5. A second substructure TL2 is formed on the side of the first substructure TL1 away from the substrate SUB, such as Figure 5e shown.

[0114] Step P5 specifically includes: depositing a conductive film layer on the side of the first substructure TL1 away from the substrate SUB, and patterning the conductive film layer through a first mask to form a pattern including the second substructure TL2. The first mask may be a semi-transparent film mask (HTM mask).

[0115] Exemplarily, the conductive film layer may be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD). The materials constituting the first substructure TL1 and the first connecting electrode may include gold (Au), gold alloys, silver (Ag), silver alloys, aluminum (Al), aluminum alloys, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0116] The present disclosure also provides a display panel, which includes the display substrate in the above embodiment. The display panel can be used in a display device, which can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or a combination of any electronic device and hardware, which is not limited by the embodiments of the present disclosure.

[0117] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a base substrate, a plurality of gate lines and a plurality of data lines arranged on the base substrate, wherein the plurality of gate lines and the plurality of data lines are arranged to cross each other to define a plurality of pixel units; the pixel unit comprises a thin film transistor and a pixel electrode electrically connected to a drain of the thin film transistor; wherein: The display substrate further comprises a touch signal line arranged on a side of the layer where the data line is located away from the base substrate, and the touch signal line is located between two adjacent columns of the pixel units.

2. The display substrate according to claim 1, wherein: For the data line and the touch signal line located between two adjacent columns of the pixel units, their orthographic projections on the substrate at least partially overlap.

3. The display substrate according to claim 1, wherein: The source and drain of the thin film transistor are arranged in the same layer as the data line, and an interlayer insulating layer is arranged on the side of the layer where the data line is located away from the base substrate. The pixel electrode is connected to the drain of the thin film transistor through a first via hole penetrating the interlayer insulating layer; the interlayer insulating layer also includes a first accommodating portion partially penetrating along its thickness direction, and the touch signal line is located in the first accommodating portion.

4. The display substrate according to claim 3, wherein: The touch signal line comprises a first substructure and a second substructure which are sequentially arranged in a direction away from the base substrate; the second substructure is arranged in the same layer as the pixel electrode and is made of the same material.

5. The display substrate according to claim 4, wherein: The pixel electrode is connected to the drain electrode of the thin film transistor via a first connecting electrode, and the first connecting electrode is arranged in the same layer as the first substructure and is made of the same material.

6. The display substrate according to claim 3, wherein: The interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer arranged in sequence along a direction away from the base substrate; a common electrode is arranged between the second sub-insulating layer and the third sub-insulating layer; and the first accommodation portion penetrates the second sub-insulating layer and the third sub-insulating layer.

7. The display substrate according to claim 6, wherein: A first auxiliary electrode is disposed on a side of the touch signal line close to the base substrate. The first auxiliary electrode is disposed in the same layer as the common electrode, and an orthographic projection of the first auxiliary electrode on the base substrate covers an orthographic projection of the first accommodation portion on the base substrate.

8. The display substrate according to claim 1, wherein: The source and drain of the thin film transistor are arranged in the same layer as the data line, an interlayer insulating layer is arranged on the side of the layer where the data line is located away from the base substrate, and the pixel electrode is connected to the drain of the thin film transistor through a first via hole penetrating the interlayer insulating layer.

9. The display substrate according to claim 8, wherein: The touch signal line is arranged on a side of the interlayer insulating layer away from the base substrate; The touch signal line comprises a first substructure and a second substructure which are sequentially arranged in a direction away from the base substrate; the first substructure is arranged in the same layer as the pixel electrode and is made of the same material.

10. The display substrate according to claim 8, wherein: The interlayer insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are arranged in sequence along a direction away from the base substrate; a common electrode is arranged between the second sub-insulating layer and the third sub-insulating layer; the common electrode at least partially overlaps with the orthographic projection of the pixel electrode on the base substrate.

11. A method for preparing a display substrate, comprising: Providing a substrate; Forming a plurality of gate lines and a plurality of data lines on the substrate, and pixel units located at intersections of the gate lines and the data lines; Forming the pixel unit includes: forming a thin film transistor on the substrate, and a pixel electrode electrically connected to the drain of the thin film transistor; Wherein, the method for preparing the display substrate further comprises: A touch signal line is formed on a side of the layer where the data line is located away from the base substrate; the touch signal line is located between two adjacent columns of the pixel units.

12. The preparation method according to claim 11, wherein The data line and the source and drain of each thin film transistor are formed in one patterning process; The preparation method further comprises, before forming the touch signal line, forming an interlayer insulating layer on a side of the layer where the data line is located away from the base substrate; the interlayer insulating layer comprises a first via hole penetrating along the thickness direction thereof, and a first receiving portion partially penetrating along the thickness direction thereof; The pixel electrode is electrically connected to the drain electrode of the thin film transistor through the first via hole, and the touch signal line is located in the first accommodation portion.

13. The preparation method according to claim 12, wherein: The interlayer insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are arranged in sequence in a direction away from the substrate; The step of forming the interlayer insulating layer comprises: Forming a first sub-insulating layer on a side of the layer where the data line is located away from the base substrate; The second sub-insulating layer is formed on a side of the first sub-insulating layer away from the base substrate; the second sub-insulating layer has a first sub-hole of the first via hole penetrating the first sub-insulating layer and the second sub-insulating layer along the thickness direction thereof, and a second sub-hole penetrating the first receiving portion of the second sub-insulating layer; The third sub-insulating layer is formed on a side of the second sub-insulating layer away from the base substrate; the third sub-insulating layer has a third sub-hole of the first via hole penetrating along the thickness direction thereof, and a fourth sub-hole penetrating the first accommodation portion of the third sub-insulating layer; The first sub-hole and the third sub-hole constitute the first via hole, and the second sub-hole and the fourth sub-hole constitute the first accommodation portion.

14. The preparation method according to claim 13, wherein: The step of forming the touch signal line includes forming a first substructure and a second substructure in sequence along a direction away from the base substrate; the second substructure and the pixel electrode are formed in one patterning process.

15. The preparation method according to claim 13, wherein: The step of forming the touch signal line includes forming a first substructure and a second substructure in sequence along a direction away from the base substrate; forming a first connecting electrode while forming the first substructure; the first connecting electrode is located in the first via hole, and the first connecting electrode is used to electrically connect the pixel electrode to the drain of the thin film transistor.

16. The preparation method according to claim 13, wherein: The method further includes forming a common electrode and a first auxiliary electrode covering the second sub-hole before forming the second sub-insulating layer and the third sub-insulating layer.

17. The preparation method according to claim 12, wherein: The interlayer insulating layer comprises a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer which are arranged in sequence in a direction away from the substrate; The step of forming the interlayer insulating layer comprises: Forming a first sub-insulating layer on a side of the layer where the data line is located away from the base substrate; The second sub-insulating layer is formed at a portion of the first sub-insulating layer away from the base substrate; the second sub-insulating layer has a first sub-hole of a first via hole penetrating through the first sub-insulating layer and the second sub-insulating layer along a thickness direction thereof; The third sub-insulating layer is formed on a side of the second sub-insulating layer away from the base substrate; the third sub-insulating layer has a third sub-hole of the first via hole penetrating along a thickness direction thereof; The first sub-hole and the third sub-hole constitute the first via hole.

18. The preparation method according to claim 17, wherein: The step of forming the touch signal line includes forming a first substructure and a second substructure in sequence along a direction away from the base substrate; the first substructure and the pixel electrode are formed in one patterning process.

19. The preparation method according to claim 17, wherein: The method further includes forming a common electrode between forming the second sub-insulating layer and the third sub-insulating layer.

20. A display panel comprising the display substrate according to any one of claims 1 to 10.

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