Test method of mask layer

Abstract

The present invention provides a method for testing a mask layer, wherein a mask layer is formed on a test wafer; an exposure process and a development process are performed in sequence, so that the mask layer on each region of the test wafer has different thicknesses; ion implantation processes of different doses are performed on mask layers of different thicknesses, and ion implantation processes of the same dose are performed on mask layers of different thicknesses, and ion implantation processes of different doses are performed on mask layers of the same thickness in different regions; the mask layer is removed and the degree of damage on the surface of the test wafer is tested to obtain the relationship between the dose, the thickness of the mask layer and the degree of damage on the surface of the test wafer in the ion implantation process and determine the range of the thickness of the mask layer in the ion implantation process. An unexpected effect is that different experimental conditions in the present invention can be completed on a test wafer, saving costs and avoiding the influence of measurement time; the example implantation conditions of different doses improve the accuracy of the penetration rate.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a method for testing a mask layer. Background Art

[0002] Ion implantation is one of the main processes in integrated circuit manufacturing. It refers to the process of accelerating the ion beam to a certain energy range (generally in the order of keV to MeV) and then implanting it into the surface of the solid material to change the physical properties of the surface of the material. In the integrated circuit process, the solid material is usually silicon, and the implanted impurity ions are usually boron ions, phosphorus ions, arsenic ions, indium ions, germanium ions, etc. The implanted ions can change the conductivity of the surface of the solid material or form a PN junction. When the feature size of the integrated circuit is reduced to the sub-micron era, the ion implantation process has been widely used. In the integrated circuit manufacturing process, ion implantation is usually used for deep buried layers, inverted doped wells, threshold voltage adjustment, source and drain extension implantation, source and drain implantation, polysilicon gate doping, forming PN junctions and resistors / capacitors, etc. When performing ion implantation, the ion beam in the area protected by the mask layer cannot penetrate the mask layer, and the ion beam can only be implanted into the substrate in the area not covered by the mask layer to achieve doping. Therefore, the mask layer used for the ion implantation process must be able to effectively block the ion beam. Mask layer barriers of different thicknesses have different blocking capabilities for ion implantation. If the thickness is too thin, ions will easily penetrate the mask layer barrier, while if the thickness is too thick, it will be difficult to control the critical dimensions during photolithography.

[0003] The thickness verification method of the mask layer in the prior art generally includes the following steps: providing a plurality of test wafers, and preparing two additional silicon wafers based on the number of test wafers, one of which is used as a reference silicon wafer (BL wafer) and does not perform an ion implantation process, and the other is used as a sacrificial wafer. This is because the thermal wave (TW) test result of the last test wafer is too low, so a sacrificial wafer is needed as the last wafer in the test process; performing a thermal wave (TW) test on the plurality of test wafers to determine the lattice damage. Wave (TW) measurement, the TW measurement difference of multiple test wafers is less than 20 to exclude the TW difference of the wafer itself. If the TW measurement difference of multiple test wafers is greater than 20, it is necessary to prepare the test wafer again; coat the test wafer and the reference wafer with a mask layer, and the thickness of the mask layer on different test wafers is different; test the thickness of the mask layer on each test wafer; perform ion implantation on the test wafer to implant ions of predetermined energy into the mask layer in the test wafer; remove the mask layer of each test wafer; and immediately perform another TW test (i.e., post-TW test) to determine whether the thickness of the mask layer can block ions in the ion implantation process.

[0004] Currently, in order to determine the blocking ability of the mask layer to ion implantation, a lot of test wafers need to be prepared, resulting in high costs. In addition, TW measurement is affected by time and has high noise. In addition, the ion implantation dose is single, and the accuracy of mask layer penetration detection is not ideal (generally only 0.2%). Summary of the invention

[0005] One of the objectives of the present invention is to provide a method for testing a mask layer to solve the problem of high cost in testing the blocking capability of the mask layer to ion implantation.

[0006] Another object of the present invention is to solve the problem of high noise in TW measurement.

[0007] Another object of the present invention is to solve the problem of unsatisfactory detection accuracy of mask layer penetration.

[0008] In order to solve the above technical problems, the present invention provides a method for testing a mask layer, comprising:

[0009] Providing a test wafer, wherein the test wafer is formed with a mask layer;

[0010] Performing an exposure process and a development process in sequence so that the mask layer on each area of ​​the test wafer has a different thickness;

[0011] Performing ion implantation processes with different doses on mask layers with different thicknesses, performing ion implantation processes with the same dose on mask layers with different thicknesses, and performing ion implantation processes with different doses on mask layers with the same thickness in different regions;

[0012] removing the mask layer;

[0013] The damage degree of the test wafer surface is tested to obtain the relationship between the dose, mask layer thickness and the damage degree of the test wafer surface in the ion implantation process, and to determine the mask layer thickness range in the ion implantation process.

[0014] Optionally, in the exposure process, the exposure energy increases sequentially from one side edge of the test wafer to the center of the test wafer, and the exposure energy decreases sequentially from the center of the test wafer to the other side edge of the test wafer.

[0015] Optionally, the maximum exposure energy in the exposure process is less than a preset exposure energy, and the preset exposure energy is a minimum exposure energy for sufficient exposure.

[0016] Optionally, after performing the development process, the thickness of the mask layer on the test wafer is axisymmetric about the longitudinal axis where the center of the test wafer is located.

[0017] Optionally, the thickness of the mask layer on the test wafer increases sequentially from the center of the test wafer to the edge of the test wafer.

[0018] Optionally, the ion implantation direction in the ion implantation process is parallel to the thickness direction of the mask layer.

[0019] Optionally, the mask layer is removed by a wet cleaning process.

[0020] Optionally, a lattice damage thermal wave measurement method is used to measure the damage degree of the test wafer surface.

[0021] Optionally, whether the mask layer is broken down is determined according to the lattice damage thermal wave measurement result, and the thickness range of the mask layer in the ion implantation process is determined according to whether the mask layer is broken down.

[0022] Optionally, if all mask layers are not broken down, the thickness of the mask layer is determined as the thickness range of the mask layer in the ion implantation process; if the mask layer is broken down, the breakdown rate of the mask layer is calculated, and the thickness of the mask layer that is not broken down is determined as the thickness range of the mask layer in the ion implantation process.

[0023] In the test method of the mask layer provided by the present invention, a mask layer is formed on a test wafer; an exposure process and a development process are performed in sequence so that the mask layer on each area of ​​the test wafer has different thicknesses; ion implantation processes of different doses are performed on mask layers of different thicknesses, and ion implantation processes of the same dose are performed on mask layers of different thicknesses, and ion implantation processes of different doses are performed on mask layers of the same thickness in different areas; the mask layer is removed and the degree of damage on the surface of the test wafer is tested to obtain the relationship between the dose, the thickness of the mask layer and the degree of damage on the surface of the test wafer in the ion implantation process and to determine the thickness range of the mask layer in the ion implantation process.

[0024] The present invention has unexpected effects. Different exposure energies can be used to make the mask layer have different thicknesses in different areas and different doses of ion implantation processes can be used to verify the blocking ability of the mask layer. Multiple experiments for mask layer thickness verification can be completed on a test wafer, saving costs. The TW of different areas can be measured on a test wafer, and there is no need to reselect the test wafer because the difference in the pre-set TW of different test wafers is too large. The experimental results of ion implantation conditions of different doses and mask layers of different thicknesses are cross-measured to measure TW, avoiding the influence of measurement time differences as much as possible. In addition, the ion implantation conditions of different doses improve the accuracy of the penetration rate. If the mask layer can be broken down, a more accurate breakdown rate can be obtained. The present invention can also confirm the process window of the mask layer thickness according to whether the mask layer is broken down and the breakdown rate, and then determine the specifications of the mask layer thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0026] Figure 1 It is a flow chart of a method for testing a mask layer according to an embodiment of the present invention.

[0027] Figure 2 It is a schematic structural diagram of a test wafer after a mask layer is formed according to an embodiment of the present invention.

[0028] Figure 3 It is a schematic diagram of the stepping direction in the exposure process of an embodiment of the present invention.

[0029] Figure 4 It is a schematic diagram of the structure of mask layers with different thicknesses according to an embodiment of the present invention.

[0030] Figure 5 It is a distribution diagram of different doses in the ion process of an embodiment of the present invention.

[0031] Figure 6 It is a schematic diagram of the ion implantation direction structure in the ion process of an embodiment of the present invention.

[0032] Figure 7 FIG. 4 is a graph showing the dose and TW measurement result when the mask layer is not penetrated according to an embodiment of the present invention.

[0033] Figure 8 FIG. 4 is a graph showing the dose of the mask layer being penetrated and the TW measurement result according to an embodiment of the present invention.

[0034] In the accompanying drawings: 10 - test wafer; 11 - mask layer; 12 - exposure area. DETAILED DESCRIPTION

[0035] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0036] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second" and "third" can explicitly or implicitly include one or at least two of the features. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, matching or transmission relationship between the two elements, and the connection, coupling, matching or transmission between the two elements can be direct or indirect through a central element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element can be in any orientation such as inside, outside, above, below or on one side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0037] Figure 1 FIG. 1 is a flow chart of a method for testing a mask layer according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for testing a mask layer, including:

[0038] Step S10, providing a test wafer, wherein a mask layer is formed on the test wafer;

[0039] Step S20, performing an exposure process and a development process in sequence, so that the mask layer on each area of ​​the test wafer has a different thickness;

[0040] Step S30, performing ion implantation processes with different doses on mask layers with different thicknesses, performing ion implantation processes with the same dose on mask layers with different thicknesses, and performing ion implantation processes with different doses on mask layers with the same thickness in different regions;

[0041] Step S40, removing the mask layer;

[0042] Step S50, testing the damage degree of the test wafer surface to obtain the relationship between the dose, mask layer thickness and the damage degree of the test wafer surface in the ion implantation process, and determining the mask layer thickness range in the ion implantation process.

[0043] Figure 2 It is a schematic structural diagram of a test wafer after a mask layer is formed according to an embodiment of the present invention. Figure 3 It is a schematic diagram of the stepping direction in the exposure process of an embodiment of the present invention. Figure 4 Schematic diagram of the structure of mask layers with different thicknesses according to an embodiment of the present invention. Figure 5 It is a distribution diagram of different doses in the ion process of an embodiment of the present invention. Figure 6 It is a schematic diagram of the ion implantation direction structure in the ion process of an embodiment of the present invention. Figure 7 FIG. 4 is a graph showing the dose and TW measurement result when the mask layer is not penetrated according to an embodiment of the present invention. Figure 8 FIG. 4 is a graph showing the dose of the mask layer being penetrated and the TW measurement result according to an embodiment of the present invention.

[0044] In order to make the above-mentioned purpose, features and beneficial effects of the present invention more obvious and easy to understand, the following is a brief description of the invention. Figures 2 to 8 The specific embodiments of the present invention are described in detail.

[0045] like Figure 2 As shown, a test wafer 10 is provided. The test wafer 10 can be a semiconductor substrate, made of a semiconductor material suitable for forming a semiconductor device (such as Si, SiC, SiGe, etc.). In other embodiments, the test wafer 10 can also be various composite substrates such as silicon on insulator (SOI) and silicon germanium on insulator. Those skilled in the art understand that the substrate is not subject to any restrictions, but can be selected according to practical applications. Some complete devices can be formed in the test wafer 10, or the test wafer 10 can be formed with partial structures of the device, such as: gate structure, contact hole, dielectric layer, metal connection and through hole, etc.

[0046] Please continue to refer to Figure 2 , the mask layer 11 formed on each area of ​​the test wafer 10 has the same thickness. The mask layer 11 is, for example, a photoresist formed by a coating process. It can be understood that the same thickness referred to here can be understood as the thickness within the fluctuation range allowed by the process, and it is not required to be absolutely the same. Then, a baking process is performed to achieve a more ideal technical effect. At this time, the thickness of the mask layer 11 formed is at least greater than the maximum thickness of the mask layer to be verified.

[0047] like Figure 3 and Figure 4As shown, the mask layer 11 is subjected to an exposure process and a development process. After the development process, the mask layer 11 on each region of the test wafer 10 has different thicknesses, and the center thickness of the mask layer 11 is lower than the edge thickness. Specifically, the exposure process can be implemented by gradually scanning the mask layer 11 of the entire test wafer 10 in units of exposure regions (shots) 12. Only the mask layer 11 that is fully exposed will be completely removed after the development process. For example, the minimum energy for full exposure is E1. If the exposure energy is less than E1, the mask layer 11 in this region cannot be completely removed after development, and a portion of the thickness remains (these thicknesses are not fully exposed). Therefore, in the exposure process of this embodiment, the exposure energy increases from one side edge of the test wafer 10 to the center area of ​​the test wafer 10 in sequence, and then the exposure energy decreases symmetrically from the center of the test wafer 10 to the other side edge of the test wafer 10 in sequence. The maximum exposure energy in the exposure process is less than the preset energy, and the preset energy is the minimum energy E1 for full exposure, that is, the exposure energy in this embodiment is less than E1. After exposure, baking and development processes are performed. Due to the different exposure energies, the thickness of each area of ​​the mask layer 11 after the development process is different. The mask layer 11 presents a morphology of being thick on both sides and thin in the center, or thick at the edges and thin in the center. The thickness of the mask layer 11 on the test wafer 10 is axially symmetrical about the axis where the center of the test wafer 10 is located.

[0048] In this embodiment, Figure 5 As shown, the test wafer 10 is divided into four regions of equal area. For example, the test wafer 10 is divided into four regions of equal area by the horizontal axis X and the vertical axis Y with the center of the test wafer 10 as the dot. Each of the four regions of equal area has a mask layer 11 of different thickness. Ion implantation processes of different doses are performed on mask layers 11 of different thicknesses in each region, and ion implantation processes of the same dose are performed on mask layers 11 of different thicknesses, and ion implantation processes of different doses are performed on mask layers 11 of the same thickness in different regions. For example, each region is further divided into four sub-regions (region A1, region A2, region A3, region A4), each sub-region corresponds to an ion implantation dose, that is, each region corresponds to four ion implantation doses. And, there are four ion implantation doses on the mask layers of the same thickness and in different regions. In the preferred embodiment, the four different doses are cross-distributed and evenly distributed, which is conducive to eliminating the influence of different test wafer positions on the ion implantation dose and the thickness of the mask layer. Preferably, the dose in the ion implantation process is, for example, 5E13ion·cm -2 To 1E15 ion·cm -2 Experiments have shown that since the ion distribution conforms to the normal distribution, the penetration accuracy of 3 sigma can reach 0.27%, and the limit measurement of the TW measurement machine is generally 1E11 ion·cm-2 The dose was selected as 5E13 ion·cm -2 The penetration rate accuracy is 0.2%. Therefore, the dose in the ion implantation process is preferably greater than or equal to 5E13 ion·cm -2 , that is, the lowest dose among the four doses is preferably 5E13 ion·cm -2 In this embodiment, the other four doses are all greater than 5E13 ion·cm -2 , assuming the maximum dose is 1E15 ion·cm -2 The penetration accuracy can even reach 0.01%. By comparison, the existing technology only has one dose, which can only be 5E13 ion·cm -2 Therefore, the different dose settings adopted by the present invention can improve the accuracy of the penetration rate in the verification experiment to 0.01%.

[0049] In this embodiment, the ion implantation direction in the ion implantation process is parallel to the thickness direction of the mask layer 11 , that is, the ion implantation beam is incident perpendicularly to the mask layer 11 .

[0050] After the ion implantation process, a wet cleaning process is used to remove the mask layer 11. The solution of the wet cleaning process is, for example, an SPM solution, which includes H2SO4 and H2O2.

[0051] After removing the mask layer 11, a lattice damage thermal wave (TW) test is used to test the degree of damage on the surface of the wafer 10. The TW measurement value is related to the number of ions that penetrate the mask layer 11 and reach the test wafer 10 during the ion implantation process. The more ions that penetrate, the greater the TW measurement value. The lattice damage thermal wave test can be used to determine whether the mask layer 11 is broken down. If the mask layer 11 is broken down, the breakdown rate of the mask layer 11 is calculated.

[0052] like Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 The horizontal axis in the graph is the dose (Dose), for example, the first dose Dose1, the second dose Dose2, the third dose Dose3 and the fourth dose Dose4. The vertical axis is the TW measurement value. Figure 7 As shown, the TW measurement values ​​under the four doses do not change much, and the TW measurement values ​​are all around 16, indicating that the mask layer 11 is not broken down, indicating that the thickness of the mask layer 11 can block the ion breakdown in the ion implantation process, and the thickness of the mask layer 11 meets the requirements. Figure 8As shown, the TW measurement values ​​under the four doses increase with the increase of the dose, and the TW measurement value changes from 16 to 19, indicating that the mask layer 11 has been broken down. At this time, an accurate breakdown rate can be obtained, and the thickness of the appropriate mask layer 11 can be selected. Therefore, if the mask layer 11 in all experiments is not broken down, it can be shown that the thickness of all mask layers 11 meets the requirements and can block ions from entering the non-ion implantation area in the ion implantation process. If the mask layer 11 of a part of the thickness is broken down, the thickness of the mask layer 11 that is not broken down is the mask layer thickness that meets the requirements. If the mask layer 11 in all experiments is broken down, it is necessary to replace the material of the mask layer and re-experiment. In this embodiment, experiments with different mask layer thicknesses and different doses are completed on the same test wafer, which saves costs, and does not require the reselection of the test wafer due to the large difference in the pre-TW test of different test wafers, and does not affect the test value of the post-TW due to the difference in the pre-TW test. The TW measurements of mask layers with different doses and different thicknesses can be performed crosswise to avoid the adverse effects of different measurement times as much as possible. In this embodiment, the accuracy of the penetration rate can be improved to 0.01% under different dose ion implantation conditions. If the mask layer can be broken down, a more accurate breakdown rate can be obtained. This embodiment can also confirm the process window (Window) of the mask layer thickness based on whether the mask layer is broken down and the breakdown rate, and then determine the specification (spec) of the mask layer thickness.

[0053] In summary, in a test method for a mask layer provided by an embodiment of the present invention, a mask layer is formed on a test wafer; an exposure process and a development process are performed in sequence, so that the mask layer on each region of the test wafer has different thicknesses; ion implantation processes of different doses are performed on mask layers of different thicknesses, and ion implantation processes of the same dose are performed on mask layers of different thicknesses, and ion implantation processes of different doses are performed on mask layers of the same thickness in different regions; the mask layer is removed and the degree of damage on the surface of the test wafer is tested to obtain the relationship between the dose, the thickness of the mask layer and the degree of damage on the surface of the test wafer in the ion implantation process and determine the thickness range of the mask layer in the ion implantation process. An unexpected effect is that in the present invention, different exposure energies can be used to make the mask layer have different thicknesses in different regions and different doses of ion implantation processes can be used to verify the blocking ability of the mask layer. Multiple experiments for mask layer thickness verification can be completed on a test wafer, saving costs. When measuring the TW of different regions on a test wafer, there is no need to reselect the test wafer due to the large difference in the pre-TW of different test wafers. The experimental results of different doses of ion implantation conditions and mask layers of different thicknesses are cross-measured to measure TW, so as to avoid the influence of the measurement time difference as much as possible. In addition, different doses of ion implantation conditions improve the accuracy of the penetration rate. If the mask layer can be broken down, a more accurate breakdown rate can be obtained. This embodiment can also confirm the process window of the mask layer thickness according to whether the mask layer is broken down and the breakdown rate, and then determine the specification of the mask layer thickness.

[0054] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for testing a mask layer, characterized in that: include: Providing a test wafer, wherein the test wafer is formed with a mask layer; Performing an exposure process and a development process in sequence so that the mask layer on each area of ​​the test wafer has a different thickness; Performing ion implantation processes with different doses on mask layers with different thicknesses, performing ion implantation processes with the same dose on mask layers with different thicknesses, and performing ion implantation processes with different doses on mask layers with the same thickness in different regions; removing the mask layer; The damage degree of the test wafer surface is tested to obtain the relationship between the dose, mask layer thickness and the damage degree of the test wafer surface in the ion implantation process, and to determine the mask layer thickness range in the ion implantation process.

2. The method for testing the mask layer according to claim 1, characterized in that: In the exposure process, the exposure energy increases from one side edge of the test wafer to the center of the test wafer, and the exposure energy decreases from the center of the test wafer to the other side edge of the test wafer.

3. The method for testing the mask layer according to claim 2, characterized in that: The maximum exposure energy in the exposure process is less than a preset exposure energy, and the preset exposure energy is a minimum exposure energy for sufficient exposure.

4. The method for testing the mask layer according to claim 1, characterized in that: After the development process is performed, the thickness of the mask layer on the test wafer is axisymmetric about the longitudinal axis where the center of the test wafer is located.

5. The method for testing the mask layer according to claim 4, characterized in that: The thickness of the mask layer on the test wafer increases sequentially from the center of the test wafer to the edge of the test wafer.

6. The method for testing the mask layer according to claim 1, characterized in that: The ion implantation direction in the ion implantation process is parallel to the thickness direction of the mask layer.

7. The method for testing the mask layer according to claim 1, characterized in that: The mask layer is removed by a wet cleaning process.

8. The method for testing the mask layer according to claim 1, characterized in that: The damage degree of the surface of the test wafer is measured by using a lattice damage thermal wave measurement method.

9. The method for testing the mask layer according to claim 8, characterized in that: Whether the mask layer is broken down is judged according to the lattice damage thermal wave measurement result, and the thickness range of the mask layer in the ion implantation process is determined according to whether the mask layer is broken down.

10. The method for testing the mask layer according to claim 9, characterized in that: If all mask layers are not broken down, the thickness of the mask layer is determined as the mask layer thickness range in the ion implantation process; if the mask layer is broken down, the breakdown rate of the mask layer is calculated, and the thickness of the mask layer that is not broken down is determined as the mask layer thickness range in the ion implantation process.

Images