LDO circuit based on current feedback

Abstract

The invention discloses an LDO (Low Dropout Regulator) circuit based on current feedback, which comprises a transconductance amplifier for amplifying reference voltage into current and inputting the current into a positive phase input end of an error transresistance amplifier; the error transimpedance amplifier, the buffer, the second PMOS transistor, the first PMOS transistor and the current-current feedback network form an error current feedback loop, the negative phase input end of the error transimpedance amplifier receives feedback current from the current-current feedback network, and the output end of the error transimpedance amplifier outputs error voltage; the buffer receives the error voltage output by the error trans-impedance amplifier, generates a buffer stage output voltage and drives the second PMOS tube to generate an output voltage; the first PMOS transistor is used for detecting fluctuation of output voltage, if the output voltage fluctuates, current flowing through the first PMOS transistor changes, the current-current feedback network generates feedback current according to the current change of the first PMOS transistor, the feedback current is input to the negative phase input end of the error trans-impedance amplifier, and fluctuation of the output voltage is counteracted.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuits, and in particular, relates to an LDO circuit based on current feedback. Background Art

[0002] The LDO (Low-Dropout Regulator) circuit is a power management circuit used to provide a stable output voltage. The LDO circuit occupies an important position in many analog and digital power management applications due to its simple structure, low noise, high stability and easy integration.

[0003] The feedback type of the traditional LDO circuit structure is voltage feedback, and this voltage feedback structure is usually achieved through feedback resistor voltage division. Figure 1 It is a traditional LDO circuit structure implemented by using feedback resistor voltage division. E is the error voltage amplifier, the reference voltage v REF and negative feedback voltage v FB The series connection generates an error voltage, which is amplified by the loop and drives the power tube to generate an output voltage. FB1 and R FB2 And through voltage division, v FB , the output voltage v O The changes are fed back to the adder at the input end, thereby offsetting the fluctuations in the output voltage and ensuring the stability of the output voltage.

[0004] However, static current will flow through the feedback resistor in this voltage feedback structure LDO, thereby increasing the power consumption of the LDO circuit, which is unacceptable for some low-power applications. If you want to reduce the additional power consumption introduced by the feedback resistor, you can only use a high-resistance feedback resistor, and high-resistance resistors generally occupy a larger layout area, resulting in higher costs. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an LDO circuit based on current feedback, which adopts current-current feedback to replace the voltage-voltage feedback in the traditional structure, thereby eliminating the area occupied by the high-resistance feedback resistor in the traditional LDO circuit structure, reducing the cost, and reducing the static power consumption additionally introduced by the feedback network in the LDO.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solution: a LDO circuit based on current feedback, comprising: a transconductance amplifier A G , Error transimpedance amplifier A E , a buffer, a current-current feedback network, a first PMOS tube M13 and a second PMOS tube MP;

[0007] The transconductance amplifier A G The reference voltage V REF Amplified into current i IN , input error transimpedance amplifier A E The positive-inverting input terminal;

[0008] The error transimpedance amplifier A E , the buffer, the second PMOS tube MP, the first PMOS tube M13 and the current-current feedback network constitute an error current feedback loop, and the error transimpedance amplifier A E The negative input terminal receives the feedback current i from the current-current feedback network. FB , the error transimpedance amplifier A E The output terminal outputs an error voltage; the buffer receives the error voltage from the error transimpedance amplifier A E The output error voltage generates a buffer output voltage, which drives the second PMOS tube MP to generate an output voltage V o The first PMOS tube M13 is used to detect the output voltage V o If the output voltage V o The current flowing through the first PMOS tube M13 fluctuates, causing the current to change. The current-current feedback network generates a feedback current i according to the current change of the first PMOS tube M13. FB , input to the error transimpedance amplifier A E The negative input terminal offsets the output voltage V o fluctuations.

[0009] Furthermore, the transconductance amplifier A G The system comprises a fifth NMOS tube M5, a sixth NMOS tube M6, a first resistor R1 and a sixth PMOS tube M12, wherein the source of the sixth PMOS tube M12 is used as a transconductance amplifier A G The non-inverting input terminal is connected to the reference voltage V REF The gate of the sixth PMOS tube M12, the drain of the sixth PMOS tube M12 and one end of the first resistor R1 are connected to the gate of the first PMOS tube M13, and the other end of the first resistor R1, the drain of the fifth NMOS tube M5, the gate of the fifth NMOS tube M5, and the gate of the sixth NMOS tube M6 are used as a transconductance amplifier A. G The output end is connected to the error transimpedance amplifier A E The source of the fifth NMOS tube M5 is connected to the drain of the sixth NMOS tube M6, and the source of the sixth NMOS tube M6 serves as a transconductance amplifier A G The negative input terminal is grounded.

[0010] Furthermore, the error transimpedance amplifier A EThe invention comprises: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a third PMOS tube M9 and a fourth PMOS tube M10, wherein the gate of the first NMOS tube M1, the gate of the second NMOS tube M2, the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 are used as an error transimpedance amplifier A E The positive input terminal of the first NMOS tube M1; the source of the first NMOS tube M1 is connected to the drain of the third NMOS tube M3, the source of the second NMOS tube M2 is connected to the drain of the fourth NMOS tube M4, the source of the third NMOS tube M3 and the source of the fourth NMOS tube M4 are both grounded; the drain of the first NMOS tube M1, the drain of the third PMOS tube M9, the gate of the third PMOS tube M9, and the gate of the fourth PMOS tube M10 are used together as an error transimpedance amplifier A E The negative phase input terminal is connected to the output terminal of the current-current feedback network; the source of the third PMOS tube M9 and the source of the fourth PMOS tube M10 are both connected to the power supply voltage V IN The drain of the fourth PMOS tube M10 and the drain of the second NMOS tube M2 are used as an error transimpedance amplifier A E The output end is connected to the input end of the buffer.

[0011] Furthermore, the buffer comprises: a current source I1, a fifth PMOS tube M11 and a second resistor R2, wherein the input end of the current source I1 is connected to the power supply voltage V IN The output end of the current source I1 and the source of the fifth PMOS tube M11 are used as the output end of the buffer to control the opening and closing of the second PMOS tube MP; the gate of the fifth PMOS tube M11 is used as the input end of the buffer, the drain of the fifth PMOS tube M11 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0012] Furthermore, the source of the second PMOS tube MP is connected to the power supply voltage V IN The gate of the second PMOS tube MP is connected to the output end of the buffer as a control end; the drain of the second PMOS tube MP is connected to the source of the first PMOS tube M13 as the output end of the LDO circuit; the drain of the first PMOS tube M13 is connected to the input end of the current-current feedback network.

[0013] Furthermore, the error current feedback loop also includes a loop stability compensation capacitor Cc, one end of the loop stability compensation capacitor Cc is connected to the source of the second NMOS tube M2 and one end of the drain of the fourth NMOS tube M4, and the other end of the loop stability compensation capacitor Cc is connected to the output end of the LDO circuit.

[0014] Further, the current-current feedback network includes: a seventh NMOS tube M7 and an eighth NMOS tube M8, wherein the gate of the seventh NMOS tube M7, the drain of the seventh NMOS tube M7, and the gate of the eighth NMOS tube M8 serve as the input end of the current-current feedback network and are connected to the drain of the first PMOS tube M13; the drain of the eighth PMOS tube M8 serves as the output end of the current-current feedback network and is connected to the error transimpedance amplifier A E The source of the seventh NMOS tube M7 and the source of the eighth NMOS tube M8 are both grounded.

[0015] Furthermore, the size of the first PMOS tube M13 and the size of the sixth PMOS tube M12 satisfy:

[0016]

[0017] Among them, (W / L) 12 represents the width-to-length ratio of the sixth PMOS tube M12, (W / L) 13 represents the width-to-length ratio of the first PMOS tube M13.

[0018] Furthermore, the size of the third PMOS tube M9 and the size of the fourth PMOS tube M10 satisfy:

[0019]

[0020] Wherein, (W / L)9 represents the width-to-length ratio of the third PMOS tube M9, (W / L) 10 represents the width-to-length ratio of the fourth PMOS tube M10.

[0021] Further, the size of the first NMOS tube M1, the size of the second NMOS tube M2, the size of the third NMOS tube M3, the size of the fourth NMOS tube M4, the size of the fifth NMOS tube M5, the size of the sixth NMOS tube M6, the size of the seventh NMOS tube M7, and the size of the eighth NMOS tube M8 satisfy:

[0022]

[0023] Among them, (W / L)1 represents the width-to-length ratio of the first NMOS tube M1, (W / L)2 represents the width-to-length ratio of the second NMOS tube M2, (W / L)3 represents the width-to-length ratio of the third NMOS tube M3, (W / L)4 represents the width-to-length ratio of the fourth NMOS tube M4, (W / L)5 represents the width-to-length ratio of the fifth NMOS tube M5, (W / L)6 represents the width-to-length ratio of the sixth NMOS tube M6, (W / L)7 represents the width-to-length ratio of the seventh NMOS tube M7, (W / L)8 represents the width-to-length ratio of the eighth NMOS tube M8, and β represents the feedback coefficient, β≤1.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention adopts a transconductance amplifier to amplify a reference voltage into a current, and adopts a first PMOS tube to sample the error voltage output by the error transimpedance amplifier, and converts it into a current flowing through the first PMOS tube. The change of the current is collected by a current-current feedback network composed of a current mirror and mirrored into a feedback current. The feedback current is input into the negative phase input terminal of the error transimpedance amplifier and superimposed with the current flowing into the positive phase input terminal of the error transimpedance amplifier, thereby realizing current-current negative feedback. Compared with the traditional LDO circuit structure based on voltage feedback, the LDO circuit based on current feedback omits the feedback resistor branch required in the voltage-voltage feedback, which not only reduces the required layout area, reduces the cost, but also reduces the static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the traditional LDO circuit structure;

[0027] Figure 2 It is a schematic diagram of the principle of the LDO circuit based on current feedback of the present invention;

[0028] Figure 3 The circuit structure diagram of the LDO circuit based on current feedback of the present invention;

[0029] Figure 4 It is a small signal block diagram of the LDO circuit based on current feedback of the present invention. DETAILED DESCRIPTION

[0030] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0031] like Figure 2 The schematic diagram of the principle of the LDO circuit based on current feedback of the present invention includes: a transconductance amplifier A G , Error transimpedance amplifier A E , buffer, current-current feedback network, first PMOS tube M13 and second PMOS tube MP; transconductance amplifier A G The reference voltage V REF Amplified into current i IN , input error transimpedance amplifier A E The positive input terminal of the error transimpedance amplifier A E , buffer, second PMOS tube MP, first PMOS tube M13 and current-current feedback network form an error current feedback loop, error transresistance amplifier A E The negative input terminal receives the feedback current i from the current-current feedback network. FB, error transimpedance amplifier A E The output terminal outputs the error voltage; the buffer receives the error voltage from the error transimpedance amplifier A E The output error voltage generates the buffer output voltage, which drives the second PMOS tube MP to generate the output voltage V of the LDO circuit. o ; The first PMOS tube M13 is used to detect the output voltage V o If the output voltage V o Fluctuations will cause the current flowing through the first PMOS tube M13 to change, and the change in current is mirrored by the current-current feedback network to the feedback current i FB In the feedback current i FB Input Error Transimpedance Amplifier A E The negative phase input terminal, and the current i IN The current-current negative feedback is realized. When the output voltage V o When the current flowing through the first PMOS tube M13 increases, the feedback current i FB increases, so the voltage flowing into the buffer increases, the gate voltage of the second PMOS tube MP increases, and finally the output voltage V o Reduce; when V o When the current flowing through the first PMOS tube M13 decreases, the feedback current i FB Therefore, the voltage flowing into the buffer decreases, and the gate voltage of the second PMOS tube MP decreases, which eventually makes the output voltage V o Therefore, the current-current feedback network can offset the output voltage V o fluctuations, ensuring the output voltage V o stability.

[0032] like Figure 3 , the transconductance amplifier A in the present invention G The device comprises a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first resistor R1 and a sixth PMOS transistor M12, wherein the source of the sixth PMOS transistor M12 is used as a transconductance amplifier A. G The non-inverting input terminal is connected to the reference voltage V REF The gate of the sixth PMOS tube M12, the drain of the sixth PMOS tube M12 and one end of the first resistor R1 are connected to the gate of the first PMOS tube M13, and the other end of the first resistor R1, the drain of the fifth NMOS tube M5, the gate of the fifth NMOS tube M5, and the gate of the sixth NMOS tube M6 are used as a transconductance amplifier A. G The output end is connected to the error transimpedance amplifier A EThe source of the fifth NMOS tube M5 is connected to the drain of the sixth NMOS tube M6, and the source of the sixth NMOS tube M6 serves as a transconductance amplifier A G The negative input terminal of the transconductance amplifier A is grounded. The transconductance amplifier A is composed of the fifth NMOS tube M5, the sixth NMOS tube M6, the first resistor R1 and the sixth PMOS tube M12. G The reference voltage V REF Converted to current i IN , thus the feedback current i generated by the current-current feedback network FB Overlay.

[0033] Error Transimpedance Amplifier A E The invention comprises: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a third PMOS tube M9 and a fourth PMOS tube M10, wherein the gate of the first NMOS tube M1, the gate of the second NMOS tube M2, the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 are used together as an error transimpedance amplifier A E The positive input terminal of the first NMOS tube M1 is connected to the drain of the third NMOS tube M3, the source of the second NMOS tube M2 is connected to the drain of the fourth NMOS tube M4, the source of the third NMOS tube M3 and the source of the fourth NMOS tube M4 are both grounded; the drain of the first NMOS tube M1, the drain of the third PMOS tube M9, the gate of the third PMOS tube M9, and the gate of the fourth PMOS tube M10 are used together as an error transimpedance amplifier A E The negative phase input terminal is connected to the output terminal of the current-current feedback network; the source of the third PMOS tube M9 and the source of the fourth PMOS tube M10 are both connected to the power supply voltage V IN The drain of the fourth PMOS tube M10 and the drain of the second NMOS tube M2 are used as an error transimpedance amplifier A E The output end is connected to the input end of the buffer.

[0034] The buffer includes: a current source I1, a fifth PMOS tube M11 and a second resistor R2, the input end of the current source I1 is connected to the power supply voltage V IN The output end of the current source I1 and the source of the fifth PMOS tube M11 are used as the output end of the buffer to control the opening and closing of the second PMOS tube MP; the gate of the fifth PMOS tube M11 is used as the input end of the buffer, the drain of the fifth PMOS tube M11 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded. When the output voltage V o When the current flowing through the first PMOS tube M13 increases, the feedback current i FBThe gate voltage of the fifth PMOS tube M11 increases, which causes the gate voltage of the second PMOS tube MP to increase, and finally the output voltage V o Reduce; when V o When the current flowing through the first PMOS tube M13 decreases, the feedback current i FB The gate voltage of the fifth PMOS tube M11 decreases, which leads to a decrease in the gate voltage of the second PMOS tube MP, and finally the output voltage V o Increase.

[0035] The source of the second PMOS tube MP is connected to the power supply voltage V IN The gate of the second PMOS tube MP is connected to the output end of the buffer as a control end; the drain of the second PMOS tube MP is connected to the source of the first PMOS tube M13 as the output end of the LDO circuit; the drain of the first PMOS tube M13 is connected to the input end of the current-current feedback network.

[0036] Since static current will flow through the feedback resistor in the LDO circuit of the voltage feedback structure, the static power consumption of the LDO circuit will be increased, which is unacceptable for some low-power application fields. If the additional power consumption introduced by the feedback resistor is to be reduced, only a high-resistance feedback resistor can be used. However, a high-resistance resistor generally occupies a large layout area, resulting in increased costs. Therefore, the present invention adopts a current-current feedback network to eliminate the feedback resistor branch required for voltage-voltage feedback, which not only reduces the required layout area, reduces costs, but also reduces static power consumption. The current-current feedback network in the present invention includes: a seventh NMOS tube M7 and an eighth NMOS tube M8, the gate of the seventh NMOS tube M7, the drain of the seventh NMOS tube M7, and the gate of the eighth NMOS tube M8 are used as the input end of the current-current feedback network, and are connected to the drain of the first PMOS tube M13; the drain of the eighth PMOS tube M8 is used as the output end of the current-current feedback network, and is connected to the error transimpedance amplifier A E The negative input terminal of the seventh NMOS tube M7 and the source of the eighth NMOS tube M8 are both grounded. The first PMOS tube M13 is used to detect the output voltage V o If the output voltage V o The fluctuation will cause the current flowing through the first PMOS tube M13 to change. The change of the current is mirrored by the current mirror formed by the seventh NMOS tube M7 and the eighth NMOS tube M8 to the feedback current i flowing through the seventh NMOS tube M7. FB In the feedback current i FB Input Error Transimpedance Amplifier A E The negative phase input terminal, and the current i IN Superposition, thus realizing current-current negative feedback.

[0037] The working process of the LDO circuit based on current feedback of the present invention is specifically as follows: the sixth PMOS tube M12, the fifth NMOS tube M5, the sixth NMOS tube M6 and the first resistor R1 convert the reference voltage v REF Amplified to current i IN The fifth NMOS tube M5, the sixth NMOS tube M6, the first NMOS tube M1, and the third NMOS tube M3 form a current mirror. The fifth NMOS tube M5 and the sixth NMOS tube M6 convert the current i IN The fifth NMOS tube M5, the sixth NMOS tube M6, the second NMOS tube M2, and the fourth NMOS tube M4 form a current mirror. The fifth NMOS tube M5 and the sixth NMOS tube M6 convert the current i IN The seventh NMOS tube M7 samples the current flowing through the first PMOS tube M13 and mirrors it to the eighth NMOS tube M8 through the current mirror, so that the feedback current i FB Flows through the eighth NMOS tube M8. Feedback current i FB The T-type network formed by the node commonly connected by the first NMOS tube M1, the eighth NMOS tube M8, and the third PMOS tube M9 and the current i IN The superimposed current is then mirrored to the fourth PMOS tube M10 through the current mirror formed by the third PMOS tube M9 and the fourth PMOS tube M10. The current flowing through the fourth PMOS tube M10 and the current flowing through the second NMOS tube M2 are superimposed again to generate an error current, which is converted into an error voltage through the small signal impedance of the N1 node formed by the drain of the second NMOS tube M2, the drain of the fourth PMOS tube M10 and the gate of the fifth PMOS tube M11. After passing through the fifth PMOS tube M11, the error voltage drives the second PMOS tube MP, thereby generating an output voltage V o When the output voltage V o When fluctuation occurs, the current flowing through the first PMOS tube M13 will also change accordingly, and the current-current feedback network will feed back the change to the error current feedback loop, thereby offsetting the output voltage V o fluctuations, ensuring the output voltage V o stability.

[0038] Output voltage V o The DC value of is determined by the size ratio and current ratio between the first PMOS tube M13 and the sixth PMOS tube M12. The size of the first PMOS tube M13 and the size of the sixth PMOS tube M12 satisfy: The size of the third PMOS tube M9 and the size of the fourth PMOS tube M10 satisfy: The size of the first NMOS tube M1, the size of the second NMOS tube M2, the size of the third NMOS tube M3, the size of the fourth NMOS tube M4, the size of the fifth NMOS tube M5, the size of the sixth NMOS tube M6, the size of the seventh NMOS tube M7, and the size of the eighth NMOS tube M8 satisfy the following: Among them, (W / L) 12 represents the width-to-length ratio of the sixth PMOS tube M12, (W / L) 13 represents the width-to-length ratio of the first PMOS tube M13, (W / L)9 represents the width-to-length ratio of the third PMOS tube M9, (W / L) 10 represents the width-to-length ratio of the fourth PMOS tube M10, (W / L)1 represents the width-to-length ratio of the first NMOS tube M1, (W / L)2 represents the width-to-length ratio of the second NMOS tube M2, (W / L)3 represents the width-to-length ratio of the third NMOS tube M3, (W / L)4 represents the width-to-length ratio of the fourth NMOS tube M4, (W / L)5 represents the width-to-length ratio of the fifth NMOS tube M5, (W / L)6 represents the width-to-length ratio of the sixth NMOS tube M6, (W / L)7 represents the width-to-length ratio of the seventh NMOS tube M7, (W / L)8 represents the width-to-length ratio of the eighth NMOS tube M8, β represents the feedback coefficient, β≤1, so that the static current flowing through the first NMOS tube M1, the second NMOS tube M2, the eighth NMOS tube M8, the sixth PMOS tube M12, and the first PMOS tube M13 satisfies I1:I2:I8:I 12 :I 13 =β:β:β:1:1, ensuring that the static current flowing through the sixth PMOS tube M12 is consistent with the static current flowing through the first PMOS tube M13, so that the output voltage V o With reference voltage V REF The DC values ​​are equal.

[0039] In one technical solution of the present invention, the error current feedback loop also includes a loop stability compensation capacitor Cc, one end of the loop stability compensation capacitor Cc is connected to the source of the second NMOS tube M2 and one end of the drain of the fourth NMOS tube M4, and the other end of the loop stability compensation capacitor Cc is connected to the output end of the LDO circuit for stability compensation of the LDO circuit. Figure 4 The small signal block diagram of the LDO circuit is used for the stability analysis of the compensation method. Because the output terminal N2 of the buffer is a low-impedance node, the pole P2 introduced by N2 is at a high-frequency position under the full range of load current, so the capacitive impedance of N2 is omitted in the stability analysis here. Figure 4 The stability of the error current feedback loop affects the stability of the entire circuit. Figure 4 After the error current feedback loop is disconnected at the position shown in , the loop gain A of the error current feedback loop Z,LG for:

[0040] A Z,LG =β·A Z,OL

[0041] Among them, A z,OL represents the open-loop gain of the error current feedback loop, A Z，CL1 Indicates the loop stability compensation capacitor C C The closed-loop gain of the internal loop composed of the second NMOS tube M2, the buffer and the second PMOS tube MP, including the loop stability compensation capacitor C C The open-loop gain of the inner loop is C1 represents the equivalent capacitance at the N1 node, r o1 represents the equivalent resistance at the N1 node, g mp represents the transconductance of the second PMOS tube MP, R oeq Indicates the output voltage V o The equivalent output impedance at C o Indicates the output voltage V o The equivalent capacitance at , s represents the complex frequency, g m2 represents the transconductance of the second NMOS tube M2, R o Indicates the output voltage V o The equivalent resistance at r op represents the small signal impedance of the second PMOS tube MP, g m13 represents the transconductance of the first PMOS tube M13, R L Represents the load resistance; includes the loop stability compensation capacitor C C The feedback coefficient of the inner loop Therefore, the loop stability compensation capacitor C C The closed-loop gain of the inner loop is The error current feedback loop gain is Due to the transconductance of the second PMOS tube MP mp It changes with the external load current. When the load current is very small and close to 0, g mp is also small, so g mp r o1 C C <<C o , the error current feedback loop gain A Z,LG Approximately equal to:

[0042]

[0043] When the load current approaches 0, there are three poles in the error current feedback loop, but one of the poles is offset by the left half plane zero, and the remaining two poles, the main pole At the output, the secondary dominant pole At the N1 node, due to the large external capacitor C o , so the main pole and the secondary main pole are separated far enough to ensure the stability of the LDO circuit.

[0044] When the load current is large, g mp is also very large, so g mp r o1 C C >>C o , error current feedback loop gain A Z,LG Approximately equal to:

[0045]

[0046] When the load current is large, the error current feedback loop has three poles, but one of the poles is offset by the left half plane zero, and the remaining two poles, the main pole Secondary main pole ω p1 <<ω p2 , so the LDO circuit remains stable.

[0047] When the load current is neither close to zero nor very large, the error current feedback loop gain A Z,LG Approximately equal to:

[0048]

[0049] When the load current is neither close to zero nor very large, the error current feedback loop has three poles, but one of the poles is offset by the left half plane zero, and the remaining two poles, the main pole Secondary main pole The voltage signal is from the transconductance amplifier A G The loop transfer function H from the input to the loop break point LG for:

[0050]

[0051] The numerator in this formula is the DC loop gain H of the LDO circuit. LG,DC , the unity gain bandwidth of the error current feedback loop ω u =H LG,DC ·ω p1 , phase margin When the phase margin PM is the smallest. Ask about g mp The derivative of , we get:

[0052]

[0053] when hour, at this time, Minimum, You can choose the PM you need min To design the loop stability compensation capacitor C C The capacitance value, Therefore, by choosing the appropriate loop stability compensation capacitor C C , which ensures that the LDO circuit remains stable under all load current ranges.

[0054] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A LDO circuit based on current feedback, characterized in that: include: Transconductance Amplifier A G , Error transimpedance amplifier A E , a buffer, a current-current feedback network, a first PMOS tube M13 and a second PMOS tube MP; The transconductance amplifier A G The reference voltage V REF Amplified into current i IN , input error transimpedance amplifier A E The positive input terminal of The error transimpedance amplifier A E , the buffer, the second PMOS tube MP, the first PMOS tube M13 and the current-current feedback network constitute an error current feedback loop, and the error transimpedance amplifier A E The negative input terminal receives the feedback current i from the current-current feedback network. FB , the error transimpedance amplifier A E The output terminal outputs an error voltage; the buffer receives the error voltage from the error transimpedance amplifier A E The output error voltage generates a buffer output voltage, which drives the second PMOS tube MP to generate an output voltage V o The first PMOS tube M13 is used to detect the output voltage V o If the output voltage V o The current flowing through the first PMOS tube M13 fluctuates, causing the current to change. The current-current feedback network generates a feedback current i according to the current change of the first PMOS tube M13. FB , input to the error transimpedance amplifier A E The negative input terminal offsets the output voltage V o fluctuations.

2. The LDO circuit based on current feedback according to claim 1, characterized in that: The transconductance amplifier A G The device comprises a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first resistor R1 and a sixth PMOS transistor M12, wherein the source of the sixth PMOS transistor M12 is used as a transconductance amplifier A G The non-inverting input terminal is connected to the reference voltage V REF The gate of the sixth PMOS tube M12, the drain of the sixth PMOS tube M12 and one end of the first resistor R1 are connected to the gate of the first PMOS tube M13, and the other end of the first resistor R1, the drain of the fifth NMOS tube M5, the gate of the fifth NMOS tube M5, and the gate of the sixth NMOS tube M6 are used as a transconductance amplifier A. G The output end is connected to the error transimpedance amplifier A E The source of the fifth NMOS tube M5 is connected to the drain of the sixth NMOS tube M6, and the source of the sixth NMOS tube M6 serves as a transconductance amplifier A G The negative input terminal is grounded.

3. The LDO circuit based on current feedback according to claim 2, characterized in that: The error transimpedance amplifier A E The invention comprises: a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a third PMOS tube M9 and a fourth PMOS tube M10, wherein the gate of the first NMOS tube M1, the gate of the second NMOS tube M2, the gate of the third NMOS tube M3 and the gate of the fourth NMOS tube M4 are used as an error transimpedance amplifier A E The positive input terminal of the first NMOS tube M1; the source of the first NMOS tube M1 is connected to the drain of the third NMOS tube M3, the source of the second NMOS tube M2 is connected to the drain of the fourth NMOS tube M4, the source of the third NMOS tube M3 and the source of the fourth NMOS tube M4 are both grounded; the drain of the first NMOS tube M1, the drain of the third PMOS tube M9, the gate of the third PMOS tube M9, and the gate of the fourth PMOS tube M10 are used together as an error transimpedance amplifier A E The negative phase input terminal is connected to the output terminal of the current-current feedback network; the source of the third PMOS tube M9 and the source of the fourth PMOS tube M10 are both connected to the power supply voltage V IN The drain of the fourth PMOS tube M10 and the drain of the second NMOS tube M2 are used as an error transimpedance amplifier A E The output end is connected to the input end of the buffer.

4. The LDO circuit based on current feedback according to claim 3, characterized in that: The buffer includes: a current source I1, a fifth PMOS tube M11 and a second resistor R2, and the input end of the current source I1 is connected to the power supply voltage V IN The output end of the current source I1 and the source of the fifth PMOS tube M11 are used as the output end of the buffer to control the opening and closing of the second PMOS tube MP; the gate of the fifth PMOS tube M11 is used as the input end of the buffer, the drain of the fifth PMOS tube M11 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

5. The LDO circuit based on current feedback according to claim 4, characterized in that: The source of the second PMOS tube MP is connected to the power supply voltage V IN The gate of the second PMOS tube MP is connected to the output end of the buffer as a control end; the drain of the second PMOS tube MP is connected to the source of the first PMOS tube M13 as the output end of the LDO circuit; the drain of the first PMOS tube M13 is connected to the input end of the current-current feedback network.

6. The LDO circuit based on current feedback according to claim 5, characterized in that: The error current feedback loop also includes a loop stability compensation capacitor Cc, one end of the loop stability compensation capacitor Cc is connected to the source of the second NMOS tube M2 and the drain of the fourth NMOS tube M4, and the other end of the loop stability compensation capacitor Cc is connected to the output end of the LDO circuit.

7. The LDO circuit based on current feedback according to claim 5, characterized in that: The current-current feedback network includes: a seventh NMOS tube M7 and an eighth NMOS tube M8, wherein the gate of the seventh NMOS tube M7, the drain of the seventh NMOS tube M7, and the gate of the eighth NMOS tube M8 serve as the input end of the current-current feedback network and are connected to the drain of the first PMOS tube M13; the drain of the eighth PMOS tube M8 serves as the output end of the current-current feedback network and is connected to the error transimpedance amplifier A E The source of the seventh NMOS tube M7 and the source of the eighth NMOS tube M8 are both grounded.

8. The LDO circuit based on current feedback according to claim 7, characterized in that: The size of the first PMOS tube M13 and the size of the sixth PMOS tube M12 satisfy: Among them, (W / L) 12 represents the width-to-length ratio of the sixth PMOS tube M12, (W / L) 13 represents the width-to-length ratio of the first PMOS tube M13.

9. The LDO circuit based on current feedback according to claim 7, characterized in that: The size of the third PMOS tube M9 and the size of the fourth PMOS tube M10 satisfy: Wherein, (W / L)9 represents the width-to-length ratio of the third PMOS tube M9, (W / L) 10 represents the width-to-length ratio of the fourth PMOS tube M10.

10. The LDO circuit based on current feedback according to claim 7, characterized in that: The size of the first NMOS tube M1, the size of the second NMOS tube M2, the size of the third NMOS tube M3, the size of the fourth NMOS tube M4, the size of the fifth NMOS tube M5, the size of the sixth NMOS tube M6, the size of the seventh NMOS tube M7, and the size of the eighth NMOS tube M8 meet the following requirements: Among them, (W / L)1 represents the width-to-length ratio of the first NMOS tube M1, (W / L)2 represents the width-to-length ratio of the second NMOS tube M2, (W / L)3 represents the width-to-length ratio of the third NMOS tube M3, (W / L)4 represents the width-to-length ratio of the fourth NMOS tube M4, (W / L)5 represents the width-to-length ratio of the fifth NMOS tube M5, (W / L)6 represents the width-to-length ratio of the sixth NMOS tube M6, (W / L)7 represents the width-to-length ratio of the seventh NMOS tube M7, (W / L)8 represents the width-to-length ratio of the eighth NMOS tube M8, and β represents the feedback coefficient, β≤1.

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