A current limiting circuit and linear voltage regulator for realizing constant power control

Abstract

A current limiting circuit and a linear voltage regulator for realizing constant power control. The current of the power tube Ppower tube of the LDO circuit is compared with the set current limiting threshold by the detection tube mirror. The output signal pulls up the gate of the Ppower tube to reduce the output current, thereby realizing output current limiting control. The channel length modulation effect of the detection tube and the power tube is utilized. When Vin rises, the rated current limiting value is reduced, thereby realizing constant power control when the input-output voltage difference of the LDO circuit rises. At the same time, in order to avoid the influence of different Vout on the current limiting value, a Vout clamping circuit is adopted to make the drain potential of Ppower and the detection tube approximately the same, thereby avoiding the current limiting difference caused by the change of Vout. The circuit of the present invention combines the difference in current limiting and channel length effects. As Vin rises, the current increase ratio of the detection tube is greater than that of the power tube, and the current limiting protection is entered in advance, thereby reducing the output current and realizing the constant power effect. The power of the power tube is prevented from rising with the increase of Vin, thereby reducing the risk of heating when the power is high.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and relates to a linear voltage regulator, which is a current limiting circuit for realizing constant power control, and a low voltage difference linear voltage regulator using the current limiting circuit. Background Art

[0002] As portable electronic products are widely used in all aspects of work and life, higher requirements are placed on the performance of power supplies, especially in terms of integration, system cost, performance indicators, etc. Low dropout linear voltage regulator (LDO) is a step-down circuit in power supplies. In principle, LDO adjusts its output impedance according to the changes in load resistance, thereby maintaining a stable output voltage.

[0003] Linear regulators have advantages such as simple design, few components, small size and low noise, but they are not as efficient and heat-generating as switching regulators, especially in terms of heat generation, and measures to control heat generation are needed to protect the device from permanent damage. When the LDO linear regulator is working, due to the voltage difference between the input and output voltages, a certain amount of power loss will be generated, and this part of the energy is converted into heat energy, causing the device to heat up.

[0004] There are two ways to control heat generation, one is to increase the heat dissipation area, and the other is to control the heat generation power. Increasing the heat dissipation area will increase the cost; while controlling the heat generation power can achieve heat control without increasing the cost. In order to reduce the heat generation of LDO, the existing technology adopts measures including: selecting low-impedance adjustment elements or selecting MOS tubes with lower ground pin resistance Rds(on) in the design, optimizing PCB layout to enhance heat dissipation, or increasing the heat conduction and convection area by installing a heat sink on the LDO or directly installing it on a larger heat sink, accelerating heat dissipation and reducing device temperature.

[0005] Using low-impedance adjustment elements or low-impedance MOS tubes in LDO products cannot reduce heat generation, but only increases the heat dissipation area, which will significantly increase the chip area and cost. Optimizing the PCB layout or installing a heat sink on the LDO will significantly increase the system cost. If a more efficient switching regulator is used to replace a linear regulator, peripheral devices such as inductors must be introduced, which increases costs. At the same time, the inductor will introduce electromagnetic interference and no longer retain the low noise characteristics of the LDO. Summary of the invention

[0006] The technical problem to be solved by the present invention is that a linear voltage stabilizer has a heating problem during operation, especially in high-power applications, and the heating problem limits the application of the linear voltage stabilizer.

[0007] The technical solution of the present invention is: a current limiting circuit for realizing constant power control, providing constant power control for the LDO circuit, the current limiting circuit includes pmos tubes P2, P6, nmos tube N3 and resistors R1, R2, the circuit is as follows:

[0008] The source and body terminals of P2 and P6 are connected to the power supply Vin, the gate of P2 and the drain of P6 are connected to the gate of the LDO circuit power tube Ppower, the drain of P2 is grounded through R1 and connected to the gate of N3, one end of R2 is connected to Vin, and the other end is connected to the gate of P6 and the drain of N3, and the source and body terminals of N3 are connected to the ground potential together;

[0009] Among them, P2 is used as a detection tube to mirror the current of Ppower. The channel length of P2 is smaller than Ppower. The current threshold of the current limiting circuit is set by the threshold of N3. The voltage divided by the current of P2 on R1 increases with the output current of the power tube Ppower. When the voltage divided is greater than the turn-on voltage of N3, N3 is turned on; at the same time, the current of N3 flows through the resistor R2. When the voltage divided by the resistor R2 is greater than the threshold of P6, P6 is turned on, and the gate potential of Ppower is pulled up. The current of Ppower decreases as the gate voltage rises, thereby limiting the output current to reach the rated current limit value; combined with the channel length modulation effect of P2 and Ppower, when Vin rises, the rated current limit value will be reduced, thereby achieving constant power control when the input-output voltage difference of the LDO circuit rises.

[0010] Furthermore, the output Vout of the LDO circuit is clamped so that at different outputs Vout, the Vds voltages of the power tube of the LDO circuit and the detection tube of the current limiting circuit are equal, Vds=Vin-Vout.

[0011] Furthermore, the clamping circuit for Vout includes pmos tubes P1, P3, P4, P5, and noms tubes N1, N2.

[0012] The source and body of P1 are connected to the power supply Vin, the gate of P1 is connected to the gate of the power tube Ppower of the LDO circuit, the drain of P1 is connected to the source and body of P4, the drain of P4 is connected to the drain, gate of N2, and the gate of N1, the gate of P4 is connected to the gate, drain of P3, the drain of N1, and the gate of P5, the source and body of P3 are connected to the output Vout of the drain of Ppower, the sources and body of N1 and N2 are connected to the ground potential, the source and body of P5 are connected to the drain of P2, the drain of P5 is grounded after R1, and the gate of N3 is connected between the drain of P5 and R1;

[0013] P3 detects the Vout signal and provides bias voltage to P4 and P5. P1 is used as a detection tube to detect the Ppower current. The channel length of P1 is smaller than Ppower. The detected current is used to form a self-biased current source through P3 / P4 / N1 / N2, so that the Ppower and Vds voltages of P1 and P2 are equal under different Vout conditions.

[0014] Furthermore, in the clamping circuit, P3, P4, and P5 have the same size, N1 and N2 have the same size, and Vsg of P3, P4, and P5 are equal, so that the source voltage of P4 and P5 is Vout, and Vds P1 =Vds P2 =Vin-Vout=Vds power .

[0015] Furthermore, the pmos tubes P1 and P2 are equal in size.

[0016] The present invention also provides a linear voltage regulator circuit with constant power control, in which the power tube Ppower of the LDO circuit is connected to the current limiting circuit as described above.

[0017] The present invention provides a current limiting circuit that can realize constant power control. The power P of the LDO product is P=I*V, I is the current, V is the voltage difference between input and output, and the power is converted into heat. Controlling the power can control the heat. The present invention can automatically adjust the output current I by current limiting in combination with the channel length modulation effect when Vin rises and V=Vin-Vout rises. The channel length of the detection tube is designed to be smaller than that of the power tube. The channel length modulation difference is utilized to reduce the current ratio between the power tube and the detection tube by channel length modulation, so that the current limiting value decreases as Vin rises, thereby realizing constant power control, thereby keeping the product P=I*V approximately unchanged, and realizing the effect of controlling the heat generation power. Since the present invention does not need to increase the heat dissipation area, the circuit structure is simple, and compared with the prior art, the cost increase caused by the increase in chip area or the increase in peripheral systems can be reduced, while the advantages of LDO such as simple design, small number of components, small size and low noise can also be maintained.

[0018] When the current limiting circuit of the present invention is used in an LDO circuit, the LDO will gradually increase the supply current when the input voltage is fixed until the current limit is reached; once the current limit is exceeded, the input voltage Vin rises, causing the input and output voltage difference to increase. Since the present invention uses different channel lengths for the detection tube and the power tube, the difference in channel length modulation can be used to reduce the current ratio between the power tube and the detection tube of the current limiting detection circuit through channel length modulation, so that the current limiting value decreases as Vin increases, and the output current is automatically adjusted down, thereby achieving constant power control. Furthermore, the present invention also designs a clamping circuit for the Vout of the LDO circuit so that the current limiting effect does not change with Vout. The present invention can avoid the risk of damage caused by heating of the chip under high power. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the current limiting circuit of the present invention.

[0020] Figure 2 The figure is a schematic diagram of a current limiting circuit with a clamping circuit according to the present invention. DETAILED DESCRIPTION

[0021] The specific implementation of the present invention is described below with reference to the accompanying drawings.

[0022] like Figure 1 As shown, the current limiting circuit for realizing constant power control of the present invention includes pmos tubes P2, P6, nmos tube N3 and resistors R1, R2, and the circuit is as follows:

[0023] The source and body of P2 and P6 are connected to the power supply Vin, the gate of P2 and the drain of P6 are connected to the gate of the LDO circuit power tube Ppower, the drain of P2 is grounded through R1 and connected to the gate of N3, one end of R2 is connected to Vin, the other end is connected to the gate of P6 and the drain of N3, and the source and body of N3 are connected to the ground potential. Among them, P2 is used as a detection tube to mirror the current of Ppower, and the channel length of P2 is smaller than Ppower.

[0024] The current limiting circuit of the constant power control of the present invention is used for the LDO circuit to realize the constant power control of the LDO circuit. The LDO basic circuit is composed of a reference, an operational amplifier EA1, an output power tube Ppower, and feedback resistors RFB1 and RFB2. The reference provides a bias current Ibias and a reference voltage VREF for the LDO circuit, the operational amplifier EA1 controls the output voltage of the LDO circuit, Ppower is the output power tube of the LDO circuit, RFB1 and RFB2 are output feedback resistors, which are used to set the output voltage Vout according to the reference voltage, that is, Vout=VREF*(RFB1+RFB2) / RFB1. The source and body of the power tube Ppower are connected to Vin together, its gate is connected to the output end of the operational amplifier EA1, its drain is connected to one end of the resistor RFB2, and the output voltage Vout. The other end of RFB2 is connected to one end of the resistor RFB1 and to one end of the input of the operational amplifier EA1. The other end of RFB1 is connected to the ground potential. The other end of the input of the operational amplifier is connected to the reference voltage VREF of the reference.

[0025] When the current limiting circuit of the present invention is used for constant power control of the LDO basic circuit, P2 is used as the detection tube to mirror the current of Ppower, and the threshold of the current limiting circuit is set by the threshold of N3. As the output current of the power tube Ppower increases, when the partial pressure of the detection current of P2 on R1 is greater than the turn-on voltage of N3, N3 is turned on; at the same time, the current of N3 flows through the resistor R2, and the partial pressure of the resistor R2 is greater than the threshold of P6, causing P6 to turn on, thereby pulling up the gate potential of Ppower. The smaller the Vsg voltage of pmos, the smaller the current, so the current of the Ppower tube will decrease as its gate voltage rises, thereby forming the effect of limiting the output current and reaching the rated current limiting value. However, only limiting the current of the power tube does not meet the constant power control requirements. P=I*V, V=Vin-Vout. As Vin rises, the input-output voltage difference increases, and the constant power control also requires a decrease in I. The present invention designs the difference in the channel length modulation effect between the detection tube and the power tube of the current limiting circuit. The detection tube current rise ratio is greater than that of the power tube, so that the circuit enters the current limiting protection in advance. The channel length modulation increases the proportion of the detection current. When Vin rises, the rated current limit value will be reduced, thereby realizing constant power control when the input-output voltage difference of the LDO circuit rises, limiting the increase in power. The constant power control of the current limiting circuit of the present invention realizes the control of the heating power of the LDO, thereby overcoming the defects of the LDO in heating.

[0026] As an embodiment, the power tube Ppower adopts a normal channel length, such as 0.6um. The detection tube channel length Ldect of the present invention adopts a channel length size smaller than Ppower, such as 0.5um or less. In normal current limiting detection, both the Ppower tube and the detection tube are in saturation state. For the MOS current in the saturation region, considering the channel length modulation effect, the following formula is obtained:

[0027] Ids=μ p C OX *(W / L) *(Vsg-Vth p )2 / 2 *(1+λ*Vds)

[0028] μ p is the mobility of holes, C OX is the gate oxide capacitance per unit area, W / L is the width-to-length ratio of the output tube, Vsg is the gate-source voltage difference of the pmos tube, Vth p is the pmos threshold, Vds is the voltage difference between the drain and source of pmos. The channel length modulation coefficient λ represents the relative change in channel length caused by a given increment, λ∝‌1 / L, therefore, the longer the channel length L, the smaller λ.

[0029] Since the channel length L of the power tube Ppower power The size is larger than the channel L of the detection tube dect Therefore, its channel length modulation coefficient is smaller than that of the detection tube, that is, λ power <λ dect Since the detection tube is in the saturation state during the mirror detection, the saturation current formula above can be used to obtain:

[0030] The power tube current is:

[0031] Ids power =μ p C OX *(W / L) power *(Vsg power -Vth power )2 / 2 *(1+λ power *Vds power ),

[0032] The size of the detection tube is equal to (W / L) dect , its saturation current is:

[0033] Ids dect =μ p C OX *(W / L) dect *(Vsg dect -Vth p )2 / 2 *(1+λdect *Vds dect ),

[0034] Because both the Ppower tube and the detection tube are pmos, μ p C OX and Vth p Approximately equal; at the same time, since the gates of the Ppower tube and the detection tube are connected, we have:

[0035] Vx power = Vsg dect

[0036] Then the mirror current ratio of the power tube and the detection tube is:

[0037] Ids power / Ids dect =μ p C OX *(W / L) power *(Vsg power -Vth p )2 / 2 *(1+λ power *Vds power ) /

[0038] [μ p C OX *(W / L) dect *(Vsg dect -Vth p )2 / 2 *(1+λ dect *Vds dect )]

[0039] It can be simplified to:

[0040] Ids power / Ids dect =(W / L) power *(1+λ power *Vds power ) / [(W / L) dect *(1+λ dect *Vds dect )]

[0041] You can get:

[0042] Ids dect =Ids power *(W / L) dect *(1+λ dect *Vds dect ) / [ (W / L) power *(1+λ power *Vds power)].

[0043] (W / L) power and (W / L) dect The size is fixed, corresponding to the same load current, that is, the output current Ids of the Ppower tube power , the same Vout, as the load current increases, Vds power and Vds dect Rise together, IDs dect will increase and reach the rated current limit value, thereby limiting the output current. power <λ dect ,λ power * Vds power <λ dect * Vds dect As Vin increases, the Ppower tube current and Idect detection ratio decreases, the output current decreases, that is, the rated current limit value decreases, which makes the output power (Vin-Vout)*I power That is, in the circuit of the present invention, under the cooperation of current limiting and channel length modulation effects, Vin-Vout increases as Vin increases, and I power It decreases as Vin increases, achieving constant power control of the output power.

[0044] Furthermore, the constant power control of the present invention is based on the difference in channel length modulation between the detection tube and the power tube. Since the detection tube needs to mirror the current of the power tube Ppower tube, for the pmos tube, the Vds voltage is the key factor that determines the influence of the channel length modulation on the current. Theoretically, if the Vds voltages of the two tubes of the current mirror are the same, the mirror ratio will be consistent with the theoretical value; if the Vds are different, the mirror ratio of the two tubes will deviate from the theoretical value. The present invention designs a clamping circuit for Vout to ensure that the Vds of the power tube and the detection tube are equal, so as to avoid different Vout causing different Vds, resulting in a difference in the mirror ratio of the two tubes, and affecting the regulation effect of the rated current limiting value.

[0045] The linear regulator LDO will have different output voltages Vout, such as Vout=1.2 or 3.3V, and the current limiting effect may be different. The present invention further designs a clamping circuit for Vout to ensure that the current limiting effect remains consistent under different Vout voltages. The present invention introduces a Vout clamping circuit to ensure that the Vds voltage of the power tube and its current limiting detection tube are equal, Vds=Vin-Vout, so that the detection ratio of the current limiting circuit detection tube is accurate and is not affected by Vds.

[0046] As an embodiment, the clamping circuit includes pmos tubes P1, P3, P4, P5, and noms tubes N1, N2, and the circuit connection is as follows: Figure 2shown.

[0047] The source and body of P1 are connected to the power supply Vin, the gate of P1 is connected to the gate of the power tube Ppower of the LDO circuit, the drain of P1 is connected to the source and body of P4, the drain of P4 is connected to the drain, gate of N2, and the gate of N1, the gate of P4 is connected to the gate, drain of P3, the drain of N1, and the gate of P5, the source and body of P3 are connected to the output Vout of the drain of Ppower, the source and body of N1 and N2 are connected to the ground potential, the source of P5 is connected to the ground potential, and the The electrode and body are connected to the drain of P2, the drain of P5 is grounded after R1, and the gate of N3 is connected between the drain of P5 and R1; P3 detects the Vout signal and provides bias voltage to P4 and P5 at the same time. P1 is used as a detection tube to detect the Ppower current. The channel length of P1 is smaller than Ppower. The detected current is used to form a self-biased current source through P3 / P4 / N1 / N2, so that under different Vout conditions, the Ppower and the Vds voltages of P1 and P2 are equal.

[0048] The clamping circuit is used to ensure that under different Vout conditions, the Vds voltages of Ppower and the detection tubes P1 and P2 are equal, reducing the impact of Vout on the channel length. Channel length modulation is related to Vds=Vin-vout. If the Vds of the power tube and the detection tube are equal, their detection ratio is approximately constant; to avoid the introduction of new channel length modulation when the Vds of the Ppower tube and the detection tube are different, the detection ratio will change. As a preferred embodiment, P3, P4, and P5 are the same size, and N1 and N2 are the same size. Since the bias currents of N1 and N2 are the same, and the sizes of P3, P4, and P5 are equal, there is Vsg P3 = Vsg P4 = Vsg P5 , so that the source voltage of P4 and P5 is Vout, that is,

[0049] VdS P1 =Vds P2 =Vin-Vout=Vds power .

[0050] For the aforementioned Ids dect Calculation:

[0051] Ids dect =Ids power *(W / L) dect *(1+λ dect *Vds dect ) / [ (W / L) power *(1+λ power *Vds power )],

[0052] Due to the introduction of Vout potential clamping circuits P3, P4, and P5, we can get: Vds power =Vds dect , corresponding to the same load current Ids power , the same Vout, as the load current increases, Vds power =Vds dect Rise together to ensure λ power *Vds power <λ dect * Vds dect , stabilize the regulation effect of the current limit value, and then ensure the same constant power control effect under different Vout.

[0053] The present invention performs Figure 2 The current limiting effect of the circuit shown was tested, as shown in Table 1.

[0054] Table 1

[0055]

[0056] It can be seen that for the two versions of Vout=1.2V and 1.8V, as the input voltage Vin increases, under the same output resistance, the output Iout current decreases, and the output Vout of the LDO circuit also decreases accordingly. Iout is the output of Ppower, which is also the rated current limit value. This achieves the effect of controlling the output power and controlling the heat of the LDO circuit.

[0057] In summary, the present invention proposes a constant power control current limiting circuit for LDO, which compares the power tube Ppower tube current of the LDO circuit with the current limiting threshold of the nmos threshold by detecting the tube mirror, and the output signal pulls up the gate of the Ppower tube to reduce the output current, and introduces the difference in channel length effect by setting the detection tube channel length to be smaller than the channel length of the power tube Ppower. As Vin rises, the detection tube current rises at a greater rate than the power tube, and enters the current limiting protection in advance, thereby reducing the output current and achieving a constant power effect, avoiding the power increase with the increase of Vin, controlling the heat generation power of the LDO circuit, and reducing the risk of heat generation when the power is high. Furthermore, in order to avoid the influence of different Vout on the current limiting value, a Vout clamping circuit is used to make the drain potential of Ppower and the detection tube approximately the same, thereby avoiding the current limiting difference caused by Vout changes.

Claims

1. A current limiting circuit for realizing constant power control, characterized in that To provide constant power control for the LDO circuit, the current limiting circuit includes pmos tubes P2, P6, nmos tube N3 and resistors R1, R2. The circuit is as follows: The source and body terminals of P2 and P6 are connected to the power supply Vin, the gate of P2 and the drain of P6 are connected to the gate of the LDO circuit power tube Ppower, the drain of P2 is grounded through R1 and connected to the gate of N3, one end of R2 is connected to Vin, and the other end is connected to the gate of P6 and the drain of N3, and the source and body terminals of N3 are connected to the ground potential together; Among them, P2 is used as a detection tube to mirror the current of Ppower. The channel length of P2 is smaller than Ppower. The current threshold of the current limiting circuit is set by the threshold of N3. The voltage divided by the current of P2 on R1 increases with the output current of the power tube Ppower. When the voltage divided is greater than the threshold of N3, N3 is turned on; at the same time, the current of N3 flows through the resistor R2. When the voltage divided by the resistor R2 is greater than the threshold of P6, P6 is turned on, and the gate potential of Ppower is pulled up. The current of Ppower decreases as the gate voltage increases, thereby limiting the output current to reach the rated current limit value; combined with the channel length modulation effect of P2 and Ppower, when Vin rises, the rated current limit value will be reduced, thereby achieving constant power control when the input-output voltage difference of the LDO circuit increases.

2. A current limiting circuit for realizing constant power control according to claim 1, characterized in that The output Vout of the LDO circuit is clamped so that at different output Vout, the Vds voltages of the LDO circuit power tube and the current limiting circuit detection tube are equal, Vds=Vin-Vout.

3. A current limiting circuit for realizing constant power control according to claim 2, characterized in that The clamping circuit for Vout clamping includes pmos tubes P1, P3, P4, P5, and nmos tubes N1, N2. The source and body of P1 are connected to the power supply Vin, the gate of P1 is connected to the gate of the power tube Ppower of the LDO circuit, the drain of P1 is connected to the source and body of P4, the drain of P4 is connected to the drain, gate of N2, and the gate of N1, the gate of P4 is connected to the gate, drain of P3, the drain of N1, and the gate of P5, the source and body of P3 are connected to the output Vout of the drain of Ppower, the sources and body of N1 and N2 are connected to the ground potential, the source and body of P5 are connected to the drain of P2, the drain of P5 is grounded after R1, and the gate of N3 is connected between the drain of P5 and R1; P3 detects the Vout signal and provides bias voltage to P4 and P5. P1 is used as a detection tube to detect the Ppower current. The channel length of P1 is smaller than Ppower. The detected current is used to form a self-biased current source through P3, P4, N1 and N2, so that the Ppower and Vds voltages of P1 and P2 are equal under different Vout conditions.

4. A current limiting circuit for realizing constant power control according to claim 3, characterized in that In the clamping circuit, P3, P4, and P5 have the same size, N1 and N2 have the same size, and Vsg of P3, P4, and P5 are equal, so that the source voltage of P4 and P5 is Vout, and Vds P1 =Vds P2 =Vin-Vout=Vds power , Vds P1、 VdS P2、 VdS power They are the Vds voltages of P1, P2 and Ppower respectively.

5. A current limiting circuit for realizing constant power control according to claim 3, characterized in that the pmos tubes P1 and P2 are equal in size.

6. A linear regulator circuit with constant power control, characterized in that The power tube Ppower of the linear regulator circuit is connected to the current limiting circuit as described in any one of claims 1-5.

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