Cache verification method, device, electronic device and readable storage medium

Abstract

The embodiments of the present invention provide a cache verification method, device, electronic device and readable storage medium. The method includes: constructing a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, constructing a second subroutine; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; generating a verification result of the cache to be verified based on the response result of the second subroutine. In this way, the embodiment of the present invention can realize hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating data access requests and obtaining the verification result based on the response result of the second subroutine, the constraints on the test can be realized according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a cache verification method, device, electronic device and readable storage medium. Background Art

[0002] With the development of computer technology, some integrated chips adopt multi-processor (Central Processing Unit, CPU) systems, that is, multiple processor cores are used for data processing.

[0003] In a multi-core CPU, multiple cores often access and update the same shared data (such as global variables, process control blocks, etc.). To ensure data consistency for each core, the cache module usually performs corresponding functional behaviors based on the cache consistency protocol. Therefore, the behavioral accuracy of the cache module is particularly important. How to verify the cache module has become an urgent problem that needs to be solved. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a cache verification method, device, electronic device, and readable storage medium to solve the problem of how to verify the cache. The specific technical solution is as follows:

[0005] In a first aspect of the present invention, a cache verification method is provided, the method comprising:

[0006] Constructing a first subroutine; the first subroutine is used to generate a data access request;

[0007] Based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information;

[0008] Based on the response result of the second subroutine, a verification result of the cache to be verified is generated.

[0009] Optionally, responding to the data access request based on the functional behavior information includes:

[0010] Determining at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request;

[0011] generating at least one data acquisition request based on the data acquisition address and outputting the data acquisition request;

[0012] At least one data write request is generated based on the data write address and output.

[0013] Optionally, the method further includes:

[0014] The second subroutine is executed cyclically to obtain a plurality of response results of the second subroutine.

[0015] Optionally, generating the verification result of the cache to be verified based on the response result of the second subroutine includes:

[0016] generating a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified;

[0017] Based on the response result of the second subroutine and the reference response result, a verification result of the cache to be verified is generated.

[0018] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0019] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0020] In a second aspect of the present invention, a cache verification device is provided, comprising:

[0021] A first building module is used to build a first subroutine; the first subroutine is used to generate a data access request;

[0022] A second construction module is configured to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is configured to receive the data access request and respond to the data access request based on the functional behavior information;

[0023] A generating module is used to generate a verification result of the cache to be verified based on the response result of the second subroutine.

[0024] Optionally, the second building block includes:

[0025] a determination submodule, configured to determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request;

[0026] a first request generating submodule, configured to generate at least one data acquisition request based on the data acquisition address and output the data acquisition request;

[0027] The second request generating submodule is configured to generate at least one data writing request based on the data writing address and output the data writing request.

[0028] Optionally, the device further comprises:

[0029] The execution module is used to execute the second subroutine in a loop to obtain multiple response results of the second subroutine.

[0030] Optionally, the generating module includes:

[0031] A reference submodule, configured to generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified;

[0032] The result generating submodule is configured to generate a verification result of the cache to be verified based on the response result of the second subprogram and the reference response result.

[0033] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0034] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0035] In a third aspect of the present invention, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0036] Memory for storing computer programs;

[0037] The processor is configured to implement the method described in the first aspect above when executing the program stored in the memory.

[0038] In a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the computer-readable storage medium is run on a computer, the computer executes the method described in the first aspect.

[0039] In a fifth aspect of the implementation of the present invention, a computer program product comprising instructions is further provided, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0040] The cache verification method provided by the embodiment of the present invention is constructed by constructing a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; and the verification result of the cache to be verified is generated based on the response result of the second subroutine. In this way, the embodiment of the present invention can realize hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating the data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be implemented according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments or the prior art.

[0042] Figure 1 This is a flowchart of a cache verification method according to an embodiment of the present invention;

[0043] Figure 2 is a schematic structural diagram of a second subroutine in an embodiment of the present invention;

[0044] Figure 3 Schematic diagram of the structure of a cache verification device in an embodiment of the present invention;

[0045] Figure 4 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0048] Figure 1 FIG. 1 is a flow chart of steps of a cache verification method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0049] Step 101: Construct a first subroutine; the first subroutine is used to generate a data access request.

[0050] Step 102: Construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information.

[0051] Step 103: Generate a verification result of the cache to be verified based on the response result of the second subroutine.

[0052] With respect to the above steps 101 to 103, the embodiment of the present invention can be applied to any computer device, and the embodiment of the present invention does not impose any restrictions on this. It should be noted that the embodiment of the present invention can be carried out in the chip design stage to perform functional verification on the designed cache module. Of course, it can also be carried out before the chip goes into production or when there is a functional abnormality, and the embodiment of the present invention does not impose any restrictions on this. Among them, the above-mentioned cache to be verified refers to a cache module that has verification requirements. Cache refers to a high-speed memory whose access speed is faster than that of system memory and is comparable to the processing speed of the CPU, but the cache capacity is much smaller than that of the system memory. The principle based on the cache is the "local behavior of program execution and data access" in the memory, that is, within a certain program execution time and space, the accessed code and data will be concentrated in a part.

[0053] The functional behavior information characterizes the cache coherence protocol implemented by the cache to be verified, i.e., the cache coherence protocol followed by the cache to be verified during normal operation. A cache coherence protocol refers to cache coherence management in a multi-processor system. In a multi-core system, multiple cores may simultaneously read and write to the same memory address. To manage these concurrent accesses and ensure data consistency across cores, a protocol is required to coordinate the cache states of each core to prevent stale or erroneous data from being read. Therefore, it is necessary for the cache module to implement the corresponding functional behavior based on the cache coherence protocol. The cache coherence protocol can be MESI (Modified, Exclusive, Shared, Invalid), MOESI (Modified, Owned, Exclusive, Shared, Invalid), MSI (Modified, Shared, Invalid), or CHI (Coherent Hub Interface), among others, though this is not a limitation in the present embodiment.

[0054] Specifically, the cache is used in the processor system to receive data access requests and respond to data access requests, that is, according to the data access requests of the CPU, CPU core or other modules, read data from the corresponding address or write data. Accordingly, in order to verify the cache module, the embodiment of the present invention can construct a first subroutine, and the first subroutine is used to generate data access requests. The above-mentioned first subroutine can be understood as a test module used to provide incentives to the cache to be verified in a test environment, and different data access requests can represent different types of incentives. Specifically, the first subroutine can randomly generate data access requests, or it can generate data access requests according to preset rules. It can be set according to actual needs, and the embodiment of the present invention does not limit this. Among them, the above-mentioned preset rules can be the parameter content required to be included in the data access request, for example, it can include the access address, and it can also include the CPU core identifier, etc. It can be set based on the verification requirements, and the embodiment of the present invention does not limit this.

[0055] Among them, the above-mentioned functional behavior information is also used to describe the functional behavior implemented when the cache to be verified is running. Specifically, the functional behavior implemented when the cache module is running refers to the request sent by the cache module during normal operation, that is, when the simulated processor is operating normally, the minimum condition for the normal operation of the cache module, which is usually provided by the hardware circuit. However, building a hardware circuit is often cumbersome, resulting in low verification efficiency. In this case, the embodiment of the present invention can construct a second subroutine based on the functional behavior information of the cache to be verified for verification, without the need to build a real hardware circuit for simulation.

[0056] Specifically, the functional behavior information often refers to operational behavior that complies with specified bus protocol rules. Based on this, the second subroutine can receive a data access request and respond to the data access request based on the specified bus protocol rules. Specifically, the response operation refers to issuing a corresponding data read or write request based on the data access request and the functional behavior information. The specified bus protocol rules can be a pre-set cache coherence protocol, such as CHI, MSI, etc.

[0057] The above-mentioned response result refers to the data read and write request issued by the second subroutine based on each data access request. Furthermore, the embodiment of the present invention can verify the cache to be verified based on the response result output by the second subroutine. Specifically, the embodiment of the present invention can generate a reference response result for each data access request based on the specified bus protocol rules. Accordingly, the response result of each data access request and the reference response result can be compared. If the comparison is consistent, it is determined that the cache to be verified complies with the specified bus protocol rules. If the comparison is inconsistent, it is determined that the cache to be verified does not comply with the specified bus protocol rules.

[0058] Optionally, embodiments of the present invention may further set a ratio threshold to determine the proportion of response results that are consistent with the comparison, and if the ratio is greater than the ratio threshold, determine that the cache to be verified complies with the specified bus protocol rules. If the ratio is not greater than the ratio threshold, determine that the cache to be verified does not comply with the specified bus protocol rules.

[0059] In summary, the cache verification method provided by the embodiment of the present invention is constructed by constructing a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; and the verification result of the cache to be verified is generated based on the response result of the second subroutine. In this way, the embodiment of the present invention can realize hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating the data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be implemented according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification.

[0060] Optionally, the operation of responding to the data access request based on the functional behavior information may include:

[0061] S21. Determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request.

[0062] S22. Generate at least one data acquisition request based on the data acquisition address and output the data acquisition request.

[0063] S23. Generate at least one data write request based on the data write address and output the data write request.

[0064] The data acquisition address and data write address can be generated based on a data access request and functional behavior information. Based on the access address carried in the data access request and the bus protocol rules corresponding to the cache to be verified, a data processing operation that complies with the bus protocol rules can be determined. Furthermore, based on the determined data processing operation, at least one data acquisition address and at least one data write address that comply with the bus protocol rules can be determined. Accordingly, a data acquisition request can be generated and output based on the data acquisition address, and a data write request can be generated and output based on the data write address.

[0065] For example, using the CHI bus, a data access request indicates a desire for a unique copy of the data. This allows the user to modify the data, otherwise other copies (if any) would not be aware that their data is no longer authentic. In this case, no cache has a valid copy at the time the request is issued, whether it's the requesting module or any other cache at a lower level. To maintain cache coherence within the CHI bus, embodiments of the present invention can first access the memory address carried in the data access request to request the current data. Based on CHI rules, a data retrieval request is then sent to the memory address in memory. Furthermore, in this example, the data at the memory address does not have a new or old relationship. Furthermore, the data retrieval request message contains the node identifier of the original request, so embodiments of the present invention can also generate a data write request to return the data to the requester. Furthermore, embodiments of the present invention can also add a unique identifier (uniqueclean, uc) to both the data retrieval and data write requests. uc indicates that the data is a unique copy that is consistent with the data in memory. The request initiator can then send a transaction completion identifier (compack) to indicate the completion of the transaction.

[0066] Specifically, since the data processing operations performed by the cache are often data transfer, each data processing operation requires data acquisition and data writing. When the data access request is a data storage request, the above-mentioned data acquisition address can be the access address carried by the data storage request, and accordingly, the above-mentioned data write address can be the address to which the data needs to be written. It can be understood that in order to ensure cache consistency, the cache consistency protocol often performs cache updates so that the data in the caches of different cores remain consistent. Therefore, the above-mentioned data write address can be one or more. When the data access request is a data access request, the above-mentioned data acquisition address can be the access address carried by the data access request, and accordingly, the above-mentioned data write address can be the destination address carried by the data access request. Furthermore, since the data transfer of multiple addresses may be involved in the data processing operation, the above-mentioned data acquisition address can also be multiple.

[0067] Furthermore, by outputting a data acquisition request and a data writing request, the response result of the second subroutine can be printed, thereby facilitating timely acquisition of the response result of the second subroutine.

[0068] In an embodiment of the present invention, based on the functional behavior information and the data access request, at least one data acquisition address and at least one data write address are determined; at least one data acquisition request is generated and output based on the data acquisition address; and at least one data write request is generated and output based on the data write address. In this way, the response of the second subroutine can be obtained through the output of the second subroutine. Furthermore, by generating data acquisition and data write requests, it is possible to verify whether the operation of the cache to be verified complies with the corresponding functional behavior information, thereby achieving cache verification.

[0069] Optionally, the embodiment of the present invention may further include:

[0070] S31 , loopingly executing the second subroutine to obtain multiple response results of the second subroutine.

[0071] The above loop operation can be implemented through a loop function, and the above second subroutine can be nested in a loop function (for loop function or while loop function, etc.), so that the second subroutine in the loop function can be executed cyclically according to the clock cycle.

[0072] Specifically, each loop can include data acquisition and data submission operations. Accordingly, each loop can output a data acquisition request and a data write request, thereby achieving the effect of data flow in a pipeline design. Specifically, in the embodiment of the present invention, the operations of submit, acquire, submit, and acquire can be executed in sequence, thereby achieving the effect of data update within a single beat of the combinational logic.

[0073] Optionally, the second subroutine can also be used to construct a first queue and a second queue. The first queue is used to store data access requests sent by the first subroutine in the order in which they were received. When the first queue is full, the first subroutine can be prepared to resend the request and store partial information in the second queue. At the same time, when there is a free position in the first queue, the first subroutine is required to resend the corresponding request based on the partial information of the original request stored in the second queue. Accordingly, the second subroutine responds to the stored data access requests in sequence according to the order in which they were stored in the first queue. In this way, the feedback queue structure of the cache module can be simulated.

[0074] Optionally, Figure 2 FIG. 1 is a schematic diagram of the structure of a second subroutine in an embodiment of the present invention, such as Figure 2 As shown, the second subroutine can specifically include a transceiver module, a cache module, and a control module. The transceiver module is used to receive data access requests and output data access requests. The cache module is used to record the addresses of global valid data and local valid data. The control module is used to execute the above-mentioned S21~S23 operations, that is, to control the process of each transaction. Each transaction starts when the request receiving module receives the request. Among them, the transceiver module can include receiving modules and sending modules of different channels, namely: a request receiving module, a data receiving module, a response receiving module, a request sending module, a data sending module, a response sending module, and a monitoring sending module. Among them, the retransmission (Retry) queue refers to the above-mentioned second queue, which is used to store partial information of the request when the first queue is full.

[0075] Optionally, the operation of generating the verification result of the cache to be verified based on the response result of the second subroutine may specifically include:

[0076] S41. Generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified.

[0077] S42: Generate a verification result of the cache to be verified based on the response result of the second subroutine and the reference response result.

[0078] Specifically, for any data access request, the reference response result may include the response operations sequentially executed by the cache when the functional behavior information is met, i.e., a series of data transfer operations performed by the cache. Accordingly, embodiments of the present invention may compare the request parameters and the execution order of each request contained in the reference response result with the response result. If they are consistent, the cache to be verified meets the requirements; if not, it does not meet the requirements.

[0079] Thus, in this embodiment of the present invention, a reference response result is generated for each data access request based on the functional behavior information of the cache to be verified; and a verification result of the cache to be verified is generated based on the response result of the second subroutine and the reference response result. In this way, cache verification can be achieved.

[0080] Optionally, the data memory access request at least includes a processor core identifier and a memory access address.

[0081] The processor core identifier is a unique identifier for each CPU core and is used to identify each processor core. Specifically, the cache consistency protocols used by multi-core CPUs (e.g., MESI, MOESI, MSI, etc.) must handle multiple cache states (e.g., shared, exclusive, modified, etc.), and these protocols must minimize redundant communication. Designing a reasonable protocol that ensures data consistency while avoiding frequent delays and conflicts is an extremely complex process. To ensure cache consistency verification, data access requests from different CPU cores can be used for verification. Therefore, the data access requests in the embodiments of the present invention may include a processor core identifier. Furthermore, the processor core identifier may be generated based on the processor core included in the system where the cache to be verified is located. It may be generated randomly according to actual needs or according to preset rules, and the embodiments of the present invention do not impose any restrictions on this.

[0082] Accordingly, since the cache may perform different response operations for different memory access addresses, the data memory access request in the embodiment of the present invention may also include the memory access address, so that the second subroutine responds based on the functional behavior information and the memory access address. The memory access address may be a memory address or an address of a first-level cache or a second-level cache, and may be randomly generated, which is not limited in the embodiment of the present invention.

[0083] Optionally, the data access request may be generated based on different verification requirements. For example, it may be verification of data sharing between threads, such as a shared counter or a lock variable.

[0084] In this way, the embodiment of the present invention can verify the cache consistency of a multi-core CPU system by carrying a processor core identifier and a data access address, ensuring that cache updates between cores are propagated in a timely manner, and avoiding calculation errors or resource competition caused by data asynchrony.

[0085] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0086] The high-level programming language mentioned above refers to a high-level software development language, as opposed to a low-level programming language. These languages ​​typically offer a good human-computer interface and powerful data abstraction capabilities. The high-level programming language can be Java, C, C++, Python, or System C, and can be selected based on actual needs, which is not limited in this embodiment of the present invention. Optionally, event-driven methods and kernel-like scheduling methods can be used to update combinatorial or sequential logic.

[0087] It's important to note that hardware description languages ​​(HDLs) such as SystemC, Verilog, and SystemVerilog are commonly used to build hardware design models. However, these languages ​​differ significantly from traditional software development languages, requiring developers to understand concepts such as hardware timing, latency, and parallelism. This can be a high learning curve for beginners, especially understanding sequential logic and circuit synchronization. Furthermore, HDLs like Verilog and VHDL primarily operate at the register transfer level (RTL), requiring developers to manually define signal transmission and states, resulting in a low level of abstraction. This low level of abstraction results in lengthy code and difficult debugging when designing complex circuits, reducing development efficiency.

[0088] The embodiments of the present invention are constructed using a high-level programming language, enabling code to be written through high-level synthesis (HLS), simplifying the tedious details of the register transfer level (RTL). By leveraging Python's advanced data structures and control statements, developers can more easily describe complex circuit behavior and data flow. Python's modular design and encapsulation of functions and classes allow for easier reuse of hardware design code, facilitating the construction of parameterized modules and functions. Developers can use object-oriented methods to build complex modules and achieve a high code reuse rate. Alternatively, compared to SystemC, which has a comprehensive library, Python requires a similar library for timing simulation and a scheduler to schedule the processes of each component, facilitating hardware language expression. The embodiments of the present invention can pre-acquire the Python library and construct the first and second subroutines described above based on the Python library.

[0089] Figure 3FIG. 1 is a schematic diagram of the structure of a cache verification device according to an embodiment of the present invention. Figure 3 As shown, the device 20 may include:

[0090] A first construction module 201 is used to construct a first subroutine; the first subroutine is used to generate a data access request;

[0091] A second construction module 202 is configured to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is configured to receive the data access request and respond to the data access request based on the functional behavior information; the functional behavior information is configured to characterize the cache coherence protocol implemented by the cache to be verified;

[0092] The generating module 203 is configured to generate a verification result of the cache to be verified based on the response result of the second subroutine.

[0093] Optionally, the second building block includes:

[0094] a determination submodule, configured to determine at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request;

[0095] a first request generating submodule, configured to generate at least one data acquisition request based on the data acquisition address and output the data acquisition request;

[0096] The second request generating submodule is configured to generate at least one data writing request based on the data writing address and output the data writing request.

[0097] Optionally, the device further comprises:

[0098] The execution module is used to execute the second subroutine in a loop to obtain multiple response results of the second subroutine.

[0099] Optionally, the generating module includes:

[0100] A reference submodule, configured to generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified;

[0101] The result generating submodule is configured to generate a verification result of the cache to be verified based on the response result of the second subprogram and the reference response result.

[0102] Optionally, the data memory access request includes at least a processor core identifier and a memory access address.

[0103] Optionally, both the first subroutine and the second subroutine are constructed based on a high-level programming language.

[0104] In summary, the cache verification device provided by the embodiment of the present invention constructs a first subroutine; the first subroutine is used to generate a data access request; based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data access request and respond to the data access request based on the functional behavior information; and the verification result of the cache to be verified is generated based on the response result of the second subroutine. In this way, the embodiment of the present invention can realize hardware modeling of the cache to be verified by constructing the second subroutine based on the functional behavior information of the cache to be verified. At the same time, by constructing the first subroutine for generating the data access request, the cache to be verified can be verified by the first subroutine and the second subroutine, and the verification result can be obtained according to the response result of the second subroutine. The constraints on the test can be realized according to different data access requests, different cache verification requirements can be met, and the effect of cache verification can be improved. At the same time, compared with the method of building a hardware circuit for verification, the cache verification method provided by the embodiment of the present invention only needs to construct the second subroutine according to the functional behavior information, which greatly improves the efficiency of cache verification.

[0105] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] Regarding the cache verification device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated on here.

[0108] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing processor-executable instructions, wherein the processor is configured to execute the above-mentioned cache verification method.

[0109] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the cache verification method of the aforementioned embodiment.

[0110] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0111] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0112] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used does not mean that there is only one bus or one type of bus.

[0113] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly Memory), a CD-ROM (Compact Disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0114] The embodiment of the present invention further provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The cache validation method shown.

[0115] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The cache validation method shown.

[0116] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned cache verification method embodiment and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0117] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0118] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0119] Those skilled in the art will appreciate that embodiments of the present invention can be provided as methods, apparatuses, or computer program products. Therefore, embodiments of the present invention can be implemented in whole or in part via software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially perform the processes or functions described in accordance with the embodiments of the present invention. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device, such as a server or data center, that integrates one or more available media. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0120] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0121] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0123] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0124] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0125] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where they are located, and with the authorization given by the owner of the corresponding device.

[0126] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0127] The above is a detailed introduction to a cache verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for general technical personnel in this field, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A cache verification method, characterized in that: The method comprises: Constructing a first subroutine; the first subroutine is used to generate a data access request; Based on the functional behavior information of the cache to be verified, a second subroutine is constructed; the second subroutine is used to receive the data memory access request and respond to the data memory access request based on the functional behavior information; the functional behavior information is used to characterize the cache coherence protocol implemented by the cache to be verified; the second subroutine is further used to construct a first queue and a second queue, the first queue is used to store the data memory access requests sent by the first subroutine in the order of receipt, and the second queue is used to store partial information of the data memory access request when there is no free position in the first queue; Generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; the reference response result includes response operations sequentially performed by the cache to be verified when the functional behavior information is met; Based on the response result of the second subroutine and the reference response result, the request parameters contained in the reference response result and the execution order of each request are compared with the response result to generate the verification result of the cache to be verified; the response result of the second subroutine includes the data read and write requests issued by the second subroutine based on each data access request.

2. The method according to claim 1, characterized in that The responding to the data access request based on the functional behavior information includes: Determining at least one data acquisition address and at least one data write address based on the functional behavior information and the data memory access request; generating at least one data acquisition request based on the data acquisition address and outputting the data acquisition request; At least one data write request is generated based on the data write address and output.

3. The method according to claim 2, characterized in that The method further comprises: The second subroutine is executed cyclically to obtain a plurality of response results of the second subroutine.

4. The method according to claim 1, wherein The data memory access request includes at least a processor core identifier and a memory access address.

5. The method according to any one of claims 1 to 4, characterized in that The first subroutine and the second subroutine are both constructed based on a high-level programming language.

6. A cache verification device, characterized in that: The device comprises: A first building module is used to build a first subroutine; the first subroutine is used to generate a data access request; A second construction module is configured to construct a second subroutine based on the functional behavior information of the cache to be verified; the second subroutine is configured to receive the data memory access request and respond to the data memory access request based on the functional behavior information; the functional behavior information is used to characterize the cache coherence protocol implemented by the cache to be verified; the second subroutine is further configured to construct a first queue and a second queue, the first queue being configured to store the data memory access requests sent by the first subroutine in a received order, and the second queue being configured to store partial information of the data memory access request when there is no free position in the first queue; A generating module, configured to generate a verification result of the cache to be verified based on a response result of the second subroutine; The generation module includes: A reference submodule, configured to generate a reference response result for each of the data access requests based on the functional behavior information of the cache to be verified; the reference response result includes response operations sequentially performed by the cache to be verified when the functional behavior information is met; A result generation submodule is used to compare the request parameters contained in the reference response result and the execution order of each request with the response result based on the response result of the second subprogram and the reference response result, so as to generate a verification result of the cache to be verified; the response result of the second subprogram includes the data read and write requests issued by the second subprogram based on each of the data access requests.

7. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory for storing computer programs; A processor, configured to implement the method according to any one of claims 1 to 5 when executing a program stored in a memory.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

9. A computer program, characterized in that When the computer program is executed by a computer, the method according to any one of claims 1 to 5 is implemented.

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