Improved process for programming field programmable gate arrays using partial reconfiguration

Abstract

The invention relates to an improved process for programming a field programmable gate array using partial reconfiguration. Programming a field programmable gate array (FPGA) digital electronic integrated circuit (IC) or other IC supporting partial reconfiguration, a particular FPGA having reconfigurable partitions and a primitive variant configurable in each reconfigurable partition, includes: prior to writing a configuration bitstream to the FPGA; compiling and storing a primitive bitstream for different primitive functions that can be implemented on the particular FPGA; receiving an input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to be implemented on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of primitive functions comprising a particular primitive function corresponding to the graphic block; obtaining a subset of the primitive bitstream corresponding to the subset of the primitive functions from a digital storage device; the subset of the primitive bitstream is written to the particular FPGA using a partial reconfiguration operation.

Description

[0001] This application is a divisional application of an application with a filing date of August 20, 2019, application number 201980070251.8, and invention name “Improved Process for Programming a Field Programmable Gate Array Using Partial Reconfiguration”. Technical Field

[0002] One technical area of ​​the present disclosure is the programming of Field Programmable Gate Array (FPGA) integrated circuits (ICs) and other types of programmable ICs. Another technical area is partial reconfiguration (PR) in the field of FPGA programming. Background Art

[0003] The approaches described in this section are approaches that could be performed, but not necessarily approaches that have been previously conceived or performed. Therefore, unless otherwise indicated, any approach described in this section should not be considered prior art merely by virtue of its inclusion in this section.

[0004] A field programmable gate array (FPGA) integrated circuit is a semiconductor device with a matrix of configurable logic blocks (CLBs) that can be configured to produce different complex digital circuits. The CLBs are connected via programmable interconnects that span the area of ​​the FPGA. FPGAs may also include random access memory, digital signal processor (DSP) chips, or other logic elements. The CLBs can be configured to produce logic operations such as AND and XOR, and then coupled in series and / or parallel with other logic elements on the FPGA to produce the specified digital circuit.

[0005] FPGA configuration is described using a hardware description language (HDL) such as Verilog or VHDL. Specialized software is used to compile programs written in HDL to generate a bitstream containing configuration information for a specific target FPGA. VIVADO is an exemplary integrated design environment that can be used to write and compile HDL designs to generate bitstreams for Xilinx FPGAs.

[0006] FPGAs have proven to be powerful for implementing high-speed DSP or highly parallel DSP algorithms. FPGAs are commercially available, for example, from Xilinx, Inc. FPGAs make it possible to create reconfigurable digital electronics. An example is Moku:Lab developed by Liquid Instruments Pty Ltd. However, current techniques for programming FPGAs have several disadvantages.

[0007] Programming FPGAs often requires specialized knowledge that can take a long time to master. Compilation tools are often only available from the manufacturer or supplier of the FPGA and have interfaces that are unique to these chips. Users must spend time installing and learning these tools. Development time can be long, depending on complexity. In addition, the time to compile a completed program (including making design changes or the entire development) can range from a few minutes to a few hours, depending on complexity. Today's developers are faced with relatively simple changes to FPGA programs, and they don't want to wait hours to recompile and deliver the entire bitstream before loading it into the FPGA.

[0008] Based on these problems, there is a need for improved FPGA programming techniques, and there has long been an unmet need for a method that can significantly reduce FPGA program compile time. Summary of the invention

[0009] This application provides the following: 1) A method for improving configuration speed and efficiency of a digital electronic integrated circuit (IC) supporting partial reconfiguration, the IC being a particular IC having a plurality of reconfigurable partitions and a plurality of primitive variants configurable in each of the reconfigurable partitions, the method comprising: Prior to writing the configuration bitstream to the particular IC, using a digital storage device to compile and store a plurality of primitive bitstreams for a plurality of different primitive functions that may be written to and implemented on the particular IC; receiving inputs specifying functional logic of an algorithm implemented on the particular IC using reconfigurable logic; automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic; Retrieving from the digital storage device a subset of the primitive bitstream corresponding to the subset of the primitive functions; writing the subset of the primitive bitstream to the particular IC using one or more partial reconfiguration operations; The method is executed by one or more computing devices.

[0010] 2) According to the method described in 1), the specific IC includes a field programmable gate array (FPGA) having M reconfigurable partitions and N variants in each of the reconfigurable partitions, and the method also includes compiling and storing the multiple primitive bitstreams for multiple different primitive functions that can be written to the FPGA and implemented on all combinations of M and N on the FPGA, thereby storing M*N primitives.

[0011] 3) The method according to 1) further includes: performing said compiling and storing using a server communicatively coupled to a client computer system; transmitting, from the client computer system to the server, a request to provide a subset of the primitive bitstream corresponding to the subset of the primitive functions; A response is transmitted from the server to the client computer, the response comprising the subset of the primitive bitstream corresponding to the subset of the primitive functions.

[0012] 4) The method according to 3), wherein automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic further includes: determining a specific partition and variant for each of the primitive functions, and storing metadata identifying the specific partition and variant, and wherein transmitting the request also includes transmitting the metadata together with the request.

[0013] 5) The method according to 1) is suitable for use with an FPGA, wherein the FPGA includes multiple rows, each row has multiple sequentially connected DSP block partial reconfiguration regions, and multiple interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions can be configured into one of N variants using different bitstream primitives in the primitive bitstream, each of the variants has one or more inputs, one or more outputs and is connected to a configuration AXI bus.

[0014] 6) The method of 5) adapted for use with said FPGA, wherein each of said variants comprises logic for a different purpose and has output multiplexing to select which signals are passed to said two or more outputs.

[0015] 7) The method according to 1), adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnectors to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first set of one or more of said DSP block partial reconfiguration regions are larger PR regions that may be configured as a single channel version of the instrument; The second group of one or more of the DSP block partial reconfiguration regions are suitable for implementing low-level functions.

[0016] 8) According to the method described in 1), adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first group of one or more of said DSP module partial reconfiguration regions are larger PR regions configured for signal generation or controller instrumentation; Wherein a second group of one or more of the DSP block partial reconfiguration regions are configured for use in measurement or monitoring instruments.

[0017] 9) The method according to 1), further comprising receiving input in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to be implemented on the specific IC, the graphical blocks being associated with the reconfigurable logic.

[0018] 10) One or more non-transitory computer-readable storage media storing sequences of instructions, the instructions providing improvements in configuration speed and efficiency of a digital electronic integrated circuit (IC) supporting partial reconfiguration, i.e., a particular IC having a plurality of reconfigurable partitions and a plurality of primitive variants configurable in each of the reconfigurable partitions, and when the instructions are executed using one or more processors, the instructions cause the one or more processors to perform the following operations: Prior to writing the configuration bitstream to the particular IC, using a digital storage device to compile and store a plurality of primitive bitstreams for a plurality of different primitive functions that may be written to and implemented on the particular IC; receiving inputs specifying functional logic of an algorithm implemented on the particular IC using reconfigurable logic; automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic; Retrieving from the digital storage device a subset of the primitive bitstream corresponding to the subset of the primitive functions; writing the subset of the primitive bitstream to the particular IC using one or more partial reconfiguration operations; The method is executed by one or more computing devices.

[0019] 11) According to the computer-readable medium described in 10), the specific IC includes a field programmable gate array (FPGA) having M reconfigurable partitions and N variants in each of the reconfigurable partitions, and the computer-readable medium also includes an instruction sequence that, when executed, compiles and stores the multiple primitive bitstreams for multiple different primitive functions that can be written to the FPGA and implemented on all combinations of M and N on the FPGA, thereby storing M*N primitives.

[0020] 12) The computer-readable medium according to 10) further comprises a sequence of instructions which, when executed, cause: performing said compiling and storing using a server communicatively coupled to a client computer system; transmitting, from the client computer system to the server, a request to provide a subset of the primitive bitstream corresponding to the subset of the primitive functions; A response is transmitted from the server to the client computer, the response comprising the subset of the primitive bitstream corresponding to the subset of the primitive functions.

[0021] 13) A computer-readable medium according to 12), wherein automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic also includes an instruction sequence that, when executed, causes determination of a specific partition and variant for each of the primitive functions, and storage of metadata identifying the specific partition and variant, and wherein transmitting the request also includes transmitting the metadata together with the request.

[0022] 14) The computer-readable medium according to 10) is suitable for use with an FPGA, wherein the FPGA includes a plurality of rows, each row having a plurality of identical DSP block partial reconfiguration regions connected sequentially, and a plurality of interconnectors to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having one or more inputs, one or more outputs and connected to a configuration AXI bus.

[0023] 15) The computer readable medium of 14) adapted for use with the FPGA, wherein each of the variants comprises logic for a different purpose and has output multiplexing to select which signals are passed to the two or more outputs.

[0024] 16) The computer readable medium according to 10), adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first set of one or more of said DSP block partial reconfiguration regions are larger PR regions that may be configured as a single channel version of the instrument; The second group of one or more of the DSP block partial reconfiguration regions are suitable for implementing low-level functions.

[0025] 17) The computer-readable medium according to 10), adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first group of one or more of said DSP module partial reconfiguration regions are larger PR regions configured for signal generation or controller instrumentation; Wherein a second group of one or more of the DSP block partial reconfiguration regions are configured for use in measurement or monitoring instruments.

[0026] 18) The computer-readable medium of 10) further comprising a sequence of instructions which, when executed, cause input to be received in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to be implemented on the specific IC, the graphical blocks being associated with reconfigurable logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the attached picture: Figure 1 An exemplary distributed computer system is shown that can be used to implement the examples.

[0028] Figure 2 An exemplary computing implementation according to an embodiment is shown.

[0029] Figure 3A An exemplary system architecture utilizing a partial reconfiguration FPGA is shown.

[0030] Figure 3BAn example of a complex DSP algorithm is shown that can be designed using the GUI of an IDE to select functional blocks representing signal processing circuitry and to graphically connect these functional blocks.

[0031] Figure 3C Shown in Figure 3A Implementation within the architecture Figure 3B .

[0032] Figure 3D A variation of the aforementioned architecture is shown, in which the low-level PR module is a secondary feature.

[0033] Figure 4 Another architectural variation is shown, where the instruments are divided into two categories: measurement or monitoring instruments, and signal generation or controller instruments.

[0034] Figure 5 is a block diagram illustrating an exemplary computer system that may be used to implement embodiments. DETAILED DESCRIPTION

[0035] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent that the present invention can be practiced without these specific details. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the present invention. The embodiments are described in each section according to the following summary:

[0036] 1. Basic Technology 2. Overall overview of the implementation plan 3. Example of structure and function of implementation scheme 4. Specific Implementation Example - Hardware Overview 1. Basic technology DSP algorithms are often described symbolically using block diagrams. Several commercial systems allow the design of algorithms for digital integrated circuits (ICs), such as FPGAs or other devices, using block diagram graphical user interfaces (GUIs). Simulink and LabVIEW are commercial examples of tools that provide block diagram environments that facilitate the design, verification, and implementation of software-based digital systems for FPGAs and other target platforms. These systems remove some of the complexity of programming the target platform, but still require long compile times and can result in long development times.

[0037] GNUradio is an example of a tool that provides an environment for dragging and dropping functional blocks together and observing their interaction on a host processor connected to GNUradio-compatible hardware. Using this system, designers do not need to generate source code for deployment to an external processing system. However, GNUradio is not suitable for hardware-based, high-bandwidth applications.

[0038] Using partial reconfiguration (PR), the FPGA programming circuit can be divided into multiple regions, which can be compiled separately, generating regional bitstreams as the result. Each regional bitstream can be loaded into the existing FPGA separately, so that the existing regional bitstream is effectively replaced with the new bitstream. Modern FPGAs can support hundreds of separate regions, each of which can be configured independently.

[0039] Partial reconfiguration (PR) is an FPGA configuration technique that allows functional blocks in an active design to be changed dynamically while the rest of the FPGA continues to run. PR can be used to change hardware blocks at different times during the FPGA runtime, allowing large or complex designs to fit on smaller FPGAs. An example is software defined radio, where different modulation and demodulation protocols are swapped at runtime. PR is available, for example, on the Xilinx Zynq family of FPGAs.

[0040] Using PR, the circuit design is divided into reconfigurable logic and non-reconfigurable logic. The term "static logic" is used for all non-reconfigurable logic elements on the FPGA, while the term "reconfigurable logic" refers to reconfigurable logic elements. A reconfigurable module (RM) (or "module") is an HDL description of logic that can be placed within a reconfigurable partition (RP) (or "partition"). Each RP is a physical collection of logic elements on the FPGA that are used exclusively within that partition. A reconfigurable frame (RF) represents the smallest reconfigurable region that can be defined as an RP. Multiple RFs can be included in a single RP and encapsulated in that RP. A partial bitstream is a generated file that contains information about the configuration details and configuration locations of the RM.

[0041] After the design is partitioned into static logic and reconfigurable logic, the reconfigurable logic is partitioned into RP sections and all RMs for each partition are identified. Each bitstream includes configuration data and location data. Therefore, a separate single bitstream is generated for all modules in all RP locations. Therefore, if the same functional module is required in two different RPs, two bitstreams are required. There are other constraints on modules and partitions that are not relevant to this disclosure but may affect the specific implementation of a particular circuit; these constraints are documented in detail in other publications.

[0042] 2.Overview of the implementation plan In one embodiment, a method is disclosed that provides improvements in configuration speed and efficiency of a digital electronic integrated circuit (IC) that supports partial reconfiguration, i.e., a specific IC having multiple reconfigurable partitions and multiple primitive variants that can be configured in each reconfigurable partition, and when the method is performed using one or more processors, the method causes the one or more processors to perform the following operations: before writing the configuration bitstream to the specific IC, using a digital storage device to compile and store multiple primitive bitstreams for multiple different primitive functions that can be written to and implemented on the specific IC; receiving input that is used to specify functional logic of an algorithm implemented on the specific IC using reconfigurable logic; automatically determining a subset of these primitive functions including specific primitive functions corresponding to these functional logics; obtaining a subset of these primitive bitstreams corresponding to the subset of these primitive functions from the digital storage device; and writing the subset of these primitive bitstreams to the specific IC using one or more partial reconfiguration operations; wherein the method is performed by one or more computing devices.

[0043] In another embodiment, a method is disclosed that provides improvements in programming speed and efficiency of a field programmable gate array (FPGA) digital electronic integrated circuit that supports partial reconfiguration, the FPGA digital electronic integrated circuit being a specific FPGA having multiple reconfigurable partitions and multiple primitive variants that can be configured in each reconfigurable partition, the method comprising: using a digital storage device to compile and store multiple primitive bitstreams for multiple different primitive functions that can be written to and implemented on the specific FPGA before writing the configuration bitstream to the specific FPGA; receiving an input that specifies the functional logic of an algorithm that is partially implemented on the specific FPGA using reconfigurable logic; automatically determining a subset of these primitive functions including specific primitive functions corresponding to these graphic blocks; obtaining a subset of these primitive bitstreams corresponding to the subset of these primitive functions from the digital storage device; and writing the subset of these primitive bitstreams to the specific FPGA using one or more partial reconfiguration operations; wherein the method is executed by one or more computing devices.

[0044] The embodiments assume that all block diagrams for FPGA algorithms can be described using N discrete block types connected in a matrix of M block regions. Although a particular embodiment is specifically described for use with an FPGA, the methods of the present disclosure are more generally applicable to other programmable integrated circuits and do not require the use of an FPGA.

[0045] One approach might be to precompile the bitstreams for all possible block diagram connections and then select based on the user's block diagram. This involves storage and compilation of N^M complete bitstreams. The storage and compilation time for this approach becomes prohibitive as M and / or N increase beyond small values. The storage and compilation time increase exponentially or polynomially with the size of M or N. Each partial bitstream is about 100kB in size and takes about 5 minutes to compile, depending on complexity. If M = N = 100, this would require about 5*100^100 minutes of compilation time and 100^98GB of storage space.

[0046] In an embodiment, a partial reconfiguration (PR) technique is employed in which each of the M regions is defined as partially reconfigurable, and for each of the M regions, a single partial bitstream for each of the N block types is compiled in advance. In this context, "ahead of time" means before the end-user computer is used to design the algorithm using a graphical tool or a non-graphical tool; when the design process begins, the user has access to a pre-compiled library of many bitstreams corresponding to the available N block types that can be configured to implement the algorithm. Therefore, only M*N bitstreams need to be compiled and stored. If M = N = 100, only 50,000 minutes of compile time and 1GB of storage space are required. The method relies to some extent on the prediction of specific functions that the user algorithm or application will require, and pre-calculates the bitstreams for these functions.

[0047] In some embodiments, a single partial bitstream for less than all N block types is compiled in advance, and the bitstreams for other block types required for the complete deployment of the algorithm to the target platform are compiled at design time and / or just before deployment. In some embodiments, a subset of less than N block types is selected for precompilation based on the popularity of the block types used by the current user or other users in the past, so that the subset contains the block types that are most likely to be selected in a specific design. For example, the compiling agent 122 can be programmed to detect the user selection of a specific block type in the IDE 120, and the report selected by the user is transmitted to the compiling server process 132, to be stored separately or in combination with the data received from other instances of the compiling agent running on different host computers of unrelated users in a similar manner. In this way, the crowdsourcing report of the actual selection of the block type may affect which block types are precompiled on the server side. Alternatively, user input and / or configuration data can specify which block types are precompiled and which block types are compiled at design or deployment time. The method can allow users to balance the time-saving and efficiency benefits of the library with the stored precompiled bitstream with the computational burden of precompilation. Other embodiments, aspects, and features will become apparent from the entire disclosure and appended claims.

[0048] 3. Example of structure and function of implementation scheme Figure 1 An exemplary distributed computer system that can be used to implement the examples is shown. In the discussion of the figures, the term "primitive" refers to a logical grouping that is compiled into a single partial bitstream for DSP or other applications of FPGA 110.

[0049] In one embodiment, the client computing device 102 is communicatively coupled to the server 106 directly or indirectly via one or more networks 104 .

[0050] The client computing device 102, which will be programmed to implement the user's algorithm, may include a desktop computer, laptop computer, mobile computing device, workstation, or other computing device capable of connecting to the FPGA 110. In one embodiment, the client computing device 102 is also connected to peripheral electronic devices 112, which in various embodiments may include one or more of a processor development board, an analog-to-digital converter, a digital-to-analog converter, a network connection, a power converter, or other devices.

[0051] The client computing device 102 hosts or executes an integrated development environment (IDE) 120, which is an application arranged to support the creation, management, and compilation of FPGA programs 114. In some embodiments, the IDE 120 generates and allows user interaction with a graphical user interface that allows programming of DSP algorithms by connecting graphical blocks, icons, or widgets that represent computational functions.

[0052] In one embodiment, the client computing device 102 is used to host or execute a compile agent 122, which is integrated with the IDE 120 or as a separate program and is programmed or configured to interoperate with a compatible compile server process 132 at the server 106, as further described. In one embodiment, the compile agent 122 is programmed to determine which bitstream primitives to obtain from the server 106 and where to place these bitstream primitives within the FPGA 110. Using these elements, the client computing device 102 can generate or obtain a set of compiled bitstreams 124, which are written to the FPGA 110 to complete the programming of the FPGA. In some embodiments, the IDE 120 and the compile agent 122 are configured or programmed to execute the communication or messaging protocols between the server 106 and the networked data storage device 140, which contain or control the distribution of the compiled bitstream primitives 142, as further described in other sections; run software and firmware to control client tasks; and store the compiled bitstream 124 for the primitives to be programmed in the FPGA 110. Depending on the number of primitives and / or storage requirements, storage of the compiled bitstream 124 may be shared or performed entirely by the server 106 using the storage device 140 .

[0053] FPGA 110 supports PR. In one embodiment, FPGA 110 is a very large unit with multiple regions, each region containing multiple processing elements sufficient to satisfy the most resource-intensive configuration that a programmed algorithm may require. It is expected that a large number of resources will be distributed across many discrete regions. Although one embodiment may be best implemented in a larger FPGA where the user is less concerned about space size, the methods described herein are applicable regardless of the size of the device and do not require a large FPGA or other large platform.

[0054] The network 104 broadly represents any combination of a local area network, a wide area network, an internetwork, or the Internet using any of terrestrial links, satellite links, wired links, or wireless links. The client computing device 102 and the server 106 each host an interface to the network 104 that is compatible with the protocols of the transport, session, and application traffic carried on the network 104. The specific protocol used on the network 104 is not critical if the client computing device 102 and the server 106 can communicate using digital electronic messages and asynchronous, stateless, or stateful protocols to exchange requests, responses, and data payloads.

[0055] In one embodiment, server 106 includes any of a desktop computer, a rack computer, or one or more virtual computing instances in a public or private cloud computing center. Server 106 may include processes that execute on a server computer or cluster with other processes, servers, or applications. Server 106 may be implemented using operating system virtualization such as using DOCKER or KUBERNETES containerization. Server 106 includes or is programmed to access memory 140, which may include a cloud-based digital data storage device or other networked data storage device.

[0056] In one embodiment, the server 106 stores source code 130 for FPGA primitive functions, which are further described in other parts of this document. The server 106 also hosts or executes a compile server process 132, which is configured or programmed to compile the source code 130 into a bitstream primitive, which is stored in a storage device 140 as indicated by a compiled bitstream 142. It is worth noting that in an embodiment, the source code 130 of all function primitives that can be used in the reconfigurable partition of the FPGA 110 can be compiled and stored in the storage device 140 before any programming activity is performed by the client computing device 102, waiting for a request for a bitstream from a client computing device. The compile server process 132 can use programs, libraries, or functions that are previously obtained from the supplier of the FPGA 110 or are otherwise compatible with the FPGA 110.

[0057] The bitstream 142 of primitives may implement any of a number of different substantial signal processing functions. Examples of primitives that may be used in various embodiments include: signal adder; signal multiplier; signal mixer; digital filter; oscillator; integrator; trigonometric operations; fast Fourier transform; PID controller; phase-locked loop; integrator; differentiator; sine wave generator; direct digital synthesizer; direct type I (single-order block) infinite impulse response filter; DC gain.

[0058] exist Figure 1 In the example of , the server 106 is programmed or configured to use the storage device 140 to store the compiled bitstream 142 of the primitives. Depending on the number and / or storage requirements of the primitives, this task may be fully shared by the client computing device 102. In response to a request from the client computing device 102, the compilation server process 132 is also programmed or configured to obtain the compiled bitstream 142 and transmit it to the client computing device 102, as further described.

[0059] An embodiment has been described in which certain operations occur in the client computing device 102, which communicates with the server 106 via the network 104, and in which the storage 140 is managed in association with the server. However, other embodiments may be implemented entirely in a single host computer or virtual computing instance and do not require a client-server architecture. Furthermore, the storage 140 may be located on the host computer, or may be associated with the virtual computing instance, and the digital storage of the pre-compiled bitstream need not be separate from the client computing device 102 or any other computer used to design the algorithm. For example, a single host computer or virtual computing instance (such as the client computing device 102) may host Figure 1 All functional elements and data storage devices are shown as an integrated system. Alternatively, Figure 1 102, but a set of precompiled bitstreams may be delivered from server 106 to client computing device 102 as a package or unit for local storage at the client computing device. In one embodiment, the delivery of the packages of precompiled bitstreams is performed using an installer process that is executed using any combination of client software at the client computing device and / or browser executable code running in a browser of the client computing device.

[0060] Figure 2 An exemplary computer-implemented process according to an embodiment is shown. Figure 2 Involves functional steps performed by the client computing device 102 and the server 106 at different times.

[0061] In one embodiment, the server or server computer precompiles all possible primitive combinations for a specified target platform at block 202. At block 204, the process stores the compiled bitstream primitives on a network storage device.

[0062] For example, the server 106 uses a compilation server process to precompile the source code 130 of the primitive into a compiled bitstream 142, which is stored using the storage device 140. In different embodiments, the number of primitives represented in the source code 130 can vary. For example, a specified FPGA can be defined in the configuration data to support "100" partitions. For each partition, N different variants can be provided to receive precompiled bitstreams. The bitstream set of a specific area is not necessarily interchangeable with the bitstream set of any other area. Therefore, area "01" of the FPGA can support a first bitstream selected from a first specific set of 20 different bitstreams, and area "64" of the same FPGA can support a second bitstream selected from a second different specific set of 20 other bitstreams.

[0063] In one embodiment, management actions or configuration data may specify changes to variants associated with a partition of a target FPGA. For example, if partition "64" is modified to add a phase-locked loop functional block to a variant in the partition, which previously did not have a PLL block associated with it or did not have a PLL block in one of its variants, all bitstreams of partition "64" will need to be recompiled using server 106. However, each functional block associated with a partition may contain several sets of unrelated logic instructions, thereby increasing flexibility. For example, a specific variant of the 20 variants associated with partition "64" may define logic for PLL and for adders. In some embodiments, any two or more sets of logic may be in a functional block associated with a variant of a partition. This arrangement may be constrained by the total computing power available in the FPGA.

[0064] Asynchronously, at block 206, an algorithm or program is defined or programmed at the client computing device using a graphical user interface. For example, a DSP algorithm may be defined. Defining the DSP algorithm may include receiving user input specifying dragging, dropping, and connecting graphical blocks that symbolically define the operation of the DSP algorithm in the GUI interface of the IDE 120.

[0065] In some embodiments, block 206 may include receiving one or more parameter values ​​to change the configuration of a particular functional block. Examples include register-level parameter values ​​or specifying that an input or output be redirected to a specified register or other output location.

[0066] At block 208, the algorithm is segmented or grouped into corresponding primitives using the client computing device 102. Block 208 may involve determining which available RPs and variants of the FPGA 110 will receive which specific pre-compiled primitive bitstreams 142 to cause the algorithm to be implemented on the FPGA.

[0067] Block 208 may also include determining an association of the algorithm's functional blocks (as specified in a GUI using IDE 120) with available primitives that have been precompiled at the server. In some embodiments, block 208 may be performed automatically based on a mapping table, configuration file, or other data that specifies how the functional blocks represented in the GUI correspond to specific primitives and / or bitstreams at the server 106. Alternatively, IDE 120 may provide GUI widgets, either natively or under the control of compile agent 122, that are programmed to accept input to select a functional block in the GUI and specify a specific primitive for implementing the functional block.

[0068] At this point, the client computing device 102 has determined the identifiers of all precompiled bitstreams 142 that are needed to implement the algorithm on the FPGA and that can be exchanged for RPs and RP variants on the FPGA.

[0069] At block 210, the client computing device 102 transmits a request to the server 106 to obtain a bitstream for the specified primitive. One or more requests may be transmitted. The one or more requests collectively specify all precompiled bitstreams 142 required to implement the algorithm on the FPGA and that may be exchanged for RPs and RP variants on the FPGA.

[0070] At block 212, the bitstream primitives corresponding to the regions and groups of DSP algorithms are retrieved from the storage device 140 or other networked storage device at the server 106 and a copy is returned in a response to the client computing device 102 via the network 104. The compiled bitstreams 142 may be stored at the client computing device 102 in the form of the compiled bitstreams 124 after they are received.

[0071] At block 214, the acquired bitstream is deployed to the FPGA. The compile agent 122, in cooperation with the IDE 120, may cause the received compiled bitstream 124 to be written to the specified FP and variant of the FPGA 110. After completion of block 214, the FPGA has been programmed with all reconfigurable logic designed using the GUI of the IDE 120 and implemented using the precompiled bitstream 142 of the primitives associated with the design. These steps are much faster than conventional methods, where the bitstream needs to be compiled at this point before the algorithm can be deployed to the IC.

[0072] Figure 3A An exemplary system architecture for an FPGA utilizing partial reconfiguration is shown. In one embodiment, two inputs "Input 1", "Input 2" are indirectly coupled to two sets of three (3) rows, each row having five (5) sequentially connected DSP block PR regions, denoted "1.1" through "6.5". Multiple interconnects 302 allow arbitrary connections between rows. Interconnects 302 can be implemented in different ways in different embodiments. Examples include large multiplexed networks, high-speed AXI data buses, or as PR regions with variants for different connections.

[0073] Each DSP PR region 1.1 through 6.5 is identical and can be configured as one of N variants, each described using different bitstream primitives in the precompiled bitstream 142. The interface of each variant is identical, including inputs "input 1", "input 2" and outputs "output 1", "output 2" and connections to the configuration AXI bus 304. Each variant contains logic for different purposes, as well as output multiplexing for selecting which signals are passed to each output.

[0074] Although certain embodiments have mentioned using up to 20 variants and about 20 logic function blocks, other embodiments may use other numbers of these elements, and in particular there is no limit to the number of different kinds of logic that may be defined for a particular variant. Examples of possible function blocks that may be used in various embodiments configured in the PR region include: signal adder; signal multiplier; signal mixer; digital filter; oscillator; integrator; trigonometric operations; fast Fourier transform; PID controller; phase-locked loop; integrator; differentiator; sine wave generator; direct digital synthesizer; direct type I (single-order block) infinite impulse response filter; DC gain; zero value. In addition, complex function blocks may cause the bitstream to be divided between two or more variants of the FPGA region.

[0075] Figure 3B An example of a complex DSP algorithm is shown that can be designed using the GUI of an IDE to select functional blocks representing signal processing circuitry and to graphically connect these functional blocks. Figure 3B A block diagram for a frequency modulation control system is included and it will be seen that the signal processing functions may include sine wave generator, demodulation, controller, scanner and IIR. The blocks 310, 312 grouped within the dashed lines are examples of elements that may be grouped into a single bitstream primitive.

[0076] Figure 3C Shown in Figure 3A Implementation within the architecture Figure 3B Example. Figure 3C middle, Figure 3B The function block has been assigned to Figure 3A specific RP or area of ​​the architecture, and in Figure 3C are appropriately labeled to indicate these associations. For example, Figure 3A Region 1.1 is allocated to the sine wave generator logic, region 1.2 is allocated to the demodulator, and so on. Selecting the regions in relation to interconnect 302 and bus 304 enables implementation in a particular chip arrangement. Figure 3B logic.

[0077] Figure 3DA variation of the foregoing architecture is shown in which the low-level PR modules are a secondary feature. In this example, blocks N.1, N.2, NX represent larger PR regions that can be configured as single-channel versions of existing instruments (such as those available on Moku:Lab). With this arrangement, users can create highly complex systems using a single hardware unit. The low-level PR modules 1.1, 1.2, 1.3 to 6.3 remain useful for further customization to meet specific use cases or user requirements. Thus, this architecture shows the possibility of integrating an FPGA with larger PR regions dedicated to complex functions with low-level modules that can be reconfigured using a pre-compiled bitstream 142 to swap out other functions on the chip, without interfering with the use of the larger areas and the main functionality of the chip.

[0078] Figure 4 Another architectural variation is shown where the instruments are divided into two categories: measurement or monitoring instruments, and signal generation or controller instruments. PR regions 402, 404, 406 are specific to signal generation or controller instruments, and PR region 408 is specific to measurement or monitoring instruments. Using this arrangement, the Moku:Lab system can maintain the same functionality with greater flexibility. Furthermore, if two (2) variants are allocated for signal generation or controller instruments, the resources required in the FPGA will not be significantly higher than the Moku:Lab devices available at the time of this writing.

[0079] The embodiments provide many benefits over previous practices. One key benefit is that, from a user's perspective, compile time is completely eliminated. The client computing device 102 can obtain a pre-compiled version of the bitstream for each functional block required to program the FPGA without the long delays involved in local compilation of the FPGA blocks. In addition, all tools required to complete the compilation are pre-installed and managed on the server computer 106 and provided as a service to the client computing device 102. Therefore, the user of the client computing device 102 does not need to install or learn chip-specific or vendor-specific compilation tools.

[0080] 4. Specific Implementation Example - Hardware Overview According to one embodiment, the technology described herein is implemented by at least one computing device. These technologies can be implemented in whole or in part using a combination of at least one server computer and / or other computing devices coupled using a network such as a packet data network. These computing devices may include at least one general-purpose hardware processor that is programmed to execute technology according to program instructions in firmware, memory, other storage devices, or combinations. Such computing devices may also combine customized hardwired logic, ASIC or FPGA with customized programming to implement the technology. These computing devices may be server computers, workstations, personal computers, portable computer systems, handheld devices, mobile computing devices, wearable devices, body-mounted or implantable devices, smart phones, smart appliances, internet interconnected devices, autonomous or semi-autonomous devices (such as robots or unmanned ground or aerial vehicles), any other electronic devices that combine hardwired and / or program logic to implement the technology, one or more virtual computing machines or instances in a data center, and / or a network of server computers and / or personal computers.

[0081] Figure 5 is a block diagram illustrating an exemplary computer system that may be used to implement the embodiments. Figure 5 In the example of FIG. 5 , a computer system 500 and instructions for implementing the disclosed techniques in hardware, software, or a combination of hardware and software are schematically represented as, for example, boxes and circles, using the same level of detail that is commonly used by those of ordinary skill in the art to which the present disclosure relates to communicate about computer architectures and computer system implementations.

[0082] Computer system 500 includes an input / output (I / O) subsystem 502, which may include a bus and / or other communication mechanism for passing information and / or instructions between components of computer system 500 via electronic signal paths. I / O subsystem 502 may include an I / O controller, a memory controller, and at least one I / O port. Electronic signal paths are schematically represented in the figures as, for example, straight lines, unidirectional arrows, or bidirectional arrows.

[0083] At least one hardware processor 504 is coupled to the I / O subsystem 502 for processing information and instructions. The hardware processor 504 may include, for example, a general purpose microprocessor or microcontroller and / or a dedicated microprocessor such as an embedded system or a graphics processing unit (GPU) or a digital signal processor or an ARM processor. The processor 504 may include an integrated arithmetic logic unit (ALU) or may be coupled to a separate ALU.

[0084] The computer system 500 includes one or more units of memory 506, such as a main memory, which is coupled to the I / O subsystem 502 for electronically digitally storing data and instructions to be executed by the processor 504. The memory 506 may include volatile memory, such as various forms of random access memory (RAM) or other dynamic storage devices. The memory 506 may also be used to store temporary variables or other intermediate information during the execution of instructions to be executed by the processor 504. When these instructions are stored in a non-transitory computer-readable storage medium accessible to the processor 504, they can make the computer system 500 a special-purpose machine customized to perform the operations specified in these instructions.

[0085] Computer system 500 also includes non-volatile memory, such as read-only memory (ROM) 508 or other static storage device coupled to I / O subsystem 502, for storing information and instructions for processor 504. ROM 508 may include various forms of programmable ROM (PROM), such as erasable PROM (EPROM) or electrically erasable PROM (EEPROM). Units of permanent storage 510 may include various forms of non-volatile RAM (NVRAM), such as flash memory, or solid-state memory, magnetic disks or optical disks such as CD-ROM or DVD-ROM, and may be coupled to I / O subsystem 502 for storing information and instructions. Memory 510 is an example of a non-transitory computer-readable medium that can be used to store instructions and data that, when executed by processor 504, cause execution of a computer-implemented method to perform the techniques herein.

[0086] The instructions in the memory 506, ROM 508, or storage device 510 may include one or more groups of instructions organized as modules, methods, objects, functions, routines, or calls. These instructions may be organized as one or more computer programs, operating system services, or applications, including mobile applications. These instructions may include operating systems and / or system software; one or more libraries for supporting multimedia, programming, or other functions; data protocol instructions or stacks for implementing TCP / IP, HTTP, or other communication protocols; file format processing instructions for parsing or presenting files encoded using HTML, XML, JPEG, MPEG, or PNG; user interface instructions for presenting or interpreting commands for a graphical user interface (GUI), command line interface, or text user interface; application software, such as office suites, Internet access applications, design and manufacturing applications, graphics applications, audio applications, software engineering applications, educational applications, games, or other applications. These instructions may implement a web server, a web application server, or a web client. These instructions may be organized into a presentation layer, an application layer, and a data storage layer, such as a relational database system, an object repository, a graph database, a flat file system, or other data storage device that uses structured query language (SQL) or does not use SQL.

[0087] The computer system 500 may be coupled to at least one output device 512 via the I / O subsystem 502. In one embodiment, the output device 512 is a digital computer display. Examples of displays that may be used in various embodiments include a touch screen display or a light emitting diode (LED) display or a liquid crystal display (LCD) or an electronic paper display. As an alternative or in addition to the display device, the computer system 500 may include other types of output devices 512. Examples of other output devices 512 include a printer, a ticket printer, a plotter, a projector, a sound card or a graphics card, a speaker, a buzzer or a piezoelectric device or other audible device, a light or an LED or LCD indicator, a tactile device, an actuator, or a servo.

[0088] At least one input device 514 is coupled to the I / O subsystem 502 for communicating signals, data, command selections, or gestures to the processor 504. Examples of input device 514 include a touch screen, a microphone, a still image and video digital camera, alphanumeric and other keys, a keypad, a keyboard, a drawing tablet, an image scanner, a joystick, a clock, a switch, a button, a dial, a slider, and / or various types of sensors (such as force sensors, motion sensors, thermal sensors, accelerometers, gyroscopes, and inertial measurement unit (IMU) sensors) and / or various types of transceivers (such as wireless transceivers, such as cellular or Wi-Fi, radio frequency (RF) or infrared (IR) transceivers, and global positioning system (GPS) transceivers).

[0089] Another type of input device is a control device 516, which can perform cursor control or other automatic control functions, such as navigating in a graphical interface on a display screen, as a substitute or supplement for the input function. The control device 516 can be a touch pad, a mouse, a trackball, or a cursor direction key, which is used to convey direction information and command selection to the processor 504 and to control the cursor movement on the display 512. The input device can have at least two degrees of freedom on two axes (a first axis (e.g., an x-axis) and a second axis (e.g., a y-axis)), which allows the device to specify a position in a plane. Another type of input device is a wired, wireless, or optical control device, such as a joystick, a handle, a console, a steering wheel, a pedal, a gearshift mechanism, or other types of control devices. The input device 514 may include a combination of multiple different input devices such as a video camera and a depth sensor.

[0090] In another embodiment, computer system 500 may include an Internet of Things (IoT) device in which one or more of output device 512, input device 514, and control device 516 are omitted. Alternatively, in such an embodiment, input device 514 may include one or more cameras, motion detectors, thermometers, microphones, earthquake detectors, other sensors or detectors, measurement devices, or encoders, and output device 512 may include a dedicated display such as a single-line LED or LCD display screen, one or more indicators, display panels, meters, valves, solenoids, actuators, or servos.

[0091] When the computer system 500 is a mobile computing device, the input device 514 may include a global positioning system (GPS) receiver coupled to a GPS module capable of triangulating a plurality of GPS satellites to determine and generate a geographic location or location data, such as a latitude-longitude value for the geophysical location of the computer system 500. The output device 512 may include hardware, software, firmware, and interfaces for generating, alone or in combination with other application-specific data, a location reporting packet, a notification, a pulse or heartbeat signal, or other repetitive data transmissions specifying the location of the computer system 500 (directed to the host 524 or the server 530).

[0092] The computer system 500 may implement the techniques described herein using custom hardwired logic, at least one ASIC or FPGA, firmware, and / or program instructions or logic that, when loaded and used or executed in conjunction with a computer system, cause or program the computer system to operate as a special purpose machine. According to one embodiment, the techniques herein are performed by the computer system 500 in response to the processor 504 executing at least one sequence of at least one instruction contained in the main memory 506. Such instructions may be read into the main memory 506 from another storage medium such as a storage device 510. The execution of the sequence of instructions contained in the main memory 506 causes the processor 504 to perform the process steps described herein. In alternative embodiments, hardwired circuits may be used in place of or in conjunction with software instructions.

[0093] As used herein, the term "storage media" refers to any non-transitory medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such storage media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 510. Volatile media include dynamic memory, such as memory 506. Common forms of storage media include, for example, hard disks, solid-state drives, flash drives, magnetic data storage media, any optical or physical data storage media, memory chips, etc.

[0094] Storage media are distinct from, but may be used in conjunction with, transmission media. Transmission media participate in the transmission of information between storage media. For example, transmission media include coaxial cables, copper wires, and optical fibers, including the wires that make up the bus of I / O subsystem 502. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0095] When at least one sequence of at least one instruction is transmitted to the processor 504 for execution, various forms of media may be involved. For example, the instructions may initially be carried on a disk or solid-state drive of a remote computer. The remote computer may load the instructions into its dynamic memory and send the instructions over a communication link (such as an optical fiber or coaxial cable or a telephone line) using a modem. A modem or router local to the computer system 500 may receive data over the communication link and convert the data into a format that can be read by the computer system 500. For example, a receiver such as a radio frequency antenna or an infrared detector may receive data carried in a wireless or optical signal, and appropriate circuitry may provide the data to the I / O subsystem 502, such as placing the data on a bus, and the I / O subsystem 502 transmits the data to the memory 506 via the bus, from which the processor 504 retrieves and executes the instructions. The instructions received by the memory 506 may optionally be stored on the storage device 510 before or after being executed by the processor 504.

[0096] The computer system 500 also includes a communication interface 518 coupled to the bus 502. The communication interface 518 provides a two-way data communication coupled to a network link 520, which is directly or indirectly connected to at least one communication network, such as a network 522 or a public or private cloud on the Internet. For example, the communication interface 518 can be an Ethernet networking interface, an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem for providing a data communication connection to a corresponding type of communication line (such as an Ethernet cable or any kind of metal cable or fiber optic line or telephone line). The network 522 broadly represents a local area network (LAN), a wide area network (WAN), a campus network, an internet network, or any combination thereof. The communication interface 518 may include a LAN card for providing a data communication connection to a compatible LAN, or a cellular radiotelephone interface connected to send or receive cellular data according to a cellular radiotelephone wireless network standard, or a satellite radio interface connected to send or receive digital data according to a satellite wireless network standard. In any such specific implementation, the communication interface 518 sends and receives electrical signals, electromagnetic signals, or optical signals on a signal path carrying a digital data stream representing various types of information.

[0097] Network link 520 typically provides electrical, electromagnetic or optical data communication to other data devices directly or through at least one network using, for example, satellite, cellular, Wi-Fi or Bluetooth technology. For example, network link 520 may provide a connection to a host computer 524 through a network 522 .

[0098] In addition, network link 520 may provide a connection through network 522, or provide a connection to other computing devices via internet equipment and / or computers operated by Internet Service Provider (ISP) 526. ISP 526 provides data communication services through a global packet data communication network represented as Internet 528. Server computer 530 may be coupled to Internet 528. Server 530 broadly represents any computer, data center, virtual machine or virtual computing instance with or without a hypervisor, or a computer executing a containerized program system such as DOCKER or Kubernetes. Server 530 may represent an electronic digital service that is implemented using more than one computer or instance and can be used by transmitting a web service request, a uniform resource locator (URL) containing parameters in an HTTP payload, an API call, an application service call, or other service call. Computer system 500 and server 530 may form an element of a distributed computing system that includes other computers, processing clusters, server farms, or other computer organizations that collaborate to perform tasks or execute applications or services. Server 530 may include one or more groups of instructions organized as modules, methods, objects, functions, routines, or calls. The instructions may be organized as one or more computer programs, operating system services, or applications, including mobile applications. The instructions may include operating systems and / or system software; one or more libraries for supporting multimedia, programming, or other functions; data protocol instructions or stacks for implementing TCP / IP, HTTP, or other communication protocols; file format processing instructions for parsing or presenting files encoded using HTML, XML, JPEG, MPEG, or PNG; user interface instructions for presenting or interpreting commands for a graphical user interface (GUI), command line interface, or text user interface; application software, such as office suites, Internet access applications, design and manufacturing applications, graphics applications, audio applications, software engineering applications, educational applications, games, or other applications. The server 530 may include a web application server that hosts a presentation layer, an application layer, and a data storage layer, such as a relational database system using structured query language (SQL) or not, an object repository, a graph database, a flat file system, or other data storage device.

[0099] Computer system 500 may send messages and receive data and instructions, including program code, through the network, network link 520, and communication interface 518. In the Internet example, server 530 may send code requesting an application through Internet 528, ISP 526, local network 522, and communication interface 518. The received code may be executed by processor 504 as it is received, and / or stored in storage device 510 or other non-volatile storage for later execution.

[0100] As described in this section, the execution of instructions may implement a process in the form of an instance of a computer program that is being executed and consists of program code and its current activity. Depending on the operating system (OS), a process may consist of multiple threads of execution that execute instructions simultaneously. In this context, a computer program is a passive collection of instructions, while a process may be the actual execution of these instructions. Multiple processes may be associated with the same program; for example, enabling multiple instances of the same program generally means that more than one process is executing. Multitasking may be implemented to allow multiple processes to share the processor 504. When each processor 504 or core of a processor executes a single task at a time, the computer system 500 may be programmed to implement multitasking to allow each processor to switch between executing tasks without having to wait for each task to complete. In one embodiment, switching may be performed when a task performs an input / output operation, when a task indicates that it can be switched, or when a hardware interrupt occurs. Time sharing may be implemented to provide the appearance of concurrent execution of multiple processes simultaneously by rapidly performing context switching, thereby allowing for rapid response of interactive user applications. In one embodiment, for security and reliability, the operating system may prevent direct communication between independent processes, thereby providing a strictly affected and controlled inter-process communication function.

[0101] In the foregoing specification, embodiments of the present invention have been described with reference to many specific details, which may vary from implementation to implementation. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive. The sole and exclusive indication of the scope of the present invention, and what the applicant intends to be the scope of the present invention, is the literal and equivalent range of the claims published in this application, in the specific form in which such claims are published, including any subsequent amendments.

Claims

1. A method for providing improved configuration speed and efficiency of a digital electronic integrated circuit (IC) supporting partial reconfiguration, the IC being a particular IC having a plurality of reconfigurable partitions and a plurality of primitive variants configurable in each of the reconfigurable partitions, the method comprising: Prior to writing the configuration bitstream to the particular IC, using a digital storage device to compile and store a plurality of primitive bitstreams for a plurality of different primitive functions that may be written to and implemented on the particular IC; receiving inputs specifying functional logic of an algorithm implemented on the particular IC using reconfigurable logic; automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic; Retrieving from the digital storage device a subset of the primitive bitstream corresponding to the subset of the primitive functions; writing the subset of the primitive bitstream to the particular IC using one or more partial reconfiguration operations; The method is executed by one or more computing devices.

2. The method of claim 1 , wherein the particular IC comprises a field programmable gate array (FPGA) having M reconfigurable partitions and N variants in each of the reconfigurable partitions, the method further comprising compiling and storing the plurality of primitive bitstreams for the plurality of different primitive functions that can be written to the FPGA and implemented on all combinations of M and N on the FPGA, thereby storing M*N primitives.

3. The method according to claim 1, further comprising: performing said compiling and storing using a server communicatively coupled to a client computer system; transmitting, from the client computer system to the server, a request to provide a subset of the primitive bitstream corresponding to the subset of the primitive functions; A response is transmitted from the server to the client computer, the response comprising the subset of the primitive bitstream corresponding to the subset of the primitive functions.

4. The method of claim 3, wherein automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic further comprises: A specific partition and variant for each of the primitive functions is determined, and metadata identifying the specific partition and variant is stored, and wherein transmitting the request further comprises transmitting the metadata with the request.

5. The method of claim 1 , adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having one or more inputs, one or more outputs and connected to a configuration AXI bus.

6. The method of claim 5, adapted for use with the FPGA, wherein each of the variants includes logic for a different purpose and has output multiplexing to select which signals are passed to the two or more outputs.

7. The method of claim 1 adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first set of one or more of said DSP block partial reconfiguration regions are larger PR regions that may be configured as a single channel version of the instrument; The second group of one or more of the DSP block partial reconfiguration regions are suitable for implementing low-level functions.

8. The method according to claim 1, adapted for use with an FPGA, the FPGA comprising a plurality of rows, each row having a plurality of sequentially connected DSP block partial reconfiguration regions, a plurality of interconnects to allow arbitrary connections between rows, each of the DSP block partial reconfiguration regions being configurable into one of N variants using a different bitstream primitive in the primitive bitstream, each of the variants having two or more inputs, two or more outputs and connected to a configuration AXI bus; wherein a first group of one or more of said DSP module partial reconfiguration regions are larger PR regions configured for signal generation or controller instrumentation; Wherein a second group of one or more of the DSP block partial reconfiguration regions are configured for use in measurement or monitoring instruments.

9. The method of claim 1, further comprising receiving input in a graphical user interface to select and connect graphical blocks representing functional logic of an algorithm to be implemented on the particular IC, the graphical blocks being associated with the reconfigurable logic.

10. One or more non-transitory computer-readable storage media storing sequences of instructions, the instructions providing improvements in configuration speed and efficiency of a digital electronic integrated circuit (IC) supporting partial reconfiguration, i.e., a particular IC having a plurality of reconfigurable partitions and a plurality of primitive variants configurable in each of the reconfigurable partitions, and when executed using one or more processors, the instructions causing the one or more processors to perform the following operations: Prior to writing the configuration bitstream to the particular IC, using a digital storage device to compile and store a plurality of primitive bitstreams for a plurality of different primitive functions that may be written to and implemented on the particular IC; receiving inputs specifying functional logic of an algorithm implemented on the particular IC using reconfigurable logic; automatically determining a subset of the primitive functions including specific primitive functions corresponding to the functional logic; Retrieving from the digital storage device a subset of the primitive bitstream corresponding to the subset of the primitive functions; writing the subset of the primitive bitstream to the particular IC using one or more partial reconfiguration operations; The method is executed by one or more computing devices.

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