Bus verification method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a bus verification method, device, electronic device and readable storage medium. The method includes: obtaining a sub-file to be verified of the bus to be verified; parsing the characters contained in the sub-file to be verified to convert the sub-file to be verified into a recognizable file recognizable by a target verification tool; inputting the recognizable file into the target verification tool to obtain the verification result of the bus to be verified. In this way, by parsing the sub-file to be verified of the bus to be verified into a recognizable file recognizable by the target verification tool, the bus to be verified can be verified by the target verification tool, so that through automated parsing modeling and verification, an automated bus verification process can be realized, reducing manual intervention and improving verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a bus verification method, device, electronic equipment and readable storage medium. Background Art

[0002] With the development of computer technology, the system structure of integrated chips is becoming more and more complex, including multiple components such as processor clusters, graphics processors, memory controllers, I / O bridges, PCIe subsystems, etc. In order to achieve shared memory access and cache consistency for each component, an on-chip interconnect bus is usually used. Therefore, the performance of the integrated chip is closely related to the bus.

[0003] In order to ensure the performance of the integrated chip, the bus used by the chip needs to be verified. Therefore, how to verify the on-chip interconnect bus has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a bus verification method, device, electronic device and readable storage medium to solve the problem of how to verify the bus. The specific technical solution is as follows:

[0005] In a first aspect of the present invention, a bus verification method is first provided, the method comprising:

[0006] Obtain the sub-file to be verified of the bus to be verified;

[0007] Based on a preset mapping rule, mapping the characters contained in the sub-file to be verified into binary elements;

[0008] generating an abstract syntax tree based on the binary element, and generating a recognizable file recognizable by a target verification tool based on the abstract syntax tree;

[0009] The identifiable file is input into the target verification tool to obtain the verification result of the bus to be verified.

[0010] In a second aspect of the present invention, a bus verification device is provided, the device comprising:

[0011] A first acquisition module is used to acquire a sub-file to be verified of a bus to be verified;

[0012] A mapping module, used for mapping the characters contained in the sub-file to be verified into binary elements based on a preset mapping rule;

[0013] A generating module, configured to generate an abstract syntax tree based on the binary element, and generate a recognizable file recognizable by a target verification tool based on the abstract syntax tree;

[0014] An input module is used to input the identifiable file into the target verification tool to obtain the verification result of the bus to be verified.

[0015] In a third aspect of the present invention, there is also provided an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0016] Memory, used to store computer programs;

[0017] The processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0018] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect above.

[0019] In a fifth aspect of the implementation of the present invention, there is also provided a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0020] The bus verification method provided by the embodiment of the present invention obtains the sub-file to be verified of the bus to be verified; parses the characters contained in the sub-file to be verified to convert the sub-file to be verified into a recognizable file recognizable by a target verification tool; and inputs the recognizable file into the target verification tool to obtain the verification result of the bus to be verified. In this way, by parsing the sub-file to be verified of the bus to be verified into a recognizable file recognizable by the target verification tool, the bus to be verified can be verified by the target verification tool, thereby realizing an automated bus verification process through automated parsing modeling and verification, reducing manual intervention, and improving verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0022] Figure 1 A flowchart of a bus verification method according to an embodiment of the present invention;

[0023] Figure 2 A schematic diagram of a bus verification method according to an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of the structure of a bus verification device in an embodiment of the present invention;

[0025] Figure 4 Schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0028] Figure 1 FIG. 1 is a flowchart of a bus verification method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0029] Step 101: Obtain the sub-file to be verified of the bus to be verified.

[0030] Step 102: Map the characters contained in the sub-file to be verified into binary elements based on a preset mapping rule.

[0031] Step 103: Generate an abstract syntax tree based on the binary element, and generate a recognizable file recognizable by a target verification tool based on the abstract syntax tree.

[0032] Step 104: input the identifiable file into the target verification tool to obtain the verification result of the bus to be verified.

[0033] For the above steps 101 to 104, the bus to be verified in the embodiment of the present invention can be a bus with verification requirements, and can be a coherent hub interface (CHI). The CHI protocol is a protocol for building high-performance, low-power multi-processor systems. It provides an efficient and low-latency method to connect multiple processors, accelerators, memory and other system components to achieve shared memory access and cache consistency. The above-mentioned bus to be verified can also be a bus such as MSI, MOESI, etc., which can be set according to the verification requirements, and the embodiment of the present invention does not limit this.

[0034] It should be noted that, since the bus is often more complex and contains multiple aspects of protocol content, some integrated chips often only need to adopt part of the protocol content, so there is no need to verify the entire content of the bus. On this basis, the embodiment of the present invention can obtain the sub-file to be verified of the bus to be verified based on the actual scenario and verification requirements. Among them, the above-mentioned sub-file to be verified refers to a subset corresponding to some functions that need to be verified in the bus to be verified. In one case, for a high-performance computing system including multiple processor cores, a graphics processor, a memory controller and an I / O bridge, they are interconnected through a CHI bus. In this system, cache consistency is the key to ensuring data consistency and system performance. The above-mentioned sub-file to be verified can be a subset of the CHI bus used to achieve cache consistency (CC-Gen architecture model), so that the embodiment of the present invention can verify the cache consistency of the CHI bus.

[0035] Specifically, the bus to be verified can be determined by receiving input information from relevant personnel, and the sub-file to be verified of the bus to be verified can be obtained. Among them, the above-mentioned sub-file to be verified can be expressed in a specific domain language. In the case where the sub-file to be verified is a cache consistency subset, the above-mentioned sub-file to be verified can be expressed in a cache consistency specific domain language, such as: the native language for implementing cache coherence (ProtoGen Language for Implementing Cache Coherence, PCC) or the specification language for implementing cache coherence (Specification Language for Implementing Cache Coherence, SLICC). The above-mentioned sub-file to be verified can be understood as a requirement model of the bus to be verified. Verifying the requirement model can verify the cache consistency function of the bus to be verified. Specifically, expressing the sub-file to be verified in the form of a specific domain language can ensure that the sub-file to be verified is verifiable and universal.

[0036] Among them, the above-mentioned target verification tool refers to an automated verification tool, which can be an integrated tool environment (Uppaal) for verifying real-time systems, or a Murϕ tool, which can be selected according to actual needs, and the embodiment of the present invention does not limit this. Specifically, the automated testing tool can quickly generate and execute test cases, which can greatly save time and reduce errors caused by human factors to a certain extent. At the same time, the target verification tool can realize the automation of the verification process. The automation of the verification process involves the control and execution of the verification process, including the scheduling, execution, result collection and report output of test cases. By automating the generation and execution of test cases and integrating continuous integration tools, the efficiency and accuracy of testing can be greatly improved.

[0037] Specifically, since different verification tools may have different file formats that can be recognized, on this basis, the embodiment of the present invention can convert the sub-file to be verified into a recognizable file that can be recognized by the target verification tool, so that the recognizable file can be input into the target verification tool for verification, and the verification result of the bus to be verified can be obtained. Exemplarily, when the above-mentioned target verification tool is the Uppaal tool, the above-mentioned recognizable file can be in the Extensible Markup Language (XML) format, so as to facilitate the target verification tool to verify the bus to be verified.

[0038] Specifically, the source code in the sub-file to be verified is composed of a large number of characters. The embodiment of the present invention can parse the characters contained in the sub-file to be verified, and convert the sub-file to be verified into a recognizable file based on the parsed character meanings. Specifically, the embodiment of the present invention can pre-build a mapping relationship based on the format of the sub-file to be verified and the format recognizable by the target verification tool, and then map the characters contained in the sub-file to be verified to a format recognizable by the target verification tool. Optionally, the embodiment of the present invention can pre-build a lexical analyzer (Lexer) and a parser (Parser) to parse the sub-file to be verified.

[0039] Among them, the above-mentioned preset mapping rules can be pre-set based on the format of the sub-file to be verified. Specifically, characters can be read one by one from the sub-file to be verified to form a character stream. At the same time, various binary elements (Tokens) in the character stream, such as keywords, identifiers, constants, operators, etc., can be identified by defining a series of rules such as regular expressions. After the recognition and classification tags are completed, a Token stream (binary file) will be generated. This Token stream is an abstract representation of the source code.

[0040] Optionally, the embodiment of the present invention may predefine binary elements that need to be identified, for example:

[0041] Keywords: such as if, else, return, etc. These are words predefined in programming languages ​​and have special meanings.

[0042] Identifiers: such as variable names and function names, usually composed of letters, numbers, and underscores.

[0043] Constants: such as numeric constants, string constants, etc.

[0044] Operators: such as "+", "-", "*", " / ", etc.

[0045] Separators: such as comma “,”, semicolon “;”, brackets “()”, etc.

[0046] Network: txreq\rxreq\txrsp\rxrsp\txdat\rxdat, etc. Channel: such as req, rsp, snp, dat, etc.

[0047] Optionally, if an unmatched character sequence is encountered during recognition, an error can be reported, such as a syntax error or illegal character.

[0048] The above-mentioned Abstract Syntax Tree (AST) is an abstract representation of the syntax structure of the source code, which is a tree structure, in which each node represents a syntax structure in the source code, such as an expression, statement, declaration, etc. Furthermore, the embodiment of the present invention can generate an abstract syntax tree based on binary elements to facilitate subsequent further parsing.

[0049] In summary, the bus verification method provided by the embodiment of the present invention obtains the sub-file to be verified of the bus to be verified; parses the characters contained in the sub-file to be verified to convert the sub-file to be verified into a recognizable file recognizable by the target verification tool; and inputs the recognizable file into the target verification tool to obtain the verification result of the bus to be verified. In this way, by parsing the sub-file to be verified of the bus to be verified into a recognizable file recognizable by the target verification tool, the bus to be verified can be verified by the target verification tool, thereby realizing an automated bus verification process through automated parsing modeling and verification, reducing manual intervention, and improving verification efficiency.

[0050] Optionally, the operation of generating a recognizable file recognizable by a target verification tool based on the abstract syntax tree may specifically include:

[0051] S21. Convert the abstract syntax tree into an executable code file according to node information of each node included in the abstract syntax tree.

[0052] S24. Based on the executable code file, generate a recognizable file that can be recognized by a target verification tool.

[0053] Specifically, the abstract syntax tree includes multiple nodes, and each node represents a syntax structure in the source code. On this basis, the embodiment of the present invention can convert the abstract syntax tree into an executable code file (.m file) according to the node information of each node of the abstract syntax tree.

[0054] Furthermore, the embodiment of the present invention can generate a recognizable file recognizable by a target verification tool based on the executable code file.

[0055] In an embodiment of the present invention, based on a preset mapping rule, the characters contained in the sub-file to be verified are mapped to binary elements. An abstract syntax tree is generated based on the binary elements. According to the node information of each node contained in the abstract syntax tree, the abstract syntax tree is converted into an executable code file. Based on the executable code file, a recognizable file recognizable by a target verification tool is generated. In this way, the sub-file to be verified can be converted into a recognizable file, ensuring the accuracy and verifiability of the recognizable file.

[0056] Optionally, the operation of generating a recognizable file recognizable by a target verification tool based on the executable code file may specifically include:

[0057] S31. Obtain a constraint file containing the attribute to be verified.

[0058] S32: Generate a recognizable file recognizable by a target verification tool based on the constraint file and the executable code file.

[0059] Among them, the above-mentioned attributes to be verified refer to the constraint rules that need to be verified, which can be set according to the cache strategy implemented by the bus to be verified, such as: deadlock freedom, cache consistency or fairness, etc., which can be obtained based on the input information of relevant personnel, or can be pre-written, and can be set according to actual verification requirements. The embodiment of the present invention does not limit this.

[0060] Specifically, the constraint file may be written in a specific language such as CC-Gen or UPPAAL, in which variables such as cache status and message type may be defined, and cache policy logic such as state transition rules and conditions for message sending and receiving may also be expressed. Furthermore, the constraint file may also include verification purposes, such as whether the system can always reach a consistent state.

[0061] Furthermore, the constraint file and the executable code file can be integrated, and both can be converted into XML files and input into a pre-written integrator. The integrator can be an integration code pre-written in a high-level programming language (e.g., crawler, python), which is used to convert the XML file into a formal model that CC-Gen can understand and process, and obtain a recognizable file, including all states, transitions, synchronization mechanisms and attributes to be verified.

[0062] Thus, in the embodiment of the present invention, by obtaining the constraint file containing the attributes to be verified, a recognizable file recognizable by the target verification tool is generated based on the constraint file and the executable code file. Thus, constraint rules can be added to the recognizable file according to the actual constraint file, thereby improving the flexibility of bus verification, abstracting the complex system behavior model, removing unnecessary details, and highlighting the key verification points.

[0063] Optionally, the operation of generating an abstract syntax tree based on the binary element in the embodiment of the present invention may specifically include:

[0064] S41. Create a root node.

[0065] S42: Create a corresponding tree node according to each of the binary elements.

[0066] S43: Generate an abstract syntax tree based on the root node and each of the tree nodes.

[0067] The root node is the parent node of the abstract syntax tree, which is the parent node of all other nodes. The embodiment of the present invention can first create the root node as the basis of the abstract syntax tree. Specifically, the root node and the tree node can be created through a node creation function.

[0068] Furthermore, the embodiment of the present invention can construct a parser, and the Parser receives the Token stream generated by the Lexer. These Tokens are keywords, identifiers, constants, operators, etc. in the source code.

[0069] Parser uses recursive descent parsing or similar algorithms to process token streams. Each function corresponds to a non-terminal symbol in the grammar rule. Parser identifies the grammar rule by matching the token and creates the corresponding AST node (tree node). Build the AST recursively. Each grammatical structure is added to the tree to form a hierarchical relationship. For example: a function declaration may have an identifier (function name) and a parameter list, which are added as child nodes under the function declaration node.

[0070] Specifically, the embodiment of the present invention can determine the basic elements of AST, such as cache lines, processors, channels, directories, etc., based on the above-mentioned sub-files to be verified. And describe the operations and states of these elements, such as reading, writing, and invalidation of cache lines. Build rules: define the interaction rules between elements, and describe how write operations affect the cache states of other processors through state machine descriptions. Generate AST: Use Parser to convert these rules and operations into AST, where each node in the AST represents a specific operation or state in the model.

[0071] Thus, in the embodiment of the present invention, by creating a root node, a corresponding tree node is created according to each of the binary elements, and an abstract syntax tree is generated based on the root node and each of the tree nodes. Through the above operations, a consistency structure AST for expressing the sub-file to be verified can be generated, thereby improving scalability.

[0072] Optionally, the operation of converting the abstract syntax tree into an executable code file according to the node information of each node included in the abstract syntax tree may specifically include:

[0073] S51. Acquire a concurrency structure, a synchronization structure, and a communication structure in the abstract syntax tree according to node information of each node included in the abstract syntax tree.

[0074] S52: Map the concurrent structure, the synchronous structure and the communication structure into executable structures respectively.

[0075] S52: Generate an executable code file based on the executable structure.

[0076] Specifically, the abstract syntax tree (AST) can be traversed, and each node in the AST can be visited in a specific order (such as pre-order, in-order, and post-order). This process can obtain a structured representation of the source code, and can extract key information to provide a basis for subsequent processing. Traverse the abstract syntax tree AST to extract the key information of each relation or expression statement in the PCC statement, match the corresponding template to each relation or expression statement according to the content of the key information, generate a concurrent transient, and save it as a .m file to obtain an executable code file. Among them, the above-mentioned template can be information pre-entered by relevant personnel, which may include static protocol jump information, so as to facilitate setting the corresponding concurrent transient for each relation or expression statement based on the static protocol jump information.

[0077] When traversing the AST, visit each node and check the node's type and attributes. Execute specific processing logic based on the node type, such as extracting variable names, function calls, control flow statements, etc. Recursively traverse the node's child nodes and extract key information, which can include variable declarations, function definitions, control flow statements, expressions, etc.

[0078] Specifically, the concurrent structure in AST can be mapped to the process template of the target verification tool UPPAAL. The synchronization and communication operations can be mapped to the channel and synchronization mechanism of the target verification tool UPPAAL, and system parameters and variables such as cache status, message type, etc. can be defined. The specific language and grammar rules of UPPAAL-CCGen can be further used to describe the behavior and properties of the model.

[0079] In an embodiment of the present invention, the concurrency structure, synchronization structure and communication structure in the abstract syntax tree are obtained according to the node information of each node contained in the abstract syntax tree. The concurrency structure, synchronization structure and communication structure are respectively mapped to executable structures. An executable code file is generated based on the executable structure. In this way, an accurate executable code file can be obtained, which is convenient for subsequent conversion into a recognizable file of a target verification tool.

[0080] Optionally, the embodiment of the present invention may specifically include:

[0081] S61. Traverse the abstract syntax tree to obtain the node type of each node.

[0082] S62: For any node, obtain node information of the node based on the node type of the node.

[0083] Specifically, when traversing the AST, the node type is identified and the corresponding information is extracted according to the type. For each node, its child nodes are checked and information is recursively extracted, such as variable declarations, function definitions, control flow statements, expressions, etc. When traversing the AST, concurrent computing model (ProtoGen Language for Implementing Cache Coherence, PCC) statements that describe concurrent behaviors, such as concurrent regions, synchronization operations, etc., can be identified and extracted.

[0084] Specifically, the embodiment of the present invention can use Depth-First-Search (DFS) to traverse the AST and visit each node. For each node, check whether it represents a concurrent structure or a synchronous operation. Extract key attributes of the node, such as the operation type, the variables and channels involved, etc.

[0085] In this way, the node information of each node can be obtained through the nodes of AST to avoid omissions and ensure the integrity of information acquisition.

[0086] Optionally, the bus to be verified is a CHI bus; and the target verification tool is UPPAAL.

[0087] Alternatively, verification tools such as model checkers can also be used as target verification tools, but UPPAAL has certain advantages in real-time system verification.

[0088] Furthermore, UPPAAL can be used to formally verify the generated recognizable files to ensure that the cache consistency requirements of the CHI bus are met. The verification results output by UPPAAL can be obtained, and the verification results include a verification report on the cache consistency requirements of the CHI bus, including indicators such as the correctness and functional completeness of the consistency protocol.

[0089] Figure 2 FIG. 1 is a flow chart of a bus verification method in an embodiment of the present invention. Figure 2 As shown, the converter is used to convert the abstract syntax tree into an executable code file (.m file), and the converter may include a protocol layer, a network layer, and a link layer. The editor is used to identify the statement information in the AST. The specification generator refers to a code model for building a property constraint file, and the executable code file generated by the converter can be integrated with the property constraint file to obtain a recognizable XML file. The XML file can be input into UPPAAL, and UPPAAL can parse and verify the XML file through the included model solver and formal verification engine, and output a verification report.

[0090] By using domain-specific languages ​​and UPPAAL, the application of formal methods is enhanced, and the consistency of the CHI bus is ensured through formal model and UPPAAL verification. By building a complete automated verification process, the systematization of verification is improved. Through formal verification methods, potential design errors and consistency issues can be discovered during the system design phase, thereby improving the reliability of the system. The automated verification process reduces the need for manual testing, thereby reducing development costs and human resource consumption.

[0091] Alternatively, some related technologies use manual testing or other formal methods to verify the bus. Manual testing increases verification coverage by increasing the number of testers and test cases, but this increases cost and time. Other formal methods: such as using proof assistants (Coq or Isabelle, etc.) to verify system properties, but these methods usually require higher expertise and longer development time. If simulation is used, advanced simulation tools are used to simulate the behavior of the CHI bus, but this may not fully capture all concurrent and real-time behaviors.

[0092] Optionally, as the scale of the system grows, the complexity of the model will also increase, and more efficient algorithms and tools may be needed to process large-scale models. As the complexity of the model increases, maintaining the readability and maintainability of the model becomes a challenge, and more advanced modeling tools and methods may need to be developed. The embodiment of the present invention can further utilize parallel computing technology to accelerate the verification process of the model by adopting target verification tools such as UPPAAL. It is also possible to use machine learning methods to assist in the construction and verification of the model with the assistance of artificial intelligence, thereby improving the level of automation. This makes it easier to handle larger-scale systems and improve the readability and maintainability of the model.

[0093] The method of the present invention supports the scalability of the CHI bus, so that when the system scale is expanded, an efficient verification process can still be maintained. The establishment of a formalized model facilitates the subsequent maintenance and upgrade of the system, making the modification and optimization of the system easier and more accurate. Due to the improvement of verification efficiency, system verification can be completed faster, shortening the cycle from design to market of the product.

[0094] Figure 3 FIG. 1 is a schematic diagram of the structure of a bus verification device in an embodiment of the present invention. Figure 3 As shown, the device 20 may include:

[0095] The first acquisition module 201 is used to acquire the sub-file to be verified of the bus to be verified;

[0096] A mapping module 202, configured to map the characters contained in the sub-file to be verified into binary elements based on a preset mapping rule;

[0097] A generating module 203, configured to generate an abstract syntax tree based on the binary element, and generate a recognizable file recognizable by a target verification tool based on the abstract syntax tree;

[0098] The input module 204 is used to input the identifiable file into the target verification tool to obtain the verification result of the bus to be verified.

[0099] Optionally, the generating module 203 includes:

[0100] A conversion submodule, configured to convert the abstract syntax tree into an executable code file according to the node information of each node included in the abstract syntax tree;

[0101] The first generating submodule is used to generate a recognizable file recognizable by a target verification tool based on the executable code file.

[0102] Optionally, the first generating submodule is specifically used to:

[0103] Get the constraint file containing the attributes to be verified;

[0104] Based on the constraint file and the executable code file, a recognizable file recognizable by a target verification tool is generated.

[0105] Optionally, the generating module further includes:

[0106] The first creation submodule is used to create a root node;

[0107] A second creation submodule, used for creating a corresponding tree node according to each of the binary elements;

[0108] The tree generation submodule is used to generate an abstract syntax tree based on the root node and each of the tree nodes.

[0109] Optionally, the conversion submodule is specifically used to:

[0110] Acquire a concurrent structure, a synchronization structure, and a communication structure in the abstract syntax tree according to node information of each node included in the abstract syntax tree;

[0111] Based on the template of the target verification tool, mapping the concurrency structure, synchronization structure and communication structure into executable structures respectively;

[0112] An executable code file is generated based on the executable structure.

[0113] Optionally, the device further comprises:

[0114] A traversal module, used for traversing the abstract syntax tree to obtain a node type of each node;

[0115] The acquisition module is used to acquire the node information of any node based on the node type of the node.

[0116] Optionally, the bus to be verified is a CHI bus; and the target verification tool is UPPAAL.

[0117] In summary, the bus verification device provided by the embodiment of the present invention obtains the sub-file to be verified of the bus to be verified; parses the characters contained in the sub-file to be verified to convert the sub-file to be verified into a recognizable file recognizable by the target verification tool; and inputs the recognizable file into the target verification tool to obtain the verification result of the bus to be verified. In this way, by parsing the sub-file to be verified of the bus to be verified into a recognizable file recognizable by the target verification tool, the bus to be verified can be verified by the target verification tool, thereby realizing an automated bus verification process through automated parsing modeling and verification, reducing manual intervention, and improving verification efficiency.

[0118] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0119] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0120] Regarding the bus verification device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0121] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to execute the above bus verification method.

[0122] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the bus verification method of the aforementioned embodiment.

[0123] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0124] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmble Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0125] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0126] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0127] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The bus verification method shown.

[0128] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The bus verification method shown.

[0129] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned bus verification method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0130] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0131] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0132] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0133] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0134] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0135] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0136] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0137] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0138] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0139] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0140] The bus verification method, device, electronic device and readable storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A bus verification method, characterized in that: The method comprises: Obtain a subfile to be verified of a bus to be verified; the bus to be verified is a CHI bus; Based on a preset mapping rule, mapping the characters contained in the sub-file to be verified into binary elements; Generate an abstract syntax tree based on the binary element, and obtain a concurrency structure, a synchronization structure, and a communication structure in the abstract syntax tree according to node information of each node included in the abstract syntax tree; Mapping the concurrency structure, synchronization structure and communication structure into executable structures respectively; generating an executable code file based on the executable structure; Obtaining a constraint file containing attributes to be verified; the attributes to be verified are set based on a cache policy of the bus to be verified; Based on the constraint file and the executable code file, generating a recognizable file recognizable by a target verification tool; The identifiable file is input into the target verification tool to obtain the verification result of the bus to be verified.

2. The method according to claim 1, characterized in that: The generating an abstract syntax tree based on the binary element comprises: Create a root node; Creating a corresponding tree node according to each of the binary elements; An abstract syntax tree is generated based on the root node and each of the tree nodes.

3. The method according to claim 1, characterized in that The method further comprises: Traversing the abstract syntax tree to obtain the node type of each node; For any node, node information of the node is obtained based on the node type of the node.

4. The method according to any one of claims 1 to 3, characterized in that: The target verification tool is UPPAAL.

5. A bus verification device, characterized in that: The device comprises: A first acquisition module is used to acquire a subfile to be verified of a bus to be verified; the bus to be verified is a CHI bus; A mapping module, used for mapping the characters contained in the sub-file to be verified into binary elements based on a preset mapping rule; A generating module, configured to generate an abstract syntax tree based on the binary element, and generate a recognizable file recognizable by a target verification tool based on the abstract syntax tree; An input module, used for inputting the identifiable file into the target verification tool to obtain the verification result of the bus to be verified; The generating module comprises: A conversion submodule, configured to convert the abstract syntax tree into an executable code file according to the node information of each node included in the abstract syntax tree; A first generating submodule, configured to generate a recognizable file recognizable by a target verification tool based on the executable code file; The first generating submodule is specifically used for: Get the constraint file containing the attributes to be verified; Based on the constraint file and the executable code file, generating a recognizable file recognizable by a target verification tool; The conversion submodule is specifically used for: Acquire a concurrent structure, a synchronization structure, and a communication structure in the abstract syntax tree according to node information of each node included in the abstract syntax tree; Based on the template of the target verification tool, mapping the concurrency structure, synchronization structure and communication structure into executable structures respectively; An executable code file is generated based on the executable structure.

6. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-4 when executing a program stored in a memory.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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