Circuits and chips that support parallel physical links of cores through PIPE interfaces

Abstract

The present invention discloses a circuit and chip that supports a core-grain parallel physical link through a PIPE interface, including a data processing module located between the PIPE interface and a parallel PHY group, including a data packaging module and a data parsing module, wherein the data packaging module is used to generate a receiving direction data signal on the PIPE interface from the data on the PIPE interface and transmit it to the parallel PHY group after compression and packaging; the data parsing module is used to parse the data from the parallel PHY group, restore the compressed data, and then transmit the data to the upper layer through the PIPE interface to send it to the core-grain interconnection controller on the PIPE interface. The present invention aims to solve the problem of how a core-grain interconnection interface compatible with a PIPE interface at the physical layer can be driven through the PIPE interface and use multiple parallel physical interfaces for data transmission, and drive through the PIPE interface and use multiple parallel physical interfaces for data transmission.

Description

Technical Field

[0001] The present invention relates to the field of high-speed interconnection interfaces between chiplets, and in particular to a circuit and a chip supporting a chiplet parallel physical link (P-PHY) through a PIPE (PHY Interface for PCI Express) interface. Background Art

[0002] Chip technology is an important way to continuously improve chip integration and chip computing power in the current era when the integration of System on Chip (SoC) is developing and Moore's Law is gradually slowing down. The PIPE (Physical Interface for PCI Express, PIPE) specification is an interface specification proposed by Intel. The PIPE interface defines a unified interface between the media access layer (MAC) and the physical coding sub-layer (PCS) in the physical layer, aiming to provide a unified industry standard. The PIPE interface diagram is shown below. Figure 1 As shown in the figure, MAC and PCS belong to the logical sub-layer of the physical layer in PCIe, while the physical media attachment layer (PMA) belongs to the electrical sub-layer of the physical layer.

[0003] Since the industry usually uses high-speed serial physical link modules (SerDes) to implement PCS and PMA in PCIe, MAC, data link layer and transaction layer above MAC and PCS / PMA are often designed relatively independently, or even designed by different manufacturers. Providing a unified industry standard - PIPE between MAC and PCS helps to make devices from different manufacturers more compatible. With the development of high-speed serial technology, the physical layers of various serial communication technologies have gradually become unified, and users can even complete the design of multiple high-speed serial communication interfaces based on SerDes / PCS in FPGA. The differences between these communication interfaces are often only reflected in the high-level protocols (data link layer and transaction layer, etc.), and are basically consistent in the physical layer, especially the electrical sublayer of the physical layer. Although the PIPE specification was first used for the serial physical interface circuit (S-PHY) of the PCIe bus, subsequent versions of the specification have gradually begun to support other protocols. Take the PIPE Spec (version 5.1) released by Intel as an example. This version involves multiple protocols such as PCI Express, SATA, USB, DisplayPort and Converged IO communicating through high-speed serial interface circuits.

[0004] High-speed data transmission generally uses serial data link protocols, such as PCIe, Gen-Z, Omni-Path, and NVLink. However, due to the overhead of the serialization / deserialization process and data load transmission, the serial link has greater latency and power consumption than the parallel bus at the same bandwidth. The parallel physical layer interface has the characteristics of low power consumption, low latency, and high bandwidth, and is more suitable for interconnection between chiplets. At present, the circuits of parallel PHY in the chiplet interconnection standards at home and abroad are mainly customized, which has the following two problems: (1) Different standards stipulate their own parallel PHY specifications, and there is no unified standard between the logical sublayer and the physical sublayer. On the one hand, it is not conducive to the reuse of the logical sublayer circuit in the physical layer, and on the other hand, it hinders the development of different types of PHY; (2) There is no consideration of how to efficiently support parallel PHY on the basis of compatibility with traditional serial PHY. The logical sublayers of parallel PHY and serial PHY are developed separately, and although they have the same logic, they cannot be reused, which reduces the reusability of the logical sublayer and increases the cost of developing the physical layer of the chiplet interface. In fact, the chip interconnect interface has requirements for both serial PHY and parallel PHY based on the indicators of transmission distance, bandwidth density, and reliability. It is urgently needed that the chip interconnect interface can adapt to different types of PHY to improve the reusability of the chip adapter and protocol layer and create a richer chip interconnect ecosystem. Summary of the invention

[0005] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a circuit and chip that support core-grain parallel physical links through a PIPE interface are provided. The present invention aims to solve the problem of how a core-grain interconnection interface that is compatible with the PIPE interface at the physical layer can be driven through the PIPE interface and use multiple parallel physical interfaces for data transmission. It drives through the PIPE interface and uses multiple parallel physical interfaces for data transmission.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A circuit supporting a core-grain parallel physical link through a PIPE interface comprises a data processing module located between the PIPE interface and a parallel PHY group, wherein the data processing module comprises a data packaging module and a data parsing module, wherein the data packaging module is used to generate a receiving direction data signal on the PIPE interface from data from a core-grain interconnection controller on the PIPE interface and transmit the data to the parallel PHY group directly or through a first-in-first-out queue FIFO after compressing and packaging the data; and the data parsing module is used to parse the data from the parallel PHY group, restore the compressed data, and then transmit the data to an upper layer through the PIPE interface to send the data to the core-grain interconnection controller on the PIPE interface.

[0008] Optionally, the data interface of the input direction on the PIPE interface includes the start of the sending direction block txstartblock, the sending electrical idle txelecidle, the sending data control character indication txdatak, the sending data valid txdatavalid, the specified receiving module type txsyncheader and the sending data txdata, and the receiving direction data signal includes the start of the receiving direction block rxstartblock, the receiving electrical idle rxelecidle, the receiving data control character indication rxdatak, the receiving data valid rxdatavalid, the specified receiving module type rxsyncheader, the receiving valid rxvalid and the receiving data rxdata; the data packaging module generates the data from the chip interconnection controller on the PIPE interface The receiving direction data signals on the PIPE interface include: using the transmit data txdata directly as the receive data rxdata, the transmit data control character indication txdatak directly as the receive data control character indication rxdatak in the receive direction, the transmit data valid txdatavalid directly as the receive data valid rxdatavalid in the receive direction, the transmit direction block start txstartblock directly as the receive direction block start rxstartblock, the specified receive module type txsyncheader directly as the specified receive module type rxsyncheader in the receive direction, and using the signal generating circuit to generate the receive electrical idle rxelecidle and receive valid rxvalid in the receive direction according to the transmit electrical idle txelecidle.

[0009] Optionally, the signal generating circuit is used to generate two bits of receiving electrical idle rxelecidle and receiving valid rxvalid in the receiving direction according to two bits of the transmitting electrical idle txelecidle, including: for the two bits of transmitting electrical idle txelecidle[1:0], the low bit txelecidle[0] of the transmitting electrical idle txelecidle is input into the buffer IBUF for buffering and then separated into two outputs, one of which is buffered by an output buffer OBUF to obtain the low bit rxelecidle[0] of the receiving electrical idle rxelecidle, and the other output is obtained by looking up a logic function table LUT1 to obtain a predefined logic function table output result as the low bit rxvalid[0] of the receiving valid rxvalid; the high bit txelecidle[1] of the transmitting electrical idle txelecidle is input into the buffer IBUF for buffering and then separated into two outputs, one of which is buffered by an output buffer OBUF to obtain the high bit rxelecidle of the receiving electrical idle rxelecidle. [1], and the other output uses a logic function table LUT2 to look up the predefined logic function table output result as the high bit rxvalid [1] of the receive valid rxvalid, thereby obtaining the two bits of transmit electrical idle txelecidle[1:0] corresponding to the two bits of receive electrical idle rxelecidle[1:0] and the receive valid rxvalid[1:0].

[0010] Optionally, the compression of the data packaging module includes compressing the receiving direction block start rxstartblock from the original 16 bits to 1 bit, compressing the designated receiving module type rxsyncheader from the original 32 bits to 2 bits, and compressing the receiving data control indicator rxdatak from the original 64 bits to 4 bits.

[0011] Optionally, the packing of the data packing module includes packing the compressed receiving direction data signal into a data packet with a width of 576 bits, and the 576-bit data packet includes in sequence: 512 bits of receiving data rxdata, a receiving direction block start rxstartblock compressed to 1 bit, a specified receiving module type rxsyncheader compressed to 2 bits, a receiving data control symbol indication rxdatak compressed to 4 bits, a 16-bit receiving electrical idle rxelecidle, a 16-bit receiving valid rxvalid, a 16-bit receiving data valid rxdatavalid and an end marker 9'b0, and the end marker 9'b0 is composed of 9 bits of 0.

[0012] Optionally, it also includes a clock divider, the input end of the clock divider is connected to the physical clock signal phy_clk of the parallel PHY group, and the divided clock signal clk_div output by the output end of the clock divider is respectively connected to the data packaging module, the data parsing module and the core grain interconnection controller of the PIPE interface.

[0013] Optionally, the parallel PHY group is composed of three parallel PHYs, and each clock cycle of the parallel PHY group can provide a 288-bit data transmission channel, and the data packaging module uses the divided clock signal clk_div generated by the clock divider to perform data transmission in batches.

[0014] Optionally, a ratio between the divided clock signal clk_div and the physical clock signal phy_clk is less than 588:phy_datanum, where phy_datanum is a data channel width provided by the parallel PHY group.

[0015] Optionally, the data processing module uses a state machine to manage the connection between the core grain interconnect controller and the parallel PHY group. The state machine includes four stages: waiting, configuring PHY, configuring the core grain interconnect controller and normal operation. The state machine first enters the PHY configuration stage after reset. In the PHY configuration stage, the data processing module performs initialization training and configuration on the parallel PHY group used. During the PHY initialization training and configuration process, the core grain interconnect interface, the data processing module and the clock divider will all remain in a reset state and wait for the parallel PHY group training configuration to be completed. When the parallel PHY group training configuration is completed, the reset state of the core grain interconnect interface, the data processing module and the clock divider will be terminated and the core grain interconnect interface, the data processing module and the clock divider will be configured. In the chip interconnect controller configuration stage, the chip interconnect controller is initialized, and the simulated PHY interacts with the upper chip interconnect controller through the control status signal phystatus on the PIPE interface to complete the initialization training of the upper chip interconnect controller. After the initialization training of the chip interconnect controller is completed, the normal working stage is entered; in the normal working stage, the data processing module executes data interaction between the chip interconnect controller and the parallel PHY group, and detects the situation where the parallel PHY group exits the normal working state. If it is detected that the parallel PHY group exits the normal working state, the normal working stage is exited and the waiting state is entered; in the waiting state, it waits for reset. If it is reset, it enters the configuration PHY stage.

[0016] In addition, the present invention also provides a chip, including core particles and physical links between core particles, wherein the physical links include the circuit supporting the parallel physical links of core particles through the PIPE interface.

[0017] Compared with the prior art, the present invention mainly has the following advantages: 1. High compatibility. The present invention does not need to modify the PIPE interface. The core-grain interconnect interface compatible with the PIPE interface can be directly driven by the circuit design and use the parallel physical interface for data transmission without modifying the original logic. 2. Support for diversified PHY. The present invention can realize the decoupling of the logical sublayer and the physical sublayer in the physical layer of the core-grain interface with the circuit. As long as the physical sublayer interface circuit supports the PIPE interface, it can be adapted and supported by this method, thereby improving the support for diversified PHY in the core-grain interconnect ecosystem. 3. High reusability and economy. On the basis of supporting the original serial physical interface circuit S-PHY, the present invention further supports the parallel physical interface circuit P-PHY that complies with the PIPE standard. In particular, when P-PHY becomes the mainstream in the core-grain interconnect interface, the method and circuit can adapt to different types of PHY and be reused as a standard module, thereby reducing the development cost of the core-grain interconnect interface protocol layer and adapter layer. 4. It is conducive to the formulation and implementation of core-grain interconnect specifications. The existing various chiplet standards and specifications have customized constraints on the physical interface circuit (PHY), limiting the specifications and parameters of PHY. The present invention further expands the scope of the PIPE interface, making it a more universal standard that supports different types of PHY, and is expected to promote the PIPE interface standard to become a more suitable standard between the logical sublayer and the physical in the chiplet interconnection interface standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a PIPE interface in the prior art.

[0019] Figure 2 Schematic diagram of the external connection structure of the circuit in the embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the internal structure of a circuit in an embodiment of the present invention.

[0021] Figure 4 FIG. 4 is another schematic diagram of the internal structure of the circuit in an embodiment of the present invention.

[0022] Figure 5 The figure is a schematic diagram of an implementation of a signal generating circuit in an embodiment of the present invention.

[0023] Figure 6 Schematic diagram of data packing rules after compression in an embodiment of the present invention.

[0024] Figure 7 Schematic diagram of the overall implementation principle of the circuit in the embodiment of the present invention.

[0025] Figure 8 Schematic diagram of state switching of a state machine in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] like Figure 2 As shown, this embodiment provides a circuit that supports chip parallel physical links through a PIPE interface, including a data processing module located between the PIPE interface and the parallel PHY group. The chip interconnection controller of the media layer (MAC) is connected to the circuit that supports the chip parallel physical link through the PIPE interface in this embodiment through the PIPE interface, and the circuit that supports the chip parallel physical link through the PIPE interface is connected to the parallel PHY (physical interface circuit) group through a data path, so that the decoupling of the logical sublayer and the physical sublayer in the chip interface physical layer can be achieved with the circuit. As long as it is a physical sublayer interface circuit that supports the PIPE interface, it can be adapted and supported by this method, thereby improving the support for diversified PHY in the chip interconnection ecosystem.

[0028] like Figure 3 As shown, the data processing module of this embodiment includes a data packaging module and a data parsing module. The data packaging module is used to generate a receiving direction data signal on the PIPE interface from the data of the core-grain interconnection controller on the PIPE interface and directly transmit it to the parallel PHY group after compressing and packaging; the data parsing module is used to parse the data from the parallel PHY group, restore the compressed data, and then transmit the data to the upper layer through the PIPE interface to send it to the core-grain interconnection controller on the PIPE interface.

[0029] See also Figure 3In this embodiment, the data interface of the input direction on the PIPE interface includes the start of the transmission direction block txstartblock, the transmission electrical idle txelecidle, the transmission data control symbol indication txdatak, the transmission data valid txdatavalid, the specified receiving module type txsyncheader and the transmission data txdata, and the receiving direction data signal includes the start of the receiving direction block rxstartblock, the receiving electrical idle rxelecidle, the receiving data control symbol indication rxdatak, the reception data valid rxdatavalid, the specified receiving module type rxsyncheader, the reception valid rxvalid and the reception data rxdata, as shown in Table 1. The 512-bit transmission data txdata is Figure 3 It is represented as txdata[511:0], which means the lowest bit index is 0 and the highest bit index is 511. The other data interfaces are represented in the same way and are not listed here one by one.

[0030] Table 1: Main data signals and meanings of PIPE interface

[0031]

[0032] In Table 1, In indicates the sending direction, and Out indicates the receiving direction.

[0033] In this embodiment, the data packaging module generates a receiving direction data signal on the PIPE interface using the data from the chip interconnect controller on the PIPE interface, including: using the sending data txdata directly as the receiving data rxdata, the sending data control symbol indication txdatak directly as the receiving data control symbol indication rxdatak in the receiving direction, the sending data valid txdatavalid directly as the receiving data valid rxdatavalid in the receiving direction, the sending direction block start txstartblock directly as the receiving direction block start rxstartblock, the designated receiving module type txsyncheader directly as the designated receiving module type rxsyncheader in the receiving direction, and using the signal generating circuit to generate the receiving electrical idle rxelecidle and receiving valid rxvalid in the receiving direction according to the sending electrical idle txelecidle.

[0034] Figure 5 The circuit implementation of the txelecidle[0] and txelecidle[1] signals generating the rxelecidle[0], rxelecidle[1] and rxvalid[0], rxvalid[1] signals is shown. The circuits for generating the remaining bits of the rxelecidle and rxvalid signals are the same. Figure 5 As shown, the signal generating circuit in this embodiment is used to generate two bits of receiving electrical idle rxelecidle and receiving valid rxvalid in the receiving direction according to two bits of transmitting electrical idle txelecidle, including: for the two bits of transmitting electrical idle txelecidle[1:0], the low bit txelecidle[0] of the transmitting electrical idle txelecidle is input into the buffer IBUF for buffering and then separated into two outputs, one of which is buffered by an output buffer OBUF to obtain the low bit rxelecidle [0] of the receiving electrical idle rxelecidle, and the other output is obtained by looking up a predefined logic function table output result using a logic function table LUT1 as the low bit rxvalid of the receiving valid rxvalid. [0]; the high bit txelecidle[1] of the transmit electrical idle txelecidle is input into the buffer IBUF for buffering and then separated into two outputs, one of which is buffered by an output buffer OBUF to obtain the high bit rxelecidle[1] of the receive electrical idle rxelecidle, and the other output is looked up by a logic function table LUT2 to obtain a predefined logic function table output result as the high bit rxvalid[1] of the receive valid rxvalid, thereby obtaining the two bits of transmit electrical idle txelecidle[1:0] corresponding to the two bits of receive electrical idle rxelecidle[1:0] and the receive valid rxvalid[1:0]. Figure 5 In the figure, IBUF (Input Buffer) and OBUF (Output Buffer) are input buffer and output buffer respectively, which can ensure the stability of input and output signals and make them reliable in the circuit. In the figure, LUT (Look-Up Table) is a logic function table, which receives input signals and outputs results according to the pre-defined logic function table. LUT can implement any logic function, such as AND, OR, NOT, XOR, etc. Figure 5 The logic function implemented by the LUT in the implementation circuit is a non-logic function. The pseudo code of the algorithm for generating the receiving electrical idle rxelecidle in the receiving direction according to the sending electrical idle txelecidle using the signal generation circuit can be expressed as:

[0035] for(var_i=0;var_i <NL;var_i=var_i+1){

[0036] rxelecidle[var_i] =(&txelecidle [var_i])

[0037] }

[0038] Among them, for is a loop execution operation, var_i is a loop variable, NL is the bit width of the transmit electrical idle txelecidle (specifically 16 in this embodiment), rxelecidle[var_i] is the var_ith bit of the transmit electrical idle txelecidle, txelecidle [var_i] is the var_ith bit of the transmit electrical idle txelecidle, & is a bitwise AND operator, &txelecidle[var_i] means performing a bitwise AND operation on the var_ith element in the transmit electrical idle txelecidle. The algorithm pseudo code for generating the receive valid rxvalid in the receive direction according to the transmit electrical idle txelecidle using the signal generation circuit can be expressed as:

[0039] for(var_j=0;var_j <NL;var_j=var_j+1) {

[0040] rxvalid[var_j] = ~(|txelecidle [var_j]);

[0041] }

[0042] Among them, var_j is the loop variable, rxvalid[var_j] is the var_jth bit of the received valid rxvalid, txelecidle [var_j] is the var_jth bit of the transmitted electrical idle txelecidle; ~(|txelecidle [var_j]) means first performing a bitwise OR operation on txelecidle[var_j], and then inverting each bit of the result.

[0043] As shown in Table 1, the receiving direction block start rxstartblock, the designated receiving module type rxsyncheader, and the receiving data control symbol rxdatak are all data-related signals. For example, the receiving direction block start rxstartblock signal width is 16 bits, and each bit indicates that 64 bits of received data rxdata are valid. In normal use, the 16-bit values ​​of the receiving direction block start rxstartblock are the same, so this signal can be compressed to improve transmission efficiency. The 32-bit values ​​of the designated receiving module type rxsyncheader are the same every 2 bits, so they can be compressed. The 64-bit values ​​of the receiving data control symbol rxdatak are the same every 4 bits and can be compressed. Therefore, the compression of the data packaging module in this embodiment includes compressing the receiving direction block start rxstartblock from the original 16 bits to 1 bit, compressing the designated receiving module type rxsyncheader from the original 32 bits to 2 bits, and compressing the receiving data control symbol rxdatak from the original 64 bits to 4 bits.

[0044] like Figure 6 As shown, the packaging of the data packaging module in this embodiment includes packaging the compressed receiving direction data signal into a data packet tx_pkg[575:0] with a width of 576 bits, and the 576-bit data packet tx_pkg[575:0] includes: 512 bits of receiving data rxdata (rxdata[511:0]), a receiving direction block start rxstartblock (rxstartblock [0:0]) compressed into 1 bit, a designated receiving module type rxsyncheader (rxsyncheader [1:0]) compressed into 2 bits, a receiving data control symbol indication rxdatak (rxdatak [3:0]) compressed into 4 bits, a 16-bit receiving electrical idle rxelecidle (rxelecidle [15:0]), a 16-bit receiving valid rxvalid (rxvalid [15:0]), and a 16-bit receiving data valid rxdatavalid (rxdatavalid [15:0]) and the end marker 9'b0, which consists of 9 bits of 0.

[0045] like Figure 3As shown, the circuit in this embodiment also includes a clock divider, the input end of the clock divider is connected to the physical clock signal phy_clk of the parallel PHY group, and the divided clock signal clk_div output by the output end of the clock divider is respectively connected to the data packaging module, the data analysis module and the core grain interconnection controller of the PIPE interface. The clock divider is an optional module used to solve the bandwidth mismatch problem between the upper layer data transmission module and the parallel PHY group. When the data channel provided by the parallel PHY group is less than 576 bits, it is used to divide the phy_clk generated by the parallel PHY group for use by the data packaging module, the data analysis module and the upper layer core grain interconnection protocol controller.

[0046] like Figure 3 As shown, the parallel PHY group in this embodiment is composed of three parallel PHYs (parallel PHY1 to parallel PHY3). The parallel PHY group can provide a 288-bit data transmission channel per clock cycle. The data packaging module uses the divided clock signal clk_div generated by the clock divider to transmit data in beats. For example, a data packet sent in a beat is a 288-bit transmission data packet tx_pkg[287:0], tx_pkg_valid is a valid signal for the transmission data packet, or a data packet received in a beat is a 288-bit reception data packet rx_pkg[287:0], rx_pkg_valid is a valid signal for the reception data packet; phy1_txdata_valid is the transmission validity of parallel PHY1, phy1_txdata[127:0] is the 128-bit transmission data of parallel PHY1, phy1_rxdata_valid is the reception validity of parallel PHY1, phy1_rxdata[127:0] is the 128-bit reception data of parallel PHY1; phy2 _txdata_valid is the transmission valid of parallel PHY2, phy2_txdata[127:0] is the 128-bit transmission data of parallel PHY2, phy2_rxdata_valid is the reception valid of parallel PHY2, phy2_rxdata[127:0] is the 128-bit reception data of parallel PHY2; phy3_txdata_valid is the transmission valid of parallel PHY3, phy3_txdata[31:0] is the 32-bit transmission data of parallel PHY2, phy3_rxdata_valid is the reception valid of parallel PHY3, phy3_rxdata[31:0] is the 32-bit reception data of parallel PHY2.

[0047] Figure 3Each bit of the phy_ready signal indicates whether the corresponding PHY in the parallel PHY group is ready to send data. If the parallel PHY is not ready to send data, the upper layer should stop sending data. Since the parallel PHY group may periodically initiate the stop of upper layer data transmission, if the upper layer has no data to send, the stop mechanism needs to be implemented as follows: Figure 4 As another optional implementation, Figure 4 As shown, the data packaging module generates a receiving direction data signal on the PIPE interface from the data of the core particle interconnection controller on the PIPE interface, compresses and packages it, and transmits it to the parallel PHY group directly or through the first-in-first-out queue FIFO; similarly, the data parsing module also obtains data from the parallel PHY group through the first-in-first-out queue FIFO. Figure 4 In the example, fifo_txdata[287:0] is the transmit data output by the FIFO, and fifo_txdata_valid is the valid signal of the transmit data packet output by the FIFO. fifo_rxdata[287:0] is the receive data output by the FIFO, and fifo_rxdata _valid is the valid signal of the receive data packet output by the FIFO. The meaning of the remaining data is the same as Figure 3 Consistent.

[0048] In this embodiment, the ratio between the divided clock signal clk_div and the physical clock signal phy_clk is less than 588:phy_datanum, where phy_datanum is the data channel width provided by the parallel PHY group. Figure 3 The data channel provided by the parallel phy group used in is 288 bits, which is less than 576 bits. Therefore, a clock divider is added to divide phy_clk by 2 to generate the clk_div clock signal for use by the upper layer. Figure 3 and Figure 4 The main difference between the circuit implemented in is that a FIFO module is added between the data processing module and the parallel PHY group to process when the parallel PHY is not ready to send data and store the data from the upper layer and wait for the PHY to be ready before sending. The depth of the FIFO depends on the frequency of the parallel PHY used to initiate the stop of data transmission, and when the implementation Figure 4The circuit shown in the figure needs to have a ratio between clk_div and phy_clk generated by the clock divider that is less than 588:phy_datanum. The data parsing module uses the clk_div clock signal generated by the clock divider to receive data. After receiving data from the parallel PHY, it will parse the data according to the data parsing rules and perform the reverse restore operation on the compressed data according to the packing rules. The redundant 9'b0 will be discarded. After the data parsing and restoration, the data will be transmitted to the upper controller through the PIPE interface.

[0049] like Figure 7 As shown, the design of the circuit supporting the chip parallel physical link through the PIPE interface in this embodiment includes a state machine that interacts with the parallel physical interface and the chip interconnect interface. The state machine is responsible for interacting with the parallel PHY group and the chip interconnect interface. The data processing module uses a state machine to manage the connection between the chip interconnect controller and the parallel PHY group. The state machine includes four stages: waiting, configuring PHY, configuring the chip interconnect controller, and normal operation.

[0050] like Figure 8 As shown, the state machine first enters the configuration PHY stage after reset;

[0051] In the PHY configuration stage, the data processing module performs initialization training and configuration on the parallel PHY group used. During the PHY initialization training and configuration process, the chip interconnect interface, the data processing module and the clock divider will remain in a reset state and wait for the parallel PHY group training and configuration to be completed. When the parallel PHY group training and configuration is completed, the reset state of the chip interconnect interface, the data processing module and the clock divider is terminated and the chip interconnect controller configuration stage is entered;

[0052] In the stage of configuring the chip interconnect controller, the initialization of the chip interconnect controller begins, and the simulated PHY interacts with the upper-layer chip interconnect controller through the control status signal phystatus on the PIPE interface to complete the initialization training of the upper-layer chip interconnect controller. After the initialization training of the chip interconnect controller is completed, it enters the normal working stage; in this state, the parallel PHY group has completed the training and can start to send and receive data. Therefore, if the upper-layer chip interconnect interface controller needs to send and receive training data, the parallel PHY group can realize data transmission such as training sequence;

[0053] In the normal working stage, the data processing module executes data interaction between the chip interconnect controller and the parallel PHY group, and detects the situation where the parallel PHY group exits the normal working state. If it is detected that the parallel PHY group exits the normal working state, the data processing module exits the normal working stage and enters the waiting state.

[0054] Wait for reset in waiting state, if reset, enter the PHY configuration stage.

[0055] Since the chip interconnect interface controller that originally supports the PIPE interface should interact with the PHY through the phystatus control signal on the PIPE interface, when the circuit of this embodiment is used to implement the use of the parallel PHY through the PIPE interface, the original chip interconnect interface no longer supports interaction with the PHY, so the low power consumption and other states related to the PHY cannot be converted. The implementation method of this state machine can be compatible with the parallel PHY without changing the logic of the original chip interconnect interface, and this state machine is simple and easy to implement.

[0056] In addition, this embodiment further provides a chip, including a core particle and a physical link between core particles, wherein the physical link includes the circuit supporting the core particle parallel physical link through the PIPE interface.

[0057] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A circuit for supporting parallel physical links of core particles through a PIPE interface, characterized in that: The invention comprises a data processing module located between a PIPE interface and a parallel PHY group, wherein the data processing module comprises a data packaging module and a data parsing module, wherein the data packaging module is used to generate a receiving direction data signal on the PIPE interface from data of a core grain interconnection controller on the PIPE interface, and transmit the data to the parallel PHY group directly or through a first-in-first-out queue FIFO after compression and packaging; the data parsing module is used to parse the data from the parallel PHY group, and transmit the compressed data to an upper layer through the PIPE interface after restoring the data to send the data to the core grain interconnection controller on the PIPE interface; the data interface of the input direction on the PIPE interface comprises a sending direction block start txstartblock, a sending electrical idle txelecidle, a sending data control character indication txdatak, a sending data valid txdatavalid, a designated receiving module type txsyncheader and a sending data txdata, and the receiving direction data signal comprises a receiving direction block start rxstartblock, a receiving electrical idle rxelecidle, a receiving data control character indication rxdatak, a receiving data valid rxdatavalid, a designated receiving module type rxsyncheader, a receiving valid rxvalid and a receiving data rxdata; The data packaging module generates the receiving direction data signal on the PIPE interface with the data from the chip interconnection controller on the PIPE interface, including: using the sending data txdata directly as the receiving data rxdata, the sending data control symbol indication txdatak directly as the receiving data control symbol indication rxdatak in the receiving direction, the sending data valid txdatavalid directly as the receiving data valid rxdatavalid in the receiving direction, the sending direction block start txstartblock directly as the receiving direction block start rxstartblock, the designated receiving module type txsyncheader directly as the designated receiving module type rxsyncheader in the receiving direction, and using the signal generating circuit to generate the receiving electrical idle rxelecidle and receiving valid rxvalid in the receiving direction according to the sending electrical idle txelecidle.

2. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 1, characterized in that: The signal generating circuit is used to generate two bits of receiving electrical idle rxelecidle and receiving valid rxvalid in the receiving direction according to two bits of the transmitting electrical idle txelecidle, including: for the two bits of transmitting electrical idle txelecidle [1:0], respectively inputting the low bit txelecidle [0] of the transmitting electrical idle txelecidle into a buffer IBUF for buffering and then separating into two outputs, wherein one output is buffered by an output buffer OBUF to obtain the low bit rxelecidle [0] of the receiving electrical idle rxelecidle, and the other output is obtained by looking up a logic function table LUT1 to obtain a predefined logic function table output result as the low bit rxvalid [0] of the receiving valid rxvalid; inputting the high bit txelecidle [1] of the transmitting electrical idle txelecidle into a buffer IBUF for buffering and then separating into two outputs, wherein one output is buffered by an output buffer OBUF to obtain the high bit rxelecidle of the receiving electrical idle rxelecidle [1], and the other output uses a logic function table LUT2 to look up the predefined logic function table output result as the high bit rxvalid [1] of the receive valid rxvalid, thereby obtaining the two bits of transmit electrical idle txelecidle[1:0] corresponding to the two bits of receive electrical idle rxelecidle[1:0] and the receive valid rxvalid[1:0].

3. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 1, characterized in that: The compression of the data packaging module includes compressing the receiving direction block start rxstartblock from the original 16 bits to 1 bit, compressing the designated receiving module type rxsyncheader from the original 32 bits to 2 bits, and compressing the receiving data control symbol rxdatak from the original 64 bits to 4 bits.

4. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 3, characterized in that: The packing of the data packing module includes packing the compressed receiving direction data signal into a data packet with a width of 576 bits, and the 576-bit data packet includes in sequence: 512 bits of receiving data rxdata, a receiving direction block start rxstartblock compressed to 1 bit, a designated receiving module type rxsyncheader compressed to 2 bits, a receiving data control symbol indication rxdatak compressed to 4 bits, a 16-bit receiving electrical idle rxelecidle, a 16-bit receiving valid rxvalid, a 16-bit receiving data valid rxdatavalid and an end marker 9'b0, and the end marker 9'b0 is composed of 9 bits of 0.

5. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 4, characterized in that: It also includes a clock divider, the input end of the clock divider is connected to the physical clock signal phy_clk of the parallel PHY group, and the divided clock signal clk_div output by the output end of the clock divider is respectively connected to the data packaging module, the data parsing module and the core grain interconnection controller of the PIPE interface.

6. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 5, characterized in that: The parallel PHY group is composed of three parallel PHYs. The parallel PHY group can provide a 288-bit data transmission channel per clock cycle. The data packaging module uses the divided clock signal clk_div generated by the clock divider to perform data transmission in divided beats.

7. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 5, characterized in that: The ratio between the divided clock signal clk_div and the physical clock signal phy_clk is less than 588:phy_datanum, where phy_datanum is the data channel width provided by the parallel PHY group.

8. The circuit for supporting chiplet parallel physical links through a PIPE interface according to claim 6, characterized in that: The data processing module uses a state machine to manage the connection between the core grain interconnect controller and the parallel PHY group. The state machine includes four stages: waiting, configuring PHY, configuring the core grain interconnect controller and normal operation. The state machine first enters the PHY configuration stage after reset. In the PHY configuration stage, the data processing module performs initialization training and configuration on the parallel PHY group used. During the PHY initialization training and configuration process, the core grain interconnect interface, the data processing module and the clock divider will all remain in a reset state and wait for the parallel PHY group training configuration to be completed. When the parallel PHY group training configuration is completed, the reset state of the core grain interconnect interface, the data processing module and the clock divider will be terminated and the core grain interconnect controller configuration will be entered. In the chip interconnect controller configuration stage, the chip interconnect controller is initialized, and the simulated PHY interacts with the upper chip interconnect controller through the control status signal phystatus on the PIPE interface to complete the initialization training of the upper chip interconnect controller. After the initialization training of the chip interconnect controller is completed, the normal working stage is entered; in the normal working stage, the data processing module executes data interaction between the chip interconnect controller and the parallel PHY group, and detects the situation where the parallel PHY group exits the normal working state. If it is detected that the parallel PHY group exits the normal working state, the normal working stage is exited and the waiting state is entered; in the waiting state, it waits for reset. If it is reset, it enters the configuration PHY stage.

9. A chip comprising a core particle and a physical link between the core particles, characterized in that: The physical link includes the circuit supporting the core particle parallel physical link through the PIPE interface as described in any one of claims 1 to 8.

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