Integrated circuit verification software development method and system supporting multiple process nodes

Abstract

The invention provides an integrated circuit verification software development method and system supporting multiple process nodes, and relates to the technical field of integrated circuits. Receiving a target integrated circuit design file input by a user and a selected process node, extracting corresponding parameter information from the process node database according to the selected process node, and extracting a corresponding verification rule set from the verification rule base; performing parameterization processing on the target integrated circuit design file by using the extracted parameter information to generate an optimization design file containing process specific information; and executing a multi-level parallel verification process based on the optimization design file and the extracted verification rule set.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and in particular to an integrated circuit verification software development method and system supporting multiple process nodes. Background Art

[0002] With the rapid development of integrated circuit technology, the complexity of chip design continues to increase, and the process nodes continue to shrink, which puts higher and higher requirements on integrated circuit verification software. Traditional verification software is usually optimized for specific process nodes and is difficult to adapt to the verification requirements of multiple process nodes, resulting in the design team needing to maintain multiple sets of verification tools, increasing development costs and complexity.

[0003] At present, integrated circuit verification mainly includes design rule checking (DRC), electrical rule checking (ERC), layout and circuit consistency checking (LVS) and manufacturability analysis (MFA). Each process node has its own specific design rules and verification requirements, which makes the development of verification software that supports multiple process nodes face many challenges:

[0004] Diversity of verification rules: Design rules for different process nodes vary significantly. How to efficiently manage and apply these rules within a software framework is an important issue.

[0005] Computational efficiency: As process nodes shrink, design size and complexity grow exponentially, and verification software needs to have higher computational efficiency to meet the verification needs of large-scale designs.

[0006] Balance between accuracy and performance: More advanced process nodes require higher verification accuracy, but this usually leads to increased computing time. How to strike a balance between accuracy and performance is a key challenge.

[0007] Process Characteristic Modeling: Each process node has its own unique physical characteristics, and how to accurately model these characteristics and integrate them into the verification flow is a complex task.

[0008] Some existing attempts include using configurable rule engines, hierarchical verification strategies, parallel computing technology, etc. However, these methods often find it difficult to meet the needs of multiple process nodes at the same time, especially when dealing with advanced process nodes, there are problems with efficiency and accuracy.

[0009] Therefore, developing an integrated circuit verification software that can efficiently support multiple process nodes, which can not only meet the specific needs of different process nodes but also maintain the uniformity and ease of use of the software, has become an important research direction in the current integrated circuit design field. Summary of the invention

[0010] The embodiments of the present invention provide an integrated circuit verification software development method and system supporting multiple process nodes, which can solve the problems in the prior art.

[0011] According to a first aspect of the embodiments of the present invention,

[0012] Provides integrated circuit verification software development methodologies that support multiple process nodes, including:

[0013] Establishing a process node database and a verification rule base, wherein the process node database stores parameter information of various process nodes, and the verification rule base stores verification rule sets corresponding to the various process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules;

[0014] Receive a target integrated circuit design file and a selected process node input by a user, extract corresponding parameter information from the process node database according to the selected process node, and extract a corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information;

[0015] Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is executed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module simultaneously; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

[0016] Establishing a process node database and verification rule base includes:

[0017] A process node database, wherein the process node database adopts a hierarchical structure design, the top layer is classified according to the process, each process is subdivided into different process options, and the process node database stores parameter information of multiple process nodes, each process node includes transistor model parameters, interconnect line parameters, parasitic parameters and process deviation parameters;

[0018] A verification rule library, wherein the verification rule library adopts a hierarchical structure corresponding to the process node database, and stores verification rule sets corresponding to the multiple process nodes, each verification rule set including design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and design for manufacturability rules;

[0019] A parameterized description module, wherein the parameterized description module uses mathematical expressions and conditional statements to describe complex parameter relationships and rules, wherein the mathematical expressions are used to describe design rules for a specific process node;

[0020] An automated update module, which automatically extracts the latest process parameters and design rules and updates the process node database and the verification rule library by keeping in sync with the wafer fab's design kit;

[0021] A version control module, the version control module records the content and timestamp of each update of the process node database and the verification rule library;

[0022] The data of the process node database and the verification rule base are used for subsequent parameterization processing and multi-level parallel verification to ensure that the design results meet the requirements of specific process nodes and adapt to the migration and comparison between different process nodes.

[0023] In an optional embodiment,

[0024] Receiving a target integrated circuit design file and a selected process node input by a user, extracting corresponding parameter information from the process node database according to the selected process node, and extracting a corresponding verification rule set from the verification rule library includes:

[0025] Receiving a target integrated circuit design file and a selected process node input by a user, wherein the target integrated circuit design file is in a GDS II or OAS IS format;

[0026] Using a parallelized file parser to split the target integrated circuit design file into a plurality of data blocks, and simultaneously processing the plurality of data blocks by using a multi-threading technology;

[0027] According to the selected process node, extract corresponding parameter information from a process node database using a fast index structure based on a hash table, wherein the process node is used as a key and the corresponding parameter set is used as a value;

[0028] Processing the dependency relationship between the extracted parameter information using a parameter dependency graph algorithm, wherein the parameter dependency graph algorithm represents the dependency relationship between the parameters as a directed acyclic graph and determines the order of parameter loading through topological sorting;

[0029] Extracting a basic verification rule set corresponding to the selected process node from a verification rule library;

[0030] Dynamically adjusting the basic verification rule set according to the characteristics of the target integrated circuit design file and the verification requirements specified by the user to form a final verification rule set;

[0031] Use the rule mapping engine to identify the commonalities and differences between rules at different process nodes and generate rule conversion functions;

[0032] Generates an extraction report containing information on the number of extracted parameters, number of rules, possible conflicts or missing items.

[0033] In an optional embodiment,

[0034] Using the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process specific information includes:

[0035] receiving a target integrated circuit design file and extracted process specific parameter information;

[0036] Using an intelligent parameter mapping algorithm to identify key elements in the target integrated circuit design file and establish a correspondence between the key elements and the process-specific parameter information, wherein the intelligent parameter mapping algorithm is based on a neural network model trained using machine learning technology;

[0037] Using a parameterized transformation engine to systematically adjust geometric and electrical information in the target integrated circuit design file based on the process-specific parameter information, wherein the parameterized transformation engine employs an iterative optimization algorithm;

[0038] Processing process variation parameters through a statistical variation model, wherein the statistical variation model generates a plurality of design variants taking into account process variation based on a Monte Carlo method;

[0039] For system-on-chip design, a hierarchical parameterization strategy is adopted, which gradually drills down from the top level to the functional modules and standard cells, and applies specific parameterization rules and optimization algorithms at each level;

[0040] Automatically partitioning large designs into multiple relatively independent regions using a parallel computing framework that dynamically allocates computing resources based on the complexity of each region using a load balancing algorithm and performs parameterized processing simultaneously on a distributed computing cluster;

[0041] During the parameterization process, a real-time design rule checking module is integrated to instantly check parameter adjustments. If a violation is found, it will automatically roll back to the last valid state and try alternative parameterization solutions;

[0042] An optimized design file containing process-specific information is generated, wherein the optimized design file contains adjusted geometric and electrical information and a parameterized processing report, wherein the parameterized processing report records the before-and-after comparison of the parameterized key design elements and the expected performance improvement information.

[0043] In an optional embodiment,

[0044] Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is performed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results, and generating a comprehensive verification report including:

[0045] receiving optimized design files and extracted validation rule sets;

[0046] Dividing the optimized design file into a plurality of sub-circuit modules using a circuit partitioning algorithm based on graph theory, wherein the circuit partitioning algorithm considers circuit topology, functional module boundaries and signal flow, and adopts a multi-level partitioning strategy;

[0047] Constructing a distributed computing framework, which includes a dynamic task allocation mechanism and a fault tolerance mechanism for managing and scheduling verification tasks;

[0048] Apply a hierarchical rule engine to dynamically load the corresponding rule set according to the verification type, and use a decision tree-based rule optimization algorithm to adjust the rule execution order;

[0049] The following verification is performed simultaneously on each of the sub-circuit modules:

[0050] Design rule checking using multi-resolution scanning algorithms;

[0051] Use symbolic execution-based static analysis technology for electrical rule checking;

[0052] Use a hierarchical matching strategy based on graph isomorphism to check the consistency of layout and circuit;

[0053] Apply physical model-based simulation techniques and adaptive sampling strategies for manufacturability analysis;

[0054] Processing validation results using a deep learning-based classification and prioritization algorithm that learns the characteristics and importance of different types of issues by analyzing historical validation data;

[0055] A comprehensive verification report is generated using an intelligent report generation system that includes natural language processing technology and an interactive visualization module to generate problem descriptions, repair suggestions, and display the location and distribution of problems in the layout.

[0056] According to a second aspect of the embodiments of the present invention,

[0057] Provides integrated circuit verification software development systems supporting multiple process nodes, including:

[0058] The first unit is used to establish a process node database and a verification rule base, wherein the process node database stores parameter information of multiple process nodes, and the verification rule base stores verification rule sets corresponding to the multiple process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules;

[0059] The second unit is used to receive the target integrated circuit design file and the selected process node input by the user, extract corresponding parameter information from the process node database according to the selected process node, and extract the corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information;

[0060] The third unit is used to execute a multi-level parallel verification process based on the optimized design file and the extracted verification rule set, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

[0061] According to a third aspect of the embodiments of the present invention,

[0062] An electronic device is provided, comprising:

[0063] processor;

[0064] a memory for storing processor-executable instructions;

[0065] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0066] A fourth aspect of the embodiments of the present invention is:

[0067] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 A schematic diagram of a flow chart of a method for developing integrated circuit verification software supporting multiple process nodes according to an embodiment of the present invention;

[0069] Figure 2 A schematic diagram of the structure of an integrated circuit verification software development system supporting multiple process nodes according to an embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0072] Figure 1 FIG. 1 is a flow chart of a method for developing integrated circuit verification software supporting multiple process nodes according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0073] S101. Establish a process node database and a verification rule base, wherein the process node database stores parameter information of various process nodes, and the verification rule base stores verification rule sets corresponding to the various process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules;

[0074] S102. Receive the target integrated circuit design file and the selected process node input by the user, extract corresponding parameter information from the process node database according to the selected process node, and extract the corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information;

[0075] S103. Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is executed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein, the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

[0076] In an optional embodiment,

[0077] Establishing a process node database and verification rule base includes:

[0078] A process node database, wherein the process node database adopts a hierarchical structure design, the top layer is classified according to the process, each process is subdivided into different process options, and the process node database stores parameter information of multiple process nodes, each process node includes transistor model parameters, interconnect line parameters, parasitic parameters and process deviation parameters;

[0079] A verification rule library, wherein the verification rule library adopts a hierarchical structure corresponding to the process node database, and stores verification rule sets corresponding to the multiple process nodes, each verification rule set including design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and design for manufacturability rules;

[0080] A parameterized description module, wherein the parameterized description module uses mathematical expressions and conditional statements to describe complex parameter relationships and rules, wherein the mathematical expressions are used to describe design rules for a specific process node;

[0081] An automated update module, which automatically extracts the latest process parameters and design rules and updates the process node database and the verification rule library by keeping in sync with the wafer fab's design kit;

[0082] A version control module, the version control module records the content and timestamp of each update of the process node database and the verification rule library;

[0083] The data of the process node database and the verification rule base are used for subsequent parameterization processing and multi-level parallel verification to ensure that the design results meet the requirements of specific process nodes and adapt to the migration and comparison between different process nodes.

[0084] Exemplarily, a process node database and a verification rule base are established, wherein the process node database stores parameter information of various process nodes, and the verification rule base stores verification rule sets corresponding to the various process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules.

[0085] In order to support the verification of integrated circuits at multiple process nodes, a comprehensive and accurate process node database needs to be established first. The database is designed with a hierarchical structure to ensure the organization and scalability of the data. At the top level, the database is classified according to process technology, such as 28nm, 14nm, 7nm, etc. Each process technology is further subdivided into different process options, such as high performance (HP), low power (LP), ultra-low power (ULP), etc.

[0086] For each specific process node, the database stores four types of key parameters: transistor model parameters, interconnect parameters, parasitic parameters, and process deviation parameters. Transistor model parameters include threshold voltage, carrier mobility, gate capacitance, etc. These parameters directly affect the switching characteristics and power consumption of the transistor. Interconnect parameters include the resistance, capacitance, and dielectric constant of different metal layers. These parameters are crucial for signal integrity and timing analysis. Parasitic parameters mainly involve source-drain junction capacitance, stack capacitance, etc. These parameters are particularly important in high-frequency circuit design. Process deviation parameters record the range of changes that may occur in the manufacturing process, such as line width changes, mask alignment errors, etc. These parameters are of great significance for statistical performance analysis and yield prediction.

[0087] Corresponding to the process node database, the verification rule library also adopts a similar hierarchical structure. Each process node corresponds to a complete set of verification rules, including design rule checking (DRC) rules, electrical rule checking (ERC) rules, layout and circuit consistency checking (LVS) rules, and design for manufacturability (DFM) rules. DRC rules define geometric constraints such as minimum line width, spacing, density, etc. to ensure that the design meets the process manufacturing capabilities. ERC rules mainly focus on the correctness of electrical connections, such as preventing short circuits, hanging nodes and other problems. LVS rules are used to verify whether the layout correctly implements the functions of the circuit schematic. DFM rules go a step further and take into account potential problems in the manufacturing process, such as lithography hotspots, etching deviations, etc., to improve the manufacturability and yield of the design.

[0088] In order to improve the practicality of the database and rule base, a flexible parameterized description language was developed. This language allows the use of mathematical expressions and conditional statements to describe complex parameter relationships and rules. For example, for the 14nm process node, the expression "Min_Width=0.014+0.002*(L / W_rat io-1)" can be used to describe the rule of minimum line width changing with aspect ratio. This parameterization method not only makes the rule description more concise, but also can better adapt to different design situations.

[0089] In addition, in order to cope with the rapid iteration and update of process nodes, an automated database update mechanism is implemented. This mechanism automatically extracts the latest process parameters and design rules by keeping in sync with the wafer fab's design kit (PDK). At the same time, a version control system is established to record the content and timestamp of each update, making it easier to track parameter change history and perform rollback operations.

[0090] By establishing such a comprehensive and dynamic process node database and verification rule base, a solid foundation has been laid for subsequent integrated circuit design verification work. These data and rules will play a key role in subsequent steps such as parameterization processing and multi-level parallel verification, ensuring that the design results not only meet the requirements of specific process nodes, but also adapt to the migration and comparison between different process nodes.

[0091] In an optional embodiment,

[0092] Receiving a target integrated circuit design file and a selected process node input by a user, extracting corresponding parameter information from the process node database according to the selected process node, and extracting a corresponding verification rule set from the verification rule library includes:

[0093] Receiving a target integrated circuit design file and a selected process node input by a user, wherein the target integrated circuit design file is in a GDS II or OAS IS format;

[0094] Using a parallelized file parser to split the target integrated circuit design file into a plurality of data blocks, and simultaneously processing the plurality of data blocks by using a multi-threading technology;

[0095] According to the selected process node, extract corresponding parameter information from a process node database using a fast index structure based on a hash table, wherein the process node is used as a key and the corresponding parameter set is used as a value;

[0096] Processing the dependency relationship between the extracted parameter information using a parameter dependency graph algorithm, wherein the parameter dependency graph algorithm represents the dependency relationship between the parameters as a directed acyclic graph and determines the order of parameter loading through topological sorting;

[0097] Extracting a basic verification rule set corresponding to the selected process node from a verification rule library;

[0098] Dynamically adjusting the basic verification rule set according to the characteristics of the target integrated circuit design file and the verification requirements specified by the user to form a final verification rule set;

[0099] Use the rule mapping engine to identify the commonalities and differences between rules at different process nodes and generate rule conversion functions;

[0100] Generates an extraction report containing information on the number of extracted parameters, number of rules, possible conflicts or missing items.

[0101] Exemplarily, receiving a target integrated circuit design file and a selected process node input by a user, extracting corresponding parameter information from the process node database according to the selected process node, and extracting a corresponding verification rule set from the verification rule library

[0102] During the development of IC verification software, an efficient design file processing and parameter extraction module was implemented. The module first receives two key inputs through the user interface: the target IC design file and the user-selected process node. Design files are usually in industry-standard GDSII or OASIS formats, which can accurately describe the physical layout information of the IC. In order to improve the efficiency of file reading, a parallelized file parser was developed, which can split large GDSII or OASIS files into multiple data blocks and use multi-threading technology to process these data blocks simultaneously, significantly reducing the file loading time.

[0103] After receiving the process node information selected by the user, the system will immediately trigger the parameter extraction process. This process adopts an innovative "delayed loading" strategy, which only extracts the parameters required for the current verification task instead of loading all parameters at once. In the specific implementation, a fast index structure based on a hash table is used, which uses the process node as the key and the corresponding parameter set as the value. This design not only improves the data access speed, but also greatly reduces memory usage.

[0104] When extracting parameter information from the process node database, we focus on four key parameters: transistor model parameters, interconnect parameters, parasitic parameters, and process deviation parameters. In order to handle the complex dependencies between different parameters, we developed a parameter dependency graph (PDG) algorithm. PDG represents the dependencies between parameters as a directed acyclic graph, and determines the optimal order of parameter loading through topological sorting, ensuring that all parameters are correctly initialized before use.

[0105] When extracting the verification rule set, a dynamic rule combination strategy is adopted. This strategy first extracts the basic rule set from the verification rule library, and then dynamically adds or modifies the rules according to the characteristics of the design file and the verification requirements specified by the user. For example, for high-frequency circuit design, the system automatically adds additional check rules related to signal integrity. This dynamic combination method greatly improves the flexibility and pertinence of verification.

[0106] In order to handle the rule differences between different process nodes, a rule mapping engine was developed. The engine can automatically identify the commonalities and differences between the rules of different process nodes and generate rule conversion functions. This makes it easier to migrate designs between different process nodes and also provides a basis for comparative analysis of multiple process nodes.

[0107] After the parameters and rules are extracted, the system will generate a detailed extraction report, including the number of extracted parameters, the number of rules, possible conflicts or missing items, etc. This report is not only for user review, but also serves as an input for the subsequent verification process to guide the formulation and optimization of verification strategies.

[0108] This carefully designed parameter and rule extraction process lays a solid foundation for the subsequent design file parameterization processing and multi-level parallel verification. The extracted parameters and rules not only ensure the precise matching of the verification process with the selected process node, but also provide the necessary data support for design optimization and process migration.

[0109] In an optional embodiment,

[0110] Using the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process specific information includes:

[0111] receiving a target integrated circuit design file and extracted process specific parameter information;

[0112] Using an intelligent parameter mapping algorithm to identify key elements in the target integrated circuit design file and establish a corresponding relationship between the key elements and the process-specific parameter information, wherein the intelligent parameter mapping algorithm is based on a neural network model trained by machine learning technology;

[0113] Using a parameterized transformation engine to systematically adjust geometric and electrical information in the target integrated circuit design file based on the process-specific parameter information, wherein the parameterized transformation engine employs an iterative optimization algorithm;

[0114] Processing process deviation parameters through a statistical variation model, wherein the statistical variation model generates a plurality of design variants taking into account process deviations based on a Monte Carlo method;

[0115] For system-on-chip design, a hierarchical parameterization strategy is adopted, which gradually drills down from the top level to the functional modules and standard cells, and applies specific parameterization rules and optimization algorithms at each level;

[0116] Automatically partitioning large designs into multiple relatively independent regions using a parallel computing framework that dynamically allocates computing resources based on the complexity of each region using a load balancing algorithm and performs parameterized processing simultaneously on a distributed computing cluster;

[0117] During the parameterization process, a real-time design rule checking module is integrated to perform instant checks on parameter adjustments. If violations are found, it will automatically roll back to the last valid state and try alternative parameterization solutions.

[0118] An optimized design file containing process-specific information is generated, wherein the optimized design file contains adjusted geometric and electrical information and a parameterized processing report, wherein the parameterized processing report records the before-and-after comparison of the parameterized key design elements and the expected performance improvement information.

[0119] Exemplarily, the target integrated circuit design file is parameterized using the extracted parameter information to generate an optimized design file containing process-specific information.

[0120] Parameterization is a key step in the integrated circuit verification process. It combines the extracted process-specific parameter information with the target design file to generate an optimized design file containing process-specific information. This process can not only improve the accuracy of subsequent verification, but also provide an important basis for design optimization.

[0121] First, an intelligent parameter mapping algorithm was developed that automatically identifies key elements in the design file and establishes a correspondence between them and the extracted process parameters. For example, for a transistor model, the algorithm identifies each transistor instance in the design and selects the best matching model parameters from the extracted parameter set based on its size and type. This process uses machine learning technology to train a neural network model that can accurately predict parameter mapping relationships by analyzing a large amount of historical design data.

[0122] Next, a parametric transformation engine was implemented. This engine systematically adjusts the geometric and electrical information in the design file based on the extracted process parameters. For example, for interconnects, the engine automatically adjusts the line width and spacing based on the extracted resistance and capacitance parameters to meet the performance and reliability requirements of a specific process node. This process uses an iterative optimization algorithm to gradually adjust the design parameters while keeping the design function unchanged until the optimal balance is reached.

[0123] In order to handle process deviation parameters, a statistical variation model was developed. This model is based on the Monte Carlo method and generates a large number of design variants that take process deviation into account. Each variant represents a situation that may occur in the actual manufacturing process. By analyzing the performance distribution of these variants, not only can the robustness of the design be evaluated, but also the design parts that are particularly sensitive to process deviations can be identified, providing direction for subsequent optimization.

[0124] When dealing with complex system-on-chip (SoC) designs, a hierarchical parameterization strategy is used. This strategy starts with global parameterization at the top level and then drills down to each functional module and standard cell. At each level, specific parameterization rules and optimization algorithms are applied. This hierarchical approach not only improves processing efficiency, but also better handles the interaction between different modules.

[0125] In order to improve the efficiency of parameterization processing, a parallel computing framework was implemented. This framework can automatically split large designs into multiple relatively independent regions and perform parameterization processing simultaneously on a distributed computing cluster. An innovative load balancing algorithm is used to dynamically allocate computing resources according to the complexity of each region, greatly reducing processing time.

[0126] During the parameterization process, a real-time design rule check (DRC) module is also integrated. This module can instantly check whether the process design rules are violated while the parameters are adjusted. If a violation is found, the system will automatically roll back to the last valid state and try an alternative parameterization scheme. This real-time checking mechanism greatly improves the reliability of the parameterization process.

[0127] Finally, an optimized design file with process-specific information is generated. This file not only contains the adjusted geometric and electrical information, but also comes with a detailed parameterization processing report. The report records the before and after parameterization of each key design element, as well as the expected performance improvement. This information provides valuable feedback to the design team and helps to further optimize the design process.

[0128] This comprehensive and sophisticated parameterization not only improves the matching degree between the design and the specific process, but also lays a solid foundation for subsequent verification and optimization. The generated optimized design file becomes an important bridge between pure design and actual process, greatly improving the efficiency and reliability of the entire integrated circuit design and verification process.

[0129] In an optional embodiment,

[0130] Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is performed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results, and generating a comprehensive verification report including:

[0131] receiving optimized design files and extracted validation rule sets;

[0132] Dividing the optimized design file into a plurality of sub-circuit modules using a circuit partitioning algorithm based on graph theory, wherein the circuit partitioning algorithm considers circuit topology, functional module boundaries and signal flow, and adopts a multi-level partitioning strategy;

[0133] Constructing a distributed computing framework, which includes a dynamic task allocation mechanism and a fault tolerance mechanism for managing and scheduling verification tasks;

[0134] Apply a hierarchical rule engine to dynamically load the corresponding rule set according to the verification type, and use a decision tree-based rule optimization algorithm to adjust the rule execution order;

[0135] The following verification is performed simultaneously on each of the sub-circuit modules:

[0136] Design rule checking using multi-resolution scanning algorithms;

[0137] Use symbolic execution-based static analysis technology for electrical rule checking;

[0138] Use a hierarchical matching strategy based on graph isomorphism to check the consistency of layout and circuit;

[0139] Apply physical model-based simulation techniques and adaptive sampling strategies for manufacturability analysis;

[0140] Processing validation results using a deep learning-based classification and prioritization algorithm that learns the characteristics and importance of different types of issues by analyzing historical validation data;

[0141] A comprehensive verification report is generated using an intelligent report generation system that includes natural language processing technology and an interactive visualization module to generate problem descriptions, repair suggestions, and display the location and distribution of problems in the layout.

[0142] For example, the multi-level parallel verification process is an efficient integrated circuit verification method that makes full use of distributed computing resources while taking into account the comprehensiveness of verification and the interpretability of results. The core of this process is to decompose complex verification tasks into subtasks that can be executed in parallel and integrate the verification results through intelligent algorithms.

[0143] First, a graph-theory-based circuit partitioning algorithm was developed to partition the optimized design file into multiple sub-circuit modules. This algorithm not only considers the topological structure of the circuit, but also the boundaries and signal flows of the functional modules. By minimizing the interconnections between modules, the algorithm is able to generate a set of relatively independent sub-circuit modules, each with clear input and output interfaces. In order to handle large-scale designs, the algorithm adopts a multi-level partitioning strategy, first performing a coarse-grained partitioning of the overall circuit, and then gradually refining it into smaller functional units.

[0144] Next, a distributed computing framework was built to manage and schedule verification tasks. The framework is based on Apache Spark and can effectively handle large-scale parallel computing tasks. In order to improve computing efficiency, a dynamic task allocation mechanism was developed to adaptively adjust the task allocation strategy according to the real-time load and performance characteristics of each computing node. In addition, a fault-tolerant mechanism was implemented to automatically detect and recover failed tasks to ensure the reliability of the verification process.

[0145] In terms of the application of verification rules, a hierarchical rule engine is used. This engine can dynamically load the corresponding rule set according to different verification types (design rule check, electrical rule check, layout and circuit consistency check, and manufacturability analysis). In order to improve the efficiency of rule checking, a rule optimization algorithm based on a decision tree was developed, which can automatically adjust the execution order of rules based on historical verification data and give priority to the rules that are more likely to find problems.

[0146] For design rule checking (DRC), a new multi-resolution scanning algorithm is implemented. The algorithm first performs a low-resolution scan of the entire layout to quickly locate potential problem areas, and then performs a high-resolution fine scan of these areas. This method greatly reduces the amount of calculation while ensuring the accuracy of the inspection.

[0147] In electrical rule checking (ERC), a static analysis technique based on symbolic execution is developed. This technique can deduce various possible states of a circuit without actually running the circuit, thereby discovering potential electrical problems such as short circuits, open circuits, floating nodes, etc.

[0148] The layout and circuit consistency check (LVS) uses an algorithm based on graph isomorphism. The algorithm first converts the layout and circuit schematic into a graph structure, and then checks the consistency of the two through graph matching technology. In order to handle large-scale circuits, the algorithm uses a hierarchical matching strategy, first matching high-level modules and then gradually going down to the bottom-level units.

[0149] In the area of ​​manufacturability analysis (MFA), a simulation technology based on physical models has been developed. This technology combines lithography simulation, etching simulation, and CMP (chemical mechanical planarization) simulation to accurately predict problems that may occur during the manufacturing process. In order to improve simulation efficiency, an adaptive sampling strategy is adopted to dynamically adjust the simulation density according to the complexity of the layout.

[0150] In terms of processing verification results, a deep learning-based classification and prioritization algorithm was developed. The algorithm analyzes a large amount of historical verification data to learn the characteristics and importance of different types of problems. In practical applications, the algorithm can automatically classify verification results and assign priorities to each problem based on factors such as the severity of the problem, the scope of impact, and the difficulty of repair.

[0151] Finally, an intelligent report generation system is designed to generate comprehensive verification reports. The system can not only summarize various verification results, but also generate easy-to-understand problem descriptions and repair suggestions through natural language processing technology. In addition, the system also integrates an interactive visualization module that can intuitively display the location and distribution of problems in the layout.

[0152] This multi-level parallel verification process not only greatly improves the efficiency and comprehensiveness of verification, but also provides more valuable verification results. This method can help the design team quickly locate and solve problems, thereby accelerating the entire integrated circuit design process.

[0153] Figure 2 FIG. 1 is a schematic diagram of the structure of an integrated circuit verification software development system supporting multiple process nodes according to an embodiment of the present invention. Figure 2As shown, the system comprises:

[0154] The first unit is used to establish a process node database and a verification rule base, wherein the process node database stores parameter information of multiple process nodes, and the verification rule base stores verification rule sets corresponding to the multiple process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules;

[0155] The second unit is used to receive the target integrated circuit design file and the selected process node input by the user, extract corresponding parameter information from the process node database according to the selected process node, and extract the corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information;

[0156] The third unit is used to execute a multi-level parallel verification process based on the optimized design file and the extracted verification rule set, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

[0157] According to a third aspect of the embodiments of the present invention,

[0158] An electronic device is provided, comprising:

[0159] processor;

[0160] a memory for storing processor-executable instructions;

[0161] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0162] A fourth aspect of the embodiments of the present invention is:

[0163] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0164] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for developing integrated circuit verification software supporting multiple process nodes, characterized in that: include: Establishing a process node database and a verification rule base, wherein the process node database stores parameter information of various process nodes, and the verification rule base stores verification rule sets corresponding to the various process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules; Receive a target integrated circuit design file and a selected process node input by a user, extract corresponding parameter information from the process node database according to the selected process node, and extract a corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information; Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is executed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module simultaneously; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

2. The method according to claim 1, characterized in that Establishing a process node database and verification rule base includes: A process node database, wherein the process node database adopts a hierarchical structure design, the top layer is classified according to the process, each process is subdivided into different process options, and the process node database stores parameter information of multiple process nodes, each process node includes transistor model parameters, interconnect line parameters, parasitic parameters and process deviation parameters; A verification rule library, wherein the verification rule library adopts a hierarchical structure corresponding to the process node database, and stores verification rule sets corresponding to the multiple process nodes, each verification rule set including design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and design for manufacturability rules; A parameterized description module, wherein the parameterized description module uses mathematical expressions and conditional statements to describe complex parameter relationships and rules, wherein the mathematical expressions are used to describe design rules for a specific process node; An automated update module, which automatically extracts the latest process parameters and design rules and updates the process node database and the verification rule library by keeping in sync with the wafer fab's design kit; A version control module, the version control module records the content and timestamp of each update of the process node database and the verification rule library; The data of the process node database and the verification rule base are used for subsequent parameterization processing and multi-level parallel verification to ensure that the design results meet the requirements of specific process nodes and adapt to the migration and comparison between different process nodes.

3. The method according to claim 1, characterized in that Receiving a target integrated circuit design file and a selected process node input by a user, extracting corresponding parameter information from the process node database according to the selected process node, and extracting a corresponding verification rule set from the verification rule library includes: Receiving a target integrated circuit design file and a selected process node input by a user, wherein the target integrated circuit design file is in GDSII or OASIS format; Using a parallelized file parser to split the target integrated circuit design file into a plurality of data blocks, and simultaneously processing the plurality of data blocks by using a multi-threading technology; According to the selected process node, extract corresponding parameter information from a process node database using a fast index structure based on a hash table, wherein the process node is used as a key and the corresponding parameter set is used as a value; Processing the dependency relationship between the extracted parameter information using a parameter dependency graph algorithm, wherein the parameter dependency graph algorithm represents the dependency relationship between the parameters as a directed acyclic graph and determines the order of parameter loading through topological sorting; Extracting a basic verification rule set corresponding to the selected process node from a verification rule library; Dynamically adjusting the basic verification rule set according to the characteristics of the target integrated circuit design file and the verification requirements specified by the user to form a final verification rule set; Use the rule mapping engine to identify the commonalities and differences between rules at different process nodes and generate rule conversion functions; Generates an extraction report containing information on the number of extracted parameters, number of rules, possible conflicts or missing items.

4. The method according to claim 1, characterized in that: Using the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process specific information includes: receiving a target integrated circuit design file and extracted process specific parameter information; Using an intelligent parameter mapping algorithm to identify key elements in the target integrated circuit design file and establish a correspondence between the key elements and the process-specific parameter information, wherein the intelligent parameter mapping algorithm is based on a neural network model trained using machine learning technology; Using a parameterized transformation engine to systematically adjust geometric and electrical information in the target integrated circuit design file based on the process-specific parameter information, wherein the parameterized transformation engine employs an iterative optimization algorithm; Processing process variation parameters through a statistical variation model, wherein the statistical variation model generates a plurality of design variants taking into account process variation based on a Monte Carlo method; For system-on-chip design, a hierarchical parameterization strategy is adopted, which gradually drills down from the top level to the functional modules and standard cells, and applies specific parameterization rules and optimization algorithms at each level; Automatically partitioning large designs into multiple relatively independent regions using a parallel computing framework that dynamically allocates computing resources based on the complexity of each region using a load balancing algorithm and performs parameterized processing simultaneously on a distributed computing cluster; During the parameterization process, a real-time design rule checking module is integrated to instantly check parameter adjustments. If a violation is found, it will automatically roll back to the last valid state and try alternative parameterization solutions; An optimized design file containing process-specific information is generated, wherein the optimized design file contains adjusted geometric and electrical information and a parameterized processing report, wherein the parameterized processing report records the before-and-after comparison of the parameterized key design elements and the expected performance improvement information.

5. The method according to claim 1, characterized in that Based on the optimized design file and the extracted verification rule set, a multi-level parallel verification process is performed, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results, and generating a comprehensive verification report including: receiving optimized design files and extracted validation rule sets; Dividing the optimized design file into a plurality of sub-circuit modules using a circuit partitioning algorithm based on graph theory, wherein the circuit partitioning algorithm considers circuit topology, functional module boundaries and signal flow, and adopts a multi-level partitioning strategy; Constructing a distributed computing framework, which includes a dynamic task allocation mechanism and a fault tolerance mechanism for managing and scheduling verification tasks; Apply a hierarchical rule engine to dynamically load the corresponding rule set according to the verification type, and use a decision tree-based rule optimization algorithm to adjust the rule execution order; The following verification is performed simultaneously on each of the sub-circuit modules: Design rule checking using multi-resolution scanning algorithms; Use symbolic execution-based static analysis technology for electrical rule checking; Use a hierarchical matching strategy based on graph isomorphism to check the consistency of layout and circuit; Apply physical model-based simulation techniques and adaptive sampling strategies for manufacturability analysis; Processing validation results using a deep learning-based classification and prioritization algorithm that learns the characteristics and importance of different types of issues by analyzing historical validation data; A comprehensive verification report is generated using an intelligent report generation system that includes natural language processing technology and an interactive visualization module to generate problem descriptions, repair suggestions, and display the location and distribution of problems in the layout.

6. An integrated circuit verification software development system supporting multiple process nodes, used to implement the method described in any one of claims 1 to 5, characterized in that: include: The first unit is used to establish a process node database and a verification rule base, wherein the process node database stores parameter information of multiple process nodes, and the verification rule base stores verification rule sets corresponding to the multiple process nodes; wherein each process node in the process node database includes transistor model parameters, interconnect line parameters, parasitic parameters, and process deviation parameters; and each verification rule set in the verification rule base includes design rule checking rules, electrical rule checking rules, layout and circuit consistency checking rules, and manufacturability design rules; The second unit is used to receive the target integrated circuit design file and the selected process node input by the user, extract corresponding parameter information from the process node database according to the selected process node, and extract the corresponding verification rule set from the verification rule library; then, use the extracted parameter information to parameterize the target integrated circuit design file to generate an optimized design file containing process-specific information; The third unit is used to execute a multi-level parallel verification process based on the optimized design file and the extracted verification rule set, and the multi-level parallel verification process includes: using a distributed computing framework to divide the optimized design file into multiple sub-circuit modules; performing design rule checking, electrical rule checking, layout and circuit consistency checking, and manufacturability analysis on each sub-circuit module at the same time; using a machine learning algorithm to classify and prioritize the verification results and generate a comprehensive verification report; wherein the machine learning algorithm can identify critical errors and potential risks through training with historical verification data, and provide intelligent repair suggestions.

7. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 5.

8. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 5 is implemented.

Images