On-chip network verification method, device, electronic device and readable storage medium

Abstract

The present application provides a verification method, device, electronic device and readable storage medium for a network on chip, including: in response to an input command, extracting a first tag carried in the input command, finding a target second tag matching the first tag from a stimulus component set according to the first tag, and obtaining a target stimulus component carrying the target second tag, wherein the stimulus component set includes multiple stimulus components, each stimulus component carries a second tag, and the second tag is used to describe the network on chip area corresponding to the stimulus component; in the process of verifying the design file of the network on chip by a verification platform, compiling and running the target stimulus component, obtaining the verification result of the network on chip area, and completing the verification of the network on chip area, which can reduce the time spent on distinguishing stimulus components and the time for obtaining the target stimulus component, thereby improving the efficiency of verifying the network on chip area.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a verification method, device, electronic device and computer-readable storage medium for a network on a chip. Background Art

[0002] When verifying the on-chip network area, it is necessary to verify the on-chip network area through the incentive component of the on-chip network area to determine whether the on-chip network area has achieved the planned goal.

[0003] The related technology manually distinguishes the excitation components of different on-chip network areas. For example, the on-chip network area includes on-chip network area A and on-chip network area B. It manually distinguishes which excitation components correspond to on-chip network area A and which excitation components correspond to on-chip network area B.

[0004] However, it takes a long time to manually distinguish the stimulus components corresponding to the on-chip network areas. Summary of the invention

[0005] The embodiments of the present application provide a verification method, device, electronic device and computer-readable storage medium for a network on chip to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for verifying a network on chip, the method comprising:

[0007] In response to an input command, extracting a first tag carried in the input command;

[0008] According to the first tag, a target second tag matching the first tag is found from a stimulus component set, and a target stimulus component carrying the target second tag is obtained; the stimulus component set includes a plurality of stimulus components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the stimulus component;

[0009] In the process of verifying the design file of the on-chip network by the verification platform, the target stimulus component is compiled and run to obtain the verification result of the on-chip network area, and the verification of the on-chip network area is completed.

[0010] In a second aspect, an embodiment of the present application provides a verification device for a network on chip, the device comprising:

[0011] an extraction module, configured to extract, in response to an input command, a first tag carried in the input command;

[0012] An acquisition module is used to find a target second tag matching the first tag from a stimulus component set according to the first tag, and acquire a target stimulus component carrying the target second tag; the stimulus component set includes a plurality of stimulus components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the stimulus component;

[0013] The verification module is used to compile and run the target stimulus component during the process of verifying the design file of the on-chip network on the verification platform, obtain the verification result of the on-chip network area, and complete the verification of the on-chip network area.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0015] a memory for storing instructions executable by the processor;

[0016] The processor is configured to execute the instructions to implement the method of the first aspect.

[0017] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0018] In an embodiment of the present application, in response to an input command, a target second label matching the first label is found from a stimulus component set according to a first label extracted from the input command, and a target stimulus component is selected according to a second label for indicating the on-chip network area corresponding to the stimulus component. There is no need to manually distinguish the stimulus components corresponding to the on-chip network area. Therefore, the time spent on distinguishing the stimulus components can be reduced, and the time for acquiring the target stimulus components can be reduced, thereby improving the efficiency of verifying the on-chip network area during the verification platform's verification of the on-chip network area.

[0019] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a flowchart of a method for verifying a network on chip provided by an embodiment of the present application;

[0022] Figure 2 It is a flowchart of the specific steps of a method for verifying a network on a chip provided by an embodiment of the present application;

[0023] Figure 3 It is a block diagram of a network-on-chip verification device provided in an embodiment of the present application;

[0024] Figure 4 is a block diagram of an electronic device provided in an embodiment of the present application;

[0025] Figure 5 It is a block diagram of another electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0028] Figure 1 is a flowchart of a method for verifying a network on chip provided by an embodiment of the present application, such as Figure 1 As shown, the method may include:

[0029] Step 101: In response to an input command, extract a first tag carried in the input command.

[0030] For example, the input command is used to run the stimulus component with the specified tag. The input command can be bsim -t soc::case_list.yml -tag tag_A, which is used to run the stimulus component with the tag tag_A. Among them, list.yml is the stimulus list containing the stimulus component with the tag tag_A, and soc refers to the testbench registration name. In response to the input command, during the verification process, it can be seen that only the stimulus component with the tag tag_A is run.

[0031] For example, the first tag may be a tag of the stimulus component to be run carried in the input command. Taking the input command as bsim -t soc::case_list.yml -tag tag_A as an example, the first tag may be tag_A. The stimulus component may be a piece of code used to verify whether the design of the on-chip network area to which the stimulus component belongs reaches the planned goal.

[0032] For example, the embodiment of the present application only needs to specify the first tag in the input command of the verification platform. The verification platform will extract the first tag carried in the input command, so that based on the first tag, it can find the target second tag that matches the first tag from the stimulus component set, and obtain the target stimulus component carrying the target second tag. It will automatically filter out other stimulus components and only complete the verification of the corresponding stimulus components.

[0033] Step 102: according to the first tag, find a target second tag matching the first tag from a stimulus component set, and obtain a target stimulus component carrying the target second tag; the stimulus component set includes multiple stimulus components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the stimulus component.

[0034] For example, the excitation component set includes multiple excitation components, and each excitation component carries a second tag for describing the on-chip network area corresponding to the excitation component. Taking the on-chip network area including the on-chip network area A and the on-chip network area B as an example, for all excitation components of the on-chip network area A, the corresponding second tag may be tag_A, and for all excitation components of the on-chip network area B, the corresponding second tag may be tag_B. If the first tag includes tag_A, all excitation components of the on-chip network area A are target excitation components, and if the first tag includes tag_B, all excitation components of the on-chip network area B are target excitation components.

[0035] For example, another markup language (YAML, YAML Ain't Markup Language) format can be used to construct an incentive component set, and each incentive component in the incentive component set is constructed into a YAML array, wherein the element of the YAML array is a dictionary constructed in the YAML format, and different second tags are added to the incentive components in the dictionary to distinguish different on-chip network areas. Taking the name of the YAML array of the incentive component as noc_sig_node_chn_snp_test as an example, the elements in the YAML array include: a key-value pair of the incentive component name, a key-value pair of the number of random seeds, and a key-value pair of the second tag. Among them, the key of the incentive component name is v_test, the value of the incentive component name is noc_sig_node_chn_snp, the key of the number of random seeds is seed, the value of the number of random seeds is (1...5), the key of the second tag is tag, and the value of the second tag is tag_A. Of course, in the incentive component set, each incentive component will also have some additional information for controlling verification, configuring EDA tools, etc., which is irrelevant to the content of the incentive component itself. By constructing a second tag in YAML, the verification platform parses the second tag and automatically filters out unnecessary incentive components, saving time in distinguishing incentive components and facilitating project management.

[0036] For example, each incentive component has a tag option, and the value corresponding to the tag option is the value of the second tag. If the second tag is not needed, this option can be omitted. If the second tag of the incentive component has multiple values, they can also be separated by spaces. The YAML array corresponding to the incentive component in the incentive component collection is as follows:

[0037] noc_sig_node_chn_snp_test:

[0038] v_test:noc_sig_node_chn_snp

[0039] seed: (1…5)

[0040] tag: tag_A

[0041] Step 103, during the process of verifying the design file of the network on chip by the verification platform, compile and run the target stimulus component, obtain the verification result of the network on chip area, and complete the verification of the network on chip area.

[0042] For example, bsim is a physics-based software simulation system for testing circuit simulation, which has the characteristics of accuracy, scalability, robustness, language, etc. Electronic Design Automation (EDA) refers to industrial software used to assist in the design of very large-scale integrated circuits, covering the entire process of circuit chip design, manufacturing, packaging and testing.

[0043] For example, the information of the stimulus components in the stimulus component set will be read by bsim, which will sort and classify the information of these stimulus components and finally store them in a hash array for bsim to call the EDA tool for verification. The key of the hash array is the name of the stimulus component, and the value of the hash array is an array containing the number of random seeds and the second label.

[0044] For example, the verification platform reads the incentive component set, filters out the incentive components containing the first label specified by the input command, and puts relevant information such as the name of the incentive component, the number of random seeds, and the second label into the hash, thereby completing the verification of the incentive component with the specified label based on the information in the hash.

[0045] For example, the verification platform supports running the corresponding stimulus component with one click, saving time and labor costs. At the same time, it can automatically filter out the abandoned stimulus components to avoid unnecessary time spent on stimulus components. In addition, it can clearly see the goals achieved by each on-chip network area and warn of delay risks early.

[0046] In summary, in an embodiment of the present application, in response to an input command, based on the first label extracted from the input command, a target second label matching the first label is found from a stimulus component set, and based on the second label used to indicate the on-chip network area corresponding to the stimulus component, the target stimulus component is selected, without manually distinguishing the stimulus components corresponding to the on-chip network area. Therefore, the time spent on distinguishing the stimulus components can be reduced, and the time for acquiring the target stimulus components can be reduced, thereby improving the efficiency of verifying the on-chip network area during the process of verifying the on-chip network area by the verification platform.

[0047] Figure 2 is a flowchart of the specific steps of a verification method for an on-chip network provided in an embodiment of the present application, such as Figure 2 As shown, the method may include:

[0048] Step 201: In response to an input command, extract a first tag carried in the input command.

[0049] This step may specifically refer to the above step 101, which will not be described in detail here.

[0050] For example, the first label includes multiple fields connected in sequence, and the multiple fields are separated by separators; the first field of the multiple fields represents the name of the on-chip network area to which the stimulus component belongs; the last field of the multiple fields represents the usage scenario of the stimulus component; the middle fields except the first field and the last field reflect the names of on-chip network sub-areas of different levels divided by the on-chip network area.

[0051] For example, the first tag may include multiple fields connected in sequence, for example, the first tag may include tag_A and update. Among them, tag_A indicates that the incentive component belongs to the on-chip network area A, and update indicates that the use scenario of the incentive component is update. For another example, the first tag may include tag_A, sub_1, and update. Among them, tag_A indicates that the incentive component belongs to the on-chip network area A, sub_1 indicates that the incentive component belongs to the on-chip network sub-area 1, and update indicates that the use scenario of the incentive component is update.

[0052] For example, if the separator is a space character, if the first tag includes tag_A and update, tag_A and update are separated by a space character, that is, tag_A update. If the first tag includes tag_A, sub_1, and update, tag_A, sub_1, and update are separated by a space character, that is, tag_A sub_1 update.

[0053] Step 202: Find a target second tag matching the first tag from a stimulus component set according to the first tag. The stimulus component set maintains a first stimulus list and a regression list corresponding to a plurality of different on-chip network areas, and the regression list includes a second stimulus list corresponding to a plurality of different on-chip network sub-areas;

[0054] This step may be specifically referred to as the above step 102, which will not be described in detail here.

[0055] For example, the second label includes multiple fields connected in sequence, and the multiple fields are separated by separators; the first field of the multiple fields represents the name of the on-chip network area to which the stimulus component belongs; the last field of the multiple fields represents the usage scenario of the stimulus component; the middle fields except the first field and the last field reflect the names of on-chip network sub-areas of different levels divided by the on-chip network area.

[0056] For example, the second tag may include multiple fields connected in sequence, for example, the second tag may include tag_A and update. Among them, tag_A indicates that the incentive component belongs to the on-chip network area A, and update indicates that the use scenario of the incentive component is update. For another example, the second tag may include tag_A, sub_1 and update. Among them, tag_A indicates that the incentive component belongs to the on-chip network area A, sub_1 indicates that the incentive component belongs to the on-chip network sub-area 1, and update indicates that the use scenario of the incentive component is update.

[0057] For example, if the separator is a space character, if the second tag includes tag_A and update, tag_A and update are separated by a space character, that is, tag_A update. If the second tag includes tag_A, sub_1, and update, tag_A, sub_1, and update are separated by a space character, that is, tag_A sub_1 update.

[0058] Step 203, when specifying the use of the first incentive list, obtain the target name corresponding to the target second label from the first incentive list, and determine the incentive component with the target name as the target incentive component; the first incentive list includes at least one incentive description information; the incentive description information includes: the name of the incentive component and the second label.

[0059] For example, taking the input command bsim -t soc::case_list.yml -tag tag_A as an example, in response to the input command, the input command specifies that the first stimulus list used is the list.yml list, then the target name corresponding to the tag_A tag is obtained from the list.yml list, and the stimulus component with the tag_A tag is determined as the target stimulus component. From the first stimulus list, the target name corresponding to the target second tag is obtained, and the stimulus component with the target name is determined as the target stimulus component. All functions of the on-chip network area to which the target stimulus component belongs can be verified through the target stimulus component, and the on-chip network area can be verified as a whole.

[0060] For example, the first incentive list can be constructed using the YAML format, and each incentive component in the first incentive list can be constructed into a YAML array, wherein the element of the YAML array is a dictionary constructed in the YAML format, and different second tags are added to the incentive components in the dictionary to distinguish different on-chip network areas. Taking the YAML array name of the incentive component as noc_sig_node_chn_snp_test as an example, the first incentive list includes incentive description information including: a key-value pair of the incentive component name, a key-value pair of the random seed number, and a key-value pair of the second tag. Among them, the key of the incentive component name is v_test, the value of the incentive component name is noc_sig_node_chn_snp, the key of the random seed number is seed, the value of the random seed number is (1…5), the key of the second tag is tag, and the value of the second tag is tag_A. Of course, in the first incentive list, each incentive component will also have some additional information for controlling verification, configuring EDA tools, etc., which is irrelevant to the content of the incentive component itself. By constructing a second tag in YAML, the verification platform parses the second tag and automatically filters out unnecessary incentive components, saving time in distinguishing incentive components and facilitating project management.

[0061] Optionally, before step 203, the method further includes:

[0062] Sub-step 2031, generating at least one excitation component for each of the on-chip network areas, and generating a second label carrying the name of the on-chip network area for each of the excitation components;

[0063] Sub-step 2032: Create a corresponding first stimulus list for each of the NOC areas, and add the name of the stimulus component and the second label to the first stimulus list corresponding to the NOC area to which the stimulus component belongs.

[0064] For sub-steps 2031 and 2032, when designing each on-chip network area, at least one stimulus component is generated, and a second tag carrying the name of the on-chip network area is generated for each stimulus component, which is used to subsequently verify whether the design of the on-chip network area has achieved the planned goal. For example, when designing on-chip network area A, at least one stimulus component is generated, and a second tag carrying tag_A is generated for each stimulus component, which is used to subsequently verify on-chip network area A to determine whether the design of on-chip network area A has achieved the planned goal.

[0065] For example, after generating an incentive component and a corresponding second label for an on-chip network area, a corresponding first incentive list is established for each on-chip network area, and the name of the incentive component and the second label are added to the first incentive list corresponding to the on-chip network area to which the incentive component belongs. For example, the first incentive list is a list.yml list, and a correspondence between the name of the incentive component and the second label can be established, and the correspondence between the name of the incentive component and the second label can be added to the list.yml list. For another example, a key-value pair of the name of the incentive component and a key-value pair of the second label can be added to the list.yml list.

[0066] Optionally, sub-step 2032 may specifically include:

[0067] Sub-step 20321, in the first stimulus list corresponding to the on-chip network area to which the stimulus component belongs, adding a name parameter and a label parameter for the stimulus component;

[0068] Sub-step 20322, modifying the default value of the name parameter of the stimulus component to the name of the stimulus component;

[0069] Sub-step 20323, modifying the default value of the label parameter of the stimulus component to the second label.

[0070] For sub-steps 20321 to 20323, the stimulus component name parameter is v_test, and the stimulus component tag parameter is tag. After obtaining the name of the stimulus component and the second tag of the stimulus component, the default value of the stimulus component name parameter is modified to the name of the stimulus component, and the default value of the stimulus component tag parameter is modified to the second tag. For example, if the stimulus component name is noc_sig_node_chn_snp, and the second tag of the stimulus component is tag_A, the value of the stimulus component name parameter is modified to noc_sig_node_chn_snp, and the value of the stimulus component tag parameter is modified to tag_A.

[0071] Step 204, when specifying the use of the regression list, obtain the target name corresponding to the target second label from the second stimulus list, and determine the stimulus component with the target name as the target stimulus component; the second stimulus list includes at least one stimulus description information; the stimulus description information includes: the name of the stimulus component and the second label.

[0072] For example, taking the input command bsim -t soc::full.yml -tag Release_Q0 as an example, in response to the input command, the input command specifies that the regression list to be used is the full.yml list, then the target name corresponding to the Release_Q0 tag is obtained from the full.yml list, and the stimulus component with the Release_Q0 tag is determined as the target stimulus component.

[0073] Taking the regression list including: the second stimulus list noc_engine_single_input.yml, the second stimulus list noc_engine_vip_smoke.yml, the second stimulus list noc_engine_smoke.yml and the second stimulus list noc_sig_node_chn.yml as an example, when the input command specifies that the regression list to be used is the full.yml list, the target name corresponding to the Release_Q0 label is obtained from each second stimulus list, and the stimulus components with the Release_Q0 label in each second stimulus list are determined as target stimulus components.

[0074] For example, the regression list full.yml list can be as follows:

[0075] Regression:

[0076] -noc_engine_single_input.yml

[0077] -noc_engine_vip_smoke.yml

[0078] -noc_engine_smoke.yml

[0079] -noc_sig_node_chn.yml

[0080] For example, the second incentive list can be constructed using the YAML format, and each incentive component in the second incentive list is constructed into a YAML array, wherein the element of the YAML array is a dictionary constructed in the YAML format, and different second tags are added to the incentive components in the dictionary to distinguish different on-chip network areas. Taking the YAML array name of the incentive component as noc_sig_node_chn_snp_test as an example, the second incentive list includes incentive description information including: a key-value pair of the incentive component name, a key-value pair of the number of random seeds, and a key-value pair of the second tag. Among them, the key of the incentive component name is v_test, the value of the incentive component name is noc_sig_node_chn_snp, the key of the number of random seeds is seed, the value of the number of random seeds is (1…5), the key of the second tag is tag, and the value of the second tag is tag_A. Of course, in the second incentive list, each incentive component will also have some additional information for controlling verification, configuring EDA tools, etc., which is irrelevant to the content of the incentive component itself. By constructing a second tag in YAML, the verification platform parses the second tag and automatically filters out unnecessary incentive components, saving time in distinguishing incentive components and facilitating project management.

[0081] For example, if the full.yml list is specified during verification, then with the -tag option, all stimulus components with the specified tag in the regression list can be run. For example, to run all stimulus components with the Release_Q0 tag, enter the command: bsim -t tb_name::full.yml -tag Release_Q0. When you need to run stimulus components with common characteristics in multiple on-chip network sub-areas, you can obtain the target stimulus components through the regression list to verify the specific functions of multiple on-chip network sub-areas, which can improve verification efficiency.

[0082] Optionally, before step 204, the method further includes:

[0083] Sub-step 2041, generating at least one excitation component for each of the on-chip network sub-areas, and determining a usage scenario description text for each of the excitation components;

[0084] Sub-step 2042, generating a second label for each of the excitation components; the second label carries the name of the on-chip network sub-area and the name of the usage scenario description text;

[0085] Sub-step 2043, establishing a corresponding second stimulus list for each of the NOC sub-areas, and adding the name of the stimulus component and the second label to the second stimulus list corresponding to the NOC sub-area to which the stimulus component belongs;

[0086] Sub-step 2044, aggregate all the second excitation lists into the regression list.

[0087] For sub-steps 2041 to 2044, when designing each on-chip network sub-area, at least one stimulus component is generated, and a second label carrying the name of the on-chip network sub-area and the name of the usage scenario description text is generated for each stimulus component, which is used to subsequently verify whether the design of the on-chip network area has achieved the planned goal. For example, when designing on-chip network sub-area 1, at least one stimulus component is generated, and a second label carrying sub_1 and update is generated for each stimulus component, which is used to subsequently verify on-chip network sub-area 1 to determine whether the design of on-chip network sub-area 1 has achieved the planned goal.

[0088] For example, after generating an incentive component and a corresponding second label for an on-chip network sub-area, a corresponding second incentive list is established for each on-chip network sub-area, and the name of the incentive component and the second label are added to the second incentive list corresponding to the on-chip network sub-area to which the incentive component belongs. For example, the second incentive list is a noc_sig_node_chn.yml list, and a correspondence between the name of the incentive component and the second label can be established, and the correspondence between the name of the incentive component and the second label can be added to the noc_sig_node_chn.yml list. For another example, a key-value pair of the name of the incentive component and a key-value pair of the second label can be added to the noc_sig_node_chn.yml list.

[0089] Optionally, sub-step 2043 may specifically include:

[0090] Sub-step 20431, in the second stimulus list corresponding to the on-chip network sub-slice to which the stimulus component belongs, adding a name parameter and a label parameter for the stimulus component;

[0091] Sub-step 20432, modifying the default value of the name parameter of the stimulus component to the name of the stimulus component;

[0092] Sub-step 20433: modify the default value of the label parameter of the stimulus component to the second label, and separate the name of the on-chip network sub-area contained in the second label and the name of the usage scenario description text with a separator.

[0093] For sub-steps 20431 to 20433, the stimulus component name parameter is v_test, the stimulus component tag parameter is tag, and after obtaining the name of the stimulus component and the second tag of the stimulus component, the default value of the stimulus component name parameter is modified to the name of the stimulus component, the default value of the stimulus component tag parameter is modified to the second tag, and the name of the on-chip network sub-area contained in the second tag, sub_1, and the name of the usage scenario description text, update, are separated by a space character. For example, if the stimulus component name is noc_sig_node_chn_pub, the second tag of the stimulus component is sub_1update, the value of the stimulus component name parameter is modified to noc_sig_node_chn_pub, and the value of the stimulus component tag parameter is modified to sub_1 update.

[0094] Step 205, in the process of verifying the design file of the network on chip by the verification platform, compile and run the target stimulus component, obtain the verification result of the network on chip area, and complete the verification of the network on chip area.

[0095] This step may be specifically referred to as the above step 104, which will not be described in detail here.

[0096] Optionally, the method further includes:

[0097] Step 206: If the input command does not include the first tag, all stimulus components in the NoC area indicated by the input command are determined as the target stimulus components.

[0098] For example, taking the input command bsim -t soc::full.yml as an example, the input command does not include the first tag, and all stimulus components in the full.yml list are determined as target stimulus components.

[0099] In summary, in an embodiment of the present application, in response to an input command, based on the first label extracted from the input command, a target second label matching the first label is found from a stimulus component set, and based on the second label used to indicate the on-chip network area corresponding to the stimulus component, the target stimulus component is selected, without manually distinguishing the stimulus components corresponding to the on-chip network area. Therefore, the time spent on distinguishing the stimulus components can be reduced, and the time for acquiring the target stimulus components can be reduced, thereby improving the efficiency of verifying the on-chip network area during the process of verifying the on-chip network area by the verification platform.

[0100] Figure 3 is a block diagram of a network-on-chip verification device 30 provided in an embodiment of the present application, the device comprising:

[0101] An extraction module 301 is used to extract a first tag carried in the input command in response to the input command;

[0102] The acquisition module 302 is used to find a target second tag matching the first tag from the excitation component set according to the first tag, and acquire a target excitation component carrying the target second tag; the excitation component set includes multiple excitation components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the excitation component;

[0103] The verification module 303 is used to compile and run the target stimulus component during the process of verifying the design file of the on-chip network on the verification platform, obtain the verification result of the on-chip network area, and complete the verification of the on-chip network area.

[0104] Optionally, the device further comprises:

[0105] The first determination module is configured to determine all the stimulus components in the network-on-chip area indicated by the input command as the target stimulus components if the input command does not include the first tag.

[0106] Optionally, the first label and the second label include multiple fields connected in sequence, and the multiple fields are separated by separators; the first field of the multiple fields represents the name of the on-chip network area to which the stimulus component belongs; the last field of the multiple fields represents the usage scenario of the stimulus component; the middle fields except the first field and the last field reflect the names of on-chip network sub-areas of different levels divided by the on-chip network area.

[0107] Optionally, the stimulus component set maintains first stimulus lists and regression lists corresponding to a plurality of different on-chip network areas, the regression list includes second stimulus lists corresponding to a plurality of different on-chip network sub-areas; the first stimulus list and the second stimulus list both include at least one stimulus description information; the stimulus description information includes: the name of the stimulus component and a second label;

[0108] The acquisition module comprises:

[0109] A first acquisition submodule is used to acquire a target name corresponding to the target second label from the first stimulus list when specifying to use the first stimulus list, and determine the stimulus component with the target name as the target stimulus component;

[0110] The second acquisition submodule is used to acquire the target name corresponding to the target second label from the second stimulus list when specifying to use the regression list, and determine the stimulus component with the target name as the target stimulus component.

[0111] Optionally, the device further comprises:

[0112] A first generating module, configured to generate at least one excitation component for each of the network on chip areas, and to generate a second label carrying the name of the network on chip area for each of the excitation components;

[0113] The first adding module is used to establish a corresponding first stimulus list for each of the on-chip network areas, and add the name of the stimulus component and the second label into the first stimulus list corresponding to the on-chip network area to which the stimulus component belongs.

[0114] Optionally, the first adding module includes:

[0115] A first adding submodule is used to add a name parameter and a label parameter for the stimulus component in a first stimulus list corresponding to the on-chip network area to which the stimulus component belongs;

[0116] A first modification submodule, used to modify a default value of a name parameter of the stimulus component to a name of the stimulus component;

[0117] The second modification submodule is used to modify the default value of the label parameter of the stimulus component to the second label.

[0118] Optionally, the device further comprises:

[0119] A second determination module is used to generate at least one excitation component for each of the on-chip network sub-areas, and determine a usage scenario description text for each of the excitation components;

[0120] A second generating module, configured to generate a second label for each of the excitation components; the second label carries the name of the on-chip network sub-area and the name of the usage scenario description text;

[0121] A second adding module is used to establish a corresponding second stimulus list for each of the on-chip network sub-areas, and add the name of the stimulus component and the second label to the second stimulus list corresponding to the on-chip network sub-area to which the stimulus component belongs;

[0122] A summarizing module is used to summarize all the second stimulus lists into the regression list.

[0123] Optionally, the second adding module includes:

[0124] A second adding submodule is used to add a name parameter and a label parameter for the stimulus component in a second stimulus list corresponding to the on-chip network sub-area to which the stimulus component belongs;

[0125] A third modification submodule, used to modify the default value of the name parameter of the stimulus component to the name of the stimulus component;

[0126] The fourth modification submodule is used to modify the default value of the label parameter of the excitation component to the second label, and separate the name of the on-chip network sub-area contained in the second label and the name of the usage scenario description text with a separator.

[0127] In summary, in an embodiment of the present application, in response to an input command, based on the first label extracted from the input command, a target second label matching the first label is found from a stimulus component set, and based on the second label used to indicate the on-chip network area corresponding to the stimulus component, the target stimulus component is selected, without manually distinguishing the stimulus components corresponding to the on-chip network area. Therefore, the time spent on distinguishing the stimulus components can be reduced, and the time for acquiring the target stimulus components can be reduced, thereby improving the efficiency of verifying the on-chip network area during the process of verifying the on-chip network area by the verification platform.

[0128] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0129] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0130] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0131] An embodiment of the present application provides a verification device for a network on chip, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the above embodiments.

[0132] Figure 4 4 is a block diagram of an electronic device 400 provided in an embodiment of the present application. For example, the electronic device 400 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0133] Reference Figure 4, the electronic device 400 may include one or more of the following components: a processing component 402 , a memory 404 , a power component 406 , a multimedia component 408 , an audio component 410 , an input / output (I / O) interface 412 , a sensor component 414 , and a communication component 416 .

[0134] The processing component 402 generally controls the overall operation of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 402 may include one or more modules to facilitate the interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate the interaction between the multimedia component 408 and the processing component 402.

[0135] The memory 404 is used to store various types of data to support the operation of the electronic device 400. Examples of such data include instructions for any application or method operating on the electronic device 400, contact data, phone book data, messages, pictures, multimedia, etc. The memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0136] The power supply component 406 provides power to the various components of the electronic device 400. The power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 400.

[0137] The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0138] The audio component 410 is used to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC), and when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 404 or sent via the communication component 416. In some embodiments, the audio component 410 also includes a speaker for outputting audio signals.

[0139] The input / output interface 412 provides an interface between the processing component 402 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0140] The sensor assembly 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor assembly 414 can detect the open / closed state of the electronic device 400, the relative positioning of the components, such as the display and keypad of the electronic device 400, and the sensor assembly 414 can also detect the position change of the electronic device 400 or a component of the electronic device 400, the presence or absence of contact between the user and the electronic device 400, the orientation or acceleration / deceleration of the electronic device 400, and the temperature change of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 414 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0141] The communication component 416 is used to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 416 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 416 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0142] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0143] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, and the instructions can be executed by a processor 420 of an electronic device 400 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0144] Figure 5 is a block diagram of another electronic device 500 provided in an embodiment of the present application. For example, the electronic device 500 may be provided as a server. Figure 5 , the electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions that can be executed by the processing component 522, such as an application. The application stored in the memory 532 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0145] The electronic device 500 may further include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0146] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0147] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0148] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A verification method for a network on chip, characterized in that: The method comprises: In response to an input command, extracting a first tag carried in the input command; According to the first tag, a target second tag matching the first tag is found from a stimulus component set, and a target stimulus component carrying the target second tag is obtained; the stimulus component set includes a plurality of stimulus components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the stimulus component; In the process of verifying the design file of the on-chip network by the verification platform, the target stimulus component is compiled and run to obtain the verification result of the on-chip network area, and the verification of the on-chip network area is completed.

2. The method according to claim 1, characterized in that The method further comprises: If the input command does not include the first tag, all the stimulus components in the on-chip network area indicated by the input command are determined as the target stimulus components.

3. The method according to claim 1, characterized in that The first label and the second label include multiple fields connected in sequence, and the multiple fields are separated by separators; the first field of the multiple fields represents the name of the on-chip network area to which the stimulus component belongs; the last field of the multiple fields represents the usage scenario of the stimulus component; the middle fields except the first field and the last field reflect the names of the on-chip network sub-areas of different levels divided by the on-chip network area.

4. The method according to claim 1, characterized in that The stimulus component set maintains first stimulus lists and regression lists corresponding to a plurality of different on-chip network areas, respectively, and the regression list includes second stimulus lists corresponding to a plurality of different on-chip network sub-areas, respectively; The first incentive list and the second incentive list both include at least one incentive description information; The incentive description information includes: the name of the incentive component and the second tag; The step of obtaining a target excitation component carrying the target second tag includes: When specifying to use the first stimulus list, obtaining a target name corresponding to the target second label from the first stimulus list, and determining a stimulus component having the target name as the target stimulus component; When specifying to use the regression list, a target name corresponding to the target second label is obtained from the second stimulus list, and a stimulus component having the target name is determined as the target stimulus component.

5. The method according to claim 4, characterized in that Before acquiring the target name corresponding to the target second tag from the first stimulus list, the method further includes: Generating at least one excitation component for each of the on-chip network areas, and generating a second label carrying the name of the on-chip network area for each of the excitation components; A corresponding first stimulus list is established for each of the on-chip network areas, and the name of the stimulus component and the second label are added to the first stimulus list corresponding to the on-chip network area to which the stimulus component belongs.

6. The method according to claim 5, characterized in that The step of adding the name of the stimulus component and the second label into a first stimulus list corresponding to the on-chip network area to which the stimulus component belongs includes: In the first stimulus list corresponding to the on-chip network area to which the stimulus component belongs, adding a name parameter and a label parameter for the stimulus component; Modify the default value of the name parameter of the stimulus component to the name of the stimulus component; The default value of the label parameter of the stimulus component is modified to the second label.

7. The method according to claim 4, characterized in that Before acquiring the target name corresponding to the target second label from the second stimulus list, the method further includes: Generate at least one excitation component for each of the on-chip network sub-areas, and determine a usage scenario description text for each of the excitation components; Generate a second label for each of the stimulus components; the second label carries the name of the on-chip network sub-area and the name of the usage scenario description text; Establishing a corresponding second stimulus list for each of the on-chip network sub-areas, and adding the name of the stimulus component and the second label to the second stimulus list corresponding to the on-chip network sub-area to which the stimulus component belongs; All of the second stimulus lists are aggregated into the regression list.

8. The method according to claim 7, characterized in that The step of adding the name of the stimulus component and the second label into a second stimulus list corresponding to the on-chip network sub-area to which the stimulus component belongs includes: In the second stimulus list corresponding to the on-chip network sub-slice to which the stimulus component belongs, adding a name parameter and a label parameter for the stimulus component; Modify the default value of the name parameter of the stimulus component to the name of the stimulus component; The default value of the label parameter of the excitation component is modified to the second label, and the name of the on-chip network sub-area contained in the second label and the name of the usage scenario description text are separated by a separator.

9. A verification device for a network on chip, characterized in that: include: an extraction module, configured to extract, in response to an input command, a first tag carried in the input command; An acquisition module is used to find a target second tag matching the first tag from a stimulus component set according to the first tag, and acquire a target stimulus component carrying the target second tag; the stimulus component set includes a plurality of stimulus components, each of which carries a second tag; the second tag is used to describe the on-chip network area corresponding to the stimulus component; The verification module is used to compile and run the target stimulus component during the process of verifying the design file of the on-chip network on the verification platform, obtain the verification result of the on-chip network area, and complete the verification of the on-chip network area.

10. An electronic device, characterized in that: The invention comprises a processor, a memory and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the verification method of the network on chip as claimed in any one of claims 1 to 8.

11. A readable storage medium, characterized in that: The readable storage medium stores a program or an instruction, and when the program or the instruction is executed by a processor, the steps of the on-chip network verification method according to any one of claims 1 to 8 are implemented.

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