Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, and relates to the technical field of display, and the layout design of a pixel circuit is better. The display panel comprises a substrate and a pixel circuit located on one side of the substrate. The pixel circuit comprises a driving transistor; the grid electrode of the data writing transistor is electrically connected with the first scanning line, the first electrode is electrically connected with the data line, and the second electrode is electrically connected with the first electrode of the driving transistor; the grid electrode of the anode reset transistor is electrically connected with the first scanning line, the first pole is electrically connected with the reset line, and the second pole is electrically connected with the light-emitting element; wherein the anode reset transistor and the data write-in transistor of the same pixel circuit are electrically connected with the same first scanning line.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes a pixel circuit and a light-emitting element, wherein the layout design of the pixel circuit is a key factor affecting circuit performance, display panel resolution, etc. Therefore, how to further optimize the layout design of the pixel circuit has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device, wherein the layout design of pixel circuits is better.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including a substrate and a pixel circuit located on one side of the substrate, wherein the pixel circuit includes: Driver transistor; a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the first scanning line, a first electrode is electrically connected to the data line, and a second electrode is electrically connected to the first electrode of the driving transistor; an anode reset transistor, wherein a gate of the anode reset transistor is electrically connected to the first scan line, a first electrode is electrically connected to the reset line, and a second electrode is electrically connected to the light emitting element; The anode reset transistor and the data writing transistor of the same pixel circuit are electrically connected to the same first scanning line.

[0005] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0006] The technical solution provided by the embodiment of the present invention has the following beneficial effects: In the related art, the first scanning signal received by the previous pixel row is the same as the second scanning signal received by the next pixel row. When both the anode reset transistor and the data write transistor in the pixel circuit receive the first scanning signal, the data write transistor is connected to the first scanning line corresponding to the pixel row, and the anode reset transistor is placed at the next pixel row position to be connected to the second scanning line corresponding to the next pixel row.

[0007] The embodiment of the present invention changes the connection method between the anode reset transistor and the scan line, so that the anode reset transistor is connected to the first scan line corresponding to the pixel row, that is, the aforementioned "the anode reset transistor and the data writing transistor of the same pixel circuit are electrically connected to the same first scan line".

[0008] In this connection mode, the anode reset transistor and the data writing transistor in the same pixel circuit are located on the same side of the driving transistor, and the anode reset transistor and other transistors in the pixel circuit are arranged more compactly, which can not only compress the layout space of the pixel circuit 2 and improve the PPI, but also reduce the length of the connection line between the anode reset transistor M3 and other transistors in the pixel circuit, thereby reducing the signal voltage drop. Moreover, with the above design, the second scan line corresponding to the current pixel row only needs to be used to provide the second scan signal to the current pixel row, and no longer needs to be used to provide the first scan signal to the previous pixel row, so the limitation between the first scan signal and the second scan signal can be eliminated, and the timing of the first scan signal and the second scan signal can be the same or different, and the design flexibility will be higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention; Figure 3 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention; Figure 4 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention; Figure 5 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention; Figure 6 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Figure 7 for Figure 6 A cross-sectional view along the A1-A2 direction; Figure 8 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig. 9 for Figure 8 A cross-sectional view along the B1-B2 direction; Fig.10 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.11A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.12 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.13 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.14 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.15 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.16 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention; Fig.17 A schematic diagram of a structure of a display panel in the related art; Fig.18 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention; Fig.19 A comparison diagram of the arrangement of data lines provided in an embodiment of the present invention; Fig. 20 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.21 Another structural comparison diagram of a data line provided by an embodiment of the present invention; Fig. 22 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.23 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.24 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.25 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.26 for Fig.25 A cross-sectional view along the C1-C2 direction; Fig. 27 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.28 Another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention; Fig.29 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention; Fig.30A schematic diagram of another structure of a display panel provided by an embodiment of the present invention; Fig.31 A schematic diagram of another film structure adhesive for a display panel provided by an embodiment of the present invention; Fig.32 for Figure 3 A schematic diagram of the structure of the corresponding semiconductor layer; Fig.33 for Figure 3 A schematic structural diagram of the corresponding first metal layer; Fig.34 for Figure 3 A schematic structural diagram of the corresponding second metal layer; Fig.35 for Figure 3 A schematic diagram of the structure of the corresponding third metal layer; Fig.36 for Figure 3 A schematic structural diagram of the corresponding fourth metal layer; Fig.37 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0014] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0015] An embodiment of the present invention provides a display panel, which may be a light-emitting diode (LED) display panel, such as a micro LED display panel.

[0016] like Figure 1 As shown, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present invention. The display panel includes a substrate 1 and a pixel circuit 2 located on one side of the substrate 1 .

[0017] like Figure 2~Figure 4 As shown, Figure 2 A schematic diagram of a circuit structure of a pixel circuit 2 provided in an embodiment of the present invention is shown in FIG. Figure 3 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention, Figure 4 Another schematic diagram of the film structure of the display panel provided in an embodiment of the present invention, the pixel circuit 2 includes a driving transistor M1, a data writing transistor M2 and an anode reset transistor M3. Among them, the gate of the data writing transistor M2 is electrically connected to the first scan line Scan1, the first electrode is electrically connected to the data line Data, and the second electrode is electrically connected to the first electrode of the driving transistor M1. The gate of the anode reset transistor M3 is electrically connected to the first scan line Scan1, the first electrode is electrically connected to the reset line Ref, and the second electrode is electrically connected to the light emitting element 3.

[0018] The anode reset transistor M3 and the data writing transistor M2 of the same pixel circuit 2 are electrically connected to the same first scanning line Scan1.

[0019] See also Figure 2~Figure 4 The pixel circuit 2 further includes a gate reset module 4, a control end of the gate reset module 4 is electrically connected to the second scan line Scan2, a first end of the gate reset module 4 is electrically connected to the reset line Ref, and a second end of the gate reset module 4 is electrically connected to the gate of the driving transistor M1.

[0020] In the related art, the first scanning signal received by the previous pixel row is the same as the second scanning signal received by the next pixel row. When both the anode reset transistor M3 and the data write transistor M2 in the pixel circuit 2 receive the first scanning signal, the data write transistor M2 is connected to the first scanning line Scan1 corresponding to the pixel row, and the anode reset transistor M3 is placed at the next pixel row position to be connected to the second scanning line Scan2 corresponding to the next pixel row.

[0021] However, in the embodiment of the present invention, the connection method between the anode reset transistor M3 and the scan line is changed, so that the anode reset transistor M3 is connected to the first scan line Scan1 corresponding to the pixel row, that is, the aforementioned "the anode reset transistor M3 and the data writing transistor M2 of the same pixel circuit 2 are electrically connected to the same first scan line Scan1".

[0022] In this connection mode, see Figure 3 and Figure 4 , the anode reset transistor M3 and the data writing transistor M2 in the same pixel circuit 2 are located on the same side of the driving transistor M1, and the anode reset transistor M3 and other transistors in the pixel circuit 2 are arranged more compactly, which can not only compress the layout space of the pixel circuit 2 and improve the PPI, but also reduce the length of the connection line between the anode reset transistor M3 and other transistors in the pixel circuit, thereby reducing the signal voltage drop. Moreover, with the above design, the second scan line Scan2 corresponding to the current pixel row only needs to be used to provide the second scan signal to the current pixel row, and no longer needs to be used to provide the first scan signal to the previous pixel row, so the limitation between the first scan signal and the second scan signal can be eliminated, and the timing of the first scan signal and the second scan signal can be the same or different, and the design flexibility will be higher.

[0023] Regarding the above-mentioned “the arrangement of the anode reset transistor M3 and other transistors in the pixel circuit 2 can be more compact”, in a specific structure, see Figure 2 and Figure 4 The pixel circuit further includes a second light emission control transistor M7, and a second electrode of the second light emission control transistor M7 is electrically connected to the light emitting element 3. Based on the above design, the anode reset transistor M3 is relatively close to the second light emission control transistor M7. When the anode reset transistor M3 is electrically connected to the second light emission control transistor M7 via a connection wire 60 located in the semiconductor layer s1 or a certain metal layer, the connection wire 60 can be designed to be shorter, thereby saving layout space to a certain extent and reducing the voltage drop of the signal during transmission.

[0024] In addition, the embodiments of the present invention can also be applied to transparent display. Figure 1 and Figure 3 , the display panel is a transparent display panel, and the display panel also includes a light-transmitting area 5. By adopting the above technical solution, it is possible to compress the layout space of the pixel circuit 2, thereby releasing a part of the area as the light-transmitting area 5, so as to increase the transmittance of the display panel. Furthermore, because the anode reset transistor M3 is located in the area where the pixel row is located, when the anode reset transistor M3 is connected to the second light-emitting control transistor M7 through the connecting wire 60, the connecting wire 60 does not need to cross the interval between two adjacent pixel rows, so it does not occupy the light-transmitting area, which can further increase the transmittance.

[0025] In a possible implementation, combining Figure 2 ,like Figure 5 As shown, Figure 5This is another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, wherein the pixel circuit 2 further includes a gate reset module 4, and the gate reset module 4 includes a first reset transistor M41 and a second reset transistor M42. The gate of the first reset transistor M41 and the gate of the second reset transistor M42 are both electrically connected to the second scan line Scan2, the first electrode of the first reset transistor M41 is electrically connected to the reset line Ref, the second electrode of the first reset transistor M41 is electrically connected to the first electrode of the second reset transistor M42 through the first connection line 6, and the second electrode of the second reset transistor M42 is electrically connected to the gate of the driving transistor M1.

[0026] The first scan line Scan1 and the second scan line Scan2 extend along the first direction x.

[0027] The reset line Ref includes a first sub-reset line Ref1 extending along the first direction x and located on a side of the second scan line Scan2 away from the first scan line Scan1. The first sub-reset line Ref1 overlaps the first connection line 6 in a direction perpendicular to the plane of the substrate 1.

[0028] The first sub-reset line Ref1 transmits a reset signal, which is a DC constant voltage signal. By overlapping the first sub-reset line Ref1 with the first connection line 6, the first sub-reset line Ref1 can act as a shielding metal for the first connection line 6, stabilize the potential of the intermediate node of the first reset transistor M41 and the second reset transistor M42, and thus reduce the influence of the leakage current of the gate reset module 4 on the stability of the gate potential of the driving transistor M1. On the other hand, under the condition that the line width of the first sub-reset line Ref1 is certain, the first sub-reset line Ref1 overlaps with the first connection line 6, which means that the first sub-reset line Ref1 is close to the second scan line Scan2, so that the layout space required to be occupied by the pixel circuit 2 and the signal line as a whole in the second direction y can be reduced, thereby improving the PPI. Among them, the second direction y intersects with the first direction x.

[0029] In addition, when the embodiment of the present invention is applied to a transparent display, see Figure 1 and Figure 3 , the display panel also includes a light-transmitting area 5. Based on the above structure, the layout space required to be occupied by the pixel circuit 2 and the signal line in the second direction y as a whole can be reduced, so a part of the space in the second direction y can be released as the light-transmitting area 5, in other words, the size of the light-transmitting area 5 in the second direction y can be increased, the light-transmitting area is increased, and the display panel has a sufficiently high transmittance.

[0030] In a possible implementation, combining Figure 2 and Figure 5The pixel circuit 2 further includes a threshold compensation module 7, which includes a first compensation transistor M51 and a second compensation transistor M52. The gate of the first compensation transistor M51 and the gate of the second compensation transistor M52 are both electrically connected to the first scan line Scan1, the first electrode of the first compensation transistor M51 is electrically connected to the second electrode of the driving transistor M1, the second electrode of the first compensation transistor M51 is electrically connected to the first electrode of the second compensation transistor M52 through the second connection line 8, and the second electrode of the second compensation transistor M52 is electrically connected to the gate of the driving transistor M1.

[0031] The anode reset transistors M3 in at least some of the pixel circuits 2 are electrically connected to the first sub-reset line Ref1 through the third connection line 9 , and the third connection line 9 overlaps the second connection line 8 in a direction perpendicular to the plane where the substrate 1 is located.

[0032] The third connection line 9 is used as a connection line between the anode reset transistor M3 and the first sub-reset line Ref1, and transmits a stable DC constant voltage signal. The third connection line 9 overlaps with the second connection line 8, and the third connection line 9 also serves as a shielding metal of the second connection line 8 to stabilize the potential of the intermediate node between the first compensation transistor M51 and the second compensation transistor M52, thereby reducing the influence of the leakage current of the threshold compensation module on the gate potential stability of the driving transistor M1.

[0033] In the embodiment of the present invention, the pixel circuit 2 where the anode reset transistor M3 connected to the third connection line 9 is located and the pixel circuit 2 where the overlapping second connection line 8 is located can be the same pixel circuit 2 or different pixel circuits 2.

[0034] For example, see Figure 5 For the same third connection line 9, the pixel circuit 2 where the anode reset transistor M3 connected thereto is located and the pixel circuit 2 where the second connection line 8 overlapped therewith is located are adjacent in the first direction x.

[0035] In other words, the anode reset transistor M3 connected to the third connection line 9 is located in one pixel circuit 2, and the second connection line 8 overlapped by the third connection line 9 is located in another pixel circuit 2, and these two pixel circuits 2 are adjacent to each other in the first direction x.

[0036] For example, see Figure 5 The pixel circuit 2 includes a first pixel circuit 2-1, a second pixel circuit 2-2 and a third pixel circuit 2-3, and the second pixel circuit 2-2 is located between the first pixel circuit 2-1 and the third pixel circuit 2-3. Figure 5Two third connection lines 9 are schematically shown. For one of the third connection lines 9, the anode reset transistor M3 connected to the third connection line 9 is located in the second pixel circuit 2-2, and the second connection line 8 overlapped by the third connection line 9 is located in the first pixel circuit 2-1; for the other third connection line, the anode reset transistor M3 connected to the third connection line 9 is located in the third pixel circuit 2-3, and the second connection line 8 overlapped by the third connection line 9 is located in the second pixel circuit 2-2.

[0037] In other words, the pixel circuit 2 where the anode reset transistor M3 connected to the third connection line 9 is located is defined as the first circuit corresponding to the third connection line 9, and the pixel circuit 2 where the second connection line 8 overlapped by the third connection line 9 is located is defined as the second circuit corresponding to the third connection line 9; the first circuit and the second circuit corresponding to the same third connection line 9 are adjacent in the first direction x.

[0038] For example, see Figure 5 The first circuit corresponding to one third connection line 9 is the second pixel circuit 2-2, and the corresponding second circuit is the first pixel circuit 2-1; the first circuit corresponding to another third connection line is the third pixel circuit 2-3, and the corresponding second circuit is the second pixel circuit 2-2.

[0039] In this configuration, after the third connection line 9 is led out from the anode reset transistor M3 of a certain pixel circuit 2, it only needs to extend along the first direction x to the second connection line 8 in the adjacent pixel circuit 2, and after overlapping with the second connection line 8, it can turn upward to connect with the first sub-reset line Ref1. Figure 5 Taking the third connection line 9 electrically connected to the anode reset transistor M3 in the second pixel circuit 2-2 as an example, the third connection line 9 is led out from the anode reset transistor M3 of the second pixel circuit 2-2, extends along the first direction x to the second connection line 8 in the first pixel circuit 2-1, and after overlapping with the second connection line 8, it can turn upward to connect with the first sub-reset line Ref1. The extension length of the third connection line 9 under this structure is small, the load is correspondingly small, and the signal voltage drop is also reduced.

[0040] Regarding the film layer position of the third connecting line 9, in a feasible implementation manner, as Figure 6 and Figure 7 As shown, Figure 6 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Figure 7 for Figure 6 A cross-sectional view along the A1-A2 direction, the display panel includes a semiconductor layer sl, a first metal layer m1 located on a side of the semiconductor layer sl away from the substrate 1, a second metal layer mc located on a side of the first metal layer m1 away from the substrate 1, and a third metal layer m2 located on a side of the second metal layer mc away from the substrate 1.

[0041] The first connection line 6 and the second connection line 8 are located in the semiconductor layer s1, the gate of the driving transistor M1 is located in the first metal layer m1, and the first sub-reset line Ref1 is located in the second metal layer mc.

[0042] The third connection line 9 includes a first sub-portion 10 and a second sub-portion 11, wherein the first sub-portion 10 is connected to the first sub-reset line Ref1, and the second sub-portion 11 is connected between the first sub-portion 10 and the anode reset transistor M3. The first sub-portion 10 is located in the second metal layer mc, the second sub-portion 11 is located in the third metal layer m2, and the first sub-portion 10 overlaps with the second connection line 8 in a direction perpendicular to the plane where the substrate 1 is located.

[0043] In the current film layer design of the display panel, compared with the first metal layer m1 and the second metal layer mc, the third metal layer m2 has a larger film thickness, and the resistance of the metal material used is lower. For example, the third metal layer m2 is a stacked structure of titanium, aluminum and titanium. Therefore, the impedance of the third metal layer m2 will be lower.

[0044] In the embodiment of the present invention, the third connection line 9 is made of two layers of metal. The third connection line 9 includes a first sub-section 10 and a second sub-section 11 of different layers. The first sub-section 10 is connected to the first sub-reset line Ref1 and overlaps with the second connection line 8. The first sub-section 10 is located in the second metal layer mc. Firstly, it can be directly connected to the first sub-reset line Ref1 without punching holes for connection. Secondly, the film layer spacing between the first sub-section 10 and the second connection line 8 can be reduced, thereby achieving a better effect on stabilizing the potential of the second connection line 8. Furthermore, the first sub-section 10 is also switched to the second sub-section 11, and the second sub-section 11 is located in the third metal layer m2. On the one hand, the lower impedance characteristic of the third metal layer m2 can be used to reduce the load of the third connecting line 9, thereby reducing the signal voltage drop. On the other hand, in the current process, there is no punching process between the second metal layer mc and the semiconductor layer sl, and there is a punching process between the third metal layer m2 and the semiconductor layer sl. The first sub-section 10 crosses the line to the second sub-section 11. When the third connecting line 9 is connected to the anode reset transistor M3, a connecting via is directly designed in the original punching process between the third metal layer m2 and the semiconductor layer sl. There is no need to add other punching processes or additional mask plates, thereby reducing process costs.

[0045] Further, see Figure 6 and Figure 7The first sub-section 10 and the second sub-section 11 are electrically connected through the first connection via 12, and the first connection via 12 overlaps the second connection line 8 in a direction perpendicular to the plane of the substrate 1. Exemplarily, the first sub-section 10 extends along the second direction y, and the second sub-section 11 extends along the first direction x, and the two are connected by punching above the second connection line 8.

[0046] As mentioned above, the third metal layer m2 has a relatively low impedance. The first connecting via 12 overlaps with the second connecting line 8, which means that the first sub-section 10 can be switched to the third metal layer m2 above the second connecting line 8, thereby increasing the length proportion of the second sub-section 11 in the third connecting line 9, and making the third connecting line 9 have a lower load.

[0047] Of course, in other optional embodiments of the present invention, in the direction perpendicular to the plane of the substrate 1, the first connecting via 12 may not overlap with the second connecting line 8. For example, the first sub-portion 10 first extends along the second direction y to overlap with the second connecting line 8, and then turns to one side of the second connecting line 8 along the first direction x, and changes to the third metal layer m2 on one side of the second connecting line 8.

[0048] In one possible implementation, see Figure 5 and Figure 6 The reset line Ref further includes a second sub-reset line Ref2, which extends along the second direction y and is electrically connected to the first sub-reset line Ref1. At this time, the first sub-reset line Ref1 and the second sub-reset line Ref2 intersect to form a grid structure, and the overall load of the reset line Ref is smaller.

[0049] The pixel circuit 2 includes a first pixel circuit 2 - 1 , which is adjacent to the second sub reset line Ref2 . The anode reset transistor M3 in the first pixel circuit 2 - 1 is electrically connected to the second sub reset line Ref2 through a fourth connection line 13 .

[0050] The first pixel circuit 2-1 is adjacent to the second sub-reset line Ref2, which means that the first pixel circuit 2-1 is close to the second sub-reset line Ref2. At this time, you can choose to connect the first pixel circuit 2-1 to the second sub-reset line Ref2 so that it can receive the reset signal, thereby facilitating the connection wiring between the first pixel circuit 2-1 and the reset line Ref.

[0051] In one possible implementation, see Figure 5 and Figure 6 , the pixel circuit 2 includes a first pixel circuit 2 - 1 , a second pixel circuit 2 - 2 and a third pixel circuit 2 - 3 .

[0052] The display panel includes a pixel circuit group 14, which includes a first pixel circuit 2-1, a second pixel circuit 2-2 and a third pixel circuit 2-3 arranged along a first direction x. Along the first direction x, a pixel circuit group 14 is spaced between two adjacent second sub-reset lines Ref2.

[0053] In the first pixel circuit 2 - 1 , the distance between the anode reset transistor M3 and the second sub reset line Ref2 is smaller than the distance between the data write transistor M2 and the second sub reset line Ref2 .

[0054] In other words, when there is a pixel circuit group 14 between two adjacent second sub-reset lines Ref2, the first pixel circuit 2-1 and the third pixel circuit 2-3 in the pixel circuit group 14 are both adjacent to the second sub-reset line Ref2. For these two pixel circuits 2, the anode reset transistor M3 in the first pixel circuit 2-1 is closer to the second sub-reset line Ref2, so the first pixel circuit 2-1 is selected to be connected to the second sub-reset line Ref2, and the connection distance between the pixel circuit 2 and the second sub-reset line Ref2 is shorter.

[0055] Among them, the distance between the anode reset transistor M3 and the second sub-reset line Ref2 can be defined by the distance between the channel of the anode reset transistor M3 and the second sub-reset line Ref2, and the distance between the data write transistor M2 and the second sub-reset line Ref2 can be defined by the distance between the channel of the data write transistor M2 and the second sub-reset line Ref2.

[0056] Further, the second pixel circuit 2-2 is electrically connected to the third connection line 9, and in a direction perpendicular to the plane where the substrate 1 is located, the third connection line 9 connected to the second pixel circuit 2-2 overlaps with the second connection line 8 in the first pixel circuit 2-1. The third pixel circuit 2-3 is electrically connected to the third connection line 9, and in a direction perpendicular to the plane where the substrate 1 is located, the third connection line 9 connected to the third pixel circuit 2-3 overlaps with the second connection line 8 in the second pixel circuit 2-2.

[0057] The display panel further includes a shielding portion 15 , which is electrically connected to the reset line Ref. In a direction perpendicular to the plane where the substrate 1 is located, the shielding portion 15 overlaps with the second connection line 8 in the third pixel circuit 2 - 3 .

[0058] When each pixel circuit 2 in the pixel circuit group 14 can be electrically connected to the reset line Ref and the second connection line 8 in each pixel circuit 2 can be blocked, the overall design composed of the third connection line 9, the fourth connection line 13 and the blocking portion 15 adopts a more reasonable wiring method, and the overall layout design of the pixel circuit 2 is better.

[0059] In the embodiment of the present invention, the fourth connection line 13 is located in the third metal layer m2, the fourth connection line 13 and the second sub-portion 11 in the third connection line 9 are arranged along the first direction x, and the length of the fourth connection line 13 can be less than the length of the second sub-portion 11. The shielding portion 15 is connected to the first sub-reset line Ref1 and is located in the second metal layer mc, and the shape of the shielding portion 15 can be consistent with the shape of the first sub-portion 10 in the third connection line 9.

[0060] In a possible implementation, Figure 8 and Fig. 9 As shown, Figure 8 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig. 9 for Figure 8 A cross-sectional view along the B1 - B2 direction, the display panel includes a first metal layer m1 , and the gate g1 of the anode reset transistor M3 and / or the gate g2 of the data writing transistor M2 are located on the first metal layer m1 .

[0061] The first scan line Scan1 includes a first portion 16, which is electrically connected to the gate g1 of the anode reset transistor M3 and / or the gate g2 of the data write transistor M2. The first portion 16 is located on a side of the first metal layer m1 away from the substrate 1, for example, on the third metal layer m2.

[0062] The gate g3 of the first reset transistor M41 and / or the gate g4 of the second reset transistor M42 are located on the first metal layer m1. The second scan line Scan2 includes a second portion 17, and the second portion 17 is electrically connected to the gate g3 of the first reset transistor M41 and / or the gate g4 of the second reset transistor M42. The second portion 17 is located on a side of the first metal layer m1 away from the substrate 1, for example, it can be located on the third metal layer m2.

[0063] In the conventional design of the scan line, the scan line is located in the first metal layer m1, and part of the scan line and the gate of the transistor connected thereto are reused. In the embodiment of the present invention, at least part of the scan line is set in other metal layers, and the gate of the transistor is connected to this part of the film layer through a via. In this way, some metal layers with lower impedance can be selected to reduce the overall load of the scan line, for example, the first part 16 and the second part 17 are located in the third metal layer m2. This structure is particularly suitable for large-size display panels, in which the scan lines are very long and the corresponding load will be very large. Routing at least part of the scan line in the third metal layer m2 can effectively reduce the load of the scan line.

[0064] Among them, the first part 16 and the second part 17 can be continuous lines extending along the first direction x, that is, in the direction perpendicular to the plane where the substrate 1 is located, the first part 16 overlaps with the multiple pixel circuits 2 arranged along the first direction x, and the second part 17 overlaps with the multiple pixel circuits 2 arranged along the first direction x.

[0065] Alternatively, the first scan line Scan1 may also include a plurality of first portions 16, with intervals between adjacent first portions 16. In a direction perpendicular to the plane where the substrate 1 is located, at least a portion of the gate g1 of the anode reset transistor M3 does not overlap with the first portion 16, and / or at least a portion of the gate g2 of the data write transistor M2 does not overlap with the first portion 16.

[0066] The second scan line Scan2 may also include a plurality of second portions 17, with intervals between adjacent second portions 17. In a direction perpendicular to the plane where the substrate 1 is located, at least a portion of the gate g3 of the first reset transistor M41 does not overlap with the second portion 17, and at least a portion of the gate g4 of the second reset transistor M42 does not overlap with the second portion 17.

[0067] When the first portion 16 and the second portion 17 are located in the third metal layer m2, see Figure 8 and Fig. 9 The display panel further includes a fourth metal layer m3, which is located on a side of the third metal layer m2 away from the substrate 1. To avoid routing conflicts between the data line Data and the scan line, the data line Data may be disposed in the fourth metal layer m3.

[0068] Regarding the second sub-reset line Ref2, in a feasible implementation manner, as Fig.10 As shown, Fig.10 This is another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention. The second sub-reset line Ref2 includes a first line segment 18 and a second line segment 19 which are electrically connected. The first line segment 18 is located in the second metal layer mc, and the second line segment 19 is located in the third metal layer m2.

[0069] As mentioned above, the third metal layer m2 has a smaller impedance than the second metal layer mc. Therefore, the second sub-reset line Ref2 can be designed to be switched between the second metal layer mc and the third metal layer m2 to reduce the overall load of the second sub-reset line Ref2.

[0070] In some implementations, the embodiments of the present invention can be applied to transparent display. In the transparent display panel, the display panel further includes a light-transmitting area 5, at least part of which is located on one side of the pixel circuit group 14 in the second direction y, for example, the pixel circuit group 14 and the light-transmitting area 5 are alternately arranged in the second direction y. Along the first direction x, the first line segment 18 at least overlaps with the pixel circuit group 14, and the second line segment 19 at least overlaps with the light-transmitting area 5, that is, the first line segment 18 is located on one side of the pixel circuit group 14, and the second line segment 19 is located on one side of the light-transmitting area 5. This avoids routing conflicts between the second line segment 19 and the scan line.

[0071] In other optional embodiments of the present invention, the second sub-reset line Ref2 may also be located only in the second metal layer mc, and then some line segments are arranged in parallel on the second sub-reset line Ref2, so as to reduce the overall load of the reset line Ref. Exemplarily, these line segments arranged in parallel may be located in the third metal layer m2. When the second sub-reset line Ref2 includes the first line segment 18 and the second line segment 19, in a feasible implementation manner, Figure 2 , Figure 3 and Fig.10 The pixel circuit 2 further includes a first light emitting control transistor M6, a gate of which is electrically connected to the light emitting control line Emit, a first electrode of which is electrically connected to the first power line PVDD, and a second electrode of which is electrically connected to the first electrode of the driving transistor M1.

[0072] The light emitting control line Emit extends along the first direction x and is located on the side of the first scanning line Scan1 away from the second scanning line Scan2. The light emitting control line Emit is located in the first metal layer m1, and in the direction perpendicular to the plane of the substrate 1, the light emitting control line Emit does not overlap with the first line segment 18.

[0073] The first metal layer m1 and the second metal layer mc are usually separated by only a thin insulating layer. The light-emitting control line Emit is located in the first metal layer m1, and the first line segment 18 is located in the second metal layer mc. By making the two non-overlapping, it is possible to avoid a large coupling between the two and an increase in the load of the light-emitting control line Emit. In other words, the position where the first line segment 18 and the second line segment 19 change lines is located on the side of the light-emitting control line Emit close to the first scan line Scan1, and in the direction perpendicular to the plane where the substrate 1 is located, the light-emitting control line Emit overlaps with the second line segment 19.

[0074] Further, see Fig.10Along the second direction y, the distance d1 between the first line segment 18 and the light-emitting control line Emit is greater than or equal to 0.8 μm, thereby leaving a margin for process errors. In this way, even if the actual position of the first line segment 18 and / or the light-emitting control line Emit is offset due to process accuracy and other reasons, a certain distance will be left between the two and no overlap will occur.

[0075] In one possible implementation, see Fig.10 The second line segment 19 includes a first edge 20, the first edge 20 is located between the first scan line Scan1 and the light emitting control line Emit, and the distance between the first edge 20 and the first scan line Scan1 is greater than the distance between the first edge 20 and the light emitting control line Emit.

[0076] This arrangement can avoid the risk of short circuit between the second line segment 19 and the first portion 16 of the first scanning line Scan1, and can also be combined with Fig.30 Sufficient accommodation space can also be provided between the second line segment 19 and the first scan line Scan1 for the third via hole 48 between the seventh connection line 35 and the first power line PVDD. This part is detailed in the subsequent embodiments.

[0077] In addition, the positions of the first edges 20 of the second line segments 19 in different second sub-reset lines Ref2 may also be different. For example, when the third via 48 does not need to be provided between the second line segments 19 in some second sub-reset lines Ref2 and the first scan line Scan1, the distance between the first edge 20 of the second line segments 19 in these parts and the first scan line Scan1 may be reduced, thereby increasing the length proportion of the second line segments 19 in the entire second sub-reset line Ref2, and reducing the load of the second sub-reset line Ref2 to a greater extent.

[0078] In a possible implementation, Fig.11 As shown, Fig.11 This is a schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention. Along the first direction x, the line width of the second line segment 19 is smaller than the line width of the first line segment 18 .

[0079] Under the premise of using the second line segment 19 to make the second reset line Ref2 have a better load, the line width of the second line segment 19 can be designed to be slightly smaller, so as to compress the wiring space occupied by the second line segment 19 and use the saved space to accommodate other metal wirings.

[0080] In some implementations, the embodiments of the present invention can be applied to transparent display. In a transparent display panel, see Fig.11The display panel further includes a light-transmitting area 5, at least part of which is located on one side of the pixel circuit group 14 in the second direction y. For example, the pixel circuit group 14 and the light-transmitting area 5 are alternately arranged in the second direction y. The line width of the second line segment 19 is reduced, which can release a part of the space as the light-transmitting area 5, that is, increase the length of the light-transmitting area 5 in the first direction x, and improve the transmittance of the display panel.

[0081] In a possible implementation, Fig.12 and Fig.13 As shown, Fig.12 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.13 This is another schematic diagram of a film structure of a display panel provided by an embodiment of the present invention. The display panel includes a pixel circuit group 14. The pixel circuit group 14 includes a plurality of pixel circuits 2 arranged along a first direction x.

[0082] The data writing transistor M2 is electrically connected to the data line Data via a fifth connecting line 21, and at least part of the fifth connecting line 21 includes a first sub-line segment 22 extending along the first direction x. In the pixel circuit group 14, the first sub-line segments 22 corresponding to at least two pixel circuits 2 are arranged along the first direction x.

[0083] Regarding the fifth connecting line 21, Fig.14 As shown, Fig.14 This is another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention, wherein the fifth connection line 21 includes a first connection line segment 23 and a second connection line segment 24. The first connection line segment 23 is located in the semiconductor layer s1 and is electrically connected to the first electrode of the data writing transistor M2, the second connection line segment 24 is located in the third metal layer m2, the second connection line segment 24 includes a first sub-line segment 22, a second sub-line segment 25 and a third sub-line segment 26, the second sub-line segment 25 is electrically connected to the first connection line segment 23 through a via, the third sub-line segment 26 is electrically connected to the data line Data through a via, and the first sub-line segment 22 is connected between the second sub-line segment 25 and the third sub-line segment 26. Along the second direction y, the width of the first sub-line segment 22 is smaller than the width of the second sub-line segment 25, and the width of the first sub-line segment 22 is smaller than the width of the third sub-line segment 26.

[0084] When the first sub-line segments 22 corresponding to at least two pixel circuits 2 in the pixel circuit group 14 are arranged along the first direction x, these at least two first sub-line segments 22 only need to occupy one routing width in the second direction y, thereby reducing the layout space required to be occupied by the pixel circuit group 14 in the vertical direction and improving the PPI.

[0085] In some implementations, the embodiments of the present invention can be applied to transparent displays. In a transparent display panel, the display panel further includes a light-transmitting area 5, at least part of which is located on one side of the pixel circuit group 14 in the second direction y, for example, the pixel circuit group 14 and the light-transmitting area 5 are alternately arranged in the second direction y. With the above structure, the layout space required to be occupied by the pixel circuit group 14 in the longitudinal direction is reduced, and the released space can be used as a light-transmitting area, which can increase the longitudinal size of the light-transmitting area 5 in the second direction y, thereby improving the transmittance of the display panel.

[0086] The at least two first sub-line segments 22 arranged along the first direction x may have different extension lengths.

[0087] In a possible implementation, Fig.15 and Fig.16 As shown, Fig.15 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.16 Another structural schematic diagram of a display panel provided by an embodiment of the present invention, the pixel circuit 2 includes a first pixel circuit 2-1, a second pixel circuit 2-2 and a third pixel circuit 2-3. The data line Data includes a first data line Data1 electrically connected to the first pixel circuit 2-1, a second data line Data2 electrically connected to the second pixel circuit 2-2 and a third data line Data3 electrically connected to the third pixel circuit 2-3.

[0088] The display panel includes a pixel circuit group 14 and a light-transmitting area 5, the pixel circuit group 14 includes a first pixel circuit 2-1, a second pixel circuit 2-2 and a third pixel circuit 2-3 arranged along a first direction x, at least part of the light-transmitting area 5 is located on one side of the pixel circuit group 14 in a second direction y, and the second direction y intersects with the first direction x.

[0089] For the data lines Data connected to the same pixel circuit group 14 , the first data line Data1 is located at a first side of the light-transmitting area 5 in the first direction x, and the second data line Data2 and the third data line Data3 are located at a second side of the light-transmitting area 5 in the first direction x.

[0090] For transparent display panels, in related designs, such as Fig.17 As shown, Fig.17Schematic diagram of a structure of a display panel in the related art, in which the three data lines Data connected to the pixel circuit group 14 are all located on the same side of the light-transmitting area 5. Under this design, when the three pixel circuits 2 are electrically connected to their corresponding data lines Data through the fifth connection lines 21, the fifth connection lines 21 need to be led to the same side, and in order to avoid each other, the first sub-line segments 22 in at least two of the fifth connection lines 21 will overlap in the second direction y, resulting in the first sub-line segments 22 needing to occupy at least two routing widths in the longitudinal direction as a whole.

[0091] In the embodiment of the present invention, the three data lines Data connected to the pixel circuit group 14 are respectively located on both sides of the light-transmitting area 5. When the pixel circuit 2 is connected to the data line Data, it is ensured that at least two first sub-line segments 22 in the fifth connecting lines 21 are led in different directions, so that the at least two first sub-line segments 22 can be arranged along the first direction x, thereby compressing the wiring width required to be occupied by the three first sub-line segments 22 in the longitudinal direction.

[0092] In addition, the three data lines Data connected to the pixel circuit group 14 are respectively located on both sides of the light-transmitting area 5, which can also increase the light-transmitting area. Fig.18 As shown, Fig.18 A schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present invention, the display panel includes an inorganic layer 27 and an organic layer 28. Among them, the inorganic layer 27 may include an inorganic insulating layer, etc., for example, it may include an inorganic insulating layer located between the semiconductor layer s1 and the first metal layer m1, an inorganic insulating layer located between the first metal layer m1 and the second metal layer mc, and an inorganic insulating layer located between the second metal layer mc and the third metal layer m2. The organic layer 28 may include a planarization layer, etc., for example, it may include a planarization layer located between the third metal layer m2 and the fourth metal layer m3. In order to improve the transmittance of the light-transmitting area 5, the inorganic layer 27 and the organic layer 28 in the light-transmitting area 5 can be designed to be excavated. In other words, the position where the light-transmitting area 5 is located is the position of the holes in the inorganic layer 27 and the organic layer 28, and the edge of the hole-excavating area can be defined as the edge of the light-transmitting area 5.

[0093] In the hole-digging process, due to the limitation of process precision, a certain avoidance distance d is required between the hole-digging area and the metal trace. Fig.19 , Fig.19 This is an arrangement comparison diagram of the data lines Data provided in an embodiment of the present invention. The three data lines Data connected to the pixel circuit group 14 are respectively located on both sides of the light-transmitting area 5. Along the first direction x, the required avoidance distance d between the light-transmitting area 5 and the data lines Data is relatively short. Accordingly, the size of the light-transmitting area 5 in the first direction x can be designed to be larger, thereby effectively increasing the light-transmitting area.

[0094] Further, see Fig.15 and Fig.16 The reset line Ref includes a second sub-reset line Ref2 extending along the second direction y, and a pixel circuit group 14 is spaced between two adjacent second sub-reset lines Ref2.

[0095] Among them, in the direction perpendicular to the plane of the substrate 1, the third data line Data3 overlaps with the third pixel circuit 2-3, the third data line Data3 is located between the second data line Data2 and the second sub-reset line Ref2, and the first data line Data1 is located between the third data line Data3 and the second sub-reset line Ref2.

[0096] In this arrangement, in the direction perpendicular to the plane where the substrate 1 is located, the fifth connection line 21 between the first pixel circuit 2-1 and the first data line Data1 will overlap with the second sub-reset line Ref2. That is to say, among the three adjacent first data lines Data1, second data lines Data2 and third data lines Data3, the second data line Data2 and the third data line Data3 are connected to the second pixel circuit 2-2 and the third pixel circuit 2-3 in the same pixel circuit group 14, and the first data line Data1 is connected to the first pixel circuit 2-1 in another pixel circuit group 14. The wiring method under this design is more reasonable, the data line Data has less influence on the light-transmitting area, and it can also achieve that the first sub-line segments 22 in at least two fifth connection lines 21 are arranged along the first direction x.

[0097] In a possible implementation, Fig. 20 As shown, Fig. 20 This is another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention. The data writing transistor M2 is electrically connected to the data line Data via a fifth connecting line 21 .

[0098] At least part of the data line Data includes a third line segment 29, a fourth line segment 30 and a fifth line segment 31. The third line segment 29 is electrically connected to the fifth connection line 21 through a first via 32. The fourth line segment 30 extends along the second direction y. The fifth line segment 31 is connected between the third line segment 29 and the fourth line segment 30, and an angle is formed between the extension direction of the fifth line segment 31 and the second direction y.

[0099] Generally, the width of the metal trace at the via position is greater than the width at the non-via position. It is understandable that a certain distance needs to be between adjacent data lines to avoid short circuit. Fig.21 , Fig.21Another structural comparison diagram of the data line Data provided in an embodiment of the present invention, assuming that the required spacing distance is h, if the entire data line Data extends in a straight line along the second direction y, the spacing distance h1 of adjacent data lines Data at non-via positions will be much larger than h, resulting in a waste of wiring space.

[0100] The embodiment of the present invention makes at least part of the data lines Data bend at the via position, which can compress the spacing distance h2 between adjacent data lines Data at non-via positions, making h2 closer to h. For example, h2 can be equal to h. In this way, the line widths of different data lines Data at non-via positions can be arranged more closely, and the wiring design is better.

[0101] When the embodiment of the present invention is applied in transparent display, see Fig. 20 The display panel includes a light-transmitting area 5, and the data lines Data are arranged more closely, which can increase the length of the light-transmitting area 5 in the first direction x, and the light-transmitting area can also be larger.

[0102] In a possible implementation, combining Figure 2 ,like Figure 22~Figure 24 As shown, Fig. 22 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.23 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.24 This is another schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, wherein the pixel circuit 2 further includes a first light-emitting control transistor M6, a gate of the first light-emitting control transistor M6 being electrically connected to a light-emitting control line Emit, a first electrode being electrically connected to a first power line PVDD, and a second electrode being electrically connected to a first electrode of a driving transistor M1.

[0103] The first power line PVDD extends along the second direction y and is disposed in the same layer as the data line Data. In the embodiment of the present invention, the first power line PVDD and the data line Data are both located in the fourth metal layer m3.

[0104] A first connection structure 33 is connected between two adjacent first power lines PVDD. The first connection structure 33 includes a sixth connection line 34 and a seventh connection line 35. The sixth connection line 34 is arranged on the same layer as the first power line PVDD. In a direction perpendicular to the plane where the substrate 1 is located, the seventh connection line 35 overlaps with the data line Data and is arranged on a different layer from the data line Data.

[0105] The first power lines PVDD are connected by the first connection structure 33 to form a grid structure as a whole, which can reduce the load. Since the first connection structure 33 overlaps with the data line Data, the seventh connection line 35 overlapping with the data line Data in the first connection structure 33 can be arranged in a different layer from the data line Data, and the sixth connection line 34 not overlapping with the data line Data can be arranged in the same layer as the data line Data, so as to achieve reasonable wiring.

[0106] For the transparent display panel, to prevent the first connection structure 33 from affecting the transmittance, in a direction perpendicular to the plane of the substrate 1 , the sixth connection line 34 and the seventh connection line 35 overlap with the pixel circuit group 14 and do not overlap with the light-transmitting area 5 .

[0107] In a possible implementation, combining Figure 2 , Figure 22~Figure 24 The pixel circuit 2 further includes a gate reset module 4, a control end of the gate reset module 4 is electrically connected to the second scan line Scan2, a first end is electrically connected to the reset line Ref, and a second end is electrically connected to the gate of the driving transistor M1. The light emitting control line Emit, the first scan line Scan1 and the second scan line Scan2 all extend along the first direction x, and the light emitting control line Emit is located at a side of the second scan line Scan2 away from the first scan line Scan1.

[0108] Among them, the sixth connecting line 34 includes a third sub-portion 36, and in a direction perpendicular to the plane of the substrate 1, the third sub-portion 36 overlaps with the first scanning line Scan1 and the second scanning line Scan2, and, along the second direction y, the width of the third sub-portion 36 is greater than the distance between the second scanning line Scan2 and the first scanning line Scan1.

[0109] More specifically, combined Figure 2 , Figure 22~Figure 24 The display panel further includes a second light emission control transistor M7, a gate of the second light emission control transistor M7 is electrically connected to the light emission control line Emit, a first electrode is electrically connected to the second electrode of the driving transistor M1, and a second electrode is electrically connected to the light emitting element 3. To improve connection reliability, the second electrode of the second light emission control transistor M7 can be electrically connected to the light emitting element 3 through an eighth connection line 37, and the eighth connection line 37 is located in the fourth metal layer m3 and is arranged in the same layer as the first power line PVDD.

[0110] Based on the existence of the eighth connection line 37, in order to avoid the sixth connection line 34 and the eighth connection line 37 from each other, the sixth connection line 34 can be designed to include an electrically connected third sub-portion 36 and a fourth sub-portion 38, the third sub-portion 36 is located on one side of the eighth connection line 37 in the second direction y, the fourth sub-portion 38 is located on one side of the eighth connection line 37 in the first direction x, and at least part of the fourth sub-portion 38 is electrically connected to the first light-emitting control transistor M6.

[0111] Based on this, when designing the third sub-portion 36 , the embodiment of the present invention designs its width in the second direction y to be larger than the distance between the first scan line Scan1 and the second scan line Scan2 , so as to reduce the load of the sixth connection line 34 as much as possible.

[0112] Furthermore, if Fig.25 and Fig.26 As shown, Fig.25 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.26 for Fig.25 A cross-sectional view along the C1-C2 direction, the display panel further includes a pixel circuit group 14 and a light-transmitting area 5, the pixel circuit group 14 includes a plurality of pixel circuits 2 arranged along the first direction x, and at least part of the light-transmitting area 5 is located on one side of the pixel circuit group 14 in the second direction y.

[0113] The display panel further includes a first metal 39 , which is located between the third sub-portion 36 and the substrate 1 , and a distance between the first metal 39 and the light-transmitting area 5 is smaller than a distance between other metals between the third sub-portion 36 and the substrate 1 and the light-transmitting area 5 .

[0114] The first metal 39 includes a second edge 40 close to the light-transmitting area 5, and the third sub-portion 36 includes a third edge 41 close to the light-transmitting area 5. In a direction perpendicular to the plane of the substrate 1, a distance k between a projection of the third edge 41 and a projection of the second edge 40 is less than or equal to 1.2 μm.

[0115] The third sub-portion 36 includes a third edge 41 and a fourth edge 45 which are opposite to each other in the second direction y, wherein the third edge 41 is close to the light-transmitting area 5 , and the fourth edge 45 is close to the eighth connecting line 37 .

[0116] Taking the third subsection 36 located in the fourth metal layer m3 as an example, there are multiple metal layers between the substrate 1 and the fourth metal layer m3, for example, the first metal layer m1, the second metal layer mc and the third metal layer m2, and each metal layer includes multiple metal traces. The first metal 39 is the metal trace closest to the light-transmitting area 5 on the side of the third edge 41 among these metal layers. In other words, the film layer between the substrate 1 and the fourth metal layer m3 is the first film layer, the first film layer includes multiple metal layers, and the first metal 39 is located in a metal layer of the first film layer. The distance between the first metal 39 and the light-transmitting area 5 on the side of the third edge 41 is greater than the distance between other metal traces in the metal layer where the first metal 39 is located and the light-transmitting area 5, and is also greater than the distance between metal traces in other metal layers in the first film layer and the light-transmitting area 5.

[0117] It should be noted that although Fig.25 The first metal 39 is used as the first reset line Ref as an example, but in other structures, the first metal 39 may also be other metal structures. Fig. 27 As shown, Fig. 27 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, wherein the display panel further comprises a fifth metal layer m0, the fifth metal layer m0 being located on a side of the semiconductor layer s1 away from the first metal layer m1, and the fifth metal layer m0 comprising a shielding metal 43, in a direction perpendicular to the plane where the substrate 1 is located, the shielding metal 43 overlaps with at least part of the channel of the transistor to prevent ambient light from irradiating the channel and affecting the formation of the transistor. When the edge of the shielding metal 43 is closer to the light-transmitting area 5, the first metal 39 may also be the shielding metal 43.

[0118] As mentioned above, the inorganic layer 27 and the organic layer 28 in the light-transmitting area 5 are designed to be dug out, and the edge of the light-transmitting area 5 can be regarded as the edge of the hole-digging area. Therefore, the distance between the edge of the light-transmitting area 5 and the edge of the metal routing can be defined by the distance between the edge of the hole-digging area and the edge of the metal routing.

[0119] The distance k between the third edge 41 of the third sub-portion 36 and the second edge 40 of the first metal 39 is less than or equal to 1.2 μm, including the case where the third edge 41 coincides with the second edge 40, the case where the third edge 41 is located on the side of the second edge 40 away from the fourth edge 45, and the case where the third edge 41 is located on the side of the second edge 40 close to the fourth edge 45. This limitation on the distance between the third edge 41 and the second edge 40 can prevent the third sub-portion 36 from expanding too much from the first metal 36 and causing the light transmission area to be blocked. Further, the third edge 41 can coincide with the second edge 40.

[0120] In addition, combined Fig.28 and Fig.29 , Fig.28 is another schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present invention, Fig.29 This is another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention. The display panel may further include a sixth metal layer m4 . The sixth metal layer m4 is located on a side of the fourth metal layer m3 away from the substrate 1 .

[0121] The sixth metal layer m4 includes a second power line PVEE and a bonding portion 44. The second power line PVEE includes a first sub-power line PVEE1 and a second sub-power line PVEE2 that are electrically connected, the first sub-power line PVEE1 extends along a first direction x, and in a direction perpendicular to the plane where the substrate 1 is located, the first sub-power line PVEE1 overlaps with the third sub-portion 36, and the second sub-power line PVEE2 extends along a second direction y, and in a direction perpendicular to the plane where the substrate 1 is located, the second sub-power line PVEE2 overlaps with the first power line PVDD.

[0122] Among them, the bonding part 44 is electrically connected to the eighth connecting line 37, and the bonding part 44 is also electrically connected to the first pole of the light-emitting element 3 (not shown in the figure), and the first sub-power line PVEE1 is electrically connected to the second pole of the light-emitting element 3 (not shown in the figure).

[0123] The first sub-power line PVEE1 includes a fourth edge 45 and a fifth edge 46 that are opposite to each other in the second direction y, and the fourth edge 45 is located on the side of the fifth edge 46 away from the bonding portion 44. In the direction perpendicular to the plane where the substrate 1 is located, the distance w between the projection of the fourth edge 45 and the projection of the second edge 40 can also be set to be less than or equal to 1.2 μm, so that the fourth edge 45 tends to coincide with the second edge 40, avoiding the second power line PVEE from expanding the first metal 36 too much and occupying the light-transmitting area.

[0124] In a possible implementation, Fig.30 As shown, Fig.30 This is another structural diagram of a display panel provided by an embodiment of the present invention, in which the seventh connection line 35 is electrically connected to the sixth connection line 34 through the second via hole 47, and the seventh connection line 35 is electrically connected to the first power line PVDD through the third via hole 48. The distance between the third via hole 48 and the first scan line Scan1 is smaller than the distance between the second via hole 47 and the first scan line Scan1.

[0125] As mentioned above, the second sub-reset line Ref2 includes a first line segment 18 and a second line segment 19 arranged in different layers, and the second line segment 19 and the seventh connection line 35 are arranged in the same layer, and both are located in the third metal layer m2.

[0126] In the embodiment of the present invention, the power line overlaps the second sub-reset line Ref2 in a direction perpendicular to the plane of the substrate 1. Compared with the second via 47, the third via 48 is closer to the first scan line Scan1, which can leave a larger wiring space for the second line segment 19, increase the length ratio of the second line segment 19 in the second sub-reset line Ref2, and help to reduce the load of the second sub-reset line Ref2 to a greater extent.

[0127] Further, see Fig. 27 The reset line Ref includes a first sub-reset line Ref1 and a second sub-reset line Ref2 that are electrically connected. The first sub-reset line Ref1 extends along a first direction x, and the second sub-reset line Ref2 extends along a second direction y. In a direction perpendicular to the plane where the substrate 1 is located, the first power line PVDD overlaps the second sub-reset line Ref2.

[0128] The second sub-reset line Ref2 includes a first line segment 18 and a second line segment 19 arranged in different layers, wherein the second line segment 18 and the seventh connection line 35 are arranged in the same layer, and the third via 48 is located between the first scan line Scan1 and the second line segment 19 to provide a reasonable arrangement space for the third via 48.

[0129] Furthermore, if Fig.31 As shown, Fig.31 A schematic diagram of another film layer structural adhesive for a display panel provided in an embodiment of the present invention, wherein a distance q1 between the third via hole 48 and the first scan line Scan1 is greater than or equal to 2.5 μm, and a distance q2 between the third via hole 48 and the second line segment 19 is greater than or equal to 2.5 μm, so that a sufficient distance is provided between the third via hole 48 and the first scan line Scan1 and the second line segment 19 to leave a margin for process errors and avoid the risk of short circuits caused by process errors and other factors.

[0130] In an embodiment of the present invention, q1 and q2 can be set to be equal to 2.5 μm respectively, so as to minimize the distance between the third via 48 and the first scan line Scan1, and the distance between the third via 48 and the second line segment 19 while leaving a margin for process errors, thereby freeing up more wiring space for the second line segment 19 and extending the length of the second line segment 19 as much as possible.

[0131] In the embodiments of the present invention, see Figure 2 The pixel circuit 2 further includes a storage capacitor Cst, a first plate of the storage capacitor Cst is electrically connected to the first power line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M1.

[0132] The present invention is as follows Figure 3Taking the illustrated film layer structure as an example, each film layer contained therein is disassembled to more clearly illustrate the structure involved in the embodiment of the present invention.

[0133] The display panel includes a semiconductor layer sl, a first metal layer m1 located on a side of the semiconductor layer sl away from a substrate 1, a second metal layer mc located on a side of the first metal layer m1 away from the semiconductor layer sl, a third metal layer m2 located on a side of the second metal layer mc away from the first metal layer m1, and a fourth metal layer m3 located on a side of the third metal layer m2 away from the substrate 1.

[0134] like Fig.32 As shown, Fig.32 for Figure 3 A schematic structural diagram of the corresponding semiconductor layer s1, wherein the semiconductor layer s1 includes a first connecting line 6, a second connecting line 8 and other structures.

[0135] like Fig.33 As shown, Fig.33 for Figure 3 The corresponding schematic diagram of the structure of the first metal layer m1, the first metal layer m1 includes structures such as the light emitting control line Emit.

[0136] like Fig.34 As shown, Fig.34 for Figure 3 The corresponding schematic diagram of the structure of the second metal layer mc, the second metal layer mc includes the first sub-reset line Ref1, the first line segment 18 in the second sub-reset line Ref2, the first sub-portion 10 in the third connection line 9, and the shielding portion 15 and other structures.

[0137] like Fig.35 As shown, Fig.35 for Figure 3 The corresponding structural schematic diagram of the third metal layer m2, the third metal layer m2 includes the second sub-portion 11 in the third connecting line 9, the fourth connecting line 13, the first part 16 in the first scanning line Scan1, the second part 17 in the second scanning line Scan2, the first sub-segment 22 in the fifth connecting line 21, the second segment 19 in the second sub-reset line Ref2 and the seventh connecting line 35 and other structures.

[0138] like Fig.36 As shown, Fig.36 for Figure 3 The corresponding schematic diagram of the structure of the fourth metal layer m3, the fourth metal layer m3 includes structures such as the data line Data, the first power line PVDD, the sixth connection line 34 and the eighth connection line 37.

[0139] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.37 As shown, Fig.371 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.37 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0140] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a pixel circuit located on one side of the substrate, wherein the pixel circuit comprises: Driver transistor; a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the first scanning line, a first electrode is electrically connected to the data line, and a second electrode is electrically connected to the first electrode of the driving transistor; an anode reset transistor, wherein a gate of the anode reset transistor is electrically connected to the first scan line, a first electrode is electrically connected to the reset line, and a second electrode is electrically connected to the light emitting element; The anode reset transistor and the data writing transistor of the same pixel circuit are electrically connected to the same first scanning line.

2. The display panel according to claim 1, characterized in that: The pixel circuit further includes a gate reset module, the gate reset module includes a first reset transistor and a second reset transistor, wherein the gate of the first reset transistor and the gate of the second reset transistor are both electrically connected to the second scan line, the first electrode of the first reset transistor is electrically connected to the reset line, the second electrode of the first reset transistor is electrically connected to the first electrode of the second reset transistor through a first connecting line, and the second electrode of the second reset transistor is electrically connected to the gate of the driving transistor; Wherein, the first scanning line and the second scanning line extend along a first direction; The reset line includes a first sub-reset line extending along the first direction and located on a side of the second scan line away from the first scan line. In a direction perpendicular to a plane where the substrate is located, the first sub-reset line overlaps the first connection line.

3. The display panel according to claim 2, characterized in that: The pixel circuit further includes a threshold compensation module, the threshold compensation module includes a first compensation transistor and a second compensation transistor, wherein the gate of the first compensation transistor and the gate of the second compensation transistor are both electrically connected to the first scan line, the first electrode of the first compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the first compensation transistor is electrically connected to the first electrode of the second compensation transistor through a second connecting line, and the second electrode of the second compensation transistor is electrically connected to the gate of the driving transistor; The anode reset transistors in at least part of the pixel circuits are electrically connected to the first sub-reset line via a third connection line, and the third connection line overlaps the second connection line in a direction perpendicular to the plane where the substrate is located.

4. The display panel according to claim 3, characterized in that: For the same third connection line, the pixel circuit where the anode reset transistor connected thereto is located and the pixel circuit where the second connection line overlapped therewith are adjacent in the first direction.

5. The display panel according to claim 3, characterized in that: The display panel comprises a first metal layer, a second metal layer located on a side of the first metal layer away from the substrate, and a third metal layer located on a side of the second metal layer away from the substrate; Wherein, the gate of the driving transistor is located in the first metal layer, and the first sub-reset line is located in the second metal layer; The third connecting line includes a first sub-portion and a second sub-portion, wherein the first sub-portion is connected to the first sub-reset line, the second sub-portion is connected between the first sub-portion and the anode reset transistor, the first sub-portion is located in the second metal layer, the second sub-portion is located in the third metal layer, and the first sub-portion overlaps with the second connecting line in a direction perpendicular to the plane where the substrate is located.

6. The display panel according to claim 5, characterized in that: The first sub-section and the second sub-section are electrically connected via a first connecting via, and the first connecting via overlaps the second connecting line in a direction perpendicular to the plane where the substrate is located.

7. The display panel according to claim 3, characterized in that: The reset line further includes a second sub-reset line, the second sub-reset line extends along a second direction and is electrically connected to the first sub-reset line, the second direction intersecting the first direction; The pixel circuit includes a first pixel circuit, the first pixel circuit is adjacent to the second sub-reset line, and the anode reset transistor in the first pixel circuit is electrically connected to the second sub-reset line through a fourth connection line.

8. The display panel according to claim 7, characterized in that: The pixel circuit further includes a second pixel circuit and a third pixel circuit; The display panel includes a pixel circuit group, and the pixel circuit group includes the first pixel circuit, the second pixel circuit and the third pixel circuit arranged along the first direction; Along the first direction, the pixel circuit group is spaced between two adjacent second sub-reset lines; In the first pixel circuit, a distance between the anode reset transistor and the second sub reset line is smaller than a distance between the data write transistor and the second sub reset line.

9. The display panel according to claim 8, characterized in that: The second pixel circuit is electrically connected to the third connection line, and in a direction perpendicular to the plane where the substrate is located, the third connection line connected to the second pixel circuit overlaps with the second connection line in the first pixel circuit; The third pixel circuit is electrically connected to the third connection line, and in a direction perpendicular to the plane where the substrate is located, the third connection line connected to the third pixel circuit overlaps with the second connection line in the second pixel circuit; The display panel further includes a shielding portion, the shielding portion is electrically connected to the reset line, and in a direction perpendicular to the plane where the substrate is located, the shielding portion overlaps with the second connecting line in the third pixel circuit.

10. The display panel according to claim 2, characterized in that: The display panel comprises a first metal layer, a second metal layer located on a side of the first metal layer away from the substrate, and a third metal layer located on a side of the second metal layer away from the substrate; The gate of the driving transistor is located in the first metal layer, and the first sub-reset line is located in the second metal layer; The reset line further includes a second sub-reset line, the second sub-reset line extends along a second direction and is electrically connected to the first sub-reset line, the second direction intersecting the first direction; The second sub-reset line includes a first line segment and a second line segment that are electrically connected, wherein the first line segment is located in the second metal layer, and the second line segment is located in the third metal layer.

11. The display panel according to claim 10, characterized in that: The pixel circuit further includes a first light emission control transistor, wherein a gate of the first light emission control transistor is electrically connected to the light emission control line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the first electrode of the driving transistor; The light emitting control line extends along the first direction and is located on a side of the first scanning line away from the second scanning line. The light emitting control line is located in the first metal layer and does not overlap with the first line segment in a direction perpendicular to the plane of the substrate.

12. The display panel according to claim 11, characterized in that: Along the second direction, a distance between the first line segment and the light emitting control line is greater than or equal to 0.8 μm.

13. The display panel according to claim 11, characterized in that: The second line segment includes a first edge, the first edge is located between the first scan line and the light emitting control line, and a distance between the first edge and the first scan line is greater than a distance between the first edge and the light emitting control line.

14. The display panel according to claim 10, characterized in that: Along the first direction, the line width of the second line segment is smaller than the line width of the first line segment.

15. The display panel according to claim 1, characterized in that: The display panel comprises a first metal layer, and the gate of the anode reset transistor and / or the gate of the data writing transistor are located in the first metal layer; The first scan line includes a first portion, the first portion is electrically connected to the gate of the anode reset transistor and / or the gate of the data write transistor; the first portion is located on a side of the first metal layer away from the substrate.

16. The display panel according to claim 1, characterized in that: The display panel includes a pixel circuit group, and the pixel circuit group includes a plurality of pixel circuits arranged along a first direction; The data writing transistor and the data line are electrically connected via a fifth connecting line, and at least part of the fifth connecting line includes a first sub-line segment extending along the first direction; In the pixel circuit group, the first sub-line segments corresponding to at least two of the pixel circuits are arranged along the first direction.

17. The display panel according to claim 1, characterized in that: The pixel circuit includes a first pixel circuit, a second pixel circuit and a third pixel circuit; the data line includes a first data line electrically connected to the first pixel circuit, a second data line electrically connected to the second pixel circuit and a third data line electrically connected to the third pixel circuit; The display panel comprises a pixel circuit group and a light-transmitting area, the pixel circuit group comprises the first pixel circuit, the second pixel circuit and the third pixel circuit arranged along a first direction, at least part of the light-transmitting area is located on one side of the pixel circuit group in a second direction, and the second direction intersects the first direction; Among them, for the data lines connected to the same pixel circuit group, the first data line is located at a first side of the light-transmitting area in the first direction, and the second data line and the third data line are located at a second side of the light-transmitting area in the first direction.

18. The display panel according to claim 17, characterized in that: The reset line includes a second sub-reset line extending along the second direction, and the pixel circuit group is spaced between two adjacent second sub-reset lines; Wherein, in a direction perpendicular to the plane of the substrate, the third data line overlaps with the third pixel circuit, the third data line is located between the second data line and the second sub-reset line, and the first data line is located between the third data line and the second sub-reset line.

19. The display panel according to claim 17, characterized in that: The data writing transistor is electrically connected to the data line via a fifth connecting line; At least part of the data line includes a third line segment, a fourth line segment and a fifth line segment, wherein the third line segment is electrically connected to the fifth connecting line through a first via, the fourth line segment extends along the second direction, the fifth line segment is connected between the third line segment and the fourth line segment, and an extension direction of the fifth line segment has an angle with the second direction.

20. The display panel according to claim 1, characterized in that: The pixel circuit further includes a first light emission control transistor, wherein a gate of the first light emission control transistor is electrically connected to the light emission control line, a first electrode is electrically connected to the first power line, and a second electrode is electrically connected to the first electrode of the driving transistor; The first power line extends along the second direction and is arranged in the same layer as the data line; A first connection structure is connected between two adjacent first power lines, and the first connection structure includes a sixth connection line and a seventh connection line. The sixth connection line is arranged on the same layer as the first power line. In a direction perpendicular to the plane where the substrate is located, the seventh connection line overlaps with the data line and is arranged on a different layer from the data line.

21. The display panel according to claim 20, characterized in that: The pixel circuit further comprises a gate reset module, wherein a control end of the gate reset module is electrically connected to the second scan line, a first end of the gate reset module is electrically connected to the reset line, and a second end of the gate reset module is electrically connected to the gate of the driving transistor; The light emitting control line, the first scanning line and the second scanning line all extend along the first direction, and the light emitting control line is located on a side of the second scanning line away from the first scanning line; The sixth connecting line includes a third sub-portion, which overlaps with the first scanning line and the second scanning line in a direction perpendicular to the plane of the substrate, and the width of the third sub-portion along the second direction is greater than the distance between the second scanning line and the first scanning line.

22. The display panel according to claim 21, characterized in that: The display panel further comprises a pixel circuit group and a light-transmitting area, wherein the pixel circuit group comprises a plurality of pixel circuits arranged along a first direction, and at least part of the light-transmitting area is located on one side of the pixel circuit group in the second direction; The display panel further includes a first metal, the first metal is located between the third sub-portion and the substrate, and the distance between the first metal and the light-transmitting area is smaller than the distance between other metals between the third sub-portion and the substrate and the light-transmitting area; The first metal includes a second edge close to the light-transmitting area, the third sub-portion includes a third edge close to the light-transmitting area, and in a direction perpendicular to the plane where the substrate is located, a distance between a projection of the third edge and a projection of the second edge is less than or equal to 1.2 μm.

23. The display panel according to claim 20, characterized in that: The seventh connection line is electrically connected to the sixth connection line through the second via hole, and the seventh connection line is electrically connected to the first power line through the third via hole; Wherein, the distance between the third via hole and the first scan line is smaller than the distance between the second via hole and the first scan line.

24. The display panel according to claim 23, characterized in that: The reset line comprises a first sub-reset line and a second sub-reset line which are electrically connected, the first sub-reset line extends along the first direction, the second sub-reset line extends along the second direction, and the first power line overlaps the second sub-reset line in a direction perpendicular to the plane where the substrate is located; The second sub-reset line includes a first line segment and a second line segment disposed in different layers, wherein the second line segment and the seventh connecting line are disposed in the same layer, and the third via hole is located between the first scan line and the second line segment.

25. The display panel according to claim 24, characterized in that: The distance between the third via hole and the first scan line is greater than or equal to 2.5 μm, and the distance between the third via hole and the second line segment is greater than or equal to 2.5 μm.

26. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 25.

Images