Pixel driving circuit, display device and driving method of pixel circuit

Abstract

The invention discloses a pixel driving circuit, a display device and a driving method of a pixel circuit, and belongs to the technical field of display. The pixel driving circuit comprises a first reset unit, a second reset unit and a driving unit, the first reset unit is connected with the driving unit and is used for receiving a first control signal and performing bias reset on the input end of the driving unit under the control of the first control signal; the driving unit is connected with a light-emitting element and is used for receiving light-emitting current of the light-emitting element and transmitting the light-emitting current to the light-emitting element; and the second reset unit is connected with the light-emitting element and is used for receiving a second control signal and resetting the light-emitting element under the control of the second control signal.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a pixel driving circuit, a display device, and a driving method for a pixel circuit. Background Art

[0002] Active Matrix Organic Light Emitting Diode (AMOLED) display technology is widely used in electronic devices such as smart phones and smart watches due to its high contrast, fast response speed, wide viewing angle and wide color gamut.

[0003] The organic light-emitting diode (OLED) of each pixel of the current AMOLED display panel is connected to its corresponding pixel driving circuit. The pixel driving circuit is used to transmit a light-emitting current to the OLED under multiple refresh cycles to drive the OLED to emit light.

[0004] However, the light-emitting current of the OLED is divided into the lighting current of the OLED and the charging current of the parasitic capacitance of the OLED. The current pixel driving circuit will cause the OLED to undergo multiple resets in a single refresh cycle, and each reset will cause the parasitic capacitance of the OLED to undergo a charge and discharge, which will cause the size of the lighting current of the OLED to change. Obviously, the lighting current of the OLED will differ in different periods of a single refresh cycle, which will cause the display panel to have uneven brightness. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a pixel driving circuit, a display device and a driving method for a pixel circuit, which can solve the problem of uneven brightness of a display panel in a current display device.

[0006] In a first aspect, an embodiment of the present application provides a pixel driving circuit, the pixel driving circuit comprising: a first reset unit, a second reset unit and a driving unit;

[0007] The first reset unit is connected to the driving unit to receive a first control signal and reset the bias of the input end of the driving unit under the control of the first control signal;

[0008] The driving unit is connected to the light emitting element, and is used to receive the light emitting current of the light emitting element and transmit the light emitting current to the light emitting element;

[0009] The second resetting unit is connected to the light emitting element, and is used for receiving a second control signal and resetting the light emitting element under the control of the second control signal.

[0010] In a second aspect, an embodiment of the present application provides a display device, comprising: a pixel driving circuit as described in any one of the first aspects.

[0011] In a third aspect, an embodiment of the present application provides a driving method of a pixel driving circuit, which is applied to any pixel driving circuit described in the first aspect, or to the display device described in the second aspect, wherein the pixel driving circuit is used to drive the light-emitting element to emit light under multiple refresh cycles, and the refresh cycle includes a data refresh frame and at least one holding frame, the data refresh frame includes an initialization stage, a compensation stage, a reset stage and a light-emitting stage, and the holding frame includes a reset stage and a light-emitting stage; the method includes:

[0012] In the reset phase of the data refresh frame, the first control signal of the valid level is sent to the first reset unit, and the second control signal of the valid level is sent to the second reset unit, so that the first reset unit performs bias reset on the input end of the driving unit, and the second reset unit resets the light emitting element;

[0013] During the reset phase of the holding frame, the first control signal of a valid level is sent to the first reset unit, and the second control signal of an invalid level is sent to the second reset unit, so that the first reset unit performs a bias reset on the input end of the driving unit, and the second reset unit does not reset the light-emitting element.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the third aspect are implemented.

[0015] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the third aspect are implemented.

[0016] In a sixth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the method described in the third aspect.

[0017] In a seventh aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the method described in the sixth aspect.

[0018] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input terminal of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0019] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a partial structural schematic diagram of a pixel driving circuit provided by the related technology;

[0021] Figure 2 It is a schematic diagram of uneven brightness of a display panel provided by the related technology;

[0022] Figure 3 It is a schematic diagram of the color cast phenomenon of a display panel provided by the related technology;

[0023] Figure 4 It is a structural schematic diagram of a pixel driving circuit provided by the related technology;

[0024] Figure 5 It is a timing diagram of a pixel driving circuit provided by the related technology;

[0025] Figure 6 It is a structural schematic diagram of a display device provided by the related technology;

[0026] Figure 7 is a structural schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0027] Figure 8 is a structural schematic diagram of another pixel driving circuit provided in an embodiment of the present application;

[0028] Fig. 9 is a timing diagram of a pixel driving circuit provided in an embodiment of the present application;

[0029] Fig.10 is a structural schematic diagram of a display device provided in an embodiment of the present application;

[0030] Fig.11 is a flow chart of a driving method of a pixel driving circuit provided in an embodiment of the present application;

[0031] Fig.12 is a block diagram of an electronic device provided in an embodiment of the present application;

[0032] Fig.13 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0034] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0035] The problem of uneven brightness of the panel provided in the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0036] AMOLED display technology is widely used in electronic devices such as smartphones and smart watches due to its high contrast, fast response speed, wide viewing angle and wide color gamut.

[0037] The OLED of each pixel of the current AMOLED display panel is connected to its corresponding pixel driving circuit. The pixel driving circuit is used to transmit the light emitting current to the OLED under multiple refresh cycles to drive the OLED to emit light. The main components of the current pixel driving circuit are as follows: Figure 1As shown, it specifically includes: transistor T01, transistor T02, transistor T03 and transistor T04. Transistor T01, transistor T02, transistor T03 and transistor T04 are all P-type metal-oxide-semiconductor field effect transistors (positive channel Metal Oxide Semiconductor, PMOS).

[0038] The gate of transistor T01 is connected to the scan enable signal terminal EM, the source is connected to the power supply terminal VDD, and the drain is connected to the source of transistor T02. The gate of transistor T02 is connected to the energy storage output terminal T1, and the drain is connected to the source of transistor T03. The gate of transistor T03 is also connected to the scan enable signal terminal EM, and the drain is connected to the source of transistor T04. The drain of transistor T03 is also connected to the parasitic resistance R OLED The anode of OLED and the parasitic capacitance C of OLED OLED The parasitic capacitance C of OLED OLED The other end of and the cathode of OLED are connected to the common voltage terminal VSS. The gate of transistor T04 is connected to the reset signal terminal Pscan1, and the drain is connected to the voltage input terminal VINT. The cathode of OLED and the parasitic capacitance C OLED The other end is connected to the common voltage terminal Vss.

[0039] Among them, when the reset signal terminal Pscan1 provides a valid reset signal, the OLED is reset by the input voltage Vin of the voltage input terminal VINT, and when the scan enable signal terminal EM provides a valid scan signal, the transistors T01 and T03 are turned on, and the voltage provided by the energy storage output terminal T1 controls the transistor T02 to be turned on. The pixel driving circuit sequentially transmits the light-emitting current ITFT to the OLED through the transistors T01, T02 and T03 to drive the OLED to emit light.

[0040] like Figure 1 As shown, the luminous current I TFT The parasitic capacitance C of the OLED is shunted at node O. OLED The charging current I OLED_Cap , OLED lighting current I OLED and the bias current I of transistor T04 Vint , that is I TFT =I OLED_Cap +I OLED +I Vint Among them, I OLED Indicates the actual light-emitting current flowing through the OLED. OLED_Cap Indicates the charging current of the parasitic capacitance of the OLED before the OLED emits light at low brightness and low grayscale. I Vintrepresents the leakage current of transistor T4 when it is turned off, that is, the bias current I of transistor T04 Vint Usually it is a fixed value. Therefore, the lighting current IOLED of the OLED is mainly affected by the charging current I OLED_Cap diversion impact.

[0041] However, in order to meet the needs of high-precision variable frequency refresh rate, the current pixel driving circuit will cause the OLED to undergo multiple resets in a single refresh cycle, and each reset will cause the parasitic capacitance of the OLED to undergo a charge and discharge, which will cause the size of the lighting current of the OLED to change. Obviously, there are differences in the size of the lighting current of the OLED in different time periods in a single refresh cycle, which in turn causes the display panel to have uneven brightness. For example, taking the refresh cycle of the display screen as 120 Hz (Hz), within a frame time of 120Hz refresh, the pixel driving circuit will undergo three resets, which will cause the anode of the OLED to undergo three resets, and the reset frequency is too high. In addition, each OLED reset will cause the parasitic capacitance of the OLED to undergo a charge and discharge, resulting in differences in the degree of reset in different time periods of a single refresh cycle, and differences in the size of the lighting current of the OLED. As a result, the display panel shows dark Mura, and there is a problem of uneven display of three-part screen at low brightness and low grayscale. Such as Figure 2 As shown, under low brightness and low grayscale conditions, the display screen will show an obvious three-screen phenomenon.

[0042] In addition, the temperature of the display panel usually increases during use. The increased temperature will cause the parasitic capacitance of the OLED to increase, causing the light-emitting current ITFT to be shunted to the charging current IOLED_Cap of the parasitic capacitance to increase, which in turn causes the lighting current IOLED of the OLED to decrease, affecting the luminous brightness of the OLED. In addition, the degree of influence of temperature on the parasitic capacitance of OLEDs emitting different colors of light is different. In particular, the size of the parasitic capacitance of OLEDs emitting green light is more susceptible to the influence of temperature. Therefore, as the temperature of the display panel increases, the luminous brightness of the OLED emitting green light in the display panel will decrease, causing the color of the display screen of the display panel to be bluish, causing the display panel to have a temperature increase color cast problem.

[0043] For example, when the display panel is heated to a temperature above 50°C, the parasitic capacitance of the OLED of the green (G) pixel and the red (R) pixel increases more than the parasitic capacitance of the OLED of the blue (B) pixel, resulting in a larger increase in the light emitting current I TFT The charging current I of the green pixel OLED is OLED_Cap And the charging current I of the red pixel OLED OLED_CapCorrespondingly, the green pixel OLED lighting current I OLED And the charging current and lighting current I of the red pixel OLED OLED Similarly, the charging current I OLED_Cap The increase is small, and accordingly, the charging current and lighting current of the blue pixel OLED are I OLED This results in the mixing of the light emitted by the green pixel OLED, the red pixel OLED and the blue pixel OLED, making the entire display screen blue. For example, take 2nit32 grayscale as an example. Figure 3 As shown, Figure 3 The left side shows the display screen of the AMOLED display panel with 8T1C low temperature polycrystalline oxide (LTPO) after the temperature is increased, and the right side shows the display screen of the AMOLED display panel at normal temperature. Obviously, the display screen of the right display panel is bluer than that of the left display panel. Figure 2 The density of “×” indicates the degree of blueness of the displayed image.

[0044] It can be seen that under normal temperature, low brightness and low grayscale conditions, the display panel has uneven brightness due to multiple OLED resets in a single refresh cycle. In addition, under high temperature, low brightness and low grayscale conditions, the display panel also has a temperature rise color cast problem due to multiple OLED resets.

[0045] For an example, please refer to Figure 4 , which shows a schematic diagram of a pixel driving circuit provided by the related art. Figure 4 As shown, the pixel driving circuit is an 8T1C LTPO AMOLED pixel driving circuit, specifically including: a power supply voltage terminal ELVDD, a common voltage terminal ELVSS, a first input voltage terminal VINT1, a second input voltage terminal VINT2, a third input voltage terminal VINT3, a frame data terminal DATA, a row scan enable terminal EM, a first row scan line terminal PScan1, a second row scan line terminal PScan2, a third row scan line terminal NScan1 and a fourth row scan line terminal NScan2, a first transistor T1 to an eighth transistor T8, and an energy storage capacitor Cst.

[0046] The power supply voltage terminal ELVDD is used to provide a constant positive voltage, usually 4.6V, as the positive voltage of the AMOLED. The common voltage terminal ELVSS is used to provide an adjustable negative voltage as the negative voltage of the AMOLED. Specifically, the common voltage terminal ELVSS can be an adjustable negative voltage provided by the display driver chip of the display device to control the power chip. In addition, Figure 4The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are all P-type thin film transistors (TFT), which are in an on-state when the control end receives a low-level control signal, and are in an off-state when the control end receives a high-level control signal. The second transistor T2 and the sixth transistor T6 are both N-type thin film transistors, which are in an off-state when the control end receives a low-level control signal, and are in an on-state when the control end receives a high-level control signal.

[0047] In addition, the gate of the first transistor T1 is connected to the second row scan line terminal PScan2, the source of the first transistor T1 is connected to the frame data terminal DATA, and the drain of the first transistor T1 is connected to the second node N2. The gate of the second transistor T2 is connected to the third row scan line terminal NScan1, the source of the second transistor T2 is connected to the third node N3, and the drain of the second transistor T2 is connected to the first node N1. The gate of the third transistor T3 is connected to the row scan enable terminal EM, the source of the third transistor T3 is connected to the power supply voltage terminal ELVDD, and the drain of the third transistor T3 is connected to the second node N2. The gate of the fourth transistor T4 is connected to the row scan enable terminal EM, the source of the fourth transistor T4 is connected to the first node N1, and the drain of the fourth transistor T4 is connected to the anode of the AMOLED. The cathode of the AMOLED is connected to the common voltage terminal ELVSS. The gate of the fifth transistor T5 is connected to the fourth node N4, the source of the fifth transistor T5 is connected to the second node N2, and the drain of the fifth transistor T5 is connected to the first node N1. The gate of the sixth transistor T6 is connected to the fourth row scan line terminal NScan2, the source of the sixth transistor T6 is connected to the third node N3, and the drain of the sixth transistor T6 is connected to the first input voltage terminal VINT1. The gate of the seventh transistor T7 is connected to the first row scan line terminal PScan1, the source of the seventh transistor T7 is connected to the third input voltage terminal VINT3, and the drain of the seventh transistor T7 is connected to the second node N2. The gate of the eighth transistor T8 is connected to the first row scan line terminal PScan1, the drain of the eighth transistor T8 is connected to the anode of the AMOLED, and the source of the eighth transistor T8 is connected to the second input voltage terminal VINT2.

[0048] Wherein, the first node N1 is the electrical connection intersection between the third electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, and the third electrode of the second transistor T2. The second node N2 is the electrical connection node between the second electrode of the fifth transistor T5, the third electrode of the third transistor T3, the third electrode of the first transistor T1, and the third electrode of the seventh transistor T7. The third node N3 is the electrical connection node between the energy storage capacitor Cst, the second electrode of the second transistor T2, and the second electrode of the sixth transistor T6. The fourth node N4 is the electrical connection node between the energy storage capacitor Cst and the gate of the fifth transistor T5.

[0049] It should be noted that Figure 1 Among the main components shown, transistor T01 is the third transistor T3, transistor T02 is the fifth transistor T5, transistor T03 is the fourth transistor T4, and transistor T04 is the eighth transistor T8. One end of the energy storage capacitor Cst is connected to the power supply voltage terminal ELVDD, and the other end is connected to the third node N3.

[0050] like Figure 5 As shown, the driving principle of the AMOLED pixel driving circuit of 8T1C LTPO is: within the refresh period T for displaying a frame of image, the entire driving timing process may include a refresh period and a holding period. A single refresh cycle includes a data refresh frame under the refresh period, and two holding frames under the holding period. Among them, the refresh period is the driving stage of the data refresh frame, specifically including the initialization stage t1, the compensation stage t2, the reset stage t3 and the light-emitting stage t4, a total of four stages. The holding period is the refresh stage of two holding frames, specifically including the reset stage t5 and the light-emitting stage t6 of the first holding frame, and the reset stage t7 and the light-emitting stage t8 of the second holding frame, a total of four stages. The pixel driving circuit refreshes and displays a frame of image under the data refresh frame, and continuously refreshes and displays the displayed image under the data refresh frame under the holding frame. For Figure 4 The pixel driving circuit shown in the figure first refreshes and displays a frame of target image in a data refresh frame, then continuously refreshes and displays the target image in a first hold frame, and finally continuously refreshes and displays the target image again in a second hold frame in one refresh cycle.

[0051] Refresh period:

[0052] Initialization stage (stage 1) t1: the fourth row scan line terminal NScan2 is connected to a high level signal, the sixth transistor T6 is turned on, and the negative voltage provided by the first input voltage terminal VINT1 is written to the gate of the fifth transistor T5 (ie, the fourth node) through the sixth transistor T6, and is stored in the energy storage capacitor Cst for maintenance.

[0053] Compensation stage (stage 2) t2: The fourth row scan line terminal NScan2 is connected to a low level signal, and the sixth transistor T6 is turned off. The third row scan line terminal NScan1 is connected to a high level signal, and the second row scan line terminal PScan2 is connected to a low level signal. The second transistor T2 and the first transistor T1 are turned on, the gate and drain of the fifth transistor T5 are short-circuited, and the voltage |VA| of the fourth node N4 is greater than the threshold voltage |Vth| of the fifth transistor T5. At the same time, the fifth transistor T5 is continuously in the on state while maintaining the storage voltage of the energy storage capacitor Cst in the previous stage. At this time, the display data voltage Vdata connected to the frame data terminal DATA is stored in the energy storage capacitor Cst through the first transistor T1, the fifth transistor T5, and the second transistor T2. As the storage voltage of the energy storage capacitor Cst increases, the voltage of the fourth node N4 gradually increases to Vdata-|Vth|. The fifth transistor T5 is turned off and enters the off state. Through this operation, the threshold voltage of the fifth transistor T5 can be effectively compensated.

[0054] Reset stage (stage 3) t3: The third row scan line terminal NScan1 is connected to a low level signal, and the second row scan line terminal PScan2 is connected to a high level signal. The second transistor T2 and the first transistor T1 are turned off. The first row scan line terminal PScan1 is connected to a low level signal. The seventh transistor T7 and the eighth transistor T8 are turned on. The eighth transistor T8 is turned on, so that the negative voltage connected to the second input voltage terminal VINT2 is written to the anode of the AMOLED, and the AMOLED is reset to release the residual charge accumulated in the AMOLED. At this time, the anode voltage of the AMOLED is the negative voltage connected to the second input voltage terminal VINT2. At the same time, the seventh transistor T7 is turned on, so that the voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5, so as to provide a bias signal for the source of the fifth transistor T5, and the source of the fifth transistor T5 is biased and reset, which is also called bias compensation.

[0055] Light-emitting stage (stage 4) t4: The first row scan line terminal PScan1 is connected to a high-level signal. The seventh transistor T7 and the eighth transistor T8 are turned off. The row scan enable terminal EM is connected to a low-level signal, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the gate of the fifth transistor T5 is controlled to be in an on state under the action of the storage voltage Vdata-Vth output from the energy storage capacitor Cst to the fourth node N4. The power supply voltage terminal ELVDD is connected to the anode of the AMOLED, and the light-emitting current connected to the power supply voltage terminal ELVDD is introduced into the anode of the AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving the AMOLED to emit light.

[0056] The driving phase of the first hold frame in the hold period:

[0057] Reset stage (stage 5) t5: The scan enable terminal EM is connected to a high-level signal, and the first row scan line terminal PScan1 is connected to a low-level signal. The third transistor T3 and the fourth transistor T4 are turned off, and the seventh transistor T7 and the eighth transistor T8 are turned on. The eighth transistor T8 is turned on, so that the negative voltage connected to the second input voltage terminal VINT2 is written to the anode of the AMOLED, and the AMOLED is reset to release the residual charge accumulated in the AMOLED. At this time, the anode voltage of the AMOLED is the negative voltage connected to the second input voltage terminal VINT2. At the same time, the seventh transistor T7 is turned on, so that the voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5, so as to provide a bias signal for the source of the fifth transistor T5, and the source of the fifth transistor T5 is biased and reset, which is also called bias compensation.

[0058] Light-emitting stage (the sixth stage) t6: The first row scan line terminal PScan1 is connected to a high-level signal. The seventh transistor T7 and the eighth transistor T8 are turned off. The row scan enable terminal EM is connected to a low-level signal, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the gate of the fifth transistor T5 is controlled to be in an on state under the action of the storage voltage Vdata-Vth output from the energy storage capacitor Cst to the fourth node N4. The power supply voltage terminal ELVDD is connected to the anode of the AMOLED, and the light-emitting current connected to the power supply voltage terminal ELVDD is introduced into the anode of the AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving the AMOLED to emit light.

[0059] The driving phase of the second hold frame in the hold period:

[0060] Reset stage (the 7th stage) t7: The scan enable terminal EM is connected to a high-level signal, and the first row scan line terminal PScan1 is connected to a low-level signal. The third transistor T3 and the fourth transistor T4 are turned off, and the seventh transistor T7 and the eighth transistor T8 are turned on. The eighth transistor T8 is turned on, so that the negative voltage connected to the second input voltage terminal VINT2 is written to the anode of the AMOLED, and the AMOLED is reset to release the residual charge accumulated in the AMOLED. At this time, the anode voltage of the AMOLED is the negative voltage connected to the second input voltage terminal VINT2. At the same time, the seventh transistor T7 is turned on, so that the voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5, so as to provide a bias signal for the source of the fifth transistor T5, and the source of the fifth transistor T5 is biased and reset, which is also called bias compensation.

[0061] Light-emitting stage (the 8th stage) t8: The first row scan line terminal PScan1 is connected to a high-level signal. The seventh transistor T7 and the eighth transistor T8 are turned off. The row scan enable terminal EM is connected to a low-level signal, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the gate of the fifth transistor T5 is controlled to be in an on state under the action of the storage voltage Vdata-Vth output from the energy storage capacitor Cst to the fourth node N4. The power supply voltage terminal ELVDD is connected to the anode of the AMOLED, and the light-emitting current connected to the power supply voltage terminal ELVDD is introduced into the anode of the AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving the AMOLED to emit light.

[0062] It should be noted that the driving principle of the above-mentioned 8T1C LTPO AMOLED pixel driving circuit is described by taking the frame refresh frequency of the display panel as 120Hz as an example. Figure 5 It is not difficult to see from the driving process shown that within the refresh cycle of a frame of image (usually 120Hz), the scan enable terminal EM is connected to a low-level signal (i.e., an invalid signal indicating that the transistor is turned off) three times, and the first row scan line terminal PScan1 is connected to a high-level signal (i.e., a valid signal indicating that the transistor is turned on) three times, so that the pixel drive circuit is reset three times, and the signal frequency of the high-level signal connected to the first row scan line terminal PScan1 is 360Hz. In addition, the first row scan line terminal PScan1 is connected to a high-level signal three times, which also enables the source of the fifth transistor T5 to obtain effective bias compensation three times, effectively reducing the aging drift of the characteristics of the fifth transistor T5. At the same time, refresh rates such as 120Hz, 90Hz, 60Hz, 40Hz, 30Hz, 24Hz, 10Hz, 5Hz, 1Hz, etc. that can be divided by 360Hz can be achieved, so that the display screen switching of the display device is smoother, and different refresh rates are also adapted to different application scenarios, and power consumption is more optimized.

[0063] However, since the AMOLED pixel driving circuit of 8T1C LTPO undergoes three resets in a single refresh cycle, the AMOLED has different lighting currents in different time periods in a single refresh cycle, which in turn causes the display panel to have uneven brightness. In addition, as the temperature of the display panel rises, the luminance of the OLED that emits green light in the display panel will decrease, causing the color of the display panel to be blue, resulting in a temperature-induced color cast problem on the display panel.

[0064] For another example, see Figure 6 , which shows a schematic diagram of the structure of a display device provided by the related art. Figure 6As shown, the display device includes: a plurality of light-emitting units 601 located in the display area (AA area), an 8T1C LTPO AMOLED pixel driving circuit and a gate drive integrated on array substrate (Gate Driven on Array, GOA) circuit.

[0065] Each light-emitting unit 601 includes a plurality of light-emitting elements. Each light-emitting element has its corresponding 8T1CLTPO AMOLED pixel driving circuit, which is used to drive the light-emitting element to emit light. The GOA circuit is arranged in the non-display area on both sides of the display area of ​​the display device. The GOA circuit is connected to the AMOLED pixel driving circuit, and is used to provide the AMOLED pixel driving circuit with input signals of its row scan enable terminal EM, the first row scan line terminal PScan1, the second row scan line terminal PScan2, the third row scan line terminal NScan1 and the fourth row scan line terminal NScan2.

[0066] Specific as Figure 6 As shown in the figure, the GOA circuit includes: a first row scan line driving circuit 602, a third row scan line driving circuit 603, and a second row scan line driving circuit 604 located in a non-display area (left GOA circuit area) on the left side of the display device. The GOA circuit also includes: a second row scan line driving circuit 604, a fourth row scan line driving circuit 605, and a row scan enable driving circuit 606 located in a non-display area (right GOA circuit area) on the right side of the display device.

[0067] The first row scan line driving circuit 602 is used to provide an input signal to the first row scan line terminal PScan1. The second row scan line driving circuit 604 is used to provide an input signal to the second row scan line terminal PScan2. The third row scan line driving circuit 603 is used to provide an input signal to the third row scan line terminal NScan1. The fourth row scan line driving circuit 605 is used to provide an input signal to the fourth row scan line terminal NScan2. The row scan enable driving circuit 606 is used to provide an input signal to the row scan enable terminal EM.

[0068] and, Figure 6The first row scan line driving circuit 602, the third row scan line driving circuit 603, the fourth row scan line driving circuit 605 and the row scan enable driving circuit 606 are all shown as one, which is intended to indicate that these four driving circuits are all unilateral driving circuits, also known as 1-push-1 mode circuits. A unilateral driving circuit refers to a single driving circuit that synchronously provides input signals to the pixel driving circuit of an entire row of pixels. The second row scan line driving circuit 604 is shown on both the left and right sides of the display area, which is intended to indicate that the second row scan line driving circuit 604 is a bilateral driving circuit, also known as a 1-push-2 mode circuit. A bilateral driving circuit refers to two driving circuits that jointly provide input signals to the pixel driving circuit of a single row of pixels. In addition, it should be noted that the AMOLED pixel driving circuit of 8T1CLTPO performs row scanning in groups of two rows of pixels. Figure 6 Take part of the light-emitting units of the n-th row of pixels and part of the light-emitting units of the n+1-th row of pixels as an example. Accordingly, in the GOA circuit, the first row scan line driving circuit 602, the third row scan line driving circuit 603, the fourth row scan line driving circuit 605 and the row scan enable driving circuit 606 are all used to synchronously provide input signals to the driving circuits of the n-th row of pixels and the n+1-th row of pixels. The GOA circuit includes four second row scan line driving circuits 604 in groups of two. One group of second row scan line driving circuits 604 jointly provides input signals to the driving circuits of the n-th row of pixels; another group of second row scan line driving circuits 604 jointly provides input signals to the driving circuits of the n+1-th row of pixels.

[0069] Please refer to Figure 7 , which shows a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present application. Figure 7 As shown, the pixel driving circuit includes: a first resetting unit 701 , a second resetting unit 702 and a driving unit 703 .

[0070] Connection between the first reset unit 701 and the driving unit 703. The first reset unit 701 is used to receive a first control signal and reset the bias of the input end of the driving unit 703 under the control of the first control signal.

[0071] The driving unit 703 is connected to the light emitting element 2. The driving unit 703 is used to receive the light emitting current of the light emitting element 2 and transmit the light emitting current to the light emitting element 2.

[0072] The second resetting unit 702 is connected to the light emitting element 2, and is used for receiving a second control signal and resetting the light emitting element 2 under the control of the second control signal.

[0073] The level of the first control signal may be an effective level or an ineffective level. The first reset unit 701 is used to reset the bias of the input end of the driving unit 703 under the control of the first control signal of the effective level; and does not reset the bias of the input end of the driving unit 703 under the control of the first control signal of the ineffective level. Similarly, the level of the second control signal may be an effective level or an ineffective level. The second reset unit 702 is used to reset the light emitting element 2 under the control of the second control signal of the effective level; and does not reset the light emitting element 2 under the control of the second control signal of the ineffective level.

[0074] In some embodiments of the present application, the first reset unit 701 is used to receive a first voltage and a first control signal, and under the control of the first control signal of a valid level, output the first voltage to the input end of the driving unit 703 to perform a bias reset on the input end of the driving unit 703; under the control of the first control signal of an invalid level, stop outputting the first voltage to the input end of the driving unit 703 to not perform a bias reset on the input end of the driving unit 703.

[0075] The second reset unit 702 is used to receive a second voltage and a second control signal, and under the control of the second control signal of a valid level, output the second voltage to the anode of the light-emitting element 2 to reset the light-emitting element; under the control of the second control signal of an invalid level, output the second voltage to the anode of the light-emitting element 2 to not perform the reset of the light-emitting element 2.

[0076] Alternatively, if Figure 8 As shown, the first reset unit 701 includes a seventh transistor T7. The control end of the seventh transistor T7 is used to receive the first control signal, the input end of the seventh transistor T7 is used to receive the first voltage, and the output end of the seventh transistor T7 is connected to the driving unit 703. The seventh transistor T7 is used to output the first voltage to the input end of the driving unit 703 under the control of the first control signal. By way of example, the seventh transistor T7 can be a P-type thin film transistor. The gate of the seventh transistor T7 is used to receive the first control signal, the source of the seventh transistor T7 is used to receive the first voltage, and the drain of the seventh transistor T7 is connected to the input end of the driving unit 703. The seventh transistor T7 is used to turn on or off under the control of the first control signal. Among them, the seventh transistor T7 is used to turn on under the control of the first control signal of the effective level to output the first voltage to the input end of the driving unit 703; and to turn off under the control of the first control signal of the invalid level to output the first voltage to the input end of the driving unit 703. The effective level of the first control signal refers to the low level, and the invalid level refers to the high level.

[0077] Alternatively, please refer to Figure 8, the second reset unit 702 includes an eighth transistor T8. The control end of the eighth transistor T8 is used to receive the second control signal, the input end of the eighth transistor T8 is used to receive the second voltage, and the output end of the eighth transistor T8 is connected to the light-emitting element 2. The eighth transistor T8 is used to output the second voltage to the light-emitting element 2 under the control of the second control signal. For example, the gate of the eighth transistor T8 is used to receive the second control signal, the source of the eighth transistor T8 is used to receive the second voltage, and the drain of the eighth transistor T8 is connected to the anode of the light-emitting element 2. The eighth transistor T8 is used to turn on or off under the control of the second control signal. Among them, the eighth transistor T8 is used to turn on under the control of the second control signal of the effective level to output the second voltage to the light-emitting element 2; and to turn off under the control of the second control signal of the invalid level to stop outputting the second voltage to the light-emitting element 2. The effective level of the second control signal refers to the low level, and the invalid level refers to the high level.

[0078] In an embodiment of the present application, the pixel driving circuit is used to drive the light-emitting element 2 to emit light under multiple refresh cycles. The refresh cycle includes a data refresh frame and at least one hold frame. Among them, the data refresh frame includes an initialization phase, a compensation phase, a reset phase and a light-emitting phase. The hold frame includes a reset phase and a light-emitting phase. In the reset phase of the data refresh frame, the first reset unit 701 can receive a first control signal of an effective level, and bias reset the input end of the driving unit 703 under the control of the first control signal of the effective level. The second reset unit 702 can receive a second control signal of an effective level, and reset the light-emitting element 2 under the control of the second control signal of the effective level.

[0079] In the reset phase of the hold frame, the first reset unit 701 may receive a first control signal of a valid level, and under the control of the first control signal of the valid level, bias reset the input end of the driving unit 703. The second reset unit 702 may receive a second control signal of an invalid level, and under the control of the second control signal of the invalid level, does not reset the light emitting element 2. It should be noted that, in some embodiments, the driving principle and process of the pixel driving circuit in the initialization phase, compensation phase and light emitting phase in the data refresh frame, and in the light emitting phase in the hold frame may refer to the relevant technology.

[0080] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input end of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0081] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent.

[0082] Alternatively, if Figure 7 As shown, the pixel driving circuit further includes: a compensation unit 704 , a light emitting control unit 705 and a storage unit 706 .

[0083] The compensation unit 704 is also connected to the first node N1 and the storage unit 706. The compensation unit 704 is used to receive frame data (i.e., display data voltage) and write the frame data into the storage unit 706 through the second node N2 and the first node N1. The first node N1 is an electrical connection point between the driving unit 703, the light emitting control unit 705 and the compensation unit 704. The second node N2 is an electrical connection point between the compensation unit 704, the first reset unit 701, the light emitting control unit 705 and the driving unit 703. The light emitting control unit 705 is used to receive the light emitting current and transmit the light emitting current to the light emitting element 2 through the driving unit 703. Optionally, as Figure 8 As shown, the storage unit 706 may be a capacitor Cst.

[0084] Optionally, the compensation unit 704 is used to receive the third control signal, the fourth control signal and the frame data, and write the frame data into the storage unit 706 through the second node N2 and the first node N1 under the control of the third control signal and the fourth control signal. The levels of the third control signal and the fourth control signal may be valid levels or invalid levels. The compensation unit 704 is used to write the frame data into the storage unit 706 through the second node N2 and the first node N1 under the control of the third control signal of the valid level and the fourth control signal of the valid level; under the control of the third control signal of the invalid level and / or the fourth control signal of the invalid level, the operation of writing the frame data into the storage unit 706 is not performed.

[0085] The light-emitting control unit 705 is used to receive the fifth control signal and the light-emitting current, and transmit the light-emitting current to the light-emitting element 2 through the driving unit 703 under the control of the fifth control signal. The level of the fifth control signal can be an effective level or an invalid level. The light-emitting control unit 705 is used to transmit the light-emitting current to the light-emitting element 2 through the driving unit 703 under the control of the fifth control signal of the effective level; under the control of the fifth control signal of the invalid level, the operation of transmitting the light-emitting current to the light-emitting element 2 is not performed.

[0086] In some embodiments of the present application, Figure 8 As shown, the compensation unit 704 includes a first transistor T1 and a second transistor T2. The control end of the first transistor T1 is used to receive a third control signal, the input end of the first transistor T1 is used to receive frame data, and the output end of the first transistor T1 is connected to the driving unit 703. The first transistor T1 is used to output frame data to the driving unit 703 under the control of the third control signal.

[0087] The control end of the second transistor T2 is used to receive the fourth control signal, the input end of the second transistor T2 is connected to the driving unit 703, and the output end of the second transistor T2 is connected to the storage unit 706. The second transistor T2 is used to write the frame data transmitted by the driving unit 703 to the storage unit 706 under the control of the fourth control signal.

[0088] By way of example, the first transistor T1 may be a P-type thin film transistor. The gate of the first transistor T1 is used to receive a third control signal, the source of the first transistor T1 is used to receive frame data, and the drain of the first transistor T1 is connected to the driving unit 703. The first transistor T1 is used to be turned on or off under the control of the third control signal. The first transistor T1 is used to be turned on under the control of the third control signal of an effective level to output frame data to the driving unit 703; and to be turned off under the control of the third control signal of an invalid level to stop outputting frame data to the driving unit 703. The effective level of the third control signal refers to a low level, and the invalid level refers to a high level.

[0089] The second transistor T2 may be an N-type thin film transistor. The gate of the second transistor T2 is used to receive the fourth control signal, the drain of the second transistor T2 is connected to the driving unit 703, and the source of the second transistor T2 is connected to the storage unit 706. The second transistor T2 is used to be turned on or off under the control of the fourth control signal. The second transistor T2 is used to be turned on under the control of the fourth control signal of the effective level to write frame data to the storage unit 706; and turned off under the control of the fourth control signal of the invalid level to stop writing frame data to the storage unit 706. The effective level of the fourth control signal refers to a high level, and the invalid level refers to a low level.

[0090] In some embodiments of the present application, Figure 8 As shown, the light-emitting control unit 705 includes: a third transistor T3 and a fourth transistor T4. The control end of the third transistor T3 is used to receive the fifth control signal, the input end of the third transistor T3 is used to receive the light-emitting current, and the output end of the third transistor T3 is connected to the driving unit 703. The control end of the fourth transistor T4 is used to receive the fifth control signal, the input end of the fourth transistor T4 is connected to the driving unit 703, and the output end of the fourth transistor T4 is connected to the light-emitting element 2. The third transistor T3 and the fourth transistor T4 are used to be synchronously turned on under the control of the fifth control signal to output the light-emitting current to the light-emitting element 2.

[0091] By way of example, the third transistor T3 may be a P-type thin film transistor. The gate of the third transistor T3 is used to receive the fifth control signal, the source of the third transistor T3 is used to receive the light-emitting current, and the drain of the third transistor T3 is connected to the driving unit 703. The fourth transistor T4 may be a P-type thin film transistor. The gate of the fourth transistor T4 is used to receive the fifth control signal, the source of the fourth transistor T4 is connected to the driving unit 703, and the drain of the fourth transistor T4 is connected to the light-emitting element 2. The third transistor T3 and the fourth transistor T4 are used to be synchronously turned on or off under the control of the fifth control signal. Among them, the third transistor T3 and the fourth transistor T4 are used to be synchronously turned on under the control of the fifth control signal to output the light-emitting current to the light-emitting element 2; and synchronously turned off under the control of the fifth control signal to stop outputting the light-emitting current to the light-emitting element 2. The effective level of the fifth control signal refers to a low level, and the invalid level refers to a high level.

[0092] Alternatively, if Figure 8As shown, the driving unit 703 includes a fifth transistor T5. The control end of the fifth transistor T5 is connected to the storage unit 706, the input end of the fifth transistor T5 is respectively connected to the output end of the first transistor T1 and the output end of the third transistor T3, and the output end of the fifth transistor T5 is respectively connected to the input end of the second transistor T2 and the input end of the fourth transistor T4. The fifth transistor T5 is used to turn on the second node N2 and the first node N1 under the control of the output voltage of the storage unit 706.

[0093] The first node N1 is an electrical connection point between the output end of the fifth transistor T5, the input end of the sixth transistor T6, and the input end of the second transistor T2. The second node N2 is an electrical connection point between the input end of the fifth transistor T5, the output end of the third transistor T3, the output end of the first transistor T1, and the output end of the seventh transistor T7.

[0094] For example, the fifth transistor T5 can be a P-type thin film transistor. The gate of the fifth transistor T5 is connected to the storage unit 706, the source of the fifth transistor T5 is respectively connected to the output end of the first transistor T1 and the output end of the third transistor T3, and the drain of the fifth transistor T5 is respectively connected to the input end of the second transistor T2 and the input end of the fourth transistor T4. The fifth transistor T5 is used to be turned on or off under the control of the output voltage of the storage unit 706. Among them, the fifth transistor T5 is used to be turned on under the control of the output voltage of the storage unit 706 to connect the second node N2 and the first node N1; and turned off under the control of the output voltage of the storage unit 706 to disconnect the second node N2 and the first node N1.

[0095] In some embodiments of the present application, Figure 7 As shown, the pixel driving circuit further includes: a third reset unit 707. The third reset unit 707 is connected to the storage unit 706. The third reset unit 707 is used to output a keep-on voltage to the storage unit 706. The keep-on voltage is used to control the driving unit 703 to connect the first node N1 and the second node N2.

[0096] Optionally, the third reset unit 707 is used to receive a sixth control signal, and output a keep-on voltage to the storage unit 706 under the control of the sixth control signal. The level of the sixth control signal may be a valid level or an invalid level. The third reset unit 707 is used to output the keep-on voltage to the storage unit 706 under the control of the sixth control signal of the valid level; and stop outputting the keep-on voltage to the storage unit 706 under the control of the sixth control signal of the invalid level.

[0097] In some embodiments of the present application, Figure 8As shown, the third reset unit 707 includes: a sixth transistor T6. The control end of the sixth transistor T6 is used to receive the sixth control signal, the input end of the sixth transistor T6 is used to receive the keep-on voltage, and the output end of the sixth transistor T6 is connected to the third node N3. The sixth transistor T6 is used to output the keep-on voltage to the storage unit 706 under the control of the sixth control unit. The third node N3 is an electrical connection intersection between the compensation unit 704 and the storage unit 706.

[0098] By way of example, the sixth transistor T6 may be an N-type thin film transistor. The gate of the sixth transistor T6 is used to receive the sixth control signal, the drain of the sixth transistor T6 is used to receive the keep-on voltage, and the source of the sixth transistor T6 is connected to the third node N3. The sixth transistor T6 is used to be turned on or off under the control of the sixth control unit. Among them, the sixth transistor T6 is used to be turned on under the control of the sixth control unit of the effective level to output the keep-on voltage to the storage unit 706; and turned off under the control of the sixth control unit of the invalid level to stop outputting the keep-on voltage to the storage unit 706. The effective level of the sixth control signal refers to a high level, and the invalid level refers to a low level. By way of further example, the third node N3 is the electrical connection intersection between the output end of the second transistor T2 and the storage unit 706. The source of the sixth transistor T6 is connected to the third node N3, so that the third node N3 is the electrical connection intersection between the output end of the second transistor T2, the output end of the sixth transistor T6, and the storage unit 706.

[0099] In some embodiments of the present application, Figure 7 The pixel driving circuit shown includes: a first resetting unit 701 , a second resetting unit 702 , a driving unit 703 , a compensation unit 704 , a light emitting control unit 705 , a storage unit 706 and a third resetting unit 707 . Figure 7 The driving timing of the pixel driving circuit shown can be:

[0100] In the refresh cycle T for displaying a frame of image, the entire driving timing process may include a refresh period and a hold period. A single refresh cycle includes a data refresh frame in the refresh period and at least one hold frame in the hold period. For example, a single refresh cycle includes a data refresh frame and a hold frame.

[0101] The refresh period is the driving stage of the data refresh frame, which specifically includes the initialization stage T1, the compensation stage T2, the reset stage T3 and the light-emitting stage T4, a total of four stages. The hold period is the refresh stage of a hold frame, which specifically includes the reset stage T5 and the light-emitting stage T6 of the first hold frame, a total of two stages. The pixel drive circuit refreshes and displays a frame of image under the data refresh frame, and continuously refreshes and displays the display image under the data refresh frame under the hold frame.

[0102] Refresh period:

[0103] Initialization stage (first stage) T1: the third reset unit 707 may receive the sixth control signal of the effective level, and output the hold-on voltage to the storage unit 706, so as to store and hold the hold-on voltage in the storage unit 706.

[0104] Compensation stage (second stage) T2: The third reset unit 707 may receive the sixth control signal of the invalid level and stop outputting the hold-on voltage to the storage unit 706. At this time, the driving unit 703 connects the first node N1 and the second node N2 under the control of the hold-on voltage of the storage unit 706. At the same time, the compensation unit 704 may receive the third control signal of the valid level and the fourth control signal of the valid level, and write the received frame data into the storage unit 706 through the second node N2 and the first node N1.

[0105] Reset stage (third stage) T3: The compensation unit 704 may receive the third control signal of the invalid level and the fourth control signal of the invalid level, and stop writing frame data to the storage unit 706. The first reset unit 701 may receive the first control signal of the valid level, and output the first voltage to the first node N1 to reset the bias of the first node N1. At the same time, the second reset unit 702 may receive the second control signal of the valid level, and output the second voltage to the anode of the light-emitting element 2 to reset the anode of the light-emitting element 2.

[0106] Light-emitting stage (the fourth stage) T4: The first reset unit 701 may receive the first control signal of the invalid level and stop outputting the first voltage to the first node N1. At the same time, the second reset unit 702 may receive the second control signal of the invalid level and stop resetting the anode of the light-emitting element 2. Furthermore, the driving unit 703 connects the first node N1 and the second node N2 under the control of the on-voltage of the storage unit 706. The light-emitting control unit 705 may receive the fifth control signal of the valid level and output the light-emitting current to the light-emitting element 2 to drive the light-emitting element 2 to emit light.

[0107] The driving phase of a hold frame in the hold period:

[0108] Reset stage (fifth stage) T5: The light emitting control unit 705 may receive the fifth control signal of the invalid level and stop outputting the light emitting current to the light emitting element 2. The first reset unit 701 may receive the first control signal of the valid level and output the first voltage to the first node N1 to reset the bias of the first node N1. At the same time, the second reset unit 702 may receive the second control signal of the invalid level and stop outputting the second voltage to the anode of the light emitting element 2 so as not to perform the reset operation of the anode of the light emitting element 2.

[0109] Light-emitting stage (sixth stage) T6: The first reset unit 701 may receive the first control signal of the invalid level and stop outputting the first voltage to the first node N1. At the same time, the second reset unit 702 may receive the second control signal of the invalid level and stop resetting the anode of the light-emitting element 2. Furthermore, the driving unit 703 connects the first node N1 and the second node N2 under the control of the on-voltage of the storage unit 706. The light-emitting control unit 705 may receive the fifth control signal of the valid level and output the light-emitting current to the light-emitting element 2 to drive the light-emitting element 2 to emit light.

[0110] To further illustrate the pixel driving circuit provided by the embodiment of the present application, the following Figure 8 The pixel driving circuit shown is further described schematically. Figure 8 The pixel driving circuit shown is a pixel driving circuit of 8T1C LTPO, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 are all P-type thin film transistors. The second transistor T2 and the sixth transistor T6 are both N-type thin film transistors. The light-emitting element driven by the pixel driving circuit is OLED. Of course, the light-emitting element can also be AMOLED, etc., without limitation.

[0111] against Figure 8The pixel driving circuit shown includes: a power supply voltage terminal ELVDD, a common voltage terminal ELVSS, a first input voltage terminal VINT1, a second input voltage terminal VINT2, a third input voltage terminal VINT3, a frame data terminal DATA, a row scan enable terminal EM, a first row scan line terminal PScan1, a second row scan line terminal PScan2, a third row scan line terminal NScan1, a fourth row scan line terminal NScan2, a fifth row scan line terminal PScan3, a first transistor T1 to an eighth transistor T7, and an energy storage capacitor Cst. The power supply voltage terminal ELVDD is used to provide a constant positive voltage. The common voltage terminal ELVSS is used to provide an adjustable negative voltage. The first input voltage terminal VINT1 is used to provide a voltage to keep the conduction on, also known as the energy storage capacitor initialization voltage. The second input voltage terminal VINT2 is used to provide a second voltage, also known as the anode reset voltage of the OLED. The third input voltage terminal VINT3 is used to provide a first voltage, also known as the source bias compensation voltage of the driving transistor (i.e., the fifth transistor T5). The row scan enable terminal EM is used to provide a fifth control signal, also known as the gate control signal of the third transistor T3 and the fourth transistor T4. The first row scan line terminal PScan1 is used to provide a second control signal, also known as the gate control signal of the eighth transistor T8. The second row scan line terminal PScan2 is used for a third control signal, also known as the gate control signal of the first transistor T1. The third row scan line terminal NScan1 is used to provide a fourth control signal, also known as the gate control signal of the second transistor T2. The fourth row scan line terminal NScan2 is used to provide a sixth control signal, also known as the gate control signal of the sixth transistor T6. The fifth row scan line terminal PScan3 is used to provide a first control signal, also known as the gate control signal of the seventh transistor T7.

[0112] Among them, the gate of the first transistor T1 is connected to the second row scan line terminal PScan2, the source of the first transistor T1 is connected to the frame data terminal DATA, and the drain of the first transistor T1 is connected to the second node N2. The gate of the second transistor T2 is connected to the third row scan line terminal NScan1, the source of the second transistor T2 is connected to the third node N3, and the drain of the second transistor T2 is connected to the first node N1. The gate of the third transistor T3 is connected to the row scan enable terminal EM, the source of the third transistor T3 is connected to the power supply voltage terminal ELVDD, and the drain of the third transistor T3 is connected to the second node N2. The gate of the fourth transistor T4 is connected to the row scan enable terminal EM, the source of the fourth transistor T4 is connected to the first node N1, and the drain of the fourth transistor T4 is connected to the anode of AMOLED. The cathode of AMOLED is connected to the common voltage terminal ELVSS. The gate of the fifth transistor T5 is connected to the fourth node N4, the source of the fifth transistor T5 is connected to the second node N2, and the drain of the fifth transistor T5 is connected to the first node N1. The gate of the sixth transistor T6 is connected to the fourth row scan line terminal NScan2, the source of the sixth transistor T6 is connected to the third node N3, and the drain of the sixth transistor T6 is connected to the first input voltage terminal VINT1. The gate of the seventh transistor T7 is connected to the first row scan line terminal PScan1, the source of the seventh transistor T7 is connected to the third input voltage terminal VINT3, and the drain of the seventh transistor T7 is connected to the second node N2. The gate of the eighth transistor T8 is connected to the fifth row scan line terminal PScan3, the drain of the eighth transistor T8 is connected to the anode of the AMOLED, and the source of the eighth transistor T8 is connected to the second input voltage terminal VINT2.

[0113] Take a single refresh cycle T including a data refresh frame in the refresh period and two hold frames in the hold period as an example. Fig. 9 As shown, the driving timing of the pixel driving circuit can be:

[0114] Refresh period:

[0115] Initialization phase (first phase) t1: the fourth row scan line terminal NScan2 is connected to the high-level sixth control signal, the sixth transistor T6 is turned on, and the hold-on voltage provided by the first input voltage terminal VINT1 is written to the fourth node through the sixth transistor T6 and stored in the energy storage capacitor Cst for maintenance.

[0116] Compensation stage (second stage) t2: The fourth row scan line terminal NScan2 is connected to the low-level sixth control signal, and the sixth transistor T6 is turned off. The third row scan line terminal NScan1 is connected to the high-level fourth control signal, and the second row scan line terminal PScan2 is connected to the low-level third control signal. The second transistor T2 and the first transistor T1 are turned on. At the same time, the fifth transistor T5 is continuously in the on state under the maintenance of the storage voltage of the energy storage capacitor Cst in the previous stage. At this time, the display data voltage connected to the frame data terminal DATA is stored in the energy storage capacitor Cst through the first transistor T1, the fifth transistor T5, and the second transistor T2.

[0117] Reset stage (stage 3) t3: The third row scan line terminal NScan1 is connected to the fourth control signal of low level, and the second row scan line terminal PScan2 is connected to the third control signal of high level. The second transistor T2 and the first transistor T1 are turned off. The first row scan line terminal PScan1 is connected to the first control signal of low level, and the seventh transistor T7 is turned on. At the same time, the fifth row scan line terminal PScan3 is connected to the second control signal of low level, and the eighth transistor T8 is turned on. The eighth transistor T8 is turned on, so that the second voltage connected to the second input voltage terminal VINT2 is written to the anode of the OLED to reset the OLED. At the same time, the seventh transistor T7 is turned on, so that the first voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5 to bias and reset the source of the fifth transistor T5.

[0118] Light-emitting stage (the fourth stage) t4: The first row scan line terminal PScan1 is connected to the first control signal of high level, and the seventh transistor T7 is turned off. The fifth row scan line terminal PScan3 is connected to the second control signal of high level, and the eighth transistor T8 is turned off. The row scan enable terminal EM is connected to the fifth control signal of low level, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the fifth transistor T5 is turned on under the action of the storage voltage output by the energy storage capacitor Cst. The power supply voltage terminal ELVDD is connected to the anode of AMOLED, and the light-emitting current connected to the power supply voltage terminal ELVDD is introduced into the anode of AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving AMOLED to emit light.

[0119] The driving phase of the first hold frame in the hold period:

[0120] Reset stage (stage 5) t5: The row scan enable terminal EM is connected to the fifth control signal of high level, and the third transistor T3 and the fourth transistor T4 are turned off. The fifth row scan line terminal PScan3 is connected to the second control signal of high level, and the eighth transistor T8 is turned off. The first row scan line terminal PScan1 is connected to the first control signal of low level, the seventh transistor T7 is turned on, and the first voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5 to reset the bias of the source of the fifth transistor T5.

[0121] Light-emitting stage (sixth stage) t6: The first row scan line terminal PScan1 is connected to a high-level signal. The seventh transistor T7 is turned off. The row scan enable terminal EM is connected to a low-level fifth control signal, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the fifth transistor T5 is turned on under the action of the storage voltage output by the energy storage capacitor Cst, and the connected light-emitting current is introduced into the anode of the AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving the AMOLED to emit light.

[0122] The driving phase of the second hold frame in the hold period:

[0123] Reset stage (stage 7) t7: The row scan enable terminal EM is connected to the fifth control signal of high level, and the third transistor T3 and the fourth transistor T4 are turned off. The fifth row scan line terminal PScan3 is connected to the second control signal of high level, and the eighth transistor T8 is turned off. The first row scan line terminal PScan1 is connected to the first control signal of low level, the seventh transistor T7 is turned on, and the first voltage connected to the third input voltage terminal VINT3 is transmitted to the source of the fifth transistor T5 to reset the bias of the source of the fifth transistor T5.

[0124] Light-emitting stage (eighth stage) t8: The first row scan line terminal PScan1 is connected to a high-level signal. The seventh transistor T7 is turned off. The row scan enable terminal EM is connected to a low-level fifth control signal, and the third transistor T3 and the fourth transistor T4 are turned on. At the same time, the fifth transistor T5 is turned on under the action of the storage voltage output by the energy storage capacitor Cst, and the connected light-emitting current is introduced into the anode of the AMOLED through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, driving the AMOLED to emit light.

[0125] It should be noted that the pixel driving circuit provided in the embodiment of the present application may also be 8T1C low temperature polysilicon (LowTemperature Poly-silicon, LTPS). In the case where the pixel driving circuit is a pixel driving circuit of 8T1C LTPS, the difference between the pixel driving circuit and the pixel driving circuit of 8T1C LTPO is that the second transistor T2 and the sixth transistor T6 are both P-type thin film transistors. Correspondingly, the effective level of the gate control signal (i.e., the fourth control signal) of the second transistor T2 is a low level, and the invalid level is a high level. The effective level of the gate control signal (i.e., the sixth control signal) of the sixth transistor T6 is a low level, and the invalid level is a high level.

[0126] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input end of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0127] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent.

[0128] The present application also provides a display device, which includes the pixel driving circuit provided by the present application. Fig.10 , which shows a schematic diagram of the structure of a display device provided by an embodiment of the present application. Fig.10 As shown, the display device includes: a plurality of light-emitting units 601 located in a display area (AA area), a pixel driving circuit ( Fig.10 not shown) and GOA circuit.

[0129] The light-emitting unit is also called a pixel 601, and each light-emitting unit 601 includes a plurality of light-emitting elements, also called sub-pixels. Each light-emitting element has a corresponding pixel driving circuit for driving the light-emitting element to emit light. Fig.10 In the figure, a module in which each light-emitting unit 601 includes two light-emitting elements G emitting green light, one light-emitting element R emitting red light, and one light-emitting element B emitting blue light is taken as an example.

[0130] In addition, the GOA circuit is arranged in the non-display area on both sides of the display area of ​​the display device. The GOA circuit is connected to the pixel driving circuit, and is used to provide the pixel driving circuit with input signals of its row scanning enable terminal EM, the first row scanning line terminal PScan1, the second row scanning line terminal PScan2, the third row scanning line terminal NScan1, the fourth row scanning line terminal NScan2, and the fifth row scanning line terminal PScan3.

[0131] Specifically, if Fig.10 As shown, the GOA circuit includes: a first row scan line driving circuit 602, a third row scan line driving circuit 603, a second row scan line driving circuit 604 and a fifth row scan line driving circuit 607 located in a non-display area (left GOA circuit area) on the left side of the display device. The GOA circuit also includes: a second row scan line driving circuit 604, a fourth row scan line driving circuit 605 and a row scan enable driving circuit 606 located in a non-display area (right GOA circuit area) on the right side of the display device.

[0132] The first row scan line driving circuit 602 is used to provide a first control signal connected to the first row scan line terminal PScan1. The second row scan line driving circuit 604 is used to provide a sixth control signal connected to the second row scan line terminal PScan2. The third row scan line driving circuit 603 is used to provide a fourth control signal connected to the third row scan line terminal NScan1. The fourth row scan line driving circuit 605 is used to provide a sixth control signal connected to the fourth row scan line terminal NScan2. The fifth row scan line driving circuit 607 is used to provide a second control signal connected to the fifth row scan line terminal PScan3. The row scan enable driving circuit 606 is used to provide a fifth control signal to the row scan enable terminal EM.

[0133] In some embodiments, the first row scan line driving circuit 602, the third row scan line driving circuit 603, the fourth row scan line driving circuit 605, the fifth row scan line driving circuit 607 and the row scan enable driving circuit 606 can all be single-sided driving circuits. The second row scan line driving circuit 604 can be a double-sided driving circuit. In addition, it should be noted that Fig.10 The pixel driving circuit performs row scanning with two rows of pixels as a group. Fig.10Take part of the light-emitting units of the n-th row of pixels and part of the light-emitting units of the n+1-th row of pixels as an example. Accordingly, in the GOA circuit, the first row scan line driving circuit 602, the third row scan line driving circuit 603, the fourth row scan line driving circuit 605, the fifth row scan line driving circuit 607 and the row scan enable driving circuit 606 are all used to synchronously provide input signals to the driving circuits of the n-th row of pixels and the n+1-th row of pixels. The GOA circuit includes four second row scan line driving circuits 604 in groups of two. One group of second row scan line driving circuits 604 jointly provides input signals to the driving circuits of the n-th row of pixels; another group of second row scan line driving circuits 604 jointly provides input signals to the driving circuits of the n+1-th row of pixels.

[0134] In the embodiment of the present application, the fifth scan line driving circuit 607 may also be arranged in the non-display area (right GOA circuit area) on the right side of the display device. Alternatively, the fifth scan line driving circuit 607 may also be partially arranged in the left GOA circuit area of ​​the display device and partially arranged in the right GOA circuit area. Of course, the fifth scan line driving circuit 607 may also be a bilateral driving circuit. The embodiment of the present application does not limit this.

[0135] For example, for the pixel driving circuit provided in the embodiment of the present application, within the refresh period T of displaying a frame of image, the entire driving timing process may include a refresh period and a hold period. A single refresh period includes a data refresh frame in the refresh period and x hold frames in the hold period, where x>1. The GOA circuit may be used to execute the driving method of the pixel driving circuit provided in the embodiment of the present application to drive the pixel driving circuit, specifically including:

[0136] In the initialization phase of the data refresh frame, a sixth control signal of a valid level is sent to the third reset unit 707;

[0137] In the compensation phase of the data refresh frame, a sixth control signal of an invalid level may be sent to the third reset unit 707, and a third control signal of an effective level and a fourth control signal of an effective level may be sent to the compensation unit 704;

[0138] In the reset phase of the data refresh frame, a third control signal of an invalid level and a fourth control signal of an invalid level are sent to the compensation unit 704. In addition, a first control signal of an effective level is sent to the first reset unit 701, and a second control signal of an effective level is sent to the second reset unit 702;

[0139] In the light-emitting phase of the data refresh frame, a first control signal of an invalid level is sent to the first reset unit 701, a second control signal of an invalid level is sent to the second reset unit 702, and a fifth control signal of a valid level is sent to the light-emitting control unit 705 to drive the light-emitting element 2 to emit light;

[0140] In the reset phase of the i-th (1≤i≤x) holding frame, a fifth control signal of an invalid level is sent to the light emitting control unit 705, a first control signal of a valid level is sent to the first reset unit 701, and a second control signal of an invalid level is sent to the second reset unit 702;

[0141] During the light-emitting stage of the i-th holding frame, a first control signal of an invalid level is sent to the first reset unit 701, a second control signal of an invalid level is sent to the second reset unit 702, and a fifth control signal of a valid level is sent to the light-emitting control unit 705 to drive the light-emitting element 2 to emit light.

[0142] As a further example, the pixel driving circuit provided in the embodiment of the present application is Figure 8 The pixel driving circuit shown in FIG. 1 is taken as an example. The GOA circuit can be used to execute the driving method of the pixel driving circuit provided in the embodiment of the present application to drive the pixel driving circuit, which specifically includes:

[0143] In the initialization phase of the data refresh frame, a sixth control signal of a valid level is sent to the control terminal of the sixth transistor T6;

[0144] In the compensation phase of the data refresh frame, a sixth control signal of an invalid level is sent to the control end of the sixth transistor T6, a third control signal of an effective level is sent to the control end of the first transistor T1, and a fourth control signal of an effective level is sent to the control end of the second transistor T2;

[0145] In the reset phase of the data refresh frame, a third control signal of an invalid level is sent to the control end of the first transistor T1, a fourth control signal of an invalid level is sent to the control end of the second transistor T2, a first control signal of an effective level is sent to the control end of the seventh transistor T7, and a second control signal of an effective level is sent to the control end of the eighth transistor T8;

[0146] In the light emitting phase of the data refresh frame, a first control signal of an invalid level is sent to the control end of the seventh transistor T7, a second control signal of an invalid level is sent to the control end of the eighth transistor T8, and a fifth control signal of an effective level is sent to the control ends of the third transistor T3 and the fourth transistor T4, so as to drive the light emitting element 2 to emit light;

[0147] In the reset phase of the i-th holding frame, a fifth control signal of an invalid level is sent to the control terminals of the third transistor T3 and the fourth transistor T4, a first control signal of an effective level is sent to the control terminal of the seventh transistor T7, and a second control signal of an invalid level is sent to the control terminal of the eighth transistor T8;

[0148] In the light-emitting stage of the i-th holding frame, a first control signal of an invalid level is sent to the control end of the seventh transistor T7, a second control signal of an invalid level is sent to the control end of the eighth transistor T8, and a fifth control signal of a valid level is sent to the control ends of the third transistor T3 and the fourth transistor T4 to drive the light-emitting element 2 to emit light.

[0149] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input end of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0150] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent.

[0151] Please refer to Fig.11 , which shows a flow chart of a driving method of a pixel driving circuit provided in an embodiment of the present application. The driving method of the pixel driving circuit can be applied to any pixel driving circuit provided in an embodiment of the present application. Alternatively, the driving method of the pixel driving circuit is applied to any display device provided in an embodiment of the present application. Optionally, the driving method of the pixel driving circuit can be executed by a GOA circuit in the display device.

[0152] The pixel driving circuit is used to drive the light-emitting element to emit light in multiple refresh cycles, the refresh cycle includes a data refresh frame and at least one holding frame, the data refresh frame includes an initialization phase, a compensation phase, a reset phase and a light-emitting phase, and the holding frame includes a reset phase and a light-emitting phase. Fig.11 As shown, the driving method of the pixel driving circuit includes:

[0153] Step 1101, in the reset phase of the data refresh frame, a valid first control signal is sent to the first reset unit, and a valid second control signal is sent to the second reset unit, so that the first reset unit performs bias reset on the input end of the driving unit and the second reset unit resets the light emitting element.

[0154] Step 1102: During the reset phase of each hold frame, a valid first control signal is sent to the first reset unit, and an invalid second control signal is sent to the second reset unit, so that the first reset unit performs bias reset on the input end of the driving unit, and the second reset unit does not reset the light-emitting element.

[0155] It should be noted that the specific implementation method of the driving method of the pixel driving circuit provided in the embodiment of the present application includes other contents in addition to step 1101 and step 1102. For details, please refer to the relevant function introduction of the GOA circuit in the above-mentioned display device side, which will not be repeated in this embodiment.

[0156] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input end of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0157] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent.

[0158] The embodiment of the present application also provides a display panel, which includes the pixel driving circuit provided in the embodiment of the present application. Since the display panel includes the pixel driving circuit provided in the embodiment of the present application, the pixel driving circuit can achieve the same technical effect, and to avoid repetition, it will not be repeated here.

[0159] The embodiment of the present application also provides an electronic device, which includes the pixel driving circuit provided in the embodiment of the present application. Or, includes the display panel provided in the embodiment of the present application. Or, includes the display device provided in the embodiment of the present application. The electronic device includes the pixel driving circuit provided in the embodiment of the present application, and the pixel driving circuit can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0160] The embodiment of the present application also provides a driving device of a pixel driving circuit, which is configured to execute the driving method of the pixel driving circuit provided in the embodiment of the present application. The driving device of the pixel driving circuit can be a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a car electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmentedreality, AR) / virtual reality (virtualreality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personalcomputer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personalcomputer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0161] The driving device of the pixel driving circuit in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0162] The driving device of the pixel driving circuit provided in the embodiment of the present application can realize Fig.11 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0163] Alternatively, if Fig.12 As shown, an embodiment of the present application further provides an electronic device 1200, including a processor 1201 and a memory 1202, wherein the memory 1202 stores programs or instructions that can be executed on the processor 1201, and when the program or instructions are executed by the processor 1201, the various steps of the driving method embodiment of the above-mentioned pixel driving circuit are implemented, and the same technical effect can be achieved. To avoid repetition, they are not described here.

[0164] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0165] Fig.13 A schematic diagram of the hardware structure of an electronic device for implementing an embodiment of the present application. The electronic device 1300 includes, but is not limited to, components such as a radio frequency unit 1301, a network module 1302, an audio output unit 1303, an input unit 1304, a sensor 1305, a display unit 1306, a user input unit 1307, an interface unit 1308, a memory 1309, and a processor 1310. In addition, the electronic device also includes a pixel driving circuit provided in an embodiment of the present application. Alternatively, it includes a display panel provided in an embodiment of the present application. Alternatively, it includes a display device provided in an embodiment of the present application.

[0166] Those skilled in the art will appreciate that the electronic device 1300 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1310 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.13 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0167] The processor 1310 is used to send a valid first control signal to the first reset unit and send a valid second control signal to the second reset unit during the reset phase of the data refresh frame, so that the first reset unit performs a bias reset on the input end of the driving unit and the second reset unit resets the light emitting element;

[0168] It is also used to send a valid first control signal to the first reset unit and an invalid second control signal to the second reset unit during the reset phase of each holding frame, so that the first reset unit performs a bias reset on the input end of the driving unit and the second reset unit does not reset the light-emitting element.

[0169] In an embodiment of the present application, a first reset unit in a pixel driving circuit is used to reset a bias of an input end of a driving unit under the control of a first control signal. A second reset unit is used to reset a light-emitting element under the control of a second control signal. In this way, since the first reset unit and the second reset unit are respectively controlled by two independent control signals. Therefore, in the process of driving a light-emitting element to emit light using a pixel driving circuit, the second control signal can be used to reduce the number of resets of the light-emitting element in the entire refresh cycle, thereby reducing the size difference of the lighting current of the light-emitting element in different time periods of a single refresh cycle, and improving the brightness uniformity of a display panel provided with the pixel driving circuit of the present application.

[0170] Furthermore, since the temperature of the display panel is negatively correlated with the number of reset times of the light emitting element, the second control signal is used to reduce the number of reset times of the light emitting element in the entire refresh cycle. When the temperature of the display panel rises, the number of reset times of the light emitting element can be reduced to reduce the number of times the charging current of the parasitic capacitor increases due to the reset of the light emitting element, and the shunt effect of the charging current of the parasitic capacitor on the lighting current of the light emitting element can be correspondingly reduced, and the effect of the reset of the light emitting element in the refresh cycle on the luminous brightness of the light emitting element can be reduced, thereby avoiding the temperature rise color cast of the display panel to a certain extent.

[0171] It should be understood that in the embodiment of the present application, the input unit 1304 may include a graphics processor (Graphics Processing Unit, GPU) 13041 and a microphone 13042, and the graphics processor 13041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1306 may include a display panel 13061, and the display panel 13061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1307 includes a touch panel 13071 and at least one of other input devices 13072. The touch panel 13071 is also called a touch screen. The touch panel 13071 may include two parts: a touch detection device and a touch controller. Other input devices 13072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0172] The memory 1309 can be used to store software programs and various data. The memory 1309 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1309 may include a volatile memory or a non-volatile memory, or the memory 1309 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1309 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0173] The processor 1310 may include one or more processing units; optionally, the processor 1310 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1310.

[0174] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the driving embodiment of the above-mentioned pixel driving circuit are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0175] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0176] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the driving method embodiment of the above-mentioned pixel driving circuit, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0177] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-on-chip, a system-on-chip, a chip system, or a system-on-chip chip, etc.

[0178] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the driving method embodiment of the pixel driving circuit as described above, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0179] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0180] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0181] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A pixel driving circuit, characterized in that: The pixel driving circuit comprises: a first reset unit, a second reset unit and a driving unit; The first reset unit is connected to the driving unit to receive a first control signal and reset the bias of the input end of the driving unit under the control of the first control signal; The driving unit is connected to the light emitting element, and is used to receive the light emitting current of the light emitting element and transmit the light emitting current to the light emitting element; The second resetting unit is connected to the light emitting element, and is used to receive a second control signal and reset the light emitting element under the control of the second control signal.

2. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: a compensation unit, a light emitting control unit and a storage unit; The compensation unit is also connected to a first node and the storage unit, and is used to receive frame data and write the frame data into the storage unit through a second node and the first node, wherein the first node is an electrical connection point between the driving unit, the light emitting control unit and the compensation unit, and the second node is an electrical connection point between the compensation unit, the first reset unit, the light emitting control unit and the driving unit; The light emitting control unit is used to receive the light emitting current and transmit the light emitting current to the light emitting element through the driving unit.

3. The pixel driving circuit according to claim 2, characterized in that: The pixel driving circuit further includes: a third resetting unit; The third reset unit is connected to the storage unit and is used to output a keep-on voltage to the storage unit, where the keep-on voltage is used to control the driving unit to connect the first node and the second node.

4. The pixel driving circuit according to claim 2, characterized in that: The compensation unit includes a first transistor and a second transistor; The control end of the first transistor is used to receive a third control signal, the input end of the first transistor is used to receive the frame data, and the output end of the first transistor is connected to the driving unit to output the frame data to the driving unit under the control of the third control signal; The control end of the second transistor is used to receive a fourth control signal, the input end of the second transistor is connected to the driving unit, and the output end of the second transistor is connected to the storage unit, and is used to write the frame data transmitted by the driving unit to the storage unit under the control of the fourth control signal.

5. The pixel driving circuit according to claim 4, characterized in that: The light emitting control unit comprises: a third transistor and a fourth transistor; The control end of the third transistor is used to receive a fifth control signal, the input end of the third transistor is used to receive the light emitting current, and the output end of the third transistor is connected to the driving unit; The control end of the fourth transistor is used to receive the fifth control signal, the input end of the fourth transistor is connected to the driving unit, the output end of the fourth transistor is connected to the light-emitting element, and the third transistor and the fourth transistor are used to be synchronously turned on under the control of the fifth control signal to output the light-emitting current to the light-emitting element.

6. The pixel driving circuit according to claim 5, characterized in that: The driving unit includes a fifth transistor; The control end of the fifth transistor is connected to the storage unit, the input end of the fifth transistor is respectively connected to the output end of the first transistor and the output end of the third transistor, the output end of the fifth transistor is respectively connected to the input end of the second transistor and the input end of the fourth transistor, and the fifth transistor is used to turn on the second node and the first node under the control of the output voltage of the storage unit.

7. The pixel driving circuit according to claim 3, characterized in that: The third reset unit includes: a sixth transistor; The control end of the sixth transistor is used to receive a sixth control signal, the input end of the sixth transistor is used to receive the keep-on voltage, the output end of the sixth transistor is connected to a third node, and is used to output the keep-on voltage to the storage unit under the control of the sixth control unit, and the third node is an electrical connection point between the compensation unit and the storage unit.

8. The pixel driving circuit according to claim 1, characterized in that: The first reset unit includes a seventh transistor; The control end of the seventh transistor is used to receive the first control signal, the input end of the seventh transistor is used to receive the first voltage, and the output end of the seventh transistor is connected to the driving unit to output the first voltage to the input end of the driving unit under the control of the first control signal; The second reset unit includes an eighth transistor; The control end of the eighth transistor is used to receive the second control signal, the input end of the eighth transistor is used to receive the second voltage, and the output end of the eighth transistor is connected to the light-emitting element for outputting the second voltage to the light-emitting element under the control of the second control signal.

9. A display device, characterized in that: The display device comprises: a pixel driving circuit as described in any one of claims 1 to 8.

10. A driving method for a pixel driving circuit, characterized in that: A pixel driving circuit applied to any one of claims 1 to 8, or applied to the display device according to claim 9, wherein the pixel driving circuit is used to drive the light-emitting element to emit light in multiple refresh cycles, the refresh cycle includes a data refresh frame and at least one hold frame, the data refresh frame includes an initialization stage, a compensation stage, a reset stage and a light-emitting stage, and the hold frame includes a reset stage and a light-emitting stage; the method includes: In the reset phase of the data refresh frame, the first control signal of the valid level is sent to the first reset unit, and the second control signal of the valid level is sent to the second reset unit, so that the first reset unit performs bias reset on the input end of the driving unit, and the second reset unit resets the light emitting element; During the reset phase of the holding frame, the first control signal of a valid level is sent to the first reset unit, and the second control signal of an invalid level is sent to the second reset unit, so that the first reset unit performs a bias reset on the input end of the driving unit, and the second reset unit does not reset the light-emitting element.

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