Storage and calculation integrated circuit and electronic equipment

Abstract

The embodiment of the invention provides a storage and calculation integrated circuit and electronic equipment. The storage and calculation integrated circuit comprises a memristor array, a digital-to-analog conversion circuit, a bit line calculation module, a source line calculation module and a control module, and the control module is configured to control operation of the memristor array, the digital-to-analog conversion circuit, the bit line calculation module and the source line calculation module based on a calculation mode of the storage and calculation integrated circuit. The calculation mode comprises a forward calculation mode and a back propagation mode. A bit line calculation module and a source line calculation module in the storage and calculation integrated circuit are used in a forward calculation mode and a back propagation mode, so that circuit redundancy is avoided, the area utilization efficiency of the storage and calculation integrated circuit is improved, and the weight and calculation power density are enhanced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a storage-computing integrated circuit and an electronic device. Background Art

[0002] The storage-computing technology can realize the integration of storage and computing functions at the bottom layer, thereby greatly reducing the delay and power consumption caused by data movement, and can also use memristor arrays to achieve high-parallel analog computing. The storage-computing technology focuses on the acceleration of forward reasoning of neural networks. However, due to the existence of some non-ideal characteristics, the on-chip reasoning accuracy based on storage-computing limits the deployment and implementation of neural networks. Updating the mapped weights through on-chip back-propagation training can make the weights adapt to the non-ideal characteristics of some hardware, thereby improving the accuracy of on-chip forward reasoning. Therefore, the storage-computing hardware required for forward reasoning operations of neural networks can also have the function of back-propagation calculations. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a storage-computation integrated circuit, comprising: a memristor array, a digital-to-analog conversion circuit, a bit line calculation module, a source line calculation module and a control module, wherein the control module is configured to control the operation of the memristor array, the digital-to-analog conversion circuit, the bit line calculation module and the source line calculation module based on a calculation mode of the storage-computation integrated circuit, wherein the calculation mode comprises a forward calculation mode and a reverse propagation mode; in the forward calculation mode, the digital-to-analog conversion circuit converts the received first data to obtain a first input voltage provided to the bit line calculation module, and the bit line calculation module provides the memristor array with a first input voltage. The first input voltage received is provided so that the memristor array generates a first load current after performing a first calculation using the first input voltage, and the source line calculation module quantifies the first load current; and in the reverse propagation mode, the digital-to-analog conversion circuit converts the received second data to obtain a second input voltage provided to the source line calculation module, and the source line calculation module provides the received second input voltage to the memristor array, so that the memristor array generates a second load current after performing a second calculation using the second input voltage, and the bit line calculation module quantifies the second load current.

[0004] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the memristor array includes multiple source lines, multiple bit lines and multiple array-arranged weight units, the bit line calculation module is coupled to the multiple bit lines of the memristor array, and is also configured to clamp the voltage of the multiple bit lines to a first clamping reference voltage in the reverse propagation mode; and the source line calculation module is coupled to the multiple source lines of the memristor array, and is also configured to clamp the voltage of the multiple source lines to a second clamping reference voltage in the forward calculation mode.

[0005] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the bit line calculation module includes: a plurality of bit line driving / clamping circuits and a first analog-to-digital converter, wherein the plurality of bit line driving / clamping circuits are respectively coupled to the plurality of bit lines, and each of the bit line driving / clamping circuits is configured to, in the forward calculation mode, provide the first input voltage to the corresponding bit line, or, in the reverse propagation mode, clamp the voltage of the corresponding bit line to the first clamping reference voltage, and generate a second load voltage based on the second load current on the corresponding bit line; the first analog-to-digital converter is coupled to the plurality of bit line driving / clamping circuits, and is configured to, in the reverse propagation mode, sequentially perform quantization operations on the second load voltages generated by the plurality of bit line driving / clamping circuits, and output a second quantization result.

[0006] For example, in the integrated storage and computing circuit provided in at least one embodiment of the present disclosure, the first analog-to-digital converter is a current type or a voltage type.

[0007] For example, in the integrated storage and computing circuit provided in at least one embodiment of the present disclosure, the bit line driving / clamping circuit is configured based on a gain amplifier or a flip voltage follower.

[0008] For example, in the storage and computing integrated circuit provided in at least one embodiment of the present disclosure, the source line computing module includes a plurality of source line driving / clamping circuits and a second analog-to-digital converter, and the plurality of source line driving / clamping circuits are respectively coupled to the plurality of source lines, and each of the source line driving / clamping circuits is configured to, in the forward computing mode, clamp the voltage of the corresponding source line to the second clamping reference voltage, and generate a first load voltage based on the first load current on the corresponding source line, or, in the reverse propagation mode, provide the second input voltage to the corresponding source line; the second analog-to-digital converter is coupled to the plurality of source line driving / clamping circuits, and is configured to, in the forward computing mode, sequentially perform quantization operations on the first load voltages generated by the plurality of source line driving / clamping circuits, and output a first quantization result.

[0009] For example, in the storage-computation integrated circuit provided in at least one embodiment of the present disclosure, the source line drive / clamp circuit includes a differential amplifier and a transistor, the output end of the differential amplifier is coupled to the control end of the transistor, and in the forward calculation mode, the first input end of the differential amplifier is clamped to the second clamp reference voltage, and the second input end of the differential amplifier receives the first load current, or, in the reverse propagation mode, the first input end of the differential amplifier receives the second input voltage, and the second input end of the differential amplifier provides the second input voltage to the corresponding source line.

[0010] For example, in the integrated storage and computing circuit provided in at least one embodiment of the present disclosure, the second analog-to-digital converter includes a comparator, a logic control circuit (SAR) and a current generating unit (IDAC), the comparator is configured to compare the first load voltage and a reference voltage (V_REF), the logic control circuit is coupled to the comparator and the current generating unit, and is configured to control the current generating unit to generate a first current according to the comparison result of the comparator, so as to adjust the first load current on the corresponding source line.

[0011] For example, in the storage-computation-in-one circuit provided in at least one embodiment of the present disclosure, the logic control circuit is further configured to output the first quantization result according to the comparison result of the comparator.

[0012] At least one embodiment of the present disclosure further provides an electronic device, wherein the cover pad device includes the storage and computing integrated circuit described in any embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0014] Figure 1 A schematic diagram of a storage-computation integrated circuit for realizing forward calculation and reverse propagation is shown;

[0015] Figure 2 A schematic diagram of a storage-computation-in-one circuit provided by at least one embodiment of the present disclosure is shown;

[0016] Figure 3A A schematic diagram of a storage-computation integrated circuit in a forward computing mode provided by at least one embodiment of the present disclosure is shown;

[0017] Figure 3B A schematic diagram of a storage-computation-in-one circuit in a reverse propagation mode provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 4AThe figure shows the connection relationship between the weight unit of the 1T1R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the forward calculation mode;

[0019] Figure 4B The figure shows the connection relationship between the weight unit of the 1T1R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the reverse propagation mode;

[0020] Figure 4C The figure shows the connection relationship between the weight unit of the 2T2R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the forward calculation mode;

[0021] Figure 4D The connection relationship between the weight unit of the 2T2R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the reverse propagation mode is shown;

[0022] Figure 5 A schematic diagram of the structure of a bit line calculation module when a 1T1R weight unit is used according to at least one embodiment of the present disclosure is shown;

[0023] Figure 6 A schematic diagram of the structure of a bit line calculation module when a 2T2R weight unit is used according to at least one embodiment of the present disclosure is shown;

[0024] Fig. 7A and Figure 7B A schematic diagram of the structure of a bit line calculation module based on a gain amplifier and a current-type analog-to-digital converter provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 7C Shows Fig. 7A and Figure 7B The schematic diagram of an analog-to-digital converter multiplexed by multiple bit line driver / clamp circuits is shown;

[0026] Fig. 8A and Figure 8B A schematic diagram showing the structure of a bit line calculation module based on a gain amplifier and a voltage-type analog-to-digital converter provided by at least one embodiment of the present disclosure

[0027] Figure 8C Shows Fig. 8A and Figure 8B The schematic diagram of an analog-to-digital converter multiplexed by multiple bit line driver / clamp circuits is shown;

[0028] Fig. 9A and 9B A schematic diagram of a bit line driving / clamping circuit based on a source follower arrangement provided by at least one embodiment of the present disclosure is shown;

[0029] Fig. 10A and Fig. 10BA schematic diagram of a bit line driving / clamping circuit based on a common gate follower arrangement provided by at least one embodiment of the present disclosure is shown;

[0030] Fig.11A and Fig. 11B A schematic diagram of the structure of a bit line calculation module based on a common gate follower arrangement provided by at least one embodiment of the present disclosure is shown;

[0031] Fig. 12A and Fig. 12B A schematic diagram showing the structure of a source line calculation module in forward calculation and reverse propagation modes provided by at least one embodiment of the present disclosure; and

[0032] Fig.13 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0035] The storage-computing integrated technology can realize the integration of storage and computing functions at the bottom layer, thereby greatly reducing the delay and power consumption caused by data movement. At the same time, it can also use the storage-computing integrated array (hereinafter also referred to as "memristor array") to realize high-parallel analog computing. The storage-computing integrated technology focuses on the acceleration of forward reasoning of neural networks. However, due to the existence of some non-ideal characteristics, the on-chip reasoning accuracy based on storage-computing integrated limits the deployment and implementation of neural networks. Updating the mapped weights through on-chip back-propagation training can make the weights adapt to the non-ideal characteristics of some hardware, thereby improving the accuracy of on-chip forward reasoning. Therefore, the storage-computing integrated hardware required for forward reasoning operations of neural networks can also have the function of back-propagation calculations.

[0036] Since the storage-computing integrated array based on resistive storage can adapt to the bidirectional calculation of forward calculation and reverse propagation, the storage-computing integrated circuit that supports bidirectional calculation can be designed based on the storage-computing integrated array. However, these storage-computing integrated circuits often require two independent input circuits and output circuits for forward calculation and reverse propagation respectively. In the forward calculation or reverse propagation mode, only half of the circuit modules of the storage-computing integrated circuit are working, and its area efficiency is very low, which affects the weight and computing power density of the storage-computing integrated circuit.

[0037] For example, Figure 1 A schematic diagram of the structure of a storage-computation integrated circuit for realizing forward calculation and reverse propagation is shown.

[0038] like Figure 1 As shown, the storage-computation integrated circuit requires two sets of independent input circuits and readout circuits. In the forward calculation mode, the forward digital-to-analog conversion circuit (i.e., "forward DAC") 110 applies a voltage representing the input data to the bit line BL of the memristor array 150, and the forward readout circuit 120 clamps the source line SL of the memristor array 150 and quantifies the current on the source line SL to obtain the calculation result, while the reverse digital-to-analog conversion circuit (i.e., "reverse DAC") 130 and the reverse readout circuit 140 are disconnected from the memristor array 150. In the reverse propagation mode, the reverse digital-to-analog conversion circuit 130 applies a voltage representing the input data to the source line SL of the memristor array 150, and the reverse readout circuit 140 clamps the bit line BL of the memristor array 150 and quantifies the current on the bit line BL to obtain the result, while the forward digital-to-analog conversion circuit 110 and the forward readout circuit 120 are disconnected from the memristor array 150.

[0039] The inventors of the present disclosure noticed that both the forward calculation and reverse propagation modes only used part of the above-mentioned storage-computation integrated circuit, which resulted in reduced chip area efficiency and made it difficult to achieve a storage-computation integrated hardware system with high computing power density and weight density.

[0040] In view of the above shortcomings, one or more embodiments of the present disclosure propose a storage-computation integrated circuit and an electronic device. The storage-computation integrated circuit includes a memristor array, a digital-to-analog conversion circuit, a bit line calculation module, a source line calculation module and a control module. The control module is configured to control the operation of the memristor array, the digital-to-analog conversion circuit, the bit line calculation module and the source line calculation module based on the calculation mode of the storage-computation integrated circuit, and the calculation mode includes a forward calculation mode and a reverse propagation mode; in the forward calculation mode, the digital-to-analog conversion circuit converts the received first data to obtain a first input voltage provided to the bit line calculation module, and the bit line calculation module provides the received first input voltage to the memristor array, so that the memristor array generates a first load current after performing a first calculation using the first input voltage, and the source line calculation module quantizes the first load current; and in the reverse propagation mode, the digital-to-analog conversion circuit converts the received second data to obtain a second input voltage provided to the source line calculation module, and the source line calculation module provides the received second input voltage to the memristor array, so that the memristor array generates a second load current after performing a second calculation using the second input voltage, and the bit line calculation module quantizes the second load current.

[0041] The storage-computation integrated circuit proposed in one or more embodiments of the present disclosure shares a set of input circuits and readout circuits in forward computing and reverse propagation modes, that is, the bit line computing module and source line computing module in the storage-computation integrated circuit are used in both the forward computing mode and the reverse propagation mode, thereby avoiding circuit redundancy, improving the area utilization efficiency of the storage-computation integrated circuit, and enhancing the weight and computing power density.

[0042] The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is represented by the same or similar reference numeral in each figure.

[0043] For example, Figure 2A schematic diagram of a storage-computation integrated circuit provided by at least one embodiment of the present disclosure is shown. In the forward calculation mode, the bit line calculation module 210 can be used as the input circuit (i.e., "forward DAC") of the storage-computation integrated circuit to apply a voltage representing input data to the bit line BL of the memristor array 230; the source line calculation module 220 can be used as the readout circuit (i.e., "forward readout circuit") of the storage-computation integrated circuit to clamp the source line SL of the memristor array 230 and quantify the current on the source line SL to obtain the calculation result. In the reverse propagation mode, the bit line calculation module 210 can be used as the readout circuit (i.e., "reverse readout circuit") of the storage-computation integrated circuit to clamp the bit line BL of the memristor array 230 and quantify the current on the bit line BL to obtain the result; the source line calculation module 220 can be used as the input circuit (i.e., "reverse DAC") of the storage-computation integrated circuit to apply a voltage representing input data to the source line SL of the memristor array 230.

[0044] For example, Figure 3A A schematic diagram of a storage-computation-in-one circuit in a forward computing mode provided by at least one embodiment of the present disclosure is shown.

[0045] like Figure 3A As shown, the storage-computation integrated circuit includes a memristor array 330, a digital-to-analog conversion circuit 340, a bit line calculation module 310, a source line calculation module 320, and a control module (not shown in the figure). The control module is configured to control the operation of the memristor array 330, the digital-to-analog conversion circuit 340, the bit line calculation module 310, and the source line calculation module 320 based on the calculation mode of the storage-computation integrated circuit, and the calculation mode includes a forward calculation mode and a reverse propagation mode.

[0046] like Figure 3A As shown, in the forward calculation mode, the control module controls the digital-to-analog conversion circuit 340 to couple with the bit line calculation module 310 and disconnect with the source line calculation module 320. The digital-to-analog conversion circuit 340 converts the received first data (i.e., the input data for the forward calculation) to obtain the first input voltage VDAC_1[m-1:0] provided to the bit line calculation module 310. The bit line calculation module 310 provides the received first input voltage VDAC_1[m-1:0] to the memristor array 330 (i.e., applies the first input voltage VDAC_1[m-1:0] to the bit line BL of the memristor array 330), so that the memristor array 330 generates a first load current after performing the first calculation using the first input voltage VDAC_1[m-1:0]. The source line calculation module 320 quantizes the first load current. The "first load current" here is the current on the source line SL of the memristor array 330 in the forward calculation mode.

[0047] For example, Figure 3BA schematic diagram of a storage-computation-in-one circuit in a reverse propagation mode provided by at least one embodiment of the present disclosure is shown.

[0048] like Figure 3B As shown, in the reverse propagation mode, the control module controls the digital-to-analog conversion circuit 340 to couple with the source line calculation module 320 and disconnect with the bit line calculation module 310. The digital-to-analog conversion circuit 340 converts the received second data (i.e., the input data for reverse propagation) to obtain the second input voltage VDAC_2[m-1:0] provided to the source line calculation module 320, and the source line calculation module provides the received second input voltage VDAC_2[m-1:0] to the memristor array 330 (i.e., applies the second input voltage VDAC_2[m-1:0] to the source line SL of the memristor array 330), so that the memristor array 330 generates a second load current after performing a second calculation using the second input voltage VDAC_2[m-1:0]. The bit line calculation module 310 quantizes the second load current. The "second load current" here is the current on the bit line BL of the memristor array 330 in the reverse propagation mode.

[0049] In the storage-computation integrated circuit provided by one or more embodiments of the present disclosure, the memristor array includes a plurality of source lines, a plurality of bit lines, and a plurality of weight units arranged in an array. The bit line calculation module is coupled to the plurality of bit lines of the memristor array, and is also configured to clamp the voltage of the plurality of bit lines to a first clamping reference voltage in a reverse propagation mode. The source line calculation module is coupled to the plurality of source lines of the memristor array, and is also configured to clamp the voltage of the plurality of source lines to a second clamping reference voltage in a forward calculation mode.

[0050] For example, a memristor is a non-volatile device that can adjust its conductance state, and the conductance value of the memristor is used to characterize the weight value involved in the calculation. For example, the weight unit in the memristor array can be a single-ended single-transistor single-memristor (1T1R) structure or a differential-based two-transistor two-memristor (2T2R) structure. The memristor in the above-mentioned weight unit can be a resistive random access memory (RRAM), a phase change memory (PCM), a conductive bridge memory, etc., and the present disclosure does not limit this.

[0051] For example, Figure 4A The figure shows the connection relationship between the weight unit of the 1T1R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the forward calculation mode; Figure 4B The figure shows the connection relationship between the weight unit of the 1T1R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the reverse propagation mode; Figure 4C The figure shows the connection relationship between the weight unit of the 2T2R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the forward calculation mode; Figure 4DThe connection relationship between the weight unit of the 2T2R structure provided by at least one embodiment of the present disclosure and the peripheral circuit in the reverse propagation mode is shown.

[0052] like Figure 4A and Figure 4B As shown, the weight unit of the 1T1R structure includes a transistor NM and a memristor R, wherein the first end of the memristor R is coupled to the bit line BL, wherein the bit line BL is also coupled to the bit line calculation module 410. The second end of the memristor R is coupled to the drain of the transistor NM. The source of the transistor NM is coupled to the source line SL, and the source line SL is also coupled to the source line calculation module 420. The gate of the transistor NM receives a control signal.

[0053] like Figure 4C and Figure 4D As shown, the weight unit of the 2T2R structure includes two transistors NM1 and NM2, and two memristors R P and R N Memristor R P The first end of the memristor R is coupled to the bit line BLP. P The second end of the memristor R is coupled to the drain of the transistor NM1. N The second end of the memristor R is coupled to the bit line BLN. N The second end of is coupled to the drain of transistor NM2, wherein the bit lines BLP and BLN are also coupled to the bit line calculation module 410. The sources of transistors NM1 and NM2 are both coupled to the same source line SL, which is also coupled to the source line calculation module 420, and the gates of transistors NM1 and NM2 receive corresponding control signals respectively.

[0054] like Figure 4A As shown, in the forward calculation mode, the source line calculation module 420 clamps the source line SL to a fixed voltage (e.g., a clamping voltage), the bit line calculation module 410 inputs a voltage to the bit line BL to drive the bit line BL, and the source line calculation module 420 receives the current on the source line SL and performs a quantization operation on the current to obtain a quantization result.

[0055] like Figure 4B As shown, in the reverse propagation mode, the bit line calculation module 410 clamps the bit line BL to a fixed voltage (e.g., a clamping voltage), the source line calculation module 420 inputs a voltage to the source line SL to drive the bit line SL, and the bit line calculation module 410 receives the current on the bit line BL and performs a quantization operation on the current to obtain a quantization result.

[0056] like Figure 4CAs shown, in the forward calculation mode, the source line calculation module 420 clamps the source line SL to a fixed voltage (e.g., a clamping voltage), the bit line calculation module 410 inputs a differential voltage to the bit line BLP and the bit line BLN to drive the bit line BLP and the bit line BLN, and the source line calculation module 420 receives the current on the source line SL and performs a quantization operation on the current to obtain a quantization result.

[0057] like Figure 4D As shown, in the reverse propagation mode, the bit line calculation module 410 clamps the bit line BLP and the bit line BLN to a fixed voltage (e.g., a clamping voltage), the source line calculation module 420 inputs a voltage to the source line SL to drive the bit line SL, and the bit line calculation module 410 sequentially receives the current on the bit line BLP and the bit line BLN and performs a quantization operation on the current to obtain a quantization result.

[0058] In the storage-computation integrated circuit provided in at least one embodiment of the present disclosure, the bit line calculation module includes a plurality of bit line driving / clamping circuits and a first analog-to-digital converter, wherein the plurality of bit line driving / clamping circuits are respectively coupled to a plurality of bit lines. Each bit line driving / clamping circuit is configured to provide a first input voltage to the corresponding bit line in a forward calculation mode, or to clamp the voltage of the corresponding bit line to a first clamping reference voltage in a reverse propagation mode, and to generate a second load voltage based on a second load current on the corresponding bit line. The first analog-to-digital converter is coupled to the plurality of bit line driving / clamping circuits, and is configured to sequentially perform quantization operations on the second load voltages generated by the plurality of bit line driving / clamping circuits in a reverse propagation mode, and output a second quantization result.

[0059] For example, Figure 5 A schematic diagram of the structure of a bit line calculation module when a 1T1R weight unit is used, provided in at least one embodiment of the present disclosure.

[0060] like Figure 5 As shown, the bit line calculation module includes n bit line driving / clamping circuits (511_0~511_(n-1)) and an analog-to-digital converter 512 (ADC). The n bit line driving / clamping circuits (511_0~511_(n-1)) are respectively coupled to n bit lines (BL[0]~BL[n-1]). The bit line calculation module also includes n switches (SW[0]~SW[n-1]), and the switches SW[0]~SW[n-1] are used to control the conduction between the bit line driving / clamping circuits 511_0~511_(n-1) and the analog-to-digital converter 512.

[0061] The following takes the bit line driving / clamping circuit 511_0 as an example to introduce the process of executing forward calculation and reverse propagation of the bit line calculation module.

[0062] In the forward calculation mode, the switch SW[0] is disconnected, and the bit line driver / clamp circuit 511_0 applies an analog input voltage (i.e., the first input voltage) representing the input data (e.g., VIN[0]) to the bit line BL[0]. At this time, the analog-to-digital converter 512 does not participate in the forward calculation. In the reverse propagation mode, the bit line driver / clamp circuit 511_0 clamps the voltage on the bit line BL[0] to a fixed level (i.e., the first clamp reference voltage) and linearly converts the current on the bit line BL[0] into a voltage V O [0]; At the same time, switch SW[0] is closed, and the analog-to-digital converter 512 is O [0] performs sampling and quantization operations to obtain the reverse propagation result. The process of performing forward calculation and reverse propagation by the remaining bit line driver / clamp circuits 511_1 to 511_(n-1) can refer to the bit line driver / clamp circuit 511_0, which will not be repeated here.

[0063] It should be noted that the above Figure 5 When the bit line calculation module is in the reverse propagation mode, the n switches (SW[0]~SW[n-1]) are closed in sequence, so that the analog-to-digital converter 512 sequentially converts the voltage V O [0]~Voltage V O [n-1] performs sampling and quantization operations.

[0064] For example, Figure 6 A schematic diagram of the structure of a bit line calculation module when a 2T2R weight unit is used, provided in at least one embodiment of the present disclosure, is shown.

[0065] like Figure 6 As shown, the bit line calculation module includes n bit line driving / clamping circuits (611_0~611_(n-1)) and an analog-to-digital converter 612 (ADC). The n bit line driving / clamping circuits (511_0~511_(n-1)) are respectively coupled to n groups of bit lines, each group of bit lines includes 2 bit lines, for example, the first group of bit lines includes bit line BLN[0] and bit line BLP[0], and the nth group of bit lines includes bit line BLN[n-1] and bit line BLP[n-1]. The bit line calculation module also includes n groups of switches, each group of switches is used to control the conduction between the corresponding bit line driving / clamping circuit and the analog-to-digital converter 612. Each group of switches includes 2 switches, for example, the first group of switches includes switch SW N [0] and switch SW P [0]), the nth switch group includes switches SW N [n-1] and switch SW P [n-1]).

[0066] The following takes the bit line driving / clamping circuit 611_0 as an example to introduce the process of executing forward calculation and reverse propagation of the bit line calculation module.

[0067] In forward calculation mode, switch SW N [0] and switch SW P [0] is disconnected, and the bit line driver / clamp circuit 611_0 applies an analog input voltage representing input data (e.g., VIN[0] and VIP[0]) to the bit line BLN[n-1] and the bit line BLP[n-1], and the analog-to-digital converter 612 does not participate in the forward calculation. In the reverse propagation mode, the bit line driver / clamp circuit 611_0 clamps the voltage on the bit line BLN[n-1] and the bit line BLP[n-1] to a fixed level (i.e., the first clamp reference voltage), and linearly converts the current on the bit line BLN[n-1] and the bit line BLP[n-1] into a voltage V OP [0] and voltage V ON [0]; switch SW at the same time N [0] and switch SW P [0] is closed, and the analog-to-digital converter 512 sequentially converts the voltage V OP [0] and voltage V ON [0] performs sampling and quantization operations, obtains and outputs the reverse propagation result. The process of performing forward calculation and reverse propagation by the remaining bit line driver / clamp circuits 611_1~611_(n-1) can refer to the bit line driver / clamp circuit 111_0, which will not be repeated here.

[0068] It should be noted that the above Figure 6 When the bit line calculation module is in reverse propagation mode, n sets of switches (SW N [0] SW P [0] SW N [1] SW P [1], ..., SW N [n-1] and SW P [n-1]) are closed in sequence, so that the analog-to-digital converter 612 sequentially converts the voltage V OP [0], V ON [0], V OP [1] V ON [1], ... V OP [n-1] and V ON [n-1] performs sampling and quantization operations.

[0069] For example, the analog-to-digital converter ADC in the bit line calculation module may be a current type or a voltage type, and the present disclosure does not limit this.

[0070] For example, the bit line driving / clamping circuit in the bit line calculation module may be configured based on a gain amplifier or a flip voltage follower, which is not limited in the present disclosure.

[0071] For example, Fig. 7A and Figure 7B A schematic structural diagram of a bit line calculation module based on a gain amplifier and a current-type analog-to-digital converter provided by at least one embodiment of the present disclosure is shown.

[0072] like Fig. 7A and Figure 7B As shown, taking the memristor array coupled to the bit line calculation module as an example, the weight unit of the 2T2R structure is used, and the bit line calculation module includes a bit line drive / clamp circuit 711 and an analog-to-digital converter 712 (ADC), and the analog-to-digital converter 712 is a current type. The bit line drive / clamp circuit 711 includes two high-gain differential amplifiers 7111 and 7112 connected in unit gain negative feedback, a resistor R P , resistor R N , switches SW.1 and SW.2, wherein the outputs of the differential amplifiers 7111 and 7112 are connected to the ADC through switches SW.1 and SW.2 respectively. The negative input of the differential amplifier 7111 is coupled to the bit line BLP of the memristor array and the analog-to-digital converter 712 respectively, and the negative input of the differential amplifier 7112 is coupled to the bit line BLN of the memristor array and the analog-to-digital converter 712 respectively.

[0073] like Figure 7B As shown, the analog-to-digital converter 712 may include a comparator 7121, a logic control circuit 7122 (e.g., a SAR logic control circuit), and a current generating unit 7123 (IDAC). The first input terminal of the comparator 7121 is coupled to the output terminal of the differential amplifier 7111 through a switch SW.1, the second input terminal of the comparator 7121 is coupled to the output terminal of the differential amplifier 7112 through a switch SW.2, and the output terminal of the comparator 7121 is coupled to the logic control circuit 7122. The logic control circuit 7122 is also coupled to the current generating unit 7123 to control the current generating unit 7123 to generate a corresponding current to the negative input terminals of the differential amplifiers 7111 and 7112 according to the comparison result output by the comparator 7121.

[0074] Below Figure 7B Taking the bit line calculation module shown in FIG. 1 as an example, the circuit working principle of the bit line calculation module is as follows.

[0075] In the forward calculation mode, the positive input terminals of the differential amplifiers 7111 and 7112 receive VIP and VIN signals from the digital-to-analog converter (not shown in the figure) to provide a differential input voltage (i.e., a driving voltage) for the memristor array. There is a voltage relationship between the VIP and VIN signals: (VIP+VIN) / 2=V CM , where V CM is the clamping voltage on the source line of the memristor array. At the same time, switches SW.1 and SW.2 are disconnected, and the analog-to-digital converter 712 (ADC) does not participate in the forward calculation.

[0076] In the reverse propagation mode, the positive input terminals of the differential amplifiers 7111 and 7112 both receive the voltage V RD (not marked in the figure), the voltage difference between the voltage VRD and the source line input voltage of the memristor array is the read voltage during the reverse propagation calculation. Differential amplifiers 7111 and 7112 clamp the source lines BLP and BLN respectively, and the current I on the source line BLP BLP Through the resistor R P Generates output voltage V OP =I BLP ×R P , the current I on the source line BLN BLN Through the resistor R N Generates output voltage V ON =I BLN ×R N At the same time, switches SW.1 and SW.2 are closed, and the analog-to-digital converter 712 is based on the voltage V OP and V ON The differential current (I BLP -I BLN ) is quantized. Specifically, during the readout quantization process, the comparator 7121 compares the voltage V OP and V ON The logic control circuit 7122 controls the current generating unit 7123 to feed back current to the clamping points coupled to the bit lines BLP and BLN according to the comparison result, so that the final current difference flowing into the two clamping points is 0, and the logic control circuit 7122 outputs the quantization result, thereby completing the quantization process of the analog-to-digital converter ADC.

[0077] Above Fig. 7A and Figure 7B The bit line calculation module shown includes a plurality of bit line driving / clamping circuits, Fig. 7A and Figure 7B Only one bit line driver / clamp circuit 711 is schematically shown. Each bit line driver / clamp circuit may use an analog-to-digital converter ADC, and multiple bit line driver / clamp circuits may also share the same analog-to-digital converter ADC, which is not limited in the present disclosure.

[0078] For example, Figure 7C Shows Fig. 7A and Figure 7B The schematic diagram shown is a schematic diagram of an analog-to-digital converter multiplexed by multiple bit line driver / clamp circuits.

[0079] like Figure 7C As shown, the bit line calculation module includes N groups of bit line driving / clamping circuits and N analog-to-digital converters. Figure 7COnly one group of bit line driving / clamping circuits and one analog-to-digital converter 712 are schematically shown. The group of bit line driving / clamping circuits includes n bit line driving / clamping circuits 711_1 to 711_n. The bit line driving / clamping circuits 711_1 to 711_n multiplex the same analog-to-digital converter 712, that is, the analog-to-digital converter 712 sequentially quantizes the n bit line driving / clamping circuits 711_1 to 711_n.

[0080] In the bit line calculation module provided by at least one embodiment of the present disclosure, each group of bit line driving / clamping circuits can reuse the same analog-to-digital converter, thereby avoiding the problem of low area utilization caused by the area difference between the analog-to-digital converter and the bit line driving / clamping circuit.

[0081] For example, Fig. 8A and Figure 8B A schematic structural diagram of a bit line calculation module based on a gain amplifier and a voltage-type analog-to-digital converter provided by at least one embodiment of the present disclosure is shown.

[0082] like Fig. 8A and Figure 8B As shown, taking the memristor array coupled to the bit line calculation module as an example, the weight unit adopting the 2T2R structure, the bit line calculation module includes a bit line drive / clamp circuit 811 and an analog-to-digital converter 812 (ADC), and the analog-to-digital converter 812 is a voltage type. The bit line drive / clamp circuit 811 includes two high-gain differential amplifiers 8111 and 8112 connected in unit gain negative feedback, a resistor R P , resistor R N , switches SW.1 and SW.2, wherein the outputs of the differential amplifiers 8111 and 8112 are connected to the analog-to-digital converter 812 through switches SW.1 and SW.2 respectively. The negative input of the differential amplifier 8111 is coupled to the bit line BLP of the memristor array, and the negative input of the differential amplifier 8112 is coupled to the bit line BLN of the memristor array.

[0083] like Figure 8B As shown, the analog-to-digital converter 812 may include a comparator 8121, a logic control circuit 8122 (eg, a SAR logic control circuit), and two current-to-digital converters (CDACs). P and CDAC N ). The first input terminal of the comparator 8121 is connected to the CDAC P The second input terminal of the comparator 8121 is coupled to CDAC N The output terminal of the comparator 8121 is coupled to the logic control circuit 8122. The logic control circuit 8122 is also coupled to the CDAC P and CDAC N Coupling.

[0084] Below Figure 8B Taking the bit line calculation module shown in FIG. 1 as an example, the circuit working principle of the bit line calculation module is as follows.

[0085] Figure 8B The working principle of the bit line calculation module in the forward calculation mode is similar to the above Figure 7B The description of the bit line calculation module shown in the forward calculation mode is the same and will not be repeated here.

[0086] In the back-propagation calculation mode, Figure 8B The positive input terminals of the differential amplifiers 8111 and 8112 in the bit line calculation module are connected to the voltage V RD (not shown in the figure), differential amplifiers 8111 and 8112 clamp the bit lines BLP and BLN. The current I BLP Through the resistor R P Generates output voltage V OP =I BLP ×R P , the current I on the bit line BLN BLN The output voltage V is generated through the resistor ON =I BLN ×R N At the same time, switches SW.1 and SW.2 are closed, and CDAC P and CDAC N The output voltage V OP and V ON Sampling and outputting voltage signal V CP and V CN Then, switches SW.1 and SW.2 are disconnected, ending the sampling process and entering the quantization phase. In the quantization phase, comparator 8121 compares the voltage signal V CP and V CN The SAR logic control circuit 8122 controls CDAC based on the comparison result. P and CDAC N The capacitor is flipped so that the voltage signal V CP and V CN The differential voltage converges to 0, and the quantization process ends. Here, CDAC in the voltage-type analog-to-digital converter ADC P and CDAC N The sampling method can be top plate sampling or bottom plate sampling, and the present disclosure does not impose any restrictions on this.

[0087] Different from the above-mentioned bit line calculation module using current-type analog-to-digital converter (such as Fig. 7A and 7B shown), in Fig. 8A and 8BIn the reverse propagation calculation process of the bit line calculation module shown, switches SW.1 and SW.2 only need to be closed during the sampling phase. After the sampling is completed, switches SW.1 and SW.2 are disconnected, and the bit line drive / clamp circuit 811 establishes the voltage for the next round of reverse propagation calculation and the analog-to-digital converter 812 performs the quantization process for the current round of reverse propagation calculation simultaneously.

[0088] Above Fig. 8A and Figure 8B The bit line calculation module shown includes a plurality of bit line driving / clamping circuits, Fig. 8A and Figure 8B Only one bit line driver / clamp circuit 811 is schematically shown. Each bit line driver / clamp circuit may use an analog-to-digital converter ADC, and multiple bit line driver / clamp circuits may also share the same analog-to-digital converter ADC, which is not limited in the present disclosure.

[0089] For example, Figure 8C Shows Fig. 8A and Figure 8B The schematic diagram shown is a schematic diagram of an analog-to-digital converter multiplexed by multiple bit line driver / clamp circuits.

[0090] like Figure 8C As shown, the bit line calculation module includes N groups of bit line driving / clamping circuits and N analog-to-digital converters. Figure 8C Only one group of bit line driving / clamping circuits and one analog-to-digital converter 812 are schematically shown. The group of bit line driving / clamping circuits includes n bit line driving / clamping circuits 811_1 to 811_n. The bit line driving / clamping circuits 811_1 to 811_n multiplex the same analog-to-digital converter 812, that is, the analog-to-digital converter 812 sequentially quantizes the n bit line driving / clamping circuits 811_1 to 811_n. Figure 8C The bit line calculation module shown can avoid the problem of low area utilization caused by the area difference between the analog-to-digital converter and the bit line driving / clamping circuit.

[0091] In the integrated storage and computing circuit provided in at least one embodiment of the present disclosure, in addition to setting up a bit line calculation module based on a differential high-gain amplifier to form a unit gain buffer, a bit line calculation module can also be set up based on a flip voltage follower (Flip Voltage Follower, FVF) to further perform voltage driving and clamping on the bit lines of the memristor array.

[0092] For example, the bit line calculation module can be based on a source follower (hereinafter referred to as "SF-FVF") or a common gate follower (hereinafter referred to as "CG-FVF"). The following takes the weight unit of the memristor array with a 2T2R structure as an example to introduce the process of the bit line calculation module driving the bit line (that is, the process of performing forward calculation).

[0093] For example, Fig. 9A and 9B A schematic diagram of a bit line driving / clamping circuit based on a source follower arrangement provided by at least one embodiment of the present disclosure is shown; Fig. 10A and Fig. 10B A schematic diagram of a bit line driving / clamping circuit based on a common gate follower arrangement provided by at least one embodiment of the present disclosure is shown.

[0094] In the forward calculation mode, the current directions on the bit line BLP and the bit line BLN are different, that is, the current I BLN The driving current flows from the bit line BLN of the memristor array, and the current I BLP From the bit line BLP of the memristor array into which the driving current flows, the bit line driver / clamp circuit can configure the output stage to output current externally (such as Fig. 9A and 10A as shown) and the internal current injection (as Fig. 9B and 10B The two modes correspond to the transistor PM.F1 being connected to the output stage circuit and the transistor NM.F3 being connected to the output stage circuit.

[0095] like Fig. 9A As shown, the bit line driving / clamping circuit includes a transistor NM.F1, a transistor NM.F2, three current generating units IG1-IG3 and an output stage circuit, wherein the output stage circuit includes a transistor NM.F3, a transistor PM.F1 and four switches SW.1-SW.4. The drain of the transistor NM.F1 is coupled to the voltage source VDD, the source of the transistor NM.F1 is coupled to the input end of the current generating unit IG2, and the gate of the transistor NM.F1 is coupled to the output end of the current generating unit IG1. The source of the transistor NM.F2 is coupled to the input end of the current generating unit IG3 and the bit line node (for example, NM.F3). BLP ) are coupled respectively, the drain of transistor NM.F2 is coupled to the output end of current generating unit IG1, and the gate of transistor NM.F2 receives an input voltage signal (for example, V IP The drain of transistor NM.F3 is connected to the bit line node (eg, N BLP ) and the drain of transistor PM.F1 are coupled respectively, the source of transistor NM.F3 is grounded, the gate of transistor NM.F3 is coupled to the second end of switch SW.3 and the first end of switch SW.4 respectively. The source of transistor PM.F1 is coupled to the voltage source VDD and the first end of switch SW.1 respectively, the drain of transistor PM.F1 is coupled to the bit line node (e.g., N BLP), the gate of transistor PM.F1 is coupled to the second end of switch SW.1 and the first end of switch SW.2. Switch SW.1 is used to control conduction between the source and gate of transistor PM.F1, switch SW.2 is used to control conduction between the gate of transistor PM.F1 and the source of transistor NM.F1, and switch SW.4 is used to control conduction between the source and gate of transistor NM.F3.

[0096] like Fig. 9A As shown, in the forward calculation mode, when the bit line driving / clamping circuit based on the source follower arrangement drives the bit line BLP, switches SW.1 and SW.3 are opened, switches SW.2 and SW.4 are closed, and the gate of transistor NM.F2 receives the input voltage signal V for the bit line BLP. IP , the bit line node coupled to the output stage circuit is N BLP At this time, only transistor PM.F1 is connected to the output stage circuit, and transistor NM.F3 does not participate in the forward calculation. The voltage change at node ND is transmitted to node NG, and the bit line driver / clamp circuit passes the bit line node N BLP Apply a voltage signal V to the bit line BLP of the memristor array BLP To drive the bit line BLP, the input voltage signal V IP Determines the voltage signal V output by the bit line driver / clamp circuit BLP size.

[0097] like Fig. 9B As shown, in the forward calculation mode, when the bit line driving / clamping circuit based on the source follower arrangement drives the bit line BLN, switches SW.1 and SW.3 are closed, switches SW.2 and SW.4 are opened, and the gate of transistor NM.F2 receives the input voltage signal V for the bit line BLN. IN , the bit line node coupled to the output stage circuit is N BLN At this time, only transistor PM.F3 is connected to the output stage circuit, and transistor PM.F1 does not participate in the forward calculation. The voltage change at node ND is transmitted to node NG, and the bit line driver / clamp circuit passes through the bit line node N BLN Apply a voltage signal V to the bit line BLN of the memristor array BLN To drive the bit line BLN, the input voltage signal V IN Determines the voltage signal V output by the bit line driver / clamp circuit BLN size.

[0098] like Fig. 10AAs shown, the bit line driving / clamping circuit includes a transistor NM.F1, a transistor PM.F2, three current generating units IG1~IG3 and an output stage circuit, wherein the output stage circuit includes a transistor PM.F2, a transistor NM.F2 and four switches SW.1~SW.4. The source of the transistor PM.F1 is coupled to the voltage source VDD and the output end of the current generating unit IG1 respectively, the drain of the transistor PM.F1 is coupled to the input end of the current generating unit IG2 and the second end of the switch SW.2 respectively, and the gate of the transistor PM.F1 receives the control signal V B The source of transistor NM.F1 is connected to the input terminal of current generating unit IG3 and the bit line node (eg, N BLP ) are coupled respectively, the drain of transistor NM.F1 and the output end of current generating unit IG1 are coupled to node ND, and the gate of transistor NM.F1 receives an input voltage signal (for example, V IP The drain of transistor PM.F2 is connected to the bit line node (eg, N BLP ), the drain of transistor NM.F2 is coupled to the input terminal of current generating unit IG3 respectively, the source of transistor PM.F2 is coupled to voltage source VDD, the gate of transistor PM.F2 is coupled to the second terminal of switch SW.1 and the first terminal of switch SW.2 respectively. The source of transistor NM.F2 is grounded, the drain of transistor NM.F2 is connected to the bit line node (for example, N BLP ), the drain of transistor PM.F2 is coupled to the input terminal of current generating unit IG3 respectively, the gate of transistor NM.F2 is coupled to the second terminal of switch SW.3 and the first terminal of switch SW.4. Switch SW.1 is used to control the conduction between the source and gate of transistor PM.F2, switch SW.2 is used to control the conduction between the gate of transistor PM.F2 and the drain of transistor PM.F1, and switch SW.4 is used to control the conduction between the source and gate of transistor NM.F2.

[0099] like Fig. 10A As shown, in the forward calculation mode, when the bit line driving / clamping circuit based on the common gate follower arrangement drives the bit line BLP, switches SW.1 and SW.3 are opened, switches SW.2 and SW.4 are closed, and the gate of transistor NM.F1 receives the input voltage signal V for the bit line BLP. IP , the bit line node coupled to the output stage circuit is N BLP At this time, only transistor PM.F2 is connected to the output stage circuit, and transistor NM.F2 does not participate in the forward calculation. The voltage change at node ND is transmitted to node NG, and the bit line driver / clamp circuit passes through the bit line node N BLP Apply a voltage signal V to the bit line BLP of the memristor array BLP To drive the bit line BLP, the input voltage signal V IPDetermines the voltage signal V output by the bit line driver / clamp circuit BLP size.

[0100] like Fig. 10B As shown, in the forward calculation mode, when the bit line driving / clamping circuit based on the common gate follower arrangement drives the bit line BLN, switches SW.2 and SW.3 are closed, switches SW.1 and SW.4 are opened, and the gate of transistor NM.F1 receives the input voltage signal V for the bit line BLN. IN , the bit line node coupled to the output stage circuit is N BLN At this time, only transistor NM.F2 is connected to the output stage circuit, and transistor PM.F1 does not participate in the forward calculation. The voltage change at node ND is transmitted to node NG, and the bit line driver / clamp circuit passes through the bit line node N BLN Apply a voltage signal V to the bit line BLN of the memristor array BLN To drive the bit line BLN, the input voltage signal V IN Determines the voltage signal V output by the bit line driver / clamp circuit BLN size.

[0101] The bit line driver / clamp circuit (such as Fig. 10A and Fig. 10B The output voltage signal V BLP and V BLN , has a voltage signal V output by the bit line driver / clamp circuit using a source follower (SF-FVF) BLP and V BLN Higher loop gain.

[0102] For example, Fig.11A and Fig. 11B A schematic diagram of the structure of a bit line calculation module based on a common-gate follower arrangement provided by at least one embodiment of the present disclosure is shown.

[0103] like Fig.11A and Fig. 11B As shown, the bit line calculation module includes a bit line driving / clamping circuit 1110, an analog-to-digital converter 1120, and four switches (i.e., switches SW.CP, SW.CN, SW.IP, and SW.IN). The switches SW.CP, SW.CN, SW.IP, and SW.IN are used to couple the bit line driving / clamping circuit 1110 and the analog-to-digital converter 1120.

[0104] The bit line driver / clamp circuit 1110 includes the following: Fig. 9A and Fig. 9B The bit line driver / clamp circuit based on the source follower arrangement is shown to simultaneously pass through the node N BLN and node N BLPThe bit line BLN and the bit line BLP are driven at the same time. The description of the bit line driving / clamping circuit 1110 can refer to the above description of Fig. 9A and Fig. 9B The description of the bit line driver / clamp circuit shown in FIG. 1 and the structure of the analog-to-digital converter 1120 can be referred to above. Figure 7B The description of the analog-to-digital converter in will not be repeated here.

[0105] In the above Fig.11A and Fig. 11B In the bit line calculation module shown, the closing or opening of switches SW.CP, SW.CN, SW.IP and SW.IN is determined according to a specific calculation mode.

[0106] For example, in forward computation mode (such as Fig.11A As shown in FIG. 1 ), switches SW.CP, SW.CN, SW.IP and SW.IN are all disconnected so that the analog-to-digital converter 1120 does not participate in the calculation, switches SW.1_1 and SW.3_1 are disconnected, switches SW.2_1 and SW.4_1 are closed, switches SW.1 and SW.3 are closed, switches SW.2 and SW.4 are disconnected, and different voltage signals V are input to the gates of transistors NM.F2 and NM.F2_1, respectively. IN and V IP , so that the voltage on the bit line BLP and the bit line BLN (ie, the node N BLN and node N BLP The voltages at the points are the differential voltages representing the input data, and satisfy the relationship (V BLP +V BLN ) / 2=V CM At this time, the bit line BLP is connected to be driven by the transistor PM.F1_1 in the output stage circuit 1102, and the bit line BLN is connected to be driven by the transistor NM.F3 in the output stage circuit 1101.

[0107] For example, in the back propagation calculation mode, if the input voltage on the source line SL is higher than the clamp voltage of the bit line BLP and the bit line BLN, the node N BLP and node N BLN The current direction is to flow into the bit line BLP and the bit line BLN, and the output stage circuits 1101 and 1102 are respectively connected by transistors NM.F3 and NM.F3_1. If the input voltage on the source line SL is lower than the clamping voltage of the bit line BLP and the bit line BLN, the output stage circuits 1101 and 1102 are respectively connected by transistors PM.F1 and PM.F1_1.

[0108] For example, in the reverse propagation calculation mode, when the output stage circuits 1101 and 1102 are connected by transistors NM.F3 and NM.F3_1 respectively (such as Fig. 11BAs shown in FIG. 1 ), the same voltage signal (V IN =V IP ), so that node N BLN and node N BLP The voltage at the same point is equal to V RD The difference between the voltage at the node CN and the voltage at the node CP represents the difference between the current on the bit line BLP and the current on the bit line BLN. At the same time, the switches SW.CP, SW.CN, SW.IP and SW.IN are all closed to couple the bit line driver / clamp circuit 1110 to the analog-to-digital converter 1120. The logic control circuit 1122 (e.g., SAR logic control circuit) in the analog-to-digital converter 1120 controls the current generating unit 1123 (IDAC) to generate a corresponding current feedback to the node N according to the magnitude relationship between the voltage at the node CP and the voltage at the node CN. BLN and node N BLP , thereby compensating the load current flowing into the bit line driving / clamping circuit 1110. Finally, the voltages of the node CP and the node CN are made the same, that is, the current difference flowing into the bit line BLP and the bit line BLN is 0, and quantization is completed.

[0109] In addition, based on the above Fig.11A and Fig. 11B The bit line calculation module shown can also be used as Fig. 10A and Fig. 10B The bit line driving / clamping circuit shown is used to set the bit line calculation module, and the present disclosure is not limited to this.

[0110] In the storage-computation integrated circuit provided in at least one embodiment of the present disclosure, the source line calculation module includes a plurality of source line driving / clamping circuits and a second analog-to-digital converter, and the plurality of source line driving / clamping circuits are respectively coupled to a plurality of source lines. Each source line driving / clamping circuit is configured to, in a forward calculation mode, clamp the voltage of the corresponding source line to a second clamping reference voltage, and generate a first load voltage based on a first load current on the corresponding source line, or, in a reverse propagation mode, provide a second input voltage to the corresponding source line. The second analog-to-digital converter is coupled to the plurality of source line driving / clamping circuits, and is configured to, in a forward calculation mode, sequentially perform quantization operations on the first load voltages generated by the plurality of source line driving / clamping circuits, and output a first quantization result.

[0111] For example, Fig. 12A and Fig. 12B A schematic diagram of the structure of a source line calculation module in forward calculation and reverse propagation modes provided by at least one embodiment of the present disclosure is shown.

[0112] like Fig. 12A (or Fig. 12B), the source line calculation module includes a plurality of source line driving / clamping circuits 1221 and an analog-to-digital converter 1270. Fig. 12B Only one source line driver / clamp circuit 1221 is schematically shown in FIG. The source line driver / clamp circuit 1221 includes a differential amplifier 1260 and a transistor NM, and the output terminal of the differential amplifier is coupled to the control terminal (i.e., the gate) of the transistor NM. In the forward calculation mode, the first input terminal (i.e., the positive input terminal) of the differential amplifier 1260 is clamped to the second clamp reference voltage V CM (a fixed voltage), the second input terminal (i.e., the negative input terminal) of the differential amplifier receives the first load current (i.e., the current on the source line SL coupled to the source line driver / clamp circuit 1221). In the reverse propagation mode, the first input terminal of the differential amplifier 1260 receives the second input voltage, and the second input terminal of the differential amplifier provides the second input voltage to the source line SL coupled to the source line driver / clamp circuit 1221. The "second input voltage" here is the analog voltage obtained after the digital-to-analog conversion circuit converts the received input data.

[0113] For example, the analog-to-digital converter 1270 includes a comparator 1271, a logic control circuit 1272 (eg, a SAR logic control circuit), and a current generating unit 1273 (IDAC). The comparator 1271 is configured to compare the first load voltage with a reference voltage V REF The logic control circuit 1272 is coupled to the output terminal of the comparator 1271 and the input terminal of the current generating unit 1273 , and is configured to control the current generating unit 1273 to generate a first current according to the comparison result of the comparator 1271 , so as to adjust the first load current on the source line SL.

[0114] For example, the logic control circuit 1272 is further configured to output a first quantization result according to the comparison result of the comparator 1271 .

[0115] Below Fig. 12A and Fig. 12B Taking the source line calculation module shown as an example, the process of the source line calculation module performing forward calculation and reverse propagation in at least one embodiment of the present disclosure is further introduced.

[0116] like Fig. 12A As shown in Figure 1, in the forward calculation mode, switch SW.S1 is open and switch SW.S2 is closed. The voltage at the positive input of the differential amplifier is clamped to the voltage V CM Then, switch SW.S3 is closed, and the voltage at the two input terminals of comparator 1271 is clamped to voltage V REF . Clamped to voltage V REFAfter that, the switch SW.S3 is disconnected, the load current accumulates (or integrates) at the top plate of the capacitor CINT, and the comparator 1271 compares the top plate voltage of the capacitor CINT with the voltage VREF and outputs the comparison result. The "load current" here is the array load current flowing into or out of the analog-to-digital converter 1270. The SAR logic circuit 1272 controls the current generating unit 1273 (IDAC) according to the comparison result, for example, by controlling the current generating unit 1273 to generate a first current to the clamping point of the source line SL to adjust the load current on the source line SL. The SAR logic circuit 1272 controls the magnitude and polarity of the first current generated by the current generating unit 1273 according to the comparison result. For example, if the top plate voltage of the capacitor CINT is greater than the voltage VREF, the current generating unit 1273 generates a negative current (that is, a current flows into the current generating unit 1273), so that the top plate voltage of the capacitor CINT becomes smaller in the next operation cycle. If the source line calculation module includes m source line driving / clamping circuits 1221, the SAR logic circuit 1272 will also output a 1-bit quantization result according to the comparison result, and the 1-bit quantization result is the highest bit of the final quantization result (including mbit). After that, the switch SW.S3 is closed, and the above process is repeated until the SAR logic circuit 1272 obtains an m-bit quantization result according to the comparison result. At this time, the first current generated by the current generating unit 1273 offsets the load current flowing from the source line SL into the clamping point, and the integrated current of the capacitor CINT is close to 0.

[0117] like Fig. 12B As shown, in the reverse propagation mode, the switch SW.S1 is closed, and the switches SW.S2 and SW.S3 are opened. At this time, the analog-to-digital converter 1270 does not participate in the process of the source line calculation module executing the reverse propagation mode. The source line drive / clamp circuit 1221 is an input drive circuit based on gain boosting technology. The first input terminal of the differential amplifier 1260 receives the voltage V IF (i.e. the analog voltage obtained by the digital-to-analog conversion circuit after converting the received input data), and then the voltage V after gain enhancement IF Applied to the source line SL.

[0118] At least one embodiment of the present disclosure further provides an electronic device, which includes the storage-computing integrated circuit provided by any embodiment of the present disclosure.

[0119] For example, Fig.13 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown.

[0120] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc., and may also be any combination of data processing devices and hardware, which is not limited by the embodiments of the present disclosure. Fig.13 The electronic device 1300 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0121] For example, Fig.13 As shown, in some examples, the electronic device 1300 includes a processing device (such as a central processing unit, a graphics processing unit, etc.) 1301, which may include the above-mentioned storage-computing integrated device and the storage-computing integrated device includes the storage-computing integrated circuit of any of the above-mentioned embodiments. The processing device can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 1302 or the program loaded from the storage device 1308 to the random access memory (RAM) 1303. In RAM 1303, various programs and data required for the operation of the computer system are also stored. The processor 1301, ROM 1302 and RAM 1303 are connected to each other through a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.

[0122] For example, the following components may be connected to the I / O interface 1305: an input device 1306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1309 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1309 may allow the electronic device 1300 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1310 is also connected to the I / O interface 1305 as needed. Removable media 1311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 1310 as needed, so that the computer program read therefrom can be installed into the storage device 1308 as needed. Although Fig.13 The electronic device 1300 is shown to include various devices, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0123] For example, the electronic device 1300 may further include a peripheral interface ( Fig.1311a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), voice transmission over Internet protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or short message service (SMS), or any other suitable communication protocol.

[0124] In addition to the above exemplary descriptions, there are a few points that need to be explained:

[0125] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to the general design.

[0126] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0127] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A storage and computing integrated circuit, comprising: Memristor array, digital-to-analog conversion circuit, bit line calculation module, source line calculation module and control module, wherein: The control module is configured to control the operations of the memristor array, the digital-to-analog conversion circuit, the bit line calculation module, and the source line calculation module based on a calculation mode of the storage-computation integrated circuit, wherein the calculation mode includes a forward calculation mode and a reverse propagation mode; In the forward calculation mode, the digital-to-analog conversion circuit converts the received first data to obtain a first input voltage provided to the bit line calculation module, the bit line calculation module provides the received first input voltage to the memristor array, so that the memristor array generates a first load current after performing a first calculation using the first input voltage, and the source line calculation module quantizes the first load current; and In the reverse propagation mode, the digital-to-analog conversion circuit converts the received second data to obtain a second input voltage provided to the source line calculation module, and the source line calculation module provides the received second input voltage to the memristor array so that the memristor array generates a second load current after performing a second calculation using the second input voltage, and the bit line calculation module quantizes the second load current.

2. The storage-computation-in-one circuit according to claim 1, wherein: The memristor array includes a plurality of source lines, a plurality of bit lines and a plurality of weight units arranged in an array. The bit line calculation module is coupled to the plurality of bit lines of the memristor array and is further configured to clamp the voltages of the plurality of bit lines to a first clamp reference voltage in the reverse propagation mode; as well as The source line calculation module is coupled to a plurality of source lines of the memristor array, and is further configured to clamp the voltages of the plurality of source lines to a second clamp reference voltage in the forward calculation mode.

3. The storage-computation-in-one circuit according to claim 2, wherein: The bit line calculation module includes: a plurality of bit line driving / clamping circuits and a first analog-to-digital converter, wherein the plurality of bit line driving / clamping circuits are respectively coupled to the plurality of bit lines, Each of the bit line driving / clamping circuits is configured to, in the forward calculation mode, provide the first input voltage to the corresponding bit line, or, in the reverse propagation mode, clamp the voltage of the corresponding bit line to the first clamping reference voltage and generate a second load voltage based on a second load current on the corresponding bit line; The first analog-to-digital converter is coupled to the plurality of bit line driving / clamping circuits, and is configured to sequentially perform quantization operations on the second load voltages generated by the plurality of bit line driving / clamping circuits in the reverse propagation mode, and output a second quantization result.

4. The storage-computation-in-one circuit according to claim 3, wherein: The first analog-to-digital converter is a current type or a voltage type.

5. The storage-computation-in-one circuit according to claim 3, wherein: The bit line driving / clamping circuit is configured based on a gain amplifier or a flip voltage follower.

6. The storage-computation-in-one circuit according to claim 2, wherein: The source line calculation module includes a plurality of source line driving / clamping circuits and a second analog-to-digital converter, wherein the plurality of source line driving / clamping circuits are respectively coupled to the plurality of source lines. Each of the source line driving / clamping circuits is configured to, in the forward calculation mode, clamp the voltage of the corresponding source line to the second clamping reference voltage and generate a first load voltage based on a first load current on the corresponding source line, or, in the reverse propagation mode, provide the second input voltage to the corresponding source line; The second analog-to-digital converter is coupled to the multiple source line driving / clamping circuits, and is configured to sequentially perform quantization operations on the first load voltages generated by the multiple source line driving / clamping circuits in the forward calculation mode, and output a first quantization result.

7. The storage-computation-in-one circuit according to claim 6, wherein: The source line driving / clamping circuit includes a differential amplifier and a transistor, wherein the output terminal of the differential amplifier is coupled to the control terminal of the transistor. In the forward calculation mode, the first input terminal of the differential amplifier is clamped to the second clamp reference voltage, and the second input terminal of the differential amplifier receives the first load current, or, in the reverse propagation mode, the first input terminal of the differential amplifier receives the second input voltage, and the second input terminal of the differential amplifier provides the second input voltage to the corresponding source line.

8. The storage-computation-in-one circuit according to claim 6, wherein: The second analog-to-digital converter includes a comparator, a logic control circuit and a current generating unit. The comparator is configured to compare the first load voltage with a reference voltage, The logic control circuit is coupled to the comparator and the current generating unit, and is configured to control the current generating unit to generate a first current according to a comparison result of the comparator, so as to adjust a first load current on the corresponding source line.

9. The storage-computation-in-one circuit according to claim 8, wherein: The logic control circuit is further configured to output the first quantization result according to the comparison result of the comparator.

10. An electronic device comprising the storage-computing integrated circuit as claimed in any one of claims 1 to 9.

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