Low-voltage intelligent arcless table area circuit breaker and control method

Abstract

The application discloses a low-voltage intelligent arcless transformer area circuit breaker and a control method, wherein a microprocessor is connected with a voltage sensor, a current sensor, a mechanical circuit breaker, a wireless communication module, an IGBT driving circuit and a converter.The microprocessor receives sensing signals of the voltage sensor and the current sensor and control information of the wireless communication module; according to the sensing signals of the voltage sensor and the current sensor, a GPS module clock signal and the control information of the wireless communication module, the operation state of a transformer area is calculated, and the mechanical circuit breaker, the IGBT driving circuit and the converter are controlled according to the calculation and analysis result, so that the problem that a traditional circuit breaker cannot meet the increasing demand for new energy such as photovoltaic and charging piles in a transformer area is solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit breakers, and particularly relates to a low-voltage intelligent arcless distribution circuit breaker and a control method. BACKGROUND

[0002] The current invention or utility model all proposes an arcless alternating current circuit breaker design scheme, such as patent No. ZL200520096776.4, an intelligent arcless circuit breaker, application No. 201020652885.0, a three-phase arcless circuit breaker, application No. CN201710544678.X, a high-breaking arcless circuit breaker, and application No. 202221641724.0, an arcless miniature circuit breaker arc extinction module, but all have certain defects. Due to the use of new energy, more and more charging piles and roof photovoltaics are connected to the distribution circuit, and the power quality of the distribution circuit is getting worse, and the traditional circuit breaker breaking decision cannot meet the increasing demand of new energy in the distribution circuit. The connection of new energy also puts forward new requirements for the arcless alternating current circuit breaker. The present application is based on the increasing demand of new energy connected to the existing distribution circuit, and designs an arcless circuit breaker. SUMMARY

[0003] In view of the above-mentioned deficiencies in the prior art, the low-voltage intelligent arcless distribution circuit breaker and the control method provided by the present application solve the problem that the traditional circuit breaker cannot meet the increasing demand of new energy such as photovoltaics and charging piles in the distribution circuit.

[0004] In order to achieve the above-mentioned purposes, the technical scheme adopted by the present application is as follows: a low-voltage intelligent arcless distribution circuit breaker, comprising a voltage sensor, a current sensor, a left end resistor, a left end inductor, a transformer, a mechanical circuit breaker, a right end resistor, a right end inductor, an IGBT, an IGBT drive circuit, a microprocessor, a wireless communication module, a GPS module and a converter;

[0005] The microprocessor is connected with the voltage sensor, the current sensor, the IGBT drive circuit, the wireless communication module, the GPS module and the converter respectively, the voltage sensor is further connected with the current sensor, the left end resistor and the left end inductor in sequence, the left end inductor is further connected with the No. 1 terminal of the transformer, the mechanical circuit breaker and the IGBT respectively, the converter is connected with the No. 3 terminal and the No. 4 terminal of the transformer, the IGBT drive circuit is connected with the IGBT, and the mechanical circuit breaker is further connected with the right end resistor and the right end inductor;

[0006] The voltage sensor is used to collect the voltage values of three phases of the transformer output of the transformer area, the current sensor is used to collect the current values of three phases of the transformer output of the transformer area, the wireless communication module is used to receive the control information of the transformer area circuit breaker, the GPS module is used to provide a clock signal for the microprocessor, the microprocessor is used to calculate the transformer area operation state according to the voltage and current values of three phases of the transformer output of the transformer area, the clock signal and the control information, control the mechanical circuit breaker and the IGBT driving circuit according to the calculation result, and the IGBT is used to control the current.

[0007] Further, the converter comprises a three-phase transformer, a first power diode, a second power diode, a third power diode and a voltage conversion circuit, the three-phase transformer is provided with a primary side A-phase terminal, a primary side B-phase terminal, a primary side C-phase terminal, a secondary side A-phase terminal, a secondary side B-phase terminal, a secondary side C-phase terminal and a secondary side neutral point, and the voltage conversion circuit is provided with a voltage conversion circuit P-pole and a voltage conversion circuit N-pole.

[0008] The primary side A-phase terminal is connected with the A-phase of the voltage, the primary side B-phase terminal is connected with the B-phase of the voltage, the primary side C-phase terminal is connected with the C-phase of the voltage, the secondary side A-phase terminal is connected with the voltage conversion circuit P-pole through the first power diode, the secondary side B-phase terminal is connected with the voltage conversion circuit P-pole through the second power diode, the secondary side C-phase terminal is connected with the voltage conversion circuit P-pole through the third power diode, and the secondary side neutral point is connected with the voltage conversion circuit N-pole.

[0009] Further, the voltage conversion circuit comprises an upper end capacitor, a lower end capacitor, an upper end power diode, a lower end power diode, a left upper switch, a left lower switch, a bridge switch, a right lower positive switch, a right lower negative switch, a right upper negative switch, a right upper positive switch, a left upper switch drive, a left lower switch drive, a bridge switch drive, a right lower positive switch drive, a right lower negative switch drive, a right upper negative switch drive and a right upper positive switch drive.

[0010] The left upper switch drive, the left lower switch drive, the bridge switch drive, the right lower positive switch drive, the right lower negative switch drive, the right upper negative switch drive and the right upper positive switch drive are all IGBT driving circuits, the left upper switch drive is connected with the gate of the left upper switch, the left lower switch drive is connected with the gate of the left lower switch, the bridge switch drive is connected with the gate of the bridge switch, the right lower positive switch drive is connected with the gate of the right lower positive switch, the right lower negative switch drive is connected with the gate of the right lower negative switch, the right upper negative switch drive is connected with the gate of the right upper negative switch, and the right upper positive switch drive is connected with the gate of the right upper positive switch.

[0011] The anodes of the upper power diodes are connected in short circuit with the P-pole of the voltage conversion circuit and the emitters of the upper left switches, respectively; the cathodes of the upper power diodes are connected in short circuit with one end of the upper capacitor, the emitters of the upper right negative switches and the emitters of the upper right positive switches, respectively; the other end of the upper capacitor is connected in short circuit with the emitters of the bridge switches and the collectors of the upper left switches;

[0012] The cathodes of the lower power diodes are connected in short circuit with the N-pole of the voltage conversion circuit and the collectors of the lower left switches, respectively; the anodes of the lower power diodes are connected in short circuit with one end of the lower capacitor, the emitters of the lower right positive switches and the emitters of the lower right negative switches, respectively; the other end of the lower capacitor is connected in short circuit with the collectors of the bridge switches and the emitters of the lower left switches;

[0013] The emitters of the lower right positive switches are connected in short circuit with the collectors of the upper right positive switches and the P-pole of the voltage conversion circuit, respectively; the collectors of the upper right negative switches are connected in short circuit with the emitters of the lower right negative switches and the N-pole of the voltage conversion circuit, respectively.

[0014] The control method of the low-voltage intelligent arcless panel circuit breaker comprises the following steps:

[0015] S1, initialization operation is performed through an initialization subroutine;

[0016] S2, in response to startF being equal to 1, a tripping and compensation calculation subroutine is called to calculate a tripping criterion;

[0017] S3, in response to the tripping criterion being equal to 1, a tripping action subroutine is called to perform a tripping action.

[0018] Further, the S1 comprises the following steps:

[0019] S11, a low-frequency interrupt clock is set to 20 milliseconds, and a high-frequency interrupt clock is set to 50 microseconds;

[0020] S12, a low-frequency interrupt condition is set, and a low-frequency interrupt subroutine is set to be called when interrupted; a high-frequency interrupt condition is set, and a high-frequency interrupt subroutine is set to be called when interrupted;

[0021] S13, variables are set, including:

[0022] A phase voltage phase zero degree millisecond counter, an A phase voltage phase zero degree microsecond counter, a high-frequency interrupt counter denoted by CH, a value range of which is 0-999, a tripping voltage threshold denoted by VY, a tripping current threshold denoted by IY, a compensation threshold denoted by BY, a tripping flag denoted by TZ, a sensor reading counter denoted by CVA, a value range of which is 0-999, a period counter denoted by CZQ, a value range of which is 0-199, a voltage summation denoted by SUMV, and a voltage summation denoted by SUMI;

[0023] The array AVINA

[400] represents the first reading value of phase A of the voltage sensor, the array AVINB

[400] represents the second reading value of phase A of the voltage sensor, the array AFV

[400] represents the floating-point value of phase A voltage, the array AIINA

[400] represents the first reading value of phase A of the current sensor, the array AIINB

[400] represents the second reading value of phase A of the current sensor, the array AFI

[400] represents the floating-point value of phase A current, and the array AVBZ

[400] represents phase A compensation.

[0024] The array BVINA

[400] represents the first reading value of phase B of the voltage sensor, the array BVINB

[400] represents the second reading value of phase B of the voltage sensor, the array BFV

[400] represents the floating-point value of phase B voltage, the array BIINA

[400] represents the first reading value of phase B of the current sensor, the array BINB

[400] represents the second reading value of phase B of the current sensor, the array BFI

[400] represents the floating-point value of phase B current, and the array BVBZ

[400] represents phase B compensation.

[0025] The array CVINA

[400] represents the first reading value of phase C of the voltage sensor, the array CVINB

[400] represents the second reading value of phase C of the voltage sensor, the array CFV

[400] represents the floating-point value of phase C voltage, the array CIINA

[400] represents the first reading value of phase C of the current sensor, the array CIINB

[400] represents the second reading value of phase C of the current sensor, the array CFI

[400] represents the floating-point value of phase C current, and the array CVBZ

[400] represents phase C compensation;

[0026] PT represents the time update data position, FTZ represents the trip calculation variable, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low-frequency interruption flag, SELF represents the storage selection flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, BZYZ represents the compensation threshold, MAXSUMBZ represents the maximum compensation sum, ACNTVI represents the A-phase storage position counter, BCNTVI represents the B-phase storage position counter, and CCNTVI represents the C-phase storage position counter.

[0027] S13. Initialize variables. The variables to be initialized are:

[0028] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0029] AVINA

[800] , AIINB

[800] , BVINA

[800] , BIINB

[800] , CVINA

[800] and CIINB

[800] are all initialized to all zeros;

[0030] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0031] Further: In S12, the method for calling the low-frequency interrupt subroutine is specifically as follows:

[0032] A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0 to 799, and proceed to A2.

[0033] If not, let ACDATA[i] = AVINB[i], where i = 0 to 799, and proceed to A2;

[0034] A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i], let WZ = i and startF = 1.

[0035] Further: In S12, the method for calling the high-frequency interrupt subroutine is specifically as follows:

[0036] B1. Determine if SELF is false. If it is, proceed to SB2.

[0037] If not, then let AVINA equal the stored value of the memory corresponding to the voltage sensor, let AIINA equal the stored value of the memory corresponding to the current sensor, let BVINA equal the stored value of the memory corresponding to the voltage sensor, let BIINA equal the stored value of the memory corresponding to the current sensor, let CVINA equal the stored value of the memory corresponding to the voltage sensor, and let CIINA equal the stored value of the memory corresponding to the current sensor.

[0038] AFV[CNTCNN]=(AVINA–32768) / 32768

[0039] AFI[CNTCNN]=(AIINA–32768) / 32768

[0040] BFV[CNTCNN]=(AVINA–32768) / 32768

[0041] BFI[CNTCNN]=(AIINA–32768) / 32768

[0042] CFV[CNTCNN]=(AVINA–32768) / 32768

[0043] CFI[CNTCNN]=(AIINA–32768) / 32768

[0044] Enter B3;

[0045] B2. Let AVINB be equal to the stored value of the memory corresponding to the voltage sensor, let AIINB be equal to the stored value of the memory corresponding to the current sensor, let BVINB be equal to the stored value of the memory corresponding to the voltage sensor, let BIINB be equal to the stored value of the memory corresponding to the current sensor, let CVINB be equal to the stored value of the memory corresponding to the voltage sensor, and let CIINB be equal to the stored value of the memory corresponding to the current sensor.

[0046] AFV[CNTCNN]=(AVINB–32768) / 32768

[0047] AFI[CNTCNN]=(AIINB–32768) / 32768

[0048] BFV[CNTCNN]=(AVINB–32768) / 32768

[0049] BFI[CNTCNN]=(AIINB–32768) / 32768

[0050] CFV[CNTCNN]=(AVINB–32768) / 32768

[0051] CFI[CNTCNN]=(AIINB–32768) / 32768

[0052] Enter B3;

[0053] B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN = 0.

[0054] Enter B4;

[0055] B4, responding to FBZ equal to 1, proceed to B5;

[0056] In this embodiment, if FBZ is not equal to 1, the high-frequency interrupt subroutine is called.

[0057] B5. Determine if CNTCNN is greater than WZ. If yes, let WZ1 = CNTCNN - WZ; otherwise, let WZ1 = 400 + CNTCNN - WZ.

[0058] Enter B6;

[0059] B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1.

[0060] Enter B7;

[0061] B7. Control the A-phase circuit, then proceed to B8;

[0062] B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If it is, let WZ1 = CNTCNN - WZ; if not, let WZ1 = 400 + CNTCNN - WZ.

[0063] Enter B9;

[0064] B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0065] Enter B10;

[0066] B10. Control the B-phase circuit, then proceed to B11;

[0067] B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If yes, set WZ1 = CNTCNN - WZ; otherwise, set WZ1 = 400 + CNTCNN - WZ and proceed to B12.

[0068] B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13.

[0069] B13. Control of the C-phase circuit;

[0070] The control methods for phases A, B, and C are the same, specifically as follows:

[0071] If the response is greater than or equal to 0.865, then:

[0072] Turn off the bridging switch, the lower right positive switch, and the upper right negative switch; turn on the upper left switch, the lower left switch, the lower right negative switch, and the upper right positive switch.

[0073] If the response is less than 0.865 and greater than or equal to 0.615:

[0074] Turn off the upper left switch, the upper right positive switch, and the lower right negative switch; turn on the lower left switch, the bridging switch, the lower right positive switch, and the upper right negative switch.

[0075] If the response is less than 0.615 and greater than or equal to 0.25:

[0076] Turn on the top left switch, bottom left switch, and bottom right positive switch; turn on the bridging switch, bottom right negative switch, and top right positive switch;

[0077] If the response is that AVBZ[WZ1] is less than 0.25 and greater than or equal to -0.25, then:

[0078] Turn off the upper left switch, lower left switch, lower right positive switch, and lower right negative switch; turn on the bridging switch, upper right negative switch, and upper right positive switch.

[0079] If the response is that AVBZ[WZ1] is less than -0.25 and greater than or equal to -0.615:

[0080] Turn off the top left switch, bottom left switch, bottom right negative switch, and top right positive switch; turn on the bridging switch, bottom right positive switch, and top right negative switch.

[0081] If the response is that AVBZ[WZ1] is less than -0.615 and greater than or equal to -0.865:

[0082] Turn off the lower left switch, bridging switch, lower right negative switch, and upper right positive switch; turn on the upper left switch, lower right positive switch, and upper right negative switch.

[0083] If the response is less than -0.865:

[0084] Turn off the bridging switch, the lower right negative switch, and the upper right positive switch; turn on the upper left switch, the lower left switch, the lower right positive switch, and the upper right negative switch.

[0085] Further: In S2, the method of calling the tripping and compensation calculation subroutine is specifically as follows:

[0086] S21. Calculate AZK, BZK, and CZK. The methods for calculating AZK, BZK, and CZK are the same. The specific expression for calculating AZK is as follows:

[0087]

[0088]

[0089] AZK = SUMV / SUMI

[0090] WZ1 = WZ + 133

[0091] In response to whether WZ1 is greater than 400, subtract 400 from the value of WZ1;

[0092] S22. Calculate the minimum value of AZK, BZK, and CZK, and assign it to MINZK;

[0093] S23. Determine whether MINZK is less than the preset threshold ZLYZ. If yes, set TZF = 1; otherwise, set TZF = 0.

[0094] S24. Calculate AVBZ[i], BVBZ[i], and CVBZ[i] using the following formula;

[0095] AVBZ[i]=M1data[i]–AFV[i+WZ]

[0096] BVBZ[i]=M1data[i]–BFV[i+WZ1]

[0097] CVBZ[i]=M1data[i]–CFV[i+WZ1]

[0098] In the formula, i = 0 to 399;

[0099] WZ1 = WZ + 133

[0100] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0101] S25. Calculate ASUMBZ, BSUMBZ, and CSUMBZ using the following formula;

[0102]

[0103] S26. Calculate the maximum value of ASUMZB, BSUMZB, and CSUMZB, assign it to MAXSUMBZ, and determine whether MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ = 1; if no, set FBZ = 0.

[0104] Furthermore, in step S3, the method of calling the tripping action subroutine includes the following steps:

[0105] S31. Control the IGBT to turn on and control the mechanical circuit breaker to turn off;

[0106] S32, Control IGBT shutdown.

[0107] The beneficial effects of this invention are as follows: This invention provides a low-voltage intelligent arc-free distribution transformer circuit breaker and its control method. It connects a microprocessor to a voltage sensor, a current sensor, a mechanical circuit breaker, a GPS module, a wireless communication module, an IGBT drive circuit, and a converter. The microprocessor receives the induced signals from the voltage and current sensors, the clock signal from the GPS module, and the control information from the wireless communication module. Based on these signals, the microprocessor calculates the operating status of the distribution transformer and controls the mechanical circuit breaker, IGBT drive circuit, and converter according to the calculation and analysis results. This solves the problem that traditional circuit breakers can no longer meet the increasing demands of photovoltaic power generation, charging piles, and other new energy sources in distribution transformer areas. Attached Figure Description

[0108] Figure 1 This is a schematic diagram of a low-voltage intelligent arc-free circuit breaker.

[0109] Figure 2 This is a schematic diagram of the transformer connection method.

[0110] Figure 3 This is a schematic diagram of the converter structure.

[0111] Figure 4 This is a diagram of a voltage conversion circuit.

[0112] Figure 5 This is a flowchart of the control method for arc-free circuit breakers in transformer substations.

[0113] Among them: 1. Voltage sensor; 2. Current sensor; 3. Left-end resistor; 4. Left-end inductor; 5. Transformer; 6. Mechanical circuit breaker; 7. Right-end resistor; 8. Right-end inductor; 9. IGBT; 10. IGBT drive circuit; 11. Microprocessor; 12. Wireless communication module; 14. Converter; 20. Three-phase transformer; 21. Primary side A-phase terminal; 22. Primary side B-phase terminal; 23. Primary side C-phase terminal; 24. Secondary side A-phase terminal; 25. Secondary side B-phase terminal; 26. Secondary side C-phase terminal; 27. Secondary side neutral point; 28-1. First power diode; 28-2. Secondary power diode; 28-3. Third power diode; 30. Electric... Voltage conversion circuit; 31. P-terminal of voltage conversion circuit; 32. N-terminal of voltage conversion circuit; 33. Positive terminal of voltage conversion circuit; 34. Negative terminal of voltage conversion circuit; 35. Upper capacitor; 36. Lower capacitor; 37. Upper power diode; 38. Lower power diode; 41. Upper left switch; 42. Lower left switch; 43. Bridge switch; 44. Lower right positive switch; 45. Lower right negative switch; 46. Upper right negative switch; 47. Upper right positive switch; 51. Upper left switch driver; 52. Lower left switch driver; 53. Bridge switch driver; 54. Lower right positive switch driver; 55. Lower right negative switch driver; 56. Upper right negative switch driver; 57. Upper right positive switch driver. Detailed Implementation

[0114] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0115] Example 1:

[0116] like Figure 1 As shown, in one embodiment of the present invention, a low-voltage intelligent arc-free circuit breaker includes a voltage sensor 1, a current sensor 2, a left-end resistor 3, a left-end inductor 4, a transformer 5, a mechanical circuit breaker 6, a right-end resistor 7, a right-end inductor 8, an IGBT 9, an IGBT drive circuit 10, a microprocessor 11, a wireless communication module 12, a GPS module, and a converter 14.

[0117] Among them, the microprocessor 11 is connected to the voltage sensor 1, the current sensor 2, the IGBT drive circuit 10, the wireless communication module 12, the GPS module and the converter 14 respectively. The voltage sensor 1 is also connected to the current sensor 2, the left end resistor 3 and the left end inductor 4 in sequence. The left end inductor 4 is also connected to the first terminal of the transformer 5, the mechanical circuit breaker 6 and the IGBT 9 respectively. The converter 14 is connected to the third and fourth terminals of the transformer 5. The IGBT drive circuit 10 is connected to the IGBT 9. The mechanical circuit breaker 6 is also connected to the right end inductor 8 through the right end resistor 7.

[0118] Voltage sensor 1 is used to collect the three-phase voltage values ​​output by the transformer in the distribution area. Current sensor 2 is used to collect the three-phase current values ​​output by the transformer in the distribution area. Wireless communication module 12 is used to receive control information from the circuit breaker in the distribution area. GPS module is used to provide clock signal to microprocessor 11. Microprocessor 11 is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, clock signal and control information. Based on the calculation results, it controls mechanical circuit breaker 6 and IGBT drive circuit 10. IGBT 9 is used to control current.

[0119] In this embodiment, the output of the transformer in the distribution area is a three-phase conductor, which passes through voltage sensor 1 and current sensor 2, and is then connected in series with a left-end resistor 3 and a left-end inductor 4, and then connected to one phase of the input of the mechanical circuit breaker 6. The connection point is connected to terminal 1 of the transformer 5. The same phase output of the mechanical circuit breaker 6 is connected to the right-end resistor 7. A right-end inductor 8 is connected in series to the right side of the right-end resistor 7. The right-end inductor 8 is connected to the distribution area load to supply power to the distribution area load and is connected to the input terminal of the mechanical circuit breaker 6. The output terminal of the mechanical circuit breaker 6 is connected to the input terminal of the power quality adjustment module.

[0120] Each phase voltage sensor 1 and current sensor 2 collect the voltage and current values ​​of the three phases (A, B, and C) output by the transformer in the distribution area. The sensor outputs are connected to the analog-to-digital conversion interface of the microprocessor 11.

[0121] The microprocessor 11 is connected to the voltage sensor 1, current sensor 2, mechanical circuit breaker 6, GPS module, wireless communication module 12, IGBT drive circuit 10, and converter 14. The microprocessor 11 receives the sensing signals from the voltage sensor 1 and current sensor 2, the clock signal from the GPS module, and the control information from the wireless communication module 12. Based on the sensing signals from the voltage sensor 1 and current sensor 2, the clock signal from the GPS module, and the control information from the wireless communication module 12, it calculates the operating status of the transformer area and controls the mechanical circuit breaker 6, IGBT drive circuit 10, and converter 14 based on the calculation and analysis results.

[0122] The output of IGBT driver circuit 10 is connected to IGBT9 to control IGBT9;

[0123] IGBT9 is a bidirectional IGBT, consisting of two IGBTs connected in reverse parallel.

[0124] Transformer 5 connection method as follows Figure 2 As shown.

[0125] like Figure 3 As shown, the converter 14 includes a three-phase transformer 20, a first power diode 28-1, a second power diode 28-2, a third power diode 28-3, and a voltage conversion circuit 30. The three-phase transformer 20 is provided with a primary side A-phase terminal 21, a primary side B-phase terminal 22, a primary side C-phase terminal 23, a secondary side A-phase terminal 24, a secondary side B-phase terminal 25, a secondary side C-phase terminal 26, and a secondary side neutral point 27. The voltage conversion circuit 30 is provided with a voltage conversion circuit P-pole 31 and a voltage conversion circuit N-pole 32.

[0126] In this circuit, the primary side A-phase terminal 21 is connected to the A-phase of the voltage, the primary side B-phase terminal 22 is connected to the B-phase of the voltage, the primary side C-phase terminal 23 is connected to the C-phase of the voltage, the secondary side A-phase terminal 24 is connected to the P-terminal 31 of the voltage conversion circuit through the first power diode 28-1, the secondary side B-phase terminal 25 is connected to the P-terminal 31 of the voltage conversion circuit through the second power diode 28-2, the secondary side C-phase terminal 26 is connected to the P-terminal 31 of the voltage conversion circuit through the third power diode 28-3, and the secondary side neutral point 27 is connected to the N-terminal 32 of the voltage conversion circuit.

[0127] like Figure 4 As shown, the voltage conversion circuit 30 includes an upper capacitor 35, a lower capacitor 36, an upper power diode 37, a lower power diode 38, an upper left switch 41, a lower left switch 42, a bridge switch 43, a lower right positive switch 44, a lower right negative switch 45, an upper right negative switch 46, an upper right positive switch 47, an upper left switch driver 51, a lower left switch driver 52, a bridge switch driver 53, a lower right positive switch driver 54, a lower right negative switch driver 55, an upper right negative switch driver 56, and an upper right positive switch driver 57.

[0128] Among them, the upper left switch driver 51, the lower left switch driver 52, the bridge switch driver 53, the lower right positive switch driver 54, the lower right negative switch driver 55, the upper right negative switch driver 56, and the upper right positive switch driver 57 are all IGBT drive circuits. The upper left switch driver 51 is connected to the gate of the upper left switch 41, the lower left switch driver 52 is connected to the gate of the lower left switch 42, the bridge switch driver 53 is connected to the gate of the bridge switch 43, the lower right positive switch driver 54 is connected to the gate of the lower right positive switch 44, the lower right negative switch driver 55 is connected to the gate of the lower right negative switch 45, the upper right negative switch driver 56 is connected to the gate of the upper right negative switch 46, and the upper right positive switch driver 57 is connected to the gate of the upper right positive switch 47.

[0129] The positive terminal of the upper power diode 37 is short-circuited to the P terminal 31 of the voltage conversion circuit and the emitter of the upper left switch 41, respectively. The negative terminal of the upper power diode 37 is short-circuited to one end of the upper capacitor 35, the emitter of the upper right negative switch 46 and the emitter of the upper right positive switch 47, respectively. The other end of the upper capacitor 35 is short-circuited to the emitter of the bridge switch 43 and the collector of the upper left switch 41.

[0130] The negative terminal of the lower power diode 38 is short-circuited to the N terminal 32 of the voltage conversion circuit and the collector of the lower left switch 42, respectively. The positive terminal of the lower power diode 38 is short-circuited to one end of the lower capacitor 36, the emitter of the lower right positive switch 44, and the emitter of the lower right negative switch 45, respectively. The other end of the lower capacitor 36 is short-circuited to the collector of the bridge switch 43 and the emitter of the lower left switch 42.

[0131] The emitter of the lower right positive switch 44 is short-circuited to the collector of the upper right positive switch 47 and the positive terminal 33 of the voltage conversion circuit, respectively; the collector of the upper right negative switch 46 is short-circuited to the emitter of the lower right negative switch 45 and the negative terminal 34 of the voltage conversion circuit, respectively.

[0132] like Figure 5 As shown, the control method for a low-voltage intelligent arc-free circuit breaker includes the following steps:

[0133] S1. Initialization is performed through an initialization subroutine;

[0134] S2. In response to startF equaling 1, the trip and compensation calculation subroutine is called to calculate the trip criteria.

[0135] S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform the tripping action.

[0136] S1 includes the following steps:

[0137] S11. Set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds;

[0138] S12. Set the low-frequency interrupt condition and set the low-frequency interrupt subroutine to be called when the interrupt occurs; set the high-frequency interrupt condition and set the high-frequency interrupt subroutine to be called when the interrupt occurs.

[0139] S13. Set variables, including:

[0140] Phase A voltage phase zero degree millisecond counter, Phase A voltage phase zero degree microsecond counter, CH represents high frequency interrupt counter, value range: 0~999, VY represents trip voltage threshold, IY represents trip current threshold, BY represents compensation threshold, TZ represents trip mark, CVA represents sensor read counter, value range: 0~999, CZQ represents period counter, value range: 0~199, SUMV represents voltage summation, SUMI represents voltage summation;

[0141] The array AVINA

[400] represents the first reading value of phase A of voltage sensor 1, the array AVINB

[400] represents the second reading value of phase A of voltage sensor 1, the array AFV

[400] represents the floating-point value of phase A voltage, the array AIINA

[400] represents the first reading value of phase A of current sensor 2, the array AIINB

[400] represents the second reading value of phase A of current sensor 2, the array AFI

[400] represents the floating-point value of phase A current, and the array AVBZ

[400] represents phase A compensation;

[0142] The array BVINA

[400] represents the first reading value of phase B of voltage sensor 1, the array BVINB

[400] represents the second reading value of phase B of voltage sensor 1, the array BFV

[400] represents the floating-point value of phase B voltage, the array BIINA

[400] represents the first reading value of phase B of current sensor 2, the array BINB

[400] represents the second reading value of phase B of current sensor 2, the array BFI

[400] represents the floating-point value of phase B current, and the array BVBZ

[400] represents phase B compensation;

[0143] The array CVINA

[400] represents the first reading value of phase C of voltage sensor 1, the array CVINB

[400] represents the second reading value of phase C of voltage sensor 1, the array CFV

[400] represents the floating-point value of phase C voltage, the array CIINA

[400] represents the first reading value of phase C of current sensor 2, the array CIINB

[400] represents the second reading value of phase C of current sensor 2, the array CFI

[400] represents the floating-point value of phase C current, and the array CVBZ

[400] represents phase C compensation;

[0144] PT represents the time update data position, FTZ represents the trip calculation variable, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low-frequency interruption flag, SELF represents the storage selection flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, BZYZ represents the compensation threshold, MAXSUMBZ represents the maximum compensation sum, ACNTVI represents the A-phase storage position counter, BCNTVI represents the B-phase storage position counter, and CCNTVI represents the C-phase storage position counter.

[0145] S13. Initialize variables. The variables to be initialized are:

[0146] MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF=0, ACNTVI=0, BCNTVI=0, CCNTVI= 0, CNTCNN=0, startF=0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0;

[0147] AVINA

[800] , AIINB

[800] , BVINA

[800] , BIINB

[800] , CVINA

[800] and CIINB

[800] are all initialized to all zeros;

[0148] S15. Set the first parameter M1data and the comparison variable BiJiao.

[0149] M1data

[400] = {0.015707,0.031411,0.047106,0.062791,0.078459,0.094108,0.109734,0.125333,0.140901,0.156434,0.171929,0.187381,0.2} 02787,0.218143,0.233445,0.248690,0.263873,0.278991,0.294040,0.309017,0.323917,0.338738,0.353475,0.368125,0.382683,0.397148,0. 411514,0.425779,0.439939,0.453990,0.467930,0.481754,0.495459,0.509041,0.522499,0.535827,0.549023,0.562083,0.575005,0.587785, 0.600420,0.612907,0.625243,0.637424,0.649448,0.661312,0.673013,0.684547,0.695913,0.707107,0.718126,0.728969,0.739631,0.750111 ,0.760406,0.770513,0.780430,0.790155,0.799685,0.809017,0.818150,0.827081,0.835807,0.844328,0.852640,0.860742,0.868632,0.8763 07,0.883766,0.891007,0.898028,0.904827,0.911403,0.917755,0.923880,0.929776,0.935444,0.940881,0.946085,0.951057,0.955793,0.960 294,0.964557,0.968583,0.972370,0.975917,0.979223,0.982287,0.985109,0.987688,0.990024,0.992115,0.993961,0.995562,0.996917,0.9 98027,0.998890,0.999507,0.999877,1.000000,0.999877,0.999507,0.998890,0.998027,0.996917,0.995562,0.993961,0.992115,0.990024,0.987688,0.985109,0.982287,0.979223,0.975917,0.972370,0.968583,0.964557,0.960294,0.955793,0.951057,0.946085,0.940881,0.935444,0.929776,0.923880,0.917755,0.911403,0.904827,0.898028,0.891007,0.883766,0.876307,0.868632,0.860742,0.852640,0.844328,0.835807,0.827081,0.818150,0.809017,0.799685,0.790155,0.780430,0.770513,0.760406,0.750111,0.739631,0.728969,0.718126,0.707107,0.695913,0.684547,0.673013,0.661312,0.649448,0.637424,0.625243,0.612907,0.600420,0.587785,0.575005,0.562083,0.549023,0.535827,0.522499,0.509041,0.495459,0.481754,0.467930,0.453990,0.439939,0.425779,0.411514,0.397148,0.382683,0.368125,0.353475,0.338738,0.323917,0.309017,0.294040,0.278991,0.263873,0.248690,0.233445,0.218143,0.202787,0.187381,0.171929,0.156434,0.140901,0.125333,0.109734,0.094108,0.078459,0.062791,0.047106,0.031411,0.015707,0.000000,-0.015707,-0.031411,-0.047106,-0.062791,-0.078459,-0.094108,-0.109734,-0.125333,-0.140901,-0.156434,-0.171929,-0.187381,-0.202787,-0.218143,-0.233445,-0.248690,-0.263873,-0.278991,-0.294040,-0.309017,-0.323917,-0.338738,-0.353475,-0.368125,-0.382683,-0.397148,-0.411514,-0.425779,-0.439939,-0.453990,-0.467930,-0.481754,-0.495459,-0.509041,-0.522499,-0.535827,-0.549023,-0.562083,-0.575005,-0.587785,-0.600420,-0.612907,-0.625243,-0.637424,-0.649448,-0.661312,-0.673013,-0.684547,-0.695913,-0.707107,-0.718126,-0.728969,-0.739631,-0.750111,-0.760406,-0.770513,-0.780430,-0.790155,-0.799685,-0.809017,-0.818150,-0.827081,-0.835807,-0.844328,-0.852640,-0.860742,-0.868632,-0.876307,-0.883766,-0.891007,-0.898028,-0.904827,-0.911403,-0.917755,-0.923880,-0.929776,-0.935444,-0.940881,-0.946085,-0.951057,-0.955793,-0.960294,-0.964557,-0.968583,-0.972370,-0.975917,-0.979223,-0.982287,-0.985109,-0.987688,-0.990024,-0.992115,-0.993961,-0.995562,-0.996917,-0.998027,-0.998890,-0.999507,-0.999877,-1.000000,-0.999877,-0.999507,-0.998890,-0.998027,-0.996917,-0.995562,-0.993961,-0.992115,-0.990024,-0.987688,-0.985109,-0.982287,-0.979223,-0.975917,-0.972370,-0.968583,-0.964557,-0.960294,-0.955793,-0.951057,-0.946085,-0.940881,-0.935444,-0.929776,-0.923880,-0.917755,-0.911403,-0.904827,-0.898028,-0.891007,-0.883766,-0.876307,-0.868632,-0.860742,-0.852640,-0.844328,-0.835807,-0.827081,-0.8181 50,-0.809017,-0.799685,-0.790155,-0.780430,-0.770513,-0.760406,-0.750111,-0.739631,-0.728969,-0.718126,-0.707107,-0.695913,-0.684547,-0.673013,-0.661312,-0.649448,-0.637424,-0.625243,-0.612907,-0.600420,-0 .587785,-0.575005,-0.562083,-0.549023,-0.535827,-0.522499,-0.509041,-0.495459,-0.481754,-0.467930,-0.453990,-0.439939,-0.425779,-0.411514,-0.397148,-0.382683,-0.368125,-0.353475,-0.338738,-0.323917,-0.3090 17,-0.294040,-0.278991,-0.263873,-0.248690,-0.233445,-0.218143,-0.202787,-0.187381,-0.171929,-0.156434,-0.140901,-0.125333,-0.109734,-0.094108,-0.078459,-0.062791,-0.047106,-0.031411,-0.015707,-0.000000,}.

[0150] BiJiao

[10] ={-1,-0.6,-0.2,0.2,0.6,1,0.6,0.2,-0.2,-0.6}

[0151] i = 0 to 399; m = i divided by 10, BiJiaoV[i] = BiJiao[m];

[0152] In step S12, the method for calling the low-frequency interrupt subroutine is as follows:

[0153] A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0 to 799, and proceed to A2.

[0154] If not, let ACDATA[i] = AVINB[i], where i = 0 to 799, and proceed to A2;

[0155] A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i], let WZ = i and startF = 1.

[0156] In S12, the method for calling the high-frequency interrupt subroutine is as follows:

[0157] B1. Determine if SELF is false. If it is, proceed to SB2.

[0158] If not, then let AVINA equal the stored value of the memory corresponding to voltage sensor 1, let AIINA equal the stored value of the memory corresponding to current sensor 2, let BVINA equal the stored value of the memory corresponding to voltage sensor 1, let BIINA equal the stored value of the memory corresponding to current sensor 2, let CVINA equal the stored value of the memory corresponding to voltage sensor 1, and let CIINA equal the stored value of the memory corresponding to current sensor 2.

[0159] AFV[CNTCNN]=(AVINA–32768) / 32768

[0160] AFI[CNTCNN]=(AIINA–32768) / 32768

[0161] BFV[CNTCNN]=(AVINA–32768) / 32768

[0162] BFI[CNTCNN]=(AIINA–32768) / 32768

[0163] CFV[CNTCNN]=(AVINA–32768) / 32768

[0164] CFI[CNTCNN]=(AIINA–32768) / 32768

[0165] Enter B3;

[0166] B2. Let AVINB be equal to the stored value of the memory corresponding to voltage sensor 1, let AIINB be equal to the stored value of the memory corresponding to current sensor 2, let BVINB be equal to the stored value of the memory corresponding to voltage sensor 1, let BIINB be equal to the stored value of the memory corresponding to current sensor 2, let CVINB be equal to the stored value of the memory corresponding to voltage sensor 1, and let CIINB be equal to the stored value of the memory corresponding to current sensor 2.

[0167] AFV[CNTCNN]=(AVINB–32768) / 32768

[0168] AFI[CNTCNN]=(AIINB–32768) / 32768

[0169] BFV[CNTCNN]=(AVINB–32768) / 32768

[0170] BFI[CNTCNN]=(AIINB–32768) / 32768

[0171] CFV[CNTCNN]=(AVINB–32768) / 32768

[0172] CFI[CNTCNN]=(AIINB–32768) / 32768

[0173] Enter B3;

[0174] B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN = 0.

[0175] Enter B4;

[0176] B4, responding to FBZ equal to 1, proceed to B5;

[0177] B5. Determine if CNTCNN is greater than WZ. If yes, let WZ1 = CNTCNN - WZ; otherwise, let WZ1 = 400 + CNTCNN - WZ.

[0178] Enter B6;

[0179] B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1.

[0180] Enter B7;

[0181] B7. Control the A-phase circuit, then proceed to B8;

[0182] B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If it is, let WZ1 = CNTCNN - WZ; if not, let WZ1 = 400 + CNTCNN - WZ.

[0183] Enter B9;

[0184] B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1;

[0185] Enter B10;

[0186] B10. Control the B-phase circuit, then proceed to B11;

[0187] B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If yes, set WZ1 = CNTCNN - WZ; otherwise, set WZ1 = 400 + CNTCNN - WZ and proceed to B12.

[0188] B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13.

[0189] B13. Control of the C-phase circuit;

[0190] The control methods for phases A, B, and C are the same, specifically as follows:

[0191] If the response is greater than or equal to 0.865, then:

[0192] Turn off the bridging switch 43, the lower right positive switch 44, and the upper right negative switch 46; turn on the upper left switch 41, the lower left switch 42, the lower right negative switch 45, and the upper right positive switch 47.

[0193] If the response is less than 0.865 and greater than or equal to 0.615:

[0194] Turn off the upper left switch 41, the upper right positive switch 47, and the lower right negative switch 45; turn on the lower left switch 42, the bridging switch 43, the lower right positive switch 44, and the upper right negative switch 46.

[0195] If the response is less than 0.615 and greater than or equal to 0.25:

[0196] Turn on the upper left switch 41, lower left switch 42 and lower right positive switch 44; turn on the bridging switch 43, lower right negative switch 45 and upper right positive switch 47;

[0197] If the response is that AVBZ[WZ1] is less than 0.25 and greater than or equal to -0.25, then:

[0198] Turn off the upper left switch 41, lower left switch 42, lower right positive switch 44 and lower right negative switch 45; turn on the bridging switch 43, upper right negative switch 46 and upper right positive switch 47.

[0199] If the response is that AVBZ[WZ1] is less than -0.25 and greater than or equal to -0.615:

[0200] Turn off the upper left switch 41, lower left switch 42, lower right negative switch 45 and upper right positive switch 47; turn on the bridging switch 43, lower right positive switch 44 and upper right negative switch 46.

[0201] If the response is that AVBZ[WZ1] is less than -0.615 and greater than or equal to -0.865:

[0202] Turn off the lower left switch 42, bridging switch 43, lower right negative switch 45 and upper right positive switch 47; turn on the upper left switch 41, lower right positive switch 44 and upper right negative switch 46.

[0203] If the response is less than -0.865:

[0204] Turn off the bridging switch 43, the lower right negative switch 45, and the upper right positive switch 47; turn on the upper left switch 41, the lower left switch 42, the lower right positive switch 44, and the upper right negative switch 46.

[0205] The specific method for calling the tripping and compensation calculation subroutine is as follows:

[0206] S21. Calculate AZK, BZK, and CZK. The methods for calculating AZK, BZK, and CZK are the same. The specific expression for calculating AZK is as follows:

[0207]

[0208]

[0209] AZK = SUMV / SUMI

[0210] WZ1 = WZ + 133

[0211] In response to whether WZ1 is greater than 400, subtract 400 from the value of WZ1;

[0212] S22. Calculate the minimum value of AZK, BZK, and CZK, and assign it to MINZK;

[0213] S23. Determine whether MINZK is less than the preset threshold ZLYZ. If yes, set TZF = 1; otherwise, set TZF = 0.

[0214] S24. Calculate AVBZ[i], BVBZ[i], and CVBZ[i] using the following formula;

[0215] AVBZ[i]=M1data[i]–AFV[i+WZ]

[0216] BVBZ[i]=M1data[i]–BFV[i+WZ1]

[0217] CVBZ[i]=M1data[i]–CFV[i+WZ1]

[0218] In the formula, i = 0 to 399;

[0219] WZ1 = WZ + 133

[0220] If WZ1 is greater than 400, then the value of WZ1 is reduced by 400.

[0221] S25. Calculate ASUMBZ, BSUMBZ, and CSUMBZ using the following formula;

[0222]

[0223] S26. Calculate the maximum value of ASUMZB, BSUMZB, and CSUMZB, assign it to MAXSUMBZ, and determine whether MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ = 1; if no, set FBZ = 0.

[0224] In step S3, the method of calling the tripping action subroutine includes the following steps:

[0225] S31. Control IGBT9 to turn on and control mechanical circuit breaker 6 to turn off;

[0226] S32, Control IGBT9 to turn off.

[0227] In the description of this invention, it should be understood that the terms "center," "thickness," "upper," "lower," "horizontal," "top," "bottom," "inner," "outer," and "radial," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying the relative importance or the number of technical features implicitly specified. Therefore, a feature defined by "first," "second," and "third" may explicitly or implicitly include one or more of that feature.

Claims

1. A low-voltage intelligent arc-free distribution circuit breaker, characterized in that, Includes voltage sensor (1), current sensor (2), left-end resistor (3), left-end inductor (4), transformer (5), mechanical circuit breaker (6), right-end resistor (7), right-end inductor (8), IGBT (9), IGBT drive circuit (10), microprocessor (11), wireless communication module (12), GPS module and converter (14). Among them, the microprocessor (11) is connected to the voltage sensor (1), the current sensor (2), the IGBT drive circuit (10), the wireless communication module (12), the GPS module and the converter (14) respectively. The voltage sensor (1) is also connected to the current sensor (2), the left end resistor (3) and the left end inductor (4) in sequence. The left end inductor (4) is also connected to the No. 1 terminal of the transformer (5), the mechanical circuit breaker (6) and the IGBT (9) respectively. The converter (14) is connected to the No. 3 and No. 4 terminals of the transformer (5). The IGBT drive circuit (10) is connected to the IGBT (9). The mechanical circuit breaker (6) is also connected to the right end inductor (8) through the right end resistor (7). The voltage sensor (1) is used to collect the three-phase voltage values ​​output by the transformer in the distribution area, the current sensor (2) is used to collect the three-phase current values ​​output by the transformer in the distribution area, the wireless communication module (12) is used to receive the control information of the circuit breaker in the distribution area, the GPS module is used to provide a clock signal to the microprocessor (11), the microprocessor (11) is used to calculate the operating status of the distribution area based on the three-phase voltage and current values ​​output by the transformer in the distribution area, the clock signal and the control information, and to control the mechanical circuit breaker (6) and the IGBT drive circuit (10) based on the calculation results, and the IGBT (9) is used to control the current; The converter (14) includes a three-phase transformer (20), a first power diode (28-1), a second power diode (28-2), a third power diode (28-3), and a voltage conversion circuit (30). The three-phase transformer (20) is provided with a primary side A-phase terminal (21), a primary side B-phase terminal (22), a primary side C-phase terminal (23), a secondary side A-phase terminal (24), a secondary side B-phase terminal (25), a secondary side C-phase terminal (26), and a secondary side neutral point (27). The voltage conversion circuit (30) is provided with a voltage conversion circuit P-pole (31) and a voltage conversion circuit N-pole (32). Among them, the primary side A phase terminal (21) is connected to the A phase of the voltage, the primary side B phase terminal (22) is connected to the B phase of the voltage, the primary side C phase terminal (23) is connected to the C phase of the voltage, the secondary side A phase terminal (24) is connected to the P pole (31) of the voltage conversion circuit through the first power diode (28-1), the secondary side B phase terminal (25) is connected to the P pole (31) of the voltage conversion circuit through the second power diode (28-2), the secondary side C phase terminal (26) is connected to the P pole (31) of the voltage conversion circuit through the third power diode (28-3), and the secondary side neutral point (27) is connected to the N pole (32) of the voltage conversion circuit. The voltage conversion circuit (30) includes an upper capacitor (35), a lower capacitor (36), an upper power diode (37), a lower power diode (38), an upper left switch (41), a lower left switch (42), a bridge switch (43), a lower right positive switch (44), a lower right negative switch (45), an upper right negative switch (46), an upper right positive switch (47), an upper left switch driver (51), a lower left switch driver (52), a bridge switch driver (53), a lower right positive switch driver (54), a lower right negative switch driver (55), an upper right negative switch driver (56), and an upper right positive switch driver (57). Among them, the upper left switch driver (51), the lower left switch driver (52), the bridge switch driver (53), the lower right positive switch driver (54), the lower right negative switch driver (55), the upper right negative switch driver (56), and the upper right positive switch driver (57) are all IGBT drive circuits. The upper left switch driver (51) is connected to the gate of the upper left switch (41), the lower left switch driver (52) is connected to the gate of the lower left switch (42), the bridge switch driver (53) is connected to the gate of the bridge switch (43), the lower right positive switch driver (54) is connected to the gate of the lower right positive switch (44), the lower right negative switch driver (55) is connected to the gate of the lower right negative switch (45), the upper right negative switch driver (56) is connected to the gate of the upper right negative switch (46), and the upper right positive switch driver (57) is connected to the gate of the upper right positive switch (47). The positive terminal of the upper power diode (37) is short-circuited to the P terminal (31) of the voltage conversion circuit and the emitter of the upper left switch (41), respectively. The negative terminal of the upper power diode (37) is short-circuited to one end of the upper capacitor (35), the emitter of the upper right negative switch (46) and the emitter of the upper right positive switch (47), respectively. The other end of the upper capacitor (35) is short-circuited to the emitter of the bridge switch (43) and the collector of the upper left switch (41); The negative terminal of the lower power diode (38) is short-circuited to the N terminal (32) of the voltage conversion circuit and the collector of the lower left switch (42), respectively. The positive terminal of the lower power diode (38) is short-circuited to one end of the lower capacitor (36), the emitter of the lower right positive switch (44), and the emitter of the lower right negative switch (45), respectively. The other end of the lower capacitor (36) is short-circuited to the collector of the bridge switch (43) and the emitter of the lower left switch (42). The emitter of the lower right positive switch (44) is short-circuited to the collector of the upper right positive switch (47) and the positive terminal (33) of the voltage conversion circuit, respectively; the collector of the upper right negative switch (46) is short-circuited to the emitter of the lower right negative switch (45) and the negative terminal (34) of the voltage conversion circuit, respectively.

2. The control method for the low-voltage intelligent arc-free circuit breaker according to claim 1, characterized in that, Includes the following steps: S1. Initialization is performed through an initialization subroutine; S2. In response to startF equaling 1, the trip and compensation calculation subroutine is called to calculate the trip criteria. S3. In response to the tripping criterion being equal to 1, the tripping action subroutine is called to perform the tripping action. S1 includes the following steps: S11. Set the low-frequency interrupt clock to 20 milliseconds and the high-frequency interrupt clock to 50 microseconds; S12. Set the low-frequency interrupt condition and set the low-frequency interrupt subroutine to be called when an interrupt occurs; Set the high-frequency interrupt conditions and configure the high-frequency interrupt subroutine to be called when an interrupt occurs; S13. Set variables, including: Phase A voltage phase zero degree millisecond counter, Phase A voltage phase zero degree microsecond counter, CH represents high frequency interrupt counter, value range: 0~999, VY represents trip voltage threshold, IY represents trip current threshold, BY represents compensation threshold, TZ represents trip mark, CVA represents sensor read counter, value range: 0~999, CZQ represents period counter, value range: 0~199, SUMV represents voltage summation, SUMI represents voltage summation; The array AVINA[400] represents the first reading value of phase A of voltage sensor (1), the array AVINB[400] represents the second reading value of phase A of voltage sensor (1), the array AFV[400] represents the floating-point value of phase A voltage, the array AIINA[400] represents the first reading value of phase A of current sensor (2), the array AIINB[400] represents the second reading value of phase A of current sensor (2), the array AFI[400] represents the floating-point value of phase A current, and the array AVBZ[400] represents phase A compensation; The array BVINA[400] represents the first reading value of phase B of voltage sensor (1), the array BVINB[400] represents the second reading value of phase B of voltage sensor (1), the array BFV[400] represents the floating point value of phase B voltage, the array BIINA[400] represents the first reading value of phase B of current sensor (2), the array BINB[400] represents the second reading value of phase B of current sensor (2), the array BFI[400] represents the floating point value of phase B current, and the array BVBZ[400] represents phase B compensation; The array CVINA[400] represents the first reading value of phase C of voltage sensor (1), the array CVINB[400] represents the second reading value of phase C of voltage sensor (1), the array CFV[400] represents the floating value of phase C voltage, the array CIINA[400] represents the first reading value of phase C of current sensor (2), the array CIINB[400] represents the second reading value of phase C of current sensor (2), the array CFI[400] represents the floating value of phase C current, and the array CVBZ[400] represents phase C compensation; PT represents the time update data position, TZF represents the trip calculation variable, FBZ represents the compensation calculation variable, FZD represents the low-frequency interruption flag, SELF represents the storage selection flag, AZK represents the A-phase impedance, BZK represents the B-phase impedance, CZK represents the C-phase impedance, MINZK represents the minimum impedance, ZKYZ represents the impedance trip threshold, BZYZ represents the compensation threshold, MAXSUMBZ represents the maximum compensation sum, ACNTVI represents the A-phase storage position counter, BCNTVI represents the B-phase storage position counter, and CCNTVI represents the C-phase storage position counter. S13. Initialize variables. The variables to be initialized are: MA=0, HA=0, UA=0, AH0=0, AU0=0, CH=0, PT=0, TZF=0, TZ=0, SELF =0, ACNTVI=0, BCNTVI=0, CCNTVI=0, CNTCNN=0, startF = 0, FZD=0, FBZ=0, XY=0, ZY=0, BY=0, CVA=0, CZQ=0, SUMV=0, SUMI=0, ZSUM=0; AVINA[800], AIINB[800], BVINA[800], BIINB[800], CVINA[800] and CIINB[800] are all initialized to all zeros; S15. Set the first parameter M1data and the comparison variable BiJiao.

3. The control method according to claim 2, characterized in that, In S12, the method for calling the low-frequency interrupt subroutine is as follows: A1. Determine if SELF is false. If it is, let ACDATA[i] = AVINA[i], where i = 0~799, and proceed to A2. If not, let ACDATA[i] = AVINB[i], where i = 0~799, and proceed to A2; A2. Invert SELF. In response to the condition that AVINA[i-2] is less than or equal to 0, AVINA[i-2] is less than or equal to AVINA[i], AVINA[i+2] is greater than or equal to zero and AVINA[i+2] is greater than or equal to AVINA[i] in the range of i=2~401, let WZ=i and startF = 1.

4. The control method according to claim 3, characterized in that, In S12, the method for calling the high-frequency interrupt subroutine is as follows: B1. Determine if SELF is false. If it is, proceed to SB2. If not, then let AVINA equal the stored value of the memory corresponding to voltage sensor (1), let AIINA equal the stored value of the memory corresponding to current sensor (2), let BVINA equal the stored value of the memory corresponding to voltage sensor (1), let BIINA equal the stored value of the memory corresponding to current sensor (2), let CVINA equal the stored value of the memory corresponding to voltage sensor (1), and let CIINA equal the stored value of the memory corresponding to current sensor (2). AFV[CNTCNN] = (AVINA–32768) / 32768 AFI [CNTCNN] = (AIINA–32768) / 32768 BFV[CNTCNN] = (AVINA–32768) / 32768 BFI [CNTCNN] = (AIINA–32768) / 32768 CFV[CNTCNN] =(AVINA–32768) / 32768 CFI [CNTCNN] = (AIINA–32768) / 32768 Enter B3; B2. Let AVINB equal the stored value of the memory corresponding to voltage sensor (1), let AIINB equal the stored value of the memory corresponding to current sensor (2), let BVINB equal the stored value of the memory corresponding to voltage sensor (1), let BIINB equal the stored value of the memory corresponding to current sensor (2), let CVINB equal the stored value of the memory corresponding to current sensor (2), let CIINB equal the stored value of the memory corresponding to current sensor (2). AFV[CNTCNN] = (AVINB–32768) / 32768 AFI [CNTCNN] = (AIINB–32768) / 32768 BFV[CNTCNN] = (AVINB–32768) / 32768 BFI [CNTCNN] = (AIINB–32768) / 32768 CFV[CNTCNN] = (AVINB–32768) / 32768 CFI [CNTCNN] = (AIINB–32768) / 32768 Enter B3; B3. Increment the value of CNTCNN by 1. In response to CNTCNN being greater than 800, set CNTCNN=0. Enter B4; B4, responding to FBZ equal to 1, proceed to B5; B5. Determine if CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then let WZ1 = 400 + CNTCNN-WZ; Enter B6; B6. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1. Enter B7; B7. Control the A-phase circuit, then proceed to B8; B8. Add 133 to the WZ value and determine whether CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then let WZ1 = 400 + CNTCNN - WZ; Enter B9; B9. In response to WZ1 being greater than 400, subtract 400 from the value of WZ1; Enter B10; B10. Control the B-phase circuit, then proceed to B11; B11. Add 266 to the WZ value and determine whether CNTCNN is greater than WZ. If so, let WZ1 = CNTCNN - WZ. If not, then set WZ1 = 400 + CNTCNN - WZ and proceed to B12; B12. In response to WZ1 being greater than 400, the value of WZ1 is reduced by 400, and then proceed to B13. B13. Control of the C-phase circuit; The control methods for phases A, B, and C are the same, specifically as follows: If the response is greater than or equal to 0.865, then: Turn off the bridging switch (43), the lower right positive switch (44), and the upper right negative switch (46); turn on the upper left switch (41), the lower left switch (42), the lower right negative switch (45), and the upper right positive switch (47); If the response is less than 0.865 and greater than or equal to 0.615: Turn off the upper left switch (41), the upper right positive switch (47), and the lower right negative switch (45); turn on the lower left switch (42), the bridging switch (43), the lower right positive switch (44), and the upper right negative switch (46); If the response is less than 0.615 and greater than or equal to 0.25, then: Turn on the upper left switch (41), lower left switch (42), and lower right positive switch (44); turn on the bridging switch (43), lower right negative switch (45), and upper right positive switch (47); If the response is less than 0.25 and greater than or equal to -0.25: Turn off the upper left switch (41), lower left switch (42), lower right positive switch (44), and lower right negative switch (45); turn on the bridging switch (43), upper right negative switch (46), and upper right positive switch (47); If the response is less than -0.25 and greater than or equal to -0.615: Turn off the upper left switch (41), lower left switch (42), lower right negative switch (45), and upper right positive switch (47); turn on the bridging switch (43), lower right positive switch (44), and upper right negative switch (46); If the response is less than -0.615 and greater than or equal to -0.865, then: Turn off the lower left switch (42), bridge switch (43), lower right negative switch (45) and upper right positive switch (47); turn on the upper left switch (41), lower right positive switch (44) and upper right negative switch (46); If the response to AVBZ[WZ1] is less than -0.865: Turn off the bridging switch (43), the lower right negative switch (45), and the upper right positive switch (47); turn on the upper left switch (41), the lower left switch (42), the lower right positive switch (44), and the upper right negative switch (46).

5. The control method according to claim 4, characterized in that, In S2, the method for calling the tripping and compensation calculation subroutine is as follows: S21. Calculate AZK, BZK, and CZK. The methods for calculating AZK, BZK, and CZK are the same. The specific expression for calculating AZK is as follows: AZK = SUMV / SUMI WZ1=WZ+133 In response to whether WZ1 is greater than 400, subtract 400 from the value of WZ1; S22. Calculate the minimum value of AZK, BZK, and CZK, and assign it to MINZK; S23. Determine whether MINZK is less than the preset threshold ZLYZ. If yes, set TZF=1; otherwise, set TZF=0. S24. Calculate AVBZ[i], BVBZ[i], and CVBZ[i] using the following formula; AVBZ[i]= M1data[i] – AFV[i+WZ] BVBZ[i]= M1data[i] – BFV[i+WZ1] CVBZ[i]= M1data[i] – CFV[i+WZ1] In the formula, i = 0~399; WZ1=WZ+133 If WZ1 is greater than 400, then the value of WZ1 is reduced by 400. S25. Calculate ASUMBZ, BSUMBZ, and CSUMBZ using the following formula; S26. Calculate the maximum value of ASUMZB, BSUMZB and CSUMZB, assign it to MAXSUMBZ, and determine whether MAXSUMBZ is greater than or equal to BZYZ; if yes, set FBZ=1; if no, set FBZ=0.

6. The control method according to claim 5, characterized in that, In step S3, the method of calling the tripping action subroutine includes the following steps: S31. Control the IGBT (9) to turn on and control the mechanical circuit breaker (6) to turn off; S32, control IGBT (9) to turn off.

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