Semiconductor device manufacturing method and semiconductor device

Abstract

The present invention provides a method for preparing a semiconductor device and a semiconductor device, and relates to the technical field of semiconductor device preparation. The method for preparing a semiconductor device comprises: forming a first epitaxial layer on a substrate; forming a first alignment mark on the first epitaxial layer by a marking mask; aligning the device mask with an exposure unit by using the first alignment mark, and forming a preset structure on the first epitaxial layer in the exposure unit by using the device mask; forming a second epitaxial layer on the first epitaxial layer; forming a second alignment mark on the second epitaxial layer by using the same marking mask, and the second alignment mark and the first alignment mark are spaced by an integer multiple of the device unit; after aligning the alignment mark pattern on the device mask with the second alignment mark, driving the device mask to move an integer multiple of the device unit, and forming a preset structure on the second epitaxial layer in the exposure unit by using the device mask. The present application only requires one marking mask, which reduces the number of marking masks.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a semiconductor device preparation method and a semiconductor device. Background Art

[0002] With the advancement of science and technology, the demand for semiconductor devices is also increasing. Some semiconductor device manufacturing processes require multi-layer preparation to finally produce finished semiconductor devices. In the multi-layer preparation process, the semiconductor structures formed in different wafer layers need to be aligned through alignment marks.

[0003] In order to prevent the alignment marks of the previous layer at the same position from interfering with the reflected light of the alignment marks of the current layer under the alignment light, thereby affecting the alignment accuracy between different wafer layers, alignment marks need to be formed at different positions of each wafer layer during the current manufacturing process, and accordingly, a corresponding alignment mask needs to be designed for each wafer layer, which greatly increases the manufacturing cost of multi-layer semiconductor devices.

[0004] In view of this, a method for preparing a semiconductor device is needed, which can reduce the cost of producing a semiconductor device by a multi-layer layer-by-layer preparation process. Summary of the invention

[0005] In view of the above shortcomings of the prior art, the present invention provides a method for preparing a semiconductor device to improve the technical problem that in the existing semiconductor device multi-layer layer-by-layer preparation process, a corresponding alignment mask needs to be designed for each wafer layer, resulting in a high process cost.

[0006] To achieve the above object and other related objects, the present invention provides a method for preparing a semiconductor device, which at least comprises the following steps:

[0007] forming a first epitaxial layer on a substrate;

[0008] Providing a marking mask plate, and forming a first alignment mark on the first epitaxial layer through the marking mask plate, wherein the first alignment mark is located in a preset exposure unit;

[0009] Providing a device mask, aligning the device mask with the exposure unit using the first alignment mark, and forming a preset structure on the first epitaxial layer in the exposure unit through the device mask;

[0010] forming a second epitaxial layer on the first epitaxial layer;

[0011] Using the same mark mask to form a second alignment mark on the second epitaxial layer, the second alignment mark is located in the exposure unit, and the second alignment mark is spaced from the first alignment mark by an integer multiple of the device unit;

[0012] After aligning the alignment mark pattern on the device mask with the second alignment mark, the device mask is driven to move an integer multiple of the device unit to align the device mask with the exposure unit, and a preset structure is formed on the second epitaxial layer in the exposure unit through the device mask.

[0013] In one embodiment of the present invention, the exposure unit includes a chip area and a cutting path, and the cutting path is arranged at the periphery of the chip area.

[0014] In one embodiment of the present invention, the first alignment mark and the second alignment mark are located in two parallel cutting lanes in the exposure unit.

[0015] In one embodiment of the present invention, it also includes: forming a third epitaxial layer on the second epitaxial layer, and then forming a preset structure on the third epitaxial layer, until a preset number of epitaxial layers are formed on the substrate, and the preset structure is formed in the preset number of epitaxial layers.

[0016] In one embodiment of the present invention, adjacent alignment marks do not overlap each other in the depth direction, and projections of adjacent alignment marks on the substrate have the same spacing in the horizontal direction.

[0017] In one embodiment of the present invention, the device mask is aligned with the exposure unit using the first alignment mark, and a preset structure is formed on the first epitaxial layer in the exposure unit through the device mask, including: forming a photoresist layer on the first epitaxial layer; aligning the alignment mark pattern on the device mask with the first alignment mark to align the device mask with the exposure unit; using the injection area pattern on the device mask to expose the photoresist layer to form an injection window; using the photoresist layer outside the injection window as a mask, injecting impurity ions into the first epitaxial layer exposed by the injection window to form a preset structure in the first epitaxial layer.

[0018] In one embodiment of the present invention, a second alignment mark is formed on the second epitaxial layer using the same marking mask plate, the second alignment mark is located in the exposure unit, and the second alignment mark is spaced apart from the first alignment mark by an integer multiple of the device unit, including: coating a photoresist layer on the second epitaxial layer; after aligning the alignment mark pattern on the same marking mask plate with the first alignment mark, driving the marking mask plate to move a distance that is an integer multiple of the device unit; and forming a second alignment mark on the second epitaxial layer using the moved marking mask plate.

[0019] In one embodiment of the present invention, after aligning the alignment mark pattern on the device mask plate with the second alignment mark, driving the device mask plate to move a distance that is an integer multiple of the device unit so that the device mask plate is aligned with the exposure unit, and forming a preset structure on the second epitaxial layer in the exposure unit through the device mask plate includes: forming a photoresist layer on the second epitaxial layer; aligning the alignment mark pattern on the device mask plate with the second alignment mark; driving the device mask plate to move a distance that is an integer multiple of the device unit so that the device mask plate is aligned with the exposure unit; using the injection area pattern on the device mask plate, exposing to form an injection window on the photoresist layer; using the photoresist layer outside the injection window as a mask, injecting impurity ions into the second epitaxial layer exposed by the injection window to form a preset structure in the second epitaxial layer.

[0020] In one embodiment of the present invention, the first epitaxial layer and the second epitaxial layer are N-type epitaxial layers, and the impurity ions are P-type impurity ions.

[0021] The present invention also provides a semiconductor device, which is prepared by using any one of the preparation methods described above.

[0022] In combination with the prior art, the beneficial effects of the present invention are:

[0023] In the process of preparing semiconductor devices with multiple layers prepared layer by layer, one or more groups of alignment marks need to be generated on each epitaxial layer for interlayer alignment. In order to ensure that the alignment marks between layers do not overlap, each epitaxial layer needs to use a different marking mask. In the method of the present application, a first alignment mark is generated on the first epitaxial layer by a marking mask. When a second alignment mark needs to be generated on the second epitaxial layer, the marking mask is moved by an integer multiple of the device unit size, so that the second alignment mark is generated on the second epitaxial layer using the same marking mask; when the device mask needs to be aligned, the device mask is aligned with the second alignment mark, and then the marking mask is moved in the opposite direction of the moving direction by the same distance as the marking mask, so as to achieve alignment of the device mask between the epitaxial layers and form a preset structure at the same position of the epitaxial layer. The method of the present application only requires one marking mask, which effectively reduces the number of marking masks and effectively reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a flow chart of a method for preparing a semiconductor device in one embodiment of the present application;

[0026] Figure 2 This is a flowchart of step S130 in an embodiment of the present application;

[0027] Figure 3 This is a flowchart of step S150 in an embodiment of the present application;

[0028] Figure 4 This is a flow chart of step S160 in one embodiment of the present application;

[0029] Figure 5 This is a schematic diagram of the first epitaxial layer after formation in one embodiment of the present application;

[0030] Figure 6 This is a schematic diagram of a first alignment mark after it is formed in one embodiment of the present application;

[0031] Figure 7 A schematic diagram of a preset structure in an embodiment of the present application;

[0032] Figure 8 This is a schematic diagram of forming a second epitaxial layer in one embodiment of the present application;

[0033] Fig. 9 A schematic diagram of generating and forming a second alignment mark in an embodiment of the present application;

[0034] Fig.10 A schematic diagram of forming a preset structure on the second epitaxial layer in one embodiment of the present application;

[0035] Fig.11 This is a schematic diagram of a multi-layer epitaxial layer after being generated in one embodiment of the present application;

[0036] Fig.12 This is a schematic diagram of a wafer in an embodiment of the present application;

[0037] Fig.13 Schematic diagram of an exposure unit in one embodiment of the present application.

[0038] Component number description

[0039] 100, substrate; 210, first epitaxial layer; 211, first alignment mark; 220, second epitaxial layer; 221, second alignment mark; 230, third epitaxial layer; 231, third alignment mark; 240, photoresist layer; 270, seventh epitaxial layer; 271, seventh alignment mark; 280, injection window; 290, preset structure; 300, exposure unit; 310, chip area; 320, cutting path. DETAILED DESCRIPTION

[0040] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the features in the following embodiments and the embodiments can be combined with each other without conflict. It should also be understood that the terms used in the embodiments of the present invention are intended to describe specific embodiments, rather than to limit the scope of protection of the present invention. The test methods for which specific conditions are not specified in the following examples are usually carried out under conventional conditions or according to the conditions recommended by the manufacturers.

[0041] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise specified in the present invention, both endpoints of each numerical range and any value between the two endpoints can be selected. Unless otherwise defined, all technical and scientific terms used in the present invention are familiar to those skilled in the art and the description of the present invention, and any methods, equipment and materials of the prior art similar or equivalent to the methods, equipment and materials described in the embodiments of the present invention can also be used to implement the present invention.

[0042] It should be noted that the terms such as "upper", "lower", "left", "right", "middle" and "one" etc. used in this specification are only for the convenience of description and are not intended to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships, without substantially changing the technical content, should also be regarded as the scope of implementation of the present invention.

[0043] In the existing multi-layer semiconductor device preparation process, one or more groups of alignment marks need to be generated on each epitaxial layer for interlayer alignment. In order to ensure that the alignment marks between layers do not interfere with each other under the alignment light, the alignment marks on each epitaxial layer need to be set at different positions. Accordingly, different marking masks need to be designed and used for each epitaxial layer to form alignment marks.

[0044] Taking super junction power devices as an example, with the development of new energy vehicles, the demand for super junction MOSFET (Super Junction>200V) used in high voltage fields is also increasing. Super junction is a groove structure with N-type and P-type vertically alternating in the epitaxial layer. After applying voltage, a depletion layer equivalent to the depth of the groove can be formed, and the diffusion path of this depletion layer is much smaller than that of general planar MOSFET, so it can effectively reduce the on-resistance (Rdson) of the device. At present, super junctions in the industry mostly use planar Multi-EPI (multi-layer epitaxial stacking) to prepare super junction structures.

[0045] The Multi-EPI process was developed the earliest and is relatively mature. The main method is: using multi-layer epitaxial growth technology on a planar silicon substrate, multiple doping and thermal advancement, that is, taking "growth-ion implantation-annealing" as a layer of steps, repeating multiple times to form multiple PN junctions, thereby realizing the structure of super junction MOS. Its advantages are relatively uniform concentrations of P and N ions, ultra-low on-resistance and junction capacitance, high efficiency, low heat generation, and can adapt to higher switching frequencies. Therefore, it has great advantages in leakage, high temperature and long-term reliability. However, after each epitaxial layer is grown, ion implantation is required. In order to ensure that the inter-layer ion implantation can be aligned, the device mask plate needs to be aligned before each ion implantation. The device mask plate can be aligned through the alignment mark on the epitaxial layer. In order to improve the accuracy of the alignment mark, the alignment marks between different layers are staggered. On the one hand, it prevents interference between the alignment marks, and on the other hand, it can ensure that the alignment mark shape is regular and easy to identify. In the prior art, the mask plate for forming the alignment mark of each layer of the multi-layer epitaxial stacking technology is different, that is, each epitaxial layer requires a marking mask plate, which requires a higher cost. In view of this, the present application provides a method for preparing a semiconductor device, which can effectively reduce the number of marking masks required in the preparation process, thereby reducing the preparation cost.

[0046] See also Figure 1 , Figure 1 A flowchart of a method for preparing a semiconductor device in an embodiment of the present application. This embodiment takes a MOSFET chip as an example to illustrate the implementation method. The preparation method may include the following steps:

[0047] Step S110, forming a first epitaxial layer 210 on the substrate 100;

[0048] Step S120, providing a marking mask plate, and forming a first alignment mark 211 on the first epitaxial layer 210 through the marking mask plate, wherein the first alignment mark 211 is located in a preset exposure unit 300;

[0049] Step S130, providing a device mask, aligning the device mask with the exposure unit 300 using the first alignment mark 211, and forming a preset structure 290 on the first epitaxial layer 210 in the exposure unit 300 through the device mask;

[0050] Step S140, forming a second epitaxial layer 220 on the first epitaxial layer 210;

[0051] Step S150, using the same marking mask to form a second alignment mark 221 on the second epitaxial layer 220, wherein the second alignment mark 221 is located in the exposure unit 300, and the second alignment mark 221 is spaced from the first alignment mark 211 by an integer multiple of a device unit.

[0052] Step S160, after aligning the alignment mark pattern on the device mask plate with the second alignment mark 221, drive the device mask plate to move an integer multiple of the device unit distance to align the device mask plate with the second alignment mark 221 and then move the device mask plate an integer multiple of the device unit distance to align the device mask plate with the exposure unit 300, and use the device mask plate to form a preset structure 290 on the second epitaxial layer 220 in the exposure unit 300.

[0053] See also Figures 5 to 13 , Figures 5 to 13 Schematic diagram of each step of an exemplary method for preparing a semiconductor device provided in an embodiment of the present application. The semiconductor device adopts a multi-layer epitaxial stacking process. It should be noted that: Figures 5 to 13 The edge lines of the chip area 310 and the cutting road 320 in FIG. 3 are drawn for example to facilitate identification. In the actual preparation process, the chip area 310 and the cutting road 320 on the epitaxial layer are not provided with edge lines. Figures 5 to 11 The method for preparing the semiconductor device provided in the embodiment of the present application is described in detail:

[0054] Step S110, forming a first epitaxial layer 210 on the substrate 100, may include: Figures 5 to 11 The substrate 100 shown, the material of the substrate 100 includes various semiconductor elements, such as silicon or silicon germanium in single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials, such as silicon carbide, gallium nitride, gallium trioxide, alloy semiconductor or a combination thereof, which is not limited here. The substrate 100 in this embodiment is a doped substrate 100. The substrate 100 in this embodiment preferably adopts a silicon carbide substrate 100, and an N-type or P-type silicon carbide substrate 100 can be adopted. In this embodiment, the doped N-type substrate 100 is used as an example for explanation. The epitaxial layer material includes silicon, silicon carbide, gallium nitride or gallium trioxide, which is not limited. In this embodiment, silicon carbide is preferably used. The substrate 100 may have a device surface and a back surface. A circuit layer may be formed on the device surface, and the back surface may be set as the surface opposite to the device surface in the substrate 100. In this embodiment, the first epitaxial layer 210 is formed on the surface of the silicon carbide substrate 100 with a specified thickness based on a planar silicon epitaxial growth process, and the first epitaxial layer 210 is an N-type epitaxial layer.

[0055] Step S120: providing a marking mask plate, and forming a first alignment mark 211 on the first epitaxial layer 210 through the marking mask plate, wherein the first alignment mark 211 is located in the preset exposure unit 300. Fig.13The exposure unit 300 includes a plurality of chip regions 310 and scribe lines 320. The chip region 310 is a region reserved for forming a device structure in the exposure unit 300, and the scribe lines 320 are located outside the chip region 310. In the exposure unit 300, each chip region 310 is surrounded by a plurality of scribe lines 320. The scribe lines 320 are used to assist wafer dicing positioning after the semiconductor device manufacturing process, so as to separate the semiconductor devices on the wafer from each other after the dicing process.

[0056] See also Figure 6 In step S120, the alignment mark pattern in the marking mask is transferred to the first epitaxial layer 210 by conventional photolithography means to form a first alignment mark 211 on the first epitaxial layer 210. Specifically, a photoresist is coated on the first epitaxial layer 210 to form a photoresist layer 240 on the first epitaxial layer 210, and then the photoresist layer 240 is exposed and developed using the marking mask to form an etching window with an alignment mark pattern on the photoresist layer. The patterned photoresist layer 240 is used as a mask, and an etching process, such as reactive ion etching (RIE), is used to etch the first epitaxial layer 210 exposed by the window. After etching, the photoresist is removed by conventional ashing or stripping processes, so that the first alignment mark 211 is formed on the first epitaxial layer 210. The first alignment mark 211 is used to assist the alignment of the device mask and the exposure unit 300. The shapes of the first alignment mark 211 include rectangle, strip, Y, X, cross, U-shaped, field, mouth, discontinuous U-shaped, etc. The first alignment mark 211 can select one of the shapes or a combination of multiple shapes. In some embodiments, the marking mask can include multiple first alignment mark 211 patterns, so as to form multiple first alignment marks 211 on the first epitaxial layer 210.

[0057] In one embodiment of the present invention, the first alignment mark 211 is located in the scribe line 320. The first alignment mark 211 located in the scribe line 320 will not affect the chip region 310 including the main circuit and functional parts, thereby reducing material loss.

[0058] Step S130, providing a device mask; in the process of photolithography scanning of the wafer, using the first alignment mark 211 to align the device mask with the exposure unit 300, and forming a preset structure 290 on the first epitaxial layer 210 in the exposure unit 300 through the device mask. The first alignment mark 211 is used for alignment between layers to ensure the accuracy of ion implantation and the consistency of ion implantation positions between layers.

[0059] See also Figure 2 , Figure 2 This is a flow chart of step S130 in an embodiment of the present application, and the specific steps are as follows:

[0060] Step S210, forming a photoresist layer 240 on the first epitaxial layer 210;

[0061] A photoresist layer 240 is coated on the first epitaxial layer 210 .

[0062] Step S220 , aligning the alignment mark pattern on the device mask with the first alignment mark 211 , so as to align the device mask with the exposure unit 300 .

[0063] In step S220, the reflected light of the first alignment mark 211 under the alignment light matches the alignment mark pattern on the device mask to confirm that the device mask is aligned with the exposure unit 300. When the device mask is aligned with the exposure unit 300, the device area pattern on the device mask is aligned with the chip area 310 in the exposure unit 300.

[0064] Step S230 , using the implantation region pattern on the device mask as a reference, and using photolithography to expose the photoresist layer 240 to form an implantation window 280 .

[0065] The photoresist layer 240 can be a positive photoresist or a negative photoresist. In one example, a positive photoresist is selected to form the photoresist layer 240, and the device mask is set above the photoresist layer 240. The first epitaxial layer 210 coated with the photoresist layer 240 is exposed to light. After the photoresist layer 240 is exposed to light, its characteristics change, and the photosensitive part of the positive photoresist becomes easy to dissolve. Then the first epitaxial layer 210 is developed, and the positive photoresist is dissolved after development, leaving only the unexposed part, thereby forming an injection window 280 on the exposed photoresist layer 240. If a negative photoresist is used, the exposed part will become difficult to dissolve, and after development, the exposed part will remain.

[0066] Step S240 , using the photoresist layer 240 outside the injection window 280 as a mask, and utilizing an ion implantation process to implant impurity ions into the first epitaxial layer 210 exposed by the injection window 280 , so as to form a preset structure 290 in the first epitaxial layer 210 .

[0067] For example, the first epitaxial layer 210 is an N-type epitaxial layer, and P-type impurity ions are implanted by impurity ion implantation to form a P-type region, and the P-type region and the N-type region are alternately arranged to form a super junction structure. The P-type impurity ions may be boron (B), aluminum (Al), gallium (Ga), or indium (In), etc.

[0068] Please continue reading Figure 1 , step S140 , forming a second epitaxial layer 220 on the first epitaxial layer 210 .

[0069] In step S140, any suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc. can be used to form a second epitaxial layer 220 that is identical to the first epitaxial layer 210 on the first epitaxial layer 210, and the second epitaxial layer 220 and the first epitaxial layer 210 form a whole.

[0070] Step S150: using the same marking mask to form a second alignment mark 221 on the second epitaxial layer 220; the second alignment mark 221 is located in the exposure unit 300 where the first alignment mark 211 is located; and the second alignment mark 221 is spaced from the first alignment mark 211 by an integer multiple of the device unit distance.

[0071] The second alignment mark 221 for interlayer alignment is formed on the second epitaxial layer 220 using the same marking mask, and the second alignment mark 221 is used to assist the device mask in aligning with the exposure area on the second epitaxial layer 220. It should be noted that the device unit size includes the sum of the sizes of the chip area 310 and the cutting road 320 on one side of the chip area 310 in a horizontal direction. For example, when the marking mask is moved by a distance of one device unit compared with the first alignment mark 211, the sum of the sizes of the chip area 310 and the cutting road 320 on one side in the horizontal direction is moved, and then the second alignment mark 221 formed on the second epitaxial layer 220 using the marking mask is still in the cutting road 320, and will not affect the chip area containing the main circuit and functional parts.

[0072] See also Figure 3 , Figure 3 This is a flow chart of step S150 in an embodiment of the present application, and the specific steps are as follows:

[0073] Step S310, coating a photoresist layer 240 on the second epitaxial layer 220;

[0074] Step S320, after aligning the alignment mark pattern on the same mark mask with the first alignment mark 211, driving the mark mask to move by an integer multiple of the device unit distance;

[0075] By moving the marking mask plate by an integer multiple of the device unit distance, the distance between the second alignment mark 221 and the first alignment mark 211 in the horizontal direction can be effectively controlled, so that alignment marks can be formed at different positions of the epitaxial layer through a marking mask plate, thereby meeting the need to form alignment marks between different epitaxial layers and meeting the alignment requirements between epitaxial layers.

[0076] Step S330: Use the moved mark mask to form a second alignment mark 221 on the second epitaxial layer 220. The first alignment mark 211 and the second alignment mark 221 are spaced apart by an integer multiple of the device unit in the horizontal direction and do not overlap in the depth direction.

[0077] Exemplarily, the first alignment mark 211 and the second alignment mark 221 are located in two parallel cutting streets 320 in the exposure unit 300 .

[0078] The first alignment mark 211 is located in the cutting road 320, and the marking mask is moved by an integer multiple of the device unit when forming the first alignment mark 211. Then, the second alignment mark 221 is still formed in the cutting road 320, and the second alignment mark 221 and the first alignment mark 211 are in parallel cutting roads 320. At the same time, it also ensures that the second alignment mark 221 does not overlap with the first alignment mark 211 in the depth direction, thereby avoiding the first alignment mark 211 from affecting the second alignment mark 221.

[0079] Please continue reading Figure 1 , step S160, after aligning the alignment mark pattern on the device mask plate with the second alignment mark 221, drive the device mask plate to move in the horizontal direction along the second alignment mark 221 toward the first alignment mark 211 by an integer multiple of the device unit distance, so that the device mask plate is aligned with the exposure unit 300, and a preset structure 290 is formed on the second epitaxial layer 220 in the exposure unit 300 through the device mask plate.

[0080] After the device mask is aligned with the second alignment mark 221, the device mask is moved in the opposite direction of the moving direction of the mark mask by a distance equal to the moving distance of the mark mask, that is, it is moved in the horizontal direction along the second alignment mark 221 toward the first alignment mark 211, and the moving distance is the horizontal distance between the second alignment mark 221 and the first alignment mark 211, thereby realizing the vertical alignment of the device mask and the first alignment mark 211, and also aligning the device mask with the exposure unit 300, and the preset structure 290 formed on the second epitaxial layer 220 by the device mask is consistent with the preset structure 290 formed on the first epitaxial layer 210, so that the impurity ions injected or diffused at the preset structure 290 are connected to form an integral area.

[0081] See also Figure 4 , Figure 4 This is a flow chart of step S160 in an embodiment of the present application, and the specific steps are as follows:

[0082] Step S410, forming a photoresist layer 240 on the second epitaxial layer 220;

[0083] Step S420, aligning the alignment mark pattern on the device mask with the second alignment mark 221;

[0084] Step S430, driving the device mask to move horizontally along the second alignment mark 221 toward the first alignment mark 211 by an integer multiple of the device unit distance, so that the device mask is aligned with the exposure unit 300;

[0085] The moving direction of the device mask is opposite to that of the marking mask. After the marking mask moves an integer multiple of the device unit, a second alignment mark 221 having a certain distance from the first alignment mark 211 in the horizontal direction is formed. After the device mask is aligned with the second alignment mark 221, it moves in the opposite direction of the moving direction of the marking mask by a distance equal to the moving distance of the marking mask, so that the device mask reaches the position aligned with the first alignment mark 211, so that the device mask is aligned with the exposure unit 300.

[0086] Step S440, using the implantation region pattern on the device mask as a reference, using conventional photolithography means, exposing the photoresist layer 240 to form an implantation window 280;

[0087] Step S450 , using the photoresist layer 240 outside the implantation window 280 as a mask, and utilizing an ion implantation process to implant impurity ions into the second epitaxial layer 220 exposed by the implantation window 280 , so as to form a preset structure 290 in the second epitaxial layer 220 .

[0088] The preset structure 290 formed on the second epitaxial layer 220 and the preset structure 290 formed on the first epitaxial layer 210 are at the same position in the vertical direction, and thus the preset structure 290 of the second epitaxial layer 220 and the preset structure 290 on the first epitaxial layer 210 are connected as a whole.

[0089] Furthermore, adjacent alignment marks do not overlap in the depth direction, and the projections of adjacent alignment marks on the substrate 100 have the same spacing in the horizontal direction, thereby facilitating the device mask to return to the first exposure position after alignment with the alignment marks, thereby ensuring the alignment of the preset structure 290 between the epitaxial layers.

[0090] In one embodiment of the present invention, the method for preparing a semiconductor device also includes forming a third epitaxial layer 230 on the second epitaxial layer 220, and then forming a preset structure 290 on the third epitaxial layer 230, until a preset number of epitaxial layers are formed on the substrate 100, and the preset structure 290 is formed in the preset number of epitaxial layers, thereby meeting the preparation of semiconductor devices with multi-layer epitaxial layer structures, such as a multi-layer epitaxial process for super junction power devices.

[0091] See also Figure 5 to Figure 11 In one embodiment of the present invention, the semiconductor device has 7 epitaxial layers, and the preparation method includes: forming 7 epitaxial layers on the substrate 100, and forming the preset structure 290 in each of the 7 epitaxial layers.

[0092] After the second epitaxial layer 220 forms the preset structure 290 , the P-type impurity ions on the second epitaxial layer 220 and the P-type impurity ions on the first epitaxial layer 210 form an overall columnar structure, thereby forming a super junction PN junction.

[0093] The third epitaxial layer 230 is generated on the second epitaxial layer 220. On the basis of forming the second alignment mark 221, the marking mask is moved in the same direction by an integer multiple of the device unit, and the third alignment mark 231 is formed on the third epitaxial layer 230 by using the moved marking mask. Further, the distance moved by the marking mask when forming the third alignment mark 231 is equal to the distance moved when forming the second alignment mark 221, that is, the horizontal distance between the first alignment mark 211 and the second alignment mark 221 is the same as the horizontal distance between the second alignment mark 221 and the third alignment mark 231, for example, both are the distance of one device unit in the horizontal direction, which makes it more convenient for the device mask to perform alignment between layers.

[0094] The device mask is aligned with the third alignment mark 231, and then the device mask is moved in the reverse direction of the movement direction of the mark mask by the total distance of the mark mask movement. In other words, after the device mask is aligned with the third alignment mark 231, the third alignment mark 231 is moved in the horizontal direction from the third alignment mark 231 to the first alignment mark 211 by the same distance as the spacing between the first alignment mark 211. Using the device mask, taking the implantation region pattern on the device mask as a reference, an implantation window 280 is formed on the third epitaxial layer 230 by photolithography, and impurity ions are implanted into the second epitaxial layer 220 exposed by the implantation window 280 by an ion implantation process, so as to form a preset structure 290 on the third epitaxial layer 230. The preset structure 290 formed on the third epitaxial layer 230 is in the same position as the preset structure 290 formed on the second epitaxial layer 220 and the preset structure 290 formed on the first epitaxial layer 210. The P-type regions on the third epitaxial layer 230, the second epitaxial layer 220 and the first epitaxial layer 210 are connected to form a super junction PN junction with the N-type epitaxial layer.

[0095] The above steps are repeated until the seventh epitaxial layer 270 is formed, and a seventh alignment mark 271 and a preset structure 290 are formed on the seventh epitaxial layer 270 .

[0096] After all epitaxial layers are formed and impurity ions are implanted, annealing is performed to repair the lattice damage caused by ion implantation and to activate the implanted impurity ions so that they occupy the correct position in the silicon lattice and form the required electrical activity.

[0097] In the preparation of the semiconductor device of the present application, other processes are also required. Please refer to the prior art and the present application will not elaborate on this.

[0098] The semiconductor device manufacturing method of the present invention can generate alignment marks on multiple epitaxial layers respectively using only one marking mask plate. Compared with the existing method of designing a different marking mask plate for each epitaxial layer, it effectively reduces costs and improves competitiveness.

[0099] The present application also provides a semiconductor device manufactured using any of the preparation methods described above. For other processes required for the preparation of the semiconductor device, please refer to the existing preparation technology of the semiconductor device, and this application will not go into details.

[0100] The semiconductor device preparation method of the present invention only needs to use one marking mask plate to form alignment marks for each epitaxial layer in the multi-layer epitaxial stacking process, which effectively reduces the number of marking masks and reduces costs. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and use significance. The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a first epitaxial layer on a substrate; Providing a marking mask plate, and forming a first alignment mark on the first epitaxial layer through the marking mask plate, wherein the first alignment mark is located in a preset exposure unit; Providing a device mask, aligning the device mask with the exposure unit using the first alignment mark, and forming a preset structure on the first epitaxial layer in the exposure unit through the device mask; forming a second epitaxial layer on the first epitaxial layer; Using the same mark mask to form a second alignment mark on the second epitaxial layer, the second alignment mark is located in the exposure unit, and the second alignment mark is spaced from the first alignment mark by an integer multiple of the device unit; After aligning the alignment mark pattern on the device mask with the second alignment mark, the device mask is driven to move an integer multiple of the device unit to align the device mask with the exposure unit, and a preset structure is formed on the second epitaxial layer in the exposure unit through the device mask.

2. The method for preparing a semiconductor device according to claim 1, characterized in that: The exposure unit includes a chip area and a cutting path, and the cutting path is arranged at the periphery of the chip area.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The first alignment mark and the second alignment mark are located in two parallel cutting lanes in the exposure unit.

4. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: A third epitaxial layer is formed on the second epitaxial layer, and then a preset structure is formed on the third epitaxial layer, until a preset number of epitaxial layers are formed on the substrate, and the preset structure is formed in the preset number of epitaxial layers.

5. The method for preparing a semiconductor device according to claim 1 or 3, characterized in that: Adjacent alignment marks do not overlap each other in the depth direction, and projections of adjacent alignment marks on the substrate have the same spacing in the horizontal direction.

6. The method for preparing a semiconductor device according to claim 1, wherein: Using the first alignment mark to align the device mask with the exposure unit, and forming a preset structure on the first epitaxial layer in the exposure unit through the device mask includes: forming a photoresist layer on the first epitaxial layer; aligning the alignment mark pattern on the device mask with the first alignment mark to align the device mask with the exposure unit; Using the implantation region pattern on the device mask, exposing the photoresist layer to form an implantation window; Using the photoresist layer outside the injection window as a mask, impurity ions are injected into the first epitaxial layer exposed by the injection window to form a preset structure in the first epitaxial layer.

7. The method for preparing a semiconductor device according to claim 1, wherein: Using the same mark mask to form a second alignment mark on the second epitaxial layer, the second alignment mark is located in the exposure unit, and the second alignment mark is spaced from the first alignment mark by an integer multiple of the device unit, including: coating a photoresist layer on the second epitaxial layer; After aligning the alignment mark pattern on the same mark mask with the first alignment mark, driving the mark mask to move a distance that is an integer multiple of the device unit; A second alignment mark is formed on the second epitaxial layer by using the moved mark mask.

8. The method for preparing a semiconductor device according to claim 1, wherein: After aligning the alignment mark pattern on the device mask with the second alignment mark, driving the device mask to move a distance that is an integer multiple of the device unit so that the device mask is aligned with the exposure unit, and forming a preset structure on the second epitaxial layer in the exposure unit through the device mask includes: forming a photoresist layer on the second epitaxial layer; Aligning the alignment mark pattern on the device mask with the second alignment mark; Driving the device mask to move an integer multiple of the device unit distance so that the device mask is aligned with the exposure unit; Using the implantation region pattern on the device mask, exposing the photoresist layer to form an implantation window; Using the photoresist layer outside the injection window as a mask, impurity ions are injected into the second epitaxial layer exposed by the injection window to form a preset structure in the second epitaxial layer.

9. The method for preparing a semiconductor device according to claim 6, wherein: The first epitaxial layer and the second epitaxial layer are N-type epitaxial layers, and the impurity ions are P-type impurity ions.

10. A semiconductor device, characterized in that: The method is prepared according to any one of claims 1 to 9.

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