Method for generating groove pattern on wafer and application thereof

Abstract

The invention discloses a method for generating a groove pattern on a wafer, and the method comprises the steps: providing a photomask which is provided with a first groove pattern arranged along a first direction; enabling the photomask to be in a first relative orientation, and exposing a first preset area on the surface of the wafer; then, enabling the photomask to be in a second relative orientation after relative rotation of a first rotation angle between the photomask and the wafer, and exposing a remaining second preset area on the surface of the wafer; and after developing, forming a second groove pattern corresponding to the first groove pattern on the surface of the wafer, so that a relative included angle corresponding to the first rotation angle is formed between the second groove pattern located in the first preset area and the second groove pattern located in the second preset area along the first trend. According to the invention, the stress brought by the groove can be mutually offset, the problems of wafer breaking and scratching caused by warping after the wafer is thinned are solved, the method can be applied to preparation of the groove type power MOSFET, and the rejection rate can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit technology, and in particular to a method for generating a groove pattern on a wafer and its application. Background Art

[0002] In order to reduce the on-resistance of trench power MOSFET, the back of the wafer is thinned after the front process of the wafer is completed. The thinned wafer will warp to varying degrees due to the stress generated by the filled trench.

[0003] The stress generated by trench power MOSFETs is closely related to the pattern design of their trenches. Since the trenches are usually designed in the form of stripe trenches, the stresses between the trenches cannot offset each other, which easily leads to obvious warping after the wafer is thinned.

[0004] If the wafer warpage is too large, it may cause the wafer to be unable to be input into the processing equipment, or even cause fragmentation during subsequent processes. In addition, during the back-end process, the wafers will be scratched to a large extent due to the excessive warpage.

[0005] There are two main methods for reducing wafer warpage for trench power MOSFETs:

[0006] One method is to add dummy grooves perpendicular to the grooves on the chip to offset the stress between the grooves and improve the problem of excessive warpage. However, if the size of the dummy grooves on the scribe line is smaller than the size of the grooves on the chip, there is a risk of peeling off after etching the top interconnect metal pattern and the passivation layer pattern. In addition, when the total number of grains on the wafer is small, the area of ​​the dummy grooves on the scribe line will also be reduced accordingly, and it may be difficult to effectively balance the stress caused by the grooves on the chip.

[0007] Another method is to use the Taiko process (Taiko ring process, a wafer thinning process) to improve wafer warpage when the wafer is thinned. The Taiko process only thins the middle part of the wafer, and does not thin the 2 to 5 mm width portion of the wafer edge, thereby forming a support ring at the edge of the wafer. However, on medium and high voltage MOSFETs, the deepening of the trench depth will further worsen the wafer warpage problem. At the same time, the warpage caused by factors such as the thickness of the oxide layer, the increase in thermal processes, and the deposition stress of the passivation layer will also be aggravated by the increase in operating voltage. These problems make the wafer still warp during back-side processing even if there is a support ring in the Taiko process. Summary of the invention

[0008] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a method for generating a groove pattern on a wafer and its application.

[0009] To achieve the above object, the technical solution of the present invention is as follows:

[0010] The present invention provides a method for generating a groove pattern on a wafer, comprising:

[0011] Providing a photomask having a first groove pattern arranged along a first direction;

[0012] The photomask is placed in a first relative position, and a first preset area on the surface of the wafer is exposed first;

[0013] Then, the photomask is placed in a second relative position after being rotated relative to the wafer by a first rotation angle, and then a second preset area remaining on the surface of the wafer is exposed;

[0014] After development, a second groove pattern corresponding to the first groove pattern is formed on the surface of the wafer, so that along the first direction, the second groove pattern located in the first preset area and the second groove pattern located in the second preset area have a relative angle corresponding to the first rotation angle.

[0015] Further, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd-numbered lines, and the second preset area includes an area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along even-numbered lines; or, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even-numbered lines, and the second preset area includes an area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along odd-numbered lines.

[0016] Further, the first preset area includes an area correspondingly formed on the chip surface when the mask is exposed and scanned along odd columns, and the second preset area includes an area correspondingly formed on the chip surface when the mask is rotated by a first rotation angle and then exposed and scanned along even columns; or, the first preset area includes an area correspondingly formed on the chip surface when the mask is exposed and scanned along even columns, and the second preset area includes an area correspondingly formed on the chip surface when the mask is rotated by a first rotation angle and then exposed and scanned along odd columns.

[0017] Further, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd rows, and the second preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even columns after the chip is rotated by a first rotation angle; or, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even rows, and the second preset area includes an area correspondingly formed on the surface of the chip when the chip is rotated by a first rotation angle and then the mask is exposed and scanned along odd columns.

[0018] Further, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd columns, and the second preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even rows after the chip is rotated by a first rotation angle; or, the first preset area includes an area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even columns, and the second preset area includes an area correspondingly formed on the surface of the chip when the chip is rotated by a first rotation angle and then the mask is exposed and scanned along odd rows.

[0019] Furthermore, the first direction of the second groove pattern is parallel or perpendicular to a row scanning direction or a column scanning direction of the mask during exposure.

[0020] Further, the first rotation angle and / or the azimuth angle between the first relative orientation and the second relative orientation includes 90 degrees or 270 degrees.

[0021] Furthermore, after the first preset area on the surface of the chip is exposed by the photolithography machine, the photolithography machine is first set to be in a chip output state, the mask or the chip is rotated to cause a relative rotation of the first rotation angle between the mask and the chip, and then the photolithography machine is set to be in a chip input state to expose the remaining second preset area on the chip surface.

[0022] The present invention also provides an application of the above-mentioned method for generating a groove pattern on a wafer in the field of trench power MOSFET.

[0023] Furthermore, the application includes forming a photolithographic pattern of a groove of the trench-type power MOSFET as a second groove pattern on the front side of the wafer, and forming and filling the groove of the trench-type power MOSFET below the front side of the wafer based on the photolithographic pattern of the groove, so as to eliminate the warping of the wafer caused by the stress generated by the filled groove after thinning the back side of the wafer.

[0024] It can be seen from the above technical scheme that the present invention is aimed at the preparation of groove-like patterns on a wafer, by adopting a step-by-step exposure method for the wafer, and making a relative rotation of a certain angle (a first rotation angle, for example, preferably 90 degrees or 270 degrees) between the mask and the wafer during the two exposures, so that the directions of the groove patterns (second groove patterns) formed by the two exposures on the wafer have a certain relative angle (the angle corresponds to the first rotation angle), so that the grooves formed correspondingly on the wafer also have a certain relative angle, so that the stresses brought by the grooves can offset each other, thus successfully eliminating the warping problem of the wafer after thinning in the past. When the present invention is applied to the preparation of trench-type power MOSFET, it can reduce the problems of broken pieces and scratches caused by excessive warping, and effectively reduce the scrap rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flow chart of a method for generating a groove pattern on a wafer according to a preferred embodiment of the present invention;

[0026] Figure 2 A schematic diagram of an exposure step and a wafer thinning state according to a preferred embodiment of the present invention;

[0027] Figure 3 It is a schematic diagram of an existing exposure step and the state of the wafer after thinning. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0029] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0030] refer to Figure 1 The method for generating a groove pattern on a wafer of the present invention comprises the following steps:

[0031] Step S1: providing a photomask having a first groove pattern arranged along a first direction.

[0032] like Figure 2 As shown, it shows along the arrow direction a plurality of exposure step stages a to g in a method for generating a groove pattern on a wafer of the present invention and a state of a side view h after the wafer 10 is thinned.

[0033] Among them, the wafer 10 can be a semiconductor wafer 10, such as a silicon wafer, etc. The shape of the silicon wafer can be, for example, circular. The multiple rectangular figures on the circular wafer 10 corresponding to each exposure step stage a to g in the figure reflect the multiple motion track figures formed when a mask 20 is scanned and exposed on the wafer 10. Since each post-exposure figure 30 corresponds to the figure on the mask 20, and the area where each post-exposure figure 30 is located corresponds to an exposure area (Shot). For ease of understanding, the motion track figure of each mask 20 can also be regarded as the post-exposure figure 30 formed on the wafer 10 after exposure (so the mark of the mask 20 and the mark of the post-exposure figure 30 are indicated on the same rectangular figure).

[0034] Furthermore, the photomask 20 has a first groove pattern arranged along a first direction, and the exposed pattern 30 on the wafer 10 has a second groove pattern corresponding to the first groove pattern. That is, the second groove pattern formed on the wafer 10 after exposure is also arranged along the first direction. Therefore, the motion trajectory pattern formed when the photomask 20 is scanned and exposed on the wafer 10 can be used to map the exposed patterns 30 formed on the wafer 10 after exposure, and the first groove pattern arranged along the first direction on the photomask 20 can be used to map the second groove pattern with the first direction formed on the wafer 10 after exposure (that is, the exposed pattern 30 generated on the wafer 10 by mapping the pattern on the photomask 20).

[0035] It should be noted that the first direction is the structural direction of the first groove pattern, not the physical direction. For example, assuming that the first groove pattern is a straight bar, the first direction can be the direction in which the first groove pattern extends along the length of the straight bar. For another example, assuming that the first groove pattern is a curved bar (e.g., C-shaped), the first direction can be the direction in which the first groove pattern extends along the length of the curved bar. Alternatively, a line segment for comparing relative orientations can be defined on the curved bar of the first groove pattern, and this line segment can be used as a standard for defining the first direction of the curved bar of the first groove pattern.

[0036] Step S2: placing the photomask in a first relative position, and first exposing a first preset area on the surface of the wafer.

[0037] like Figure 2As shown in the figure, the motion track graphics formed on the wafer 10 after the mask 20 is exposed and scanned in the row direction in each exposure step stage a to g are sequentially shown in the direction of the arrow. Among them, a mark 21 reflecting the orientation is provided on one corner of the mask 20 graphic, and this orientation mark 21 will be correspondingly reflected on the exposed graphic 30 of the wafer 10 (that is, the exposed graphic 30 also has an orientation mark 31). It can be seen that in each exposure step stage a to d for odd rows, the orientation mark 21 of the mask 20 graphic (exposed graphic 30) displayed on the wafer 10 is the same relative to the wafer 10 (the figure shows that it points to the upper left corner). Assuming that the orientation of the orientation mark 21 relative to the wafer 10 in this state is the first relative orientation, then in the above exposure step stages a to d for odd rows, the orientation mark 21 on the mask 20 is in the first relative orientation, that is, the mask 20 is in the first relative orientation, and the wafer 10 is exposed in this orientation.

[0038] The exposure methods of the exposure steps a to d for the odd-numbered rows are specifically as follows:

[0039] In the first exposure step stage a, the photomask 20 is placed in the first relative orientation, and the first row is scanned and exposed on the wafer 10, and the exposed pattern 30 arranged in the first relative orientation can be formed on the area corresponding to the first row on the wafer 10. For example, the figure shows that the photomask 20 is exposed three times on the area corresponding to the first row on the wafer 10, and three exposed patterns 30 arranged in the first relative orientation can be formed (actually, the three-dimensional exposed pattern 30 (photoresist pattern) can be displayed after development), but it is not limited to this. In addition, during this exposure process, the relative orientation between the photomask 20 and the wafer 10 remains unchanged, and the orientation mark 21 on the photomask 20 points to the upper left corner relative to the wafer 10 during each exposure.

[0040] In the second exposure step phase b, the photomask 20 is still in the first relative orientation, but the second row is skipped and the third row is directly exposed through the machine setting. Thus, a post-exposure pattern 30 arranged in the first relative orientation can be formed on the area corresponding to the third row on the wafer 10. For example, the figure schematically shows that the photomask 20 is exposed 6 times on the area corresponding to the third row on the wafer 10, and 6 post-exposure patterns 30 arranged in the first relative orientation can be formed accordingly. In addition, during this exposure process, the relative orientation between the photomask 20 and the wafer 10 remains unchanged, and the orientation mark 21 on the photomask 20 points to the upper left corner relative to the wafer 10 during each exposure.

[0041] In the third exposure step stage c, the mask 20 is still in the first relative orientation, but the machine setting skips the fourth row and directly exposes the fifth row. This is done until all odd rows are exposed as shown in the fourth exposure step stage d. It can be seen that the orientation marks 31 on the exposed pattern 30 (mask 20) ​​on each odd row point to the same upper left corner relative to the wafer 10.

[0042] The area where all the odd-numbered rows are located is defined as the first preset area on the surface of the wafer 10 .

[0043] It can be understood that in the above-mentioned exposure step stages a to d, by setting the exposure scanning program of the mask 20, the mask 20 can also be exposed and scanned on the even-numbered rows of the first preset area such as the second row and the fourth row, and the odd-numbered rows can be skipped. Alternatively, the mask 20 can be exposed and scanned on the odd-numbered columns of the first preset area, and the even-numbered columns can be skipped. Alternatively, the mask 20 can be exposed and scanned on the even-numbered columns of the first preset area, and the odd-numbered columns can be skipped. No further description will be given.

[0044] Step S3: Then, the mask is placed in a second relative position after being rotated relative to the wafer by the first rotation angle, and then the remaining second preset area on the surface of the wafer is exposed.

[0045] After completing the exposure scan for all odd-numbered rows (the first preset area), the photolithography machine can be set to "Track Out" (the action of sending the wafer out of the machine after the photolithography machine completes the operation) to put the photolithography machine in a wafer output state. Then, by rotating the mask 20 (or the wafer 10), the mask 20 and the wafer 10 are rotated relative to each other at a first rotation angle. After that, the photolithography machine is set to "Track In" (the action of sending the wafer into the machine before the photolithography machine starts the operation) to put the photolithography machine in a wafer input state, and then the remaining second preset area on the surface of the wafer 10 is exposed.

[0046] like Figure 2 As shown, in one example, the lithography machine can be set to "Track Out" and the mask 20 can be rotated 90 degrees (or 270 degrees) to make a relative rotation of 90 degrees (or 270 degrees) with the wafer 10. Assuming that the orientation of the position mark 21 relative to the wafer 10 in this state is the second relative orientation, the mask 20 will be in the second relative orientation after the relative rotation of the first rotation angle with the wafer 10. For example, the orientation mark 21 on the mask 20 can be rotated to the orientation located in the upper right corner by rotating the mask 20 90 degrees in the clockwise direction as shown in the figure. That is, the orientation angle between the second relative orientation and the first relative orientation is 90 degrees (or 270 degrees).

[0047] It should be emphasized that the above relative rotation angle of 90 degrees or 270 degrees is only used to illustrate the preferred mode of the embodiment of the present invention, and should not be understood as limiting the first rotation angle of the present invention. In addition, the first rotation angle can be any other rotation angle that avoids 0 degrees (or 360 degrees) and 180 degrees on the plane where the mask 20 or the wafer 10 is located.

[0048] Then, the photolithography machine is set to “Track In” to expose the remaining even-numbered rows (the second preset area) on the surface of the wafer 10 .

[0049] The figure shows the exposure steps e to g that need to be performed in sequence according to the arrow direction. The exposure method is specifically:

[0050] In the fifth exposure step phase e, the photomask 20 is placed in the second relative orientation (i.e., the orientation mark 21 is located in the upper right corner direction), and the second row skipped in the exposure step phase b is scanned and exposed on the wafer 10 through the machine setting, and the exposed pattern 30 arranged in the second relative orientation can be formed on the area corresponding to the second row on the wafer 10. For example, the figure schematically shows that the photomask 20 is exposed 5 times on the area corresponding to the second row on the wafer 10, and 5 exposed patterns 30 arranged in the second relative orientation can be formed. In addition, during this exposure process, the relative orientation between the photomask 20 and the wafer 10 remains unchanged, and the orientation mark 21 on the photomask 20 points to the upper right corner direction relative to the wafer 10 during each exposure.

[0051] In the sixth exposure step stage f, the mask 20 is still in the second relative orientation, and the fourth row skipped in the exposure step stage c is directly exposed through the machine setting. Thus, the exposed pattern 30 arranged in the second relative orientation can be formed on the area corresponding to the fourth row on the wafer 10. For example, the figure schematically shows that the mask 20 is exposed 6 times on the area corresponding to the fourth row on the wafer 10, and 6 exposed patterns 30 arranged in the second relative orientation can be formed. In addition, during this exposure process, the relative orientation between the mask 20 and the wafer 10 remains unchanged, and the orientation mark 21 on the mask 20 points to the upper right corner relative to the wafer 10 at each exposure. In this way, the exposure of all even-numbered rows is completed as shown in the seventh exposure step stage g. It can be seen that the orientation marks 21 on the exposed pattern 30 (mask 20) ​​on each even-numbered row point to the same upper right corner relative to the wafer 10.

[0052] The area where all the even-numbered rows are located is defined as the remaining second preset area on the surface of the wafer 10 .

[0053] It can be understood that in the above-mentioned exposure step stages a~d, by setting the exposure scanning program of the mask 20, the mask 20 is exposed and scanned on the even rows of the second row, the fourth row, etc. as the first preset area, and the odd rows are skipped, or the mask 20 is exposed and scanned on the odd columns as the first preset area, and the even columns are skipped, or the mask 20 is exposed and scanned on the even columns as the first preset area, and the odd columns are skipped, etc., in the optional manner, the exposure step stages e~g will complete the corresponding exposure scan of the remaining unexposed area (the second preset area) on the surface of the chip 10 by setting the corresponding exposure scanning program of the mask 20.

[0054] It can also be understood that in exposure step stages e to g, by rotating the mask 20 90 degrees (or 270 degrees), the second groove pattern formed in the odd rows (first preset area) and the second groove pattern in the even rows (second preset area) formed on the chip 10 can be formed perpendicular to each other in their respective directions (first direction).

[0055] It should be noted that in the exposure step stages e to g, when the first rotation angle of the wafer 10 is adopted to rotate 90 degrees (or 270 degrees) so that the orientation mark 21 of the mask 20 changes its corresponding orientation relative to the wafer 10, due to the rotation of the wafer 10, the remaining second preset area on the wafer 10 will be converted into an area in the form of an area on the surface of the wafer 10 in the form of an area where all even-numbered columns are located. At this time, it is necessary to set the machine and adopt a program to make the mask 20 perform exposure scanning along the even-numbered columns to complete the exposure scanning of the remaining second preset area.

[0056] Similarly, when the first preset area is the area formed on the surface of the wafer 10 when the mask 20 is exposed and scanned along the odd columns, in the exposure step stages e to g, when the wafer 10 is rotated by a first rotation angle of 90 degrees (or 270 degrees) so that the orientation mark 21 of the mask 20 changes its corresponding orientation relative to the wafer 10, the second preset area will be the area formed on the surface of the wafer 10 when the mask 20 is exposed and scanned along the even columns after the wafer 10 is rotated by the first rotation angle. This will not be described one by one.

[0057] Step S4: After development, a second groove pattern corresponding to the first groove pattern is formed on the surface of the wafer, so that along the first direction, the second groove pattern located in the first preset area and the second groove pattern located in the second preset area have a relative angle corresponding to the first rotation angle.

[0058] After the above-mentioned exposure steps a to g and after development, a second groove pattern corresponding to the first groove pattern on the mask 20 can be formed on the surface of the chip 10, and along the first direction, the second groove pattern located in the first preset area and the second groove pattern located in the second preset area have a relative angle of 90 degrees (or 270 degrees) corresponding to the first rotation angle of 90 degrees (or 270 degrees), that is, the direction of the second groove pattern located in the first preset area and the direction of the second groove pattern located in the second preset area are perpendicular to each other.

[0059] In some embodiments, the first direction of the first groove pattern on the mask 20 can be designed to be parallel or perpendicular to the row scanning direction or column scanning direction when the mask 20 is exposed. Therefore, the first direction of the second groove pattern in the exposed pattern 30 formed on the wafer 10 after exposure is also parallel or perpendicular to the row scanning direction or column scanning direction when the mask 20 is exposed. For example, in the above-mentioned exposure step stages a to d, the first direction of the first groove pattern on the mask 20 (or the second groove pattern on the wafer 10) can be parallel to the odd-numbered row scanning direction when the mask 20 is exposed. In the exposure step stages e to g, the first direction of the first groove pattern on the mask 20 (or the second groove pattern on the wafer 10) can be perpendicular to the scanning direction of the mask 20 on the even-numbered rows. Thus, a structural feature is formed on the wafer 10 that the directions (first directions) of the second groove pattern in the odd-numbered rows (first preset area) and the second groove pattern in the even-numbered rows (second preset area) are perpendicular to each other.

[0060] As a comparison, Figure 3 An existing exposure step for forming a groove pattern on a wafer is shown, which includes exposure step stages A to D displayed in sequence in the direction of the arrows. It can be seen that the existing exposure method adopts a row-by-row exposure scanning method, and during all row scans, the mask is located in the same orientation relative to the wafer (that is, the orientation marks on the mask are all uniformly facing the same direction (shown as facing the lower left corner)). That is, at different stages of scanning, the mask does not rotate relative to the wafer. When a groove pattern is formed on a wafer in such an exposure method, the orientation of all the groove patterns on the wafer is consistent, which will result in the stress caused by subsequent etching and filling of the grooves being unable to be offset between the grooves, causing the wafer to produce obvious warping after thinning, such as Figure 3 E shows the top view of the wafer warpage and Figure 3 F shows the side view of the wafer warpage.

[0061] Compared with the above-mentioned existing exposure method, the present invention uses a mask 20 with different relative orientations to expose different set areas (first preset area, second preset area) on the wafer 10 respectively, and forms a conversion form alternating by row or column, so that the groove patterns (second groove patterns) located in adjacent rows or adjacent columns have mutually perpendicular directions, so that the stress caused by subsequent etching and filling of the grooves is offset between the grooves of adjacent rows or adjacent columns, and the groove stress on the entire wafer 10 tends to zero. Therefore, after the wafer 10 is thinned, the wafer 10 will no longer have obvious warping, such as Figure 2 h shows the flat side view of the wafer 10. This effectively solves the problem of obvious warping of the wafer, which may lead to breakage and scratches when using the exposure method of the prior art.

[0062] The method for generating a groove pattern on a wafer of the present invention can be advantageously applied in the field of trench power MOSFET.

[0063] In some embodiments, the above-mentioned application includes using the above-mentioned method for generating a groove pattern on a chip of the present invention to form a photolithography pattern of a groove of a trench-type power MOSFET as a second groove pattern on the front side of the chip 10, and based on the photolithography pattern of the groove, forming and filling a groove of a trench-type power MOSFET below the front side of the chip 10, so as to eliminate the warping of the chip 10 caused by the stress generated by the filled groove after thinning the back side of the chip 10.

[0064] In addition, the method for generating a groove pattern on a wafer of the present invention is not limited to the preparation of a trench-type power MOSFET, and it should be understood that it can be applied to the preparation of other types of groove structures on the wafer 10. For example, it can be applied to the preparation of a variety of groove structures with a strip-shaped non-enclosed form on the wafer 10.

[0065] In summary, the present invention is directed to the preparation of groove-like patterns (especially strip grooves) on a wafer 10, by adopting a step-by-step exposure method for the wafer 10, and during the two exposures, the mask 20 and the wafer 10 are relatively rotated at a certain angle (a first rotation angle, such as 90 degrees or 270 degrees), so that the directions of the groove patterns (second groove patterns) formed by the two exposures on the wafer 10 have a certain relative angle (the angle corresponds to the first rotation angle), so that the grooves formed correspondingly on the wafer 10 also have a certain relative angle, so that the stresses brought by the grooves can offset each other, thus successfully eliminating the warping problem of the wafer after thinning in the past. When the present invention is applied to the preparation of trench-type power MOSFETs, it can reduce the problems of broken pieces and scratches caused by excessive warping, and effectively reduce the scrap rate.

[0066] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A method for generating a groove pattern on a wafer, characterized in that: include: Providing a photomask having a first groove pattern arranged along a first direction; The photomask is placed in a first relative position, and a first preset area on the surface of the wafer is exposed first; Then, the photomask is placed in a second relative position after being rotated relative to the wafer by a first rotation angle, and then a second preset area remaining on the surface of the wafer is exposed; After development, a second groove pattern corresponding to the first groove pattern is formed on the surface of the wafer, so that along the first direction, the second groove pattern located in the first preset area and the second groove pattern located in the second preset area have a relative angle corresponding to the first rotation angle.

2. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd-numbered lines, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along even-numbered lines; or, the first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even-numbered lines, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along odd-numbered lines.

3. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along the odd columns, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along the even columns; or, the first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along the even columns, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is rotated by a first rotation angle and then exposed and scanned along the odd columns.

4. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd rows, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even columns after the chip is rotated by a first rotation angle; or, the first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even rows, and the second preset area includes the area correspondingly formed on the surface of the chip when the chip is rotated by a first rotation angle and then the mask is exposed and scanned along odd columns.

5. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along odd columns, and the second preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even rows after the chip is rotated by a first rotation angle; or, the first preset area includes the area correspondingly formed on the surface of the chip when the mask is exposed and scanned along even columns, and the second preset area includes the area correspondingly formed on the surface of the chip when the chip is rotated by a first rotation angle and then the mask is exposed and scanned along odd rows.

6. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first direction of the second groove pattern is parallel or perpendicular to a row scanning direction or a column scanning direction of the mask during exposure.

7. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: The first rotation angle and / or the azimuth angle between the first relative orientation and the second relative orientation include 90 degrees or 270 degrees.

8. The method for generating a groove pattern on a wafer according to claim 1, characterized in that: After the first preset area on the surface of the chip is exposed by the photolithography machine, the photolithography machine is first set to be in a chip output state, the mask or the chip is rotated to cause a relative rotation of the first rotation angle between the mask and the chip, and then the photolithography machine is set to be in a chip input state to expose the remaining second preset area on the chip surface.

9. Application of the method for generating a groove pattern on a wafer according to any one of claims 1 to 8 in the field of trench power MOSFET.

10. The use according to claim 9, characterized in that: The application includes forming a photolithographic pattern of a groove of the trench-type power MOSFET as a second groove pattern on the front side of the wafer, and forming and filling the groove of the trench-type power MOSFET below the front side of the wafer based on the photolithographic pattern of the groove, so as to eliminate the warping of the wafer caused by the stress generated by the filled groove after thinning the back side of the wafer.

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