Integrated circuit device and method of forming same

Abstract

Some embodiments relate to an integrated circuit (IC) device including a substrate, a plurality of conductive structures disposed on the substrate and separated from each other, and at least one electrically insulating structure disposed over the substrate and directly contacting each of the plurality of conductive structures. The at least one electrically insulating structure has a thermal conductivity greater than 5 watts per meter Kelvin (W / m-K). The embodiment of the invention also discloses a method for forming the integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices and methods of forming the same. Background Art

[0002] Advances in integrated circuit (IC) design are not limited to reductions in circuit geometry, but also include multi-level chip / wafer designs, packaging innovations, and more. These advances may address previously recognized needs, but in some cases, may also create separate problems. One such problem is the generation of excess heat, which can negatively impact the performance or physical integrity of the IC. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a substrate; a plurality of conductive structures disposed above the substrate and separated from each other; and at least one electrically insulating structure disposed above the substrate and directly contacting each of the plurality of conductive structures, the at least one electrically insulating structure having a thermal conductivity greater than 5 watts per meter Kelvin (W / mK).

[0004] According to another aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a substrate; a first dielectric layer disposed above the substrate; a plurality of conductive structures disposed above the first dielectric layer and separated from each other; and at least one electrically insulating structure disposed above the first dielectric layer and adjacent to each of the plurality of conductive structures, the thermal conductivity of the at least one electrically insulating structure being greater than the thermal conductivity of the first dielectric layer.

[0005] According to another aspect of an embodiment of the present application, a method for forming an integrated circuit device is provided, comprising: providing a substrate; forming a first dielectric layer above the substrate; and forming a plurality of conductive structures and at least one electrically insulating structure above the first dielectric layer, wherein the at least one electrically insulating structure is adjacent to each of the plurality of conductive structures, and the thermal conductivity of the at least one electrically insulating structure is greater than the thermal conductivity of the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Schematic cross-sectional views of some embodiments of IC devices employing heat collection networks including high thermal conductivity electrically insulating structures according to the present disclosure are shown.

[0008] Figure 2A-2C , Figure 3A-3C , Figure 4A-4Cand Figure 5A-Figure 5C Plan views and cross-sectional views of some embodiments of high thermal conductivity electrically insulating structures relative to various configurations of multiple electrically conductive structures according to the present disclosure are shown.

[0009] Figure 6A-6C Plan views and cross-sectional views of some embodiments of IC devices employing multiple high thermal conductivity electrically insulating structures coupled to multiple electrically conductive structures according to the present disclosure are shown.

[0010] Figure 7A-7C Cross-sectional views of some embodiments of IC devices according to the present disclosure are shown, wherein the thickness of at least one high thermal conductivity electrically insulating structure varies within a dielectric layer.

[0011] Figure 8A-8C Cross-sectional views of some embodiments of IC devices according to the present disclosure are shown, wherein the thickness of at least one high thermal conductivity electrically insulating structure varies across one or more dielectric layers.

[0012] Fig.9A and Fig. 9B Cross-sectional views of some embodiments of IC devices according to the present disclosure are shown in which the functionality of one or more of the plurality of conductive structures is varied.

[0013] Figure 10A-10C Plan views and cross-sectional views of some embodiments of IC devices according to the present disclosure that employ multiple discrete high thermal conductivity electrically insulating structures connected to multiple electrically conductive structures are shown.

[0014] Figures 11A-11C Plan views and cross-sectional views of some embodiments of IC devices employing a single high thermal conductivity electrically insulating structure connected to multiple electrically conductive structures according to the present disclosure are shown.

[0015] FIG. 12A to FIG. 12L It is shown that according to the present disclosure, Figure 10A-10C Some embodiments of IC devices showing multiple high thermal conductivity electrically insulating structures are shown in cross-sectional views at various stages of fabrication.

[0016] Fig.13A and Fig. 13B Cross-sectional views of some embodiments of two-step etching of a high thermal conductivity electrically insulating structure prior to depositing a plurality of electrically conductive structures according to the present disclosure are shown.

[0017] Fig.14A and Fig. 14B Cross-sectional views of some embodiments employing a one-step etch of a high thermal conductivity electrically insulating structure prior to depositing a plurality of electrically conductive structures according to the present disclosure are shown.

[0018] Fig.15Methods of forming an IC device employing at least one high thermal conductivity electrically insulating structure coupled to a plurality of electrically conductive structures are shown in accordance with some embodiments of the present disclosure.

[0019] Fig.16 Methods of forming an IC device employing a plurality of high thermal conductivity electrically insulating structures coupled to a plurality of electrically conductive structures are shown in accordance with some embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] A recent advance in IC design is to locate conductive structures for signals and power on opposite sides of a semiconductor substrate. More specifically, by implementing the power conductive structures as buried power rails in the substrate and / or backside power rails near the backside of the substrate, additional useful volume can be provided inside the IC device for both types of conductive structures. However, a potential adverse side effect of placing the conductive structures and their associated dielectric layers on both sides of the substrate is the retention of heat generated by integrated circuit components (e.g., transistors, etc.) that are integrated into and / or adjacent to the substrate, primarily due to the sometimes low thermal conductivity of the dielectric materials used in the dielectric layers. In addition, in some cases, the dielectric layer carrying the power conductive structures on the backside of the substrate is sometimes thicker than that typically used on the front side of the substrate, thereby potentially increasing the retention of thermal energy within and near the substrate.

[0023] To address these issues, the present disclosure provides some embodiments of an IC device that employs at least one electrically insulating structure having a thermal conductivity greater than the thermal conductivity of typical dielectric materials commonly used in IC devices, such as the thermal conductivity of silicon dioxide (SiO2). In some embodiments, at least one electrically insulating structure may be diamond, although other dielectric materials or electrically insulating materials may be employed in other embodiments.

[0024] In some embodiments, the IC device may include a substrate, a plurality of conductive structures disposed on the substrate and separated from each other, and at least one electrically insulating structure disposed above the substrate and directly contacting each of the plurality of conductive structures. In some embodiments, the at least one electrically insulating structure may have a thermal conductivity greater than 1 Watt per meter Kelvin (W / mK), while in other embodiments, at least one electrically insulating structure may have a thermal conductivity significantly greater than 1 W / mK (e.g., 2 W / mK, 5 W / mK, 10 W / mK, 20 W / mK, 30 W / mK, or more W / mK). In some embodiments, such an electrically insulating structure may be described herein as a high thermal conductivity electrically insulating structure or a high thermal conductivity electrically insulating structure. Thus, in some embodiments, a low thermal conductivity electrically insulating structure may be a structure having a thermal conductivity of approximately 1 W / mK or less.

[0025] Thus, in some embodiments, at least one electrically insulating structure can be used as a thermal conduit to conduct heat from some of the plurality of electrically conductive structures to other electrically conductive structures of the plurality of electrically conductive structures, which can be coupled to vias that conduct heat to an external area of ​​the IC device (e.g., a heat sink, a solder connection, or another interface with an external environment). Thus, as described in more detail below, the electrically insulating structure can provide better operating characteristics and a longer life expectancy for an IC device employing such an electrically insulating structure.

[0026] Figure 1 A schematic cross-sectional view of some embodiments of an IC device 100 employing a thermal collection network (TCN) 101 including a high thermal conductivity electrically insulating structure according to the present disclosure is shown. The IC device 100 employs a buried power rail (BPR) 106 within a device substrate 102, resulting in the use of a backside metal (BSM) region 110 (e.g., carrying a power connection 112) in addition to a frontside metal (FSM) region 120 (e.g., carrying a conductive structure 124). In addition, the device substrate 102 includes a through silicon via (TSV) 108, such as a nano-TSV (nTSV), coupling the BPR 106 to the power connection 112 in the BSM 110.

[0027] In this configuration, the conductive structures 124 of the FSM 120 may carry electrical signals associated with transistors and other components implemented through the doped (e.g., n-doped or p-doped) regions 104 in the device substrate 102 and the associated gate structures 122 in the FSM 120. The operation of these components may result in a significant amount of heat being generated in at least the lower portion of the device substrate 102 and the FSM 120, as well as the BPRs 106 and TSVs 108 in the device substrate 102 and the power connections 112 of the BSM 110. As described above, due to the use of low thermal conductivity dielectric materials in the FSM 120 and the BSM 110 that carry the conductive structures 124 and the power connections 112, it may be difficult to dissipate the generated heat. In addition, in this configuration, the device substrate 102 may be thinned to facilitate the use of the BPRs 106 and TSVs 108 to transmit power between the FSM 120 and the BSM 110. The BSM 110 may also carry various signal connections from the FSM 120 and received through the device substrate 102 and conductive structures 124 .

[0028] Therefore, in embodiments described in more detail below, a thermal collection network (TCN) 101 including a plurality of electrically conductive structures and at least one highly thermally conductive electrically insulating structure may be disposed within the BSM 110 to facilitate enhanced dissipation of thermal energy through the BSM 110 away from the device substrate 102 .

[0029] Continue to refer Figure 1 , various signal connections and power connections 112 may be made between the IC device 100 and the printed circuit board 130, on which the IC device 100 is mounted via a plurality of connection layers. More specifically, the signal connections and power connections 112 may be made with solder bumps 123 that couple the BSM 110 to the package substrate 126. The solder bumps 123 may be deposited on chip pads on the BSM 110 and / or the package substrate 126, and may provide a so-called controlled collapse chip connection (C4). In some embodiments, to enhance mechanical stability, an underfill 125 of a non-conductive material may fill the gaps between the solder bumps 123, the BSM 110, and the package substrate 126. In turn, the package substrate 126 may include conductive elements (e.g., forming a ball grid array (BGA) 128) that connect the solder bumps 123 to solder balls 129, which may mechanically and electrically connect the package substrate 126 to the printed circuit board 130.

[0030] On the opposite side of the device substrate 102, the FSM 120 may be coupled to a carrier 134 of the IC device 100 via an adhesive layer 132. Thereafter, a housing / integrated heat sink (IHS) 138 may be mechanically coupled to the carrier 134 via a thermal interface material (TIM) 136. Finally, a heat sink 140 may be attached to the housing / IHS 138 (e.g., via a heat sink 140). Figure 1 A thermal adhesive (not shown) may be provided to facilitate heat dissipation from the top surface of FSM 120.

[0031] Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-Figure 5C Plan views and cross-sectional views of some embodiments of a highly thermally conductive electrically insulating structure 201 in accordance with the present disclosure are shown relative to various configurations of a plurality of electrically conductive structures 202. These views may correspond to Figure 1 Although the TCN 101 and the various embodiments described below may be implemented in addition to Figure 1 The IC device 100 may be used in various IC structures other than the various IC configurations shown in FIG.

[0032] Figure 2A-2C , Figure 3A-3C , Figure 4A-4C and Figure 5A-Figure 5C Each of the illustrative embodiments shows basic physical relationships between electrically insulating structures 201 and conductive structures 202 that help distribute thermal energy among conductive structures 202, such that any conductive structure 202 that is not directly connected to a via or other conductive structure that may carry heat can transfer heat through the electrically insulating structure 201 to another conductive structure 202, which can distribute the heat elsewhere.

[0033] For example, Figure 2A , Figure 2B and Figure 2C A plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of a high thermal conductivity dielectric structure 201 bridging a space between two parallel arranged conductive structures 202 are shown, respectively. In these embodiments, the electrically insulating structure 201 can be disposed along a major length of the conductive structure 202 to exclude other dielectric materials. More specifically, at each cross-section along the conductive structure 202, the electrically insulating structure 201 can fill at least a majority of the space between the conductive structures 202 (e.g., contact the conductive structure 202 at a surface of the conductive structure 202 facing the opposite conductive structure 202).

[0034] Figure 3A , Figure 3B and Figure 3CA plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of a high thermal conductivity electrically insulating structure 201 bridging a portion of the space between two parallel arranged conductive structures 202 are shown. In these embodiments, the electrically insulating structure 201 can be arranged along a relatively short length of the conductive structure 202, and the remaining space between the conductive structures 202 is occupied by a dielectric material 203 (e.g., SiO2 or another dielectric material) having a lower thermal conductivity (e.g., 1 W / mK) than the electrically insulating structure 202. Therefore, at some cross-sections along the conductive structure 202 (e.g., Figure 3B ), the electrically insulating structure 201 may fill the space between the conductive structures 202 (eg, contact the conductive structures 202 at the surfaces facing opposite sides of the conductive structures 202), while in other cross sections (eg, Figure 3C ), the dielectric structures 203 with lower thermal conductivity may fill the corresponding spaces between the conductive structures 202. In other embodiments, a plurality of high thermal conductivity electrical insulating structures 201 may be distributed along the conductive structures 202 to form contacts therebetween, with the dielectric structures 203 with lower thermal conductivity interspersed therebetween.

[0035] Figure 4A , Figure 4B and Figure 4C 1 and 2 respectively show a plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of a high thermal conductivity electrically insulating structure 201 that couples corresponding parallel surfaces of an electrically conductive structure 202 (e.g., Figure 4B and Figure 4C 203). In some embodiments, the low thermal conductivity dielectric structure 203 may be disposed in a manner similar to that of FIG. Figure 2A-2C In some embodiments, the high thermal conductivity electrical insulation structure 201 and the low thermal conductivity dielectric structure 203 may extend along the main length of the conductive structure 202, such as Figure 4A As shown in multiple cross sections, for example Figure 4B and Figure 4C Place.

[0036] Figure 5A , Figure 5B and Figure 5C 1 and 2 respectively show a plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of a high thermal conductivity electrically insulating structure 201 that couples corresponding parallel surfaces of an electrically conductive structure 202 (e.g., Figure 5B and Figure 5CIn some embodiments, the low thermal conductivity dielectric structure 203 may fill the space between the conductive structures 202, as well as the space adjacent to the high thermal conductivity dielectric structure 201, such as Figure 5C Therefore, in some embodiments, the high thermal conductivity electrical insulation structures 201 and the low thermal conductivity dielectric structures 203 may extend below (or above) the conductive structures 202 in an alternating manner along the main length of the conductive structures 202, while the low thermal conductivity dielectric structures 203 also fill the areas between the conductive structures 202 substantially along the entire length of the conductive structures 202.

[0037] Figure 6A-6C 1 and 2 respectively show a plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of an IC device according to the present disclosure that uses a plurality of high thermal conductivity electrically insulating structures 201 coupled to a plurality of conductive structures 202. In some embodiments, as Figure 6B and Figure 6C As shown, and in other embodiments described below, a conductive structure 202, an electrically insulating structure 201, and a dielectric structure 203 are employed in a TCN 101 disposed in a BSM 110, and the BSM 110 has at least two backside metal layers: a first backside metal layer BM0 and a second backside metal layer BM1. Other configurations of IC devices 100 in which TCN 101 may be employed are also possible.

[0038] exist Figure 6A-6C In the embodiment of the present invention, alternating regions of high thermal conductivity electrical insulating structures 201 and low thermal conductivity dielectric structures 203 are disposed on a substrate 102 (e.g., a semiconductor substrate such as silicon). In some embodiments, the low thermal conductivity dielectric structures 203 may include one or more dielectric materials, including but not limited to silicon oxide (SiO x) (e.g., silicon oxide (SiO2)), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc. In addition, in some embodiments, the high thermal conductivity electrical insulation structure 201 may include one or more materials having a thermal conductivity higher than the thermal conductivity of the low thermal conductivity dielectric structure 203. For example, assuming that the low thermal conductivity dielectric structure 203 has a thermal conductivity of 1 W / mK, in some embodiments, the thermal conductivity of the high thermal conductivity electrical insulation structure 201 may be greater than 1 W / mK. For example, in some embodiments, the high thermal conductivity electrical insulation structure 201 may have a thermal conductivity greater than or equal to 2 W / mK. In other embodiments, the high thermal conductivity electrical insulation structure 201 may have a thermal conductivity greater than or equal to 5 W / mK. In other embodiments, the high thermal conductivity electrical insulation structure 201 may have a thermal conductivity greater than or equal to 10 W / mK. In some other embodiments, the high thermal conductivity electrical insulation structure 201 may have a thermal conductivity greater than or equal to 20 W / mK. In some other embodiments, the high thermal conductivity electrical insulation structure 201 may have a thermal conductivity greater than or equal to 30 W / mK. In other embodiments, the insulation structure 201 may include, but is not limited to, diamond, aluminum nitride (AlN), silicon carbide, silicon nitride (SiN), boron nitride (BN), or beryllium oxide (BeO).

[0039] like Figure 6A-6C As shown, a plurality of conductive structures 202 are disposed within a high thermal conductivity electrical insulating structure 201 and a low thermal conductivity dielectric structure 203. More specifically, the conductive structures 202 may be arranged longitudinally along a first longitudinal axis (e.g., Fig. 6A The high thermal conductivity electrical insulating structure 201 and the low thermal conductivity dielectric structure 203 are longitudinally arranged along a second longitudinal axis perpendicular to the first longitudinal axis (e.g., as shown in FIG. Fig. 6A In some embodiments, the conductive structure 202 may include a metal (e.g., copper (Cu)), a metal alloy, or another conductive material. In some embodiments, the conductive structure 202 may also have a high thermal conductivity (e.g., greater than the low thermal conductivity dielectric structure 203).

[0040] In some embodiments, Figure 6B and Figure 6CAs shown, the first backside metal layer BM0 can be disposed above the substrate 102, and the substrate 102 includes a high thermal conductivity electrical insulation structure 201 and a low thermal conductivity dielectric structure 203, as well as a conductive structure 202. In addition, an etch stop layer (ESL) 604 can be disposed above the first backside metal layer BM0. In some embodiments, the ESL 604 may include silicon nitride (SiN), silicon nitride carbon (SiCN) or another metal-based oxide and / or nitride material. In addition, in some embodiments, the ESL 604 can be formed using physical vapor deposition (PVD), chemical vapor deposition, atomic layer deposition (ALD), etc. In addition, in some embodiments, based on the material used by the ESL 604, the thickness of the ESL 604 can range from about 30 angstroms to about 200 angstroms.

[0041] Furthermore, in some embodiments, the second backside metal layer BM1 may be disposed over the first backside metal layer BM0 and the ESL 604 , and may include at least one conductive structure 606 over one or both of the high thermal conductivity electrical insulation structure 201 and / or the low thermal conductivity dielectric structure 203 .

[0042] like Figure 6B and Figure 6C As shown, one or more conductive structures 202 may extend to the upper surface of the substrate 102 (e.g., through vias 602 or other conductive structures). In addition, in some embodiments, one or more TSVs (e.g., nTSVs) 108 may be disposed in the substrate 102 and connected to corresponding conductive structures 202, thereby providing an electrical path and a thermal path from the conductive structures 202 to the TSVs 108. Therefore, in some embodiments, the high thermal conductivity electrically insulating structures 201 may provide an effective thermal path to couple the conductive structures 202 together, so that those conductive structures 202 that are not electrically connected to the TSVs 108 may transfer thermal energy to the conductive structures 202 that are electrically connected to the TSVs 108 through the one or more high thermal conductivity electrically insulating structures 201. Fig. 6A Potential heat paths 610 are indicated by dashed arrows.

[0043] Thus, in some embodiments, the use of one or more high thermal conductivity electrically insulating structures 201 provides an additional thermal path to facilitate heat dissipation. Furthermore, such thermal paths use the same conductive vias 602 as used for power and / or signal flow; thus, no IC area is lost due to the use of high thermal conductivity electrically insulating structures 201. Furthermore, in some embodiments, there are other possible ways of incorporating high thermal conductivity electrically insulating structures 201 in a plan view (e.g., as shown in FIG. 1 ). Fig. 6A As shown in FIG. 1 , using one or more high thermal conductivity electrically insulating structures 201 in less than the entire area of ​​the substrate 102 may reduce process integration difficulty.

[0044] Figure 7A-7C , Figure 8A-8C , Figure 9A-9B , Figure 10A-10C and Figures 11A-11C Various plan views and cross-sectional views of some embodiments of IC devices using another backside metal structure are shown, in which at least one high thermal conductivity electrically insulating structure 201 is used. In each of these embodiments, a first backside metal layer BM0, a second backside metal layer BM1, and a third backside metal layer BM3 are sequentially disposed above a substrate 102. One or more conductive structures 202 and associated vias 602 may be disposed in each of the first backside metal layer BM0 and the third backside metal layer BM2. In addition, the first backside metal layer BM0 may include a low thermal conductivity dielectric structure 203, and the third backside metal layer BM2 may include a low thermal conductivity dielectric structure 203 or a high thermal conductivity electrically insulating structure 201.

[0045] Furthermore, in some embodiments, a plurality of conductive structures 202 are included in the second back metal layer BM1, and at least one of the conductive structures 202 is connected to the conductive structures 202 of the first back metal layer BM0 and / or the third back metal layer BM2 through corresponding vias. In some embodiments, the conductive structures 202 of the second back metal layer BM1 may each have a longitudinal axis that is longitudinally aligned parallel to the longitudinal axes of the other conductive structures 202. Furthermore, in some embodiments, the plurality of conductive structures 202 in any one of the back metal layers BM0, BM1, and / or BM2 may have a width of 36 nanometers (nm) or greater, and a spacing (e.g., pitch) therebetween of 36 nm or greater.

[0046] Although the figures described below may depict only a small portion of TCN 101, in some embodiments, the area in the plan view of TCN 101 may extend vertically through substantially all of substrate 102 having IC device 100, or may be limited to a smaller area of ​​substrate 102 to address portions of IC device 100 associated with heat dissipation issues.

[0047] Figure 7A-7C 1 shows a cross-sectional view of some embodiments of IC devices according to the present disclosure, wherein the thickness of at least one high thermal conductivity electrically insulating structure varies within the dielectric layer. Fig. 7A In the embodiment, at least one high thermal conductivity electrical insulation layer 201 vertically extends through the entire second back metal layer BM1. Figure 7BIn the embodiment, at least one high thermal conductivity electrical insulation layer 201 extends downward from the upper surface of the second back metal layer BM1 to an intermediate depth between at least some of the conductive structures 202 and the upper surface of the first back metal layer BM0. In some embodiments, another low thermal conductivity dielectric layer 203A may be provided to fill the remaining depth of the second back metal layer BM1 below the high thermal conductivity electrical insulation layer 201. Figure 7C In the embodiment, at least one high thermal conductivity electrical insulation layer 201 extends downward from the upper surface of the second back metal layer BM1 to the lower surface of at least some of the conductive structures 202, and another low thermal conductivity dielectric layer 203A may be provided to fill the remaining depth of the second back metal layer BM1 below the high thermal conductivity electrical insulation layer 201 and at least some of the conductive structures 202. In some embodiments, the low thermal conductivity dielectric layer 203A may include the same or different dielectric material as the low thermal conductivity dielectric structure 203, and like the low thermal conductivity dielectric structure 203, may have a thermal conductivity less than that of the high thermal conductivity electrical insulation structure 201.

[0048] Figure 8A-8C 1 shows a cross-sectional view of some embodiments of IC devices according to the present disclosure, wherein the thickness of at least one high thermal conductivity electrically insulating structure varies across one or more dielectric layers. Fig. 8A In the embodiment, one or more highly thermally conductive electrically insulating structures 201 substantially fill all portions of the second backside metal layer BM1 and the third backside metal layer BM2 that are not occupied by the conductive structures 202 and the corresponding through holes 602. Figure 8B In the embodiment, one or more high thermal conductivity electrically insulating structures 201 fill substantially all portions of the second back metal layer BM1 not occupied by the conductive structures 202 and the corresponding through holes 602, and low thermal conductivity dielectric structures 203 fill substantially all portions of the third back metal layer BM2 not occupied by the conductive structures 202 and the corresponding through holes 602. Figure 8C In the embodiment, one or more high thermal conductivity electrically insulating structures 201 fill substantially all portions of the third back metal layer BM2 not occupied by the conductive structure 202 and the corresponding through-hole 602, while the low thermal conductivity dielectric structure 203 or the low thermal conductivity dielectric layer 203A fills substantially all portions of the second back metal layer BM1 not occupied by the conductive structure 202 and the corresponding through-hole 602.

[0049] Fig.9A and Fig. 9B 1 shows a cross-sectional view of some embodiments of IC devices according to the present disclosure, wherein the function of one or more of the plurality of conductive structures is changed. Fig.9A In FIG. 6 , those conductive structures 202 in the second backside metal layer BM1 that are not connected to corresponding vias 602 can each be used as a signal or power connection 902. Fig. 9BOf those conductive structures 202 in the second backside metal layer BM1 that are not connected to the corresponding vias 602, some may be used as signal or power connectors 902, while one or more other conductive structures 202 may be used as "dummy" connectors 904. In some embodiments, the dummy connectors 904 may not be connected to signal or power levels, but may be used primarily as thermal paths to distribute thermal energy, as described above. In other embodiments, in addition to being used as thermal conductors, the dummy connectors 904 may also be connected to a ground connection (e.g., to reduce noise coupling between signals).

[0050] Figure 10A-10C A plan view, a first cross-sectional view, and a second cross-sectional view are respectively shown of some embodiments of an IC device according to the present disclosure, the IC device employing a plurality of discrete high thermal conductivity electrically insulating structures connected to a plurality of electrically conductive structures. Figure 10A-10C As shown, a plurality of high thermal conductivity electrical insulation structures 201 (eg, Fig. 10A Left and right in the text) can be combined similarly to the above Figure 6A-6C The first back metal layer BM0 is coupled to the plurality of conductive structures 202 in the second back metal layer BM1 in the same manner as discussed above. Although the high thermal conductivity electrically insulating structure 201 is shown as Fig. 7A The second backside metal layer BM1 is filled in the manner shown, but Figure 7B , Figure 7C and Figure 8A-8C Other configurations of the high thermal conductivity electrical insulation structure 201 shown may also be used with Figure 10A-10C Related embodiments.

[0051] Figures 11A-11C 1 and 2 respectively show a plan view, a first cross-sectional view, and a second cross-sectional view of some embodiments of IC devices according to the present disclosure that employ a single high thermal conductivity electrically insulating structure connected to multiple electrically conductive structures. Figures 11A-11C As shown, a single continuous high thermal conductivity electrical insulation structure 201 is connected to a plurality of conductive structures 202 in the second backside metal layer BM1. Fig. 7A The second backside metal layer BM1 is filled in the manner shown, but Figure 7B , Figure 7C and Figure 8A-8C Other configurations of the high thermal conductivity electrical insulation structure 201 shown may also be used with Figures 11A-11C Related embodiments.

[0052] FIG. 12A to FIG. 12L The invention shows a method of using multiple high thermal conductivity electrical insulation structures (e.g., Figure 10A-10C ) are cross-sectional views of some embodiments of IC devices. FIG. 12A to FIG. 12LDescribed as a series of actions, it should be understood that these actions are not limiting, as in other embodiments, the order of actions within each series may be changed, and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part. In addition, in some embodiments, the high thermal conductivity electrical insulation structure may include diamond, although other materials with high thermal conductivity (e.g., greater than 1 W / mK, 2 W / mK, 5 W / mK, 10 W / mK, 20 W / mK, 30 W / mK or more W / mK, depending on the embodiment) may be included. For example, some diamonds may have dielectric properties including a low dielectric constant of 5.7 and a high dielectric strength of 1000000 V / cm.

[0053] For example, Fig. 12A A substrate 102 (eg, a semiconductor substrate such as a silicon substrate) is shown. In some embodiments, the substrate 102 is used as a substrate for a backside metal (BSM) region, such as Figure 1 The BSM 110, whose manufacturing process will be combined below Figure 12B-12L In addition, in some embodiments, the substrate 102 can be used as a substrate for a front side metal (FSM) region, such as Figure 1 However, to simplify the following discussion, Figure 12A-12L Not clearly shown Figure 1 FSM 120 or other parts of IC device 100. In addition, in some embodiments, substrate 102 may be a substrate that has been thinned to facilitate forming FSM 120 and BSM 110 on opposite surfaces of substrate 102. In addition, in some embodiments, substrate 102 may include doped regions (e.g., Figure 1 doped region 104), but to simplify the following discussion, Figure 12A-12L These areas are not depicted.

[0054] Fig. 12B The low thermal conductivity dielectric layer 203 is shown to be formed (e.g., deposited) on the substrate 102. As described above, in some embodiments, the low thermal conductivity dielectric layer 203 may include at least one dielectric material, including but not limited to silicon oxide (SiO x ) (e.g., silicon oxide (SiO2)), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc.

[0055] Fig. 12CA plurality of trenches 1202 are shown formed (eg, etched) on the upper surface of the low thermal conductivity layer 203. In some embodiments, the trenches 1202 may extend partially (eg, approximately halfway) into the low thermal conductivity dielectric layer 203.

[0056] Fig.12D The formation (e.g., deposition) of at least one conductive structure 202 is shown to substantially complete the first backside metal layer BM0. In some embodiments, the at least one conductive structure 202 may be used to provide power and / or signal connections between the substrate 102 and other conductive structures disposed above the first backside metal layer BM0. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), may be performed after the formation of the at least one conductive structure 202. In some embodiments, the conductive structure 202 may include a metal (e.g., copper (Cu)), a metal alloy, or another conductive material.

[0057] Fig.12E The second low thermal conductivity dielectric layer 203 is shown to be formed (e.g., deposited) on the first low thermal conductivity dielectric layer 203 and at least one conductive structure 202 of the first backside metal layer BM0. In some embodiments, the second low thermal conductivity dielectric layer 203 may include but is not limited to SiO x (e.g., SiO2), carbon-doped SiO2, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, porous dielectric materials, etc. In addition, the second low thermal conductivity dielectric layer 203 may include a dielectric material that is the same as or different from the first low thermal conductivity dielectric layer 203 of BM0. In addition, in some embodiments, before forming the second low thermal conductivity dielectric layer 203, an ESL may be formed on the first backside metal layer BM0.

[0058] Fig.12F It is shown that a plurality of trenches 1204 are formed (eg, etched) in the second low thermal conductivity dielectric layer 203. Fig.12F The trench 1204 is depicted as extending to the upper surface of the first backside metal layer BM0 , but in some embodiments, the trench 1204 may partially extend to the upper surface of the first backside metal layer BM0 .

[0059] Figure 12G The deposition (e.g., seeding) of crystals 1206 of a high thermal conductivity electrically insulating material (e.g., diamond) is shown. In some embodiments, the crystals 1206 form a thin layer (e.g., one to two crystal depths) on the remaining upper surface of the second low thermal conductivity layer 203 and the surface of the trench 1204. In some embodiments, the seeding can be achieved by ultrasonic deposition, spin coating, ultrasonic assisted polymerization, or another process for substantially uniformly depositing the crystals 1206 (e.g., as a thin layer) on the upper surface of the second low thermal conductivity layer 203 and the surface of the trench 1204.

[0060] Fig.12H Deposition (e.g., growth of grains) of highly thermally conductive electrically insulating material 1208 is shown on crystal 1206 (e.g., in and between trenches 1204). In some embodiments, such deposition may be performed using microwave induced plasma chemical vapor deposition (CVD) (e.g., using methane (CH3), hydrogen (H2), oxygen (O2), and / or another gas) or another process for forming dielectric or insulating materials.

[0061] In some embodiments, Figure 12G Related crystal seeds and Fig.12H The growth of the corresponding grains may represent a two-step deposition process of the high thermal conductivity electrically insulating material 1208 that complies with the thermal budget allocated for the manufacturing process (eg, back end of line (BEOL) process) of the BSM 110 of the IC device 100 .

[0062] Fig.12I The removal (e.g., by planarization) of excess high thermal conductivity electrically insulating material 1208 between trenches 1204 is shown to form a plurality of high thermal conductivity electrically insulating structures 201. In some embodiments, this removal results in the completion of a second backside metal layer BM1 including a plurality of high thermal conductivity electrically insulating structures 201. In some embodiments, this removal may be performed using chemical mechanical planarization (CMP) or another material removal method to complete an upper surface 1210 of the second backside metal layer BM1.

[0063] Furthermore, in some embodiments, in combination with forming the high thermal conductivity electrical insulation structure 201, a plurality of conductive structures 202 (eg, Fig. 10A and Fig. 10B ), so that they are connected to the high thermal conductivity electrical insulation structure 201. For example, in some embodiments, after removing Fig.12I After that, a groove ( Fig.12I ), the trench is perpendicular to the plurality of high thermal conductivity electrically insulating structures 201. Thereafter, such trenches may be filled with a conductive material (eg, copper or another metal or metal alloy) to form a plurality of conductive structures 202.

[0064] Fig.12J FIG. 2 shows that a third low thermal conductivity dielectric layer 203 is formed (e.g., deposited) on the second backside metal layer BM1. In some embodiments, the third low thermal conductivity dielectric layer 203 may include one or more dielectric materials (e.g., SiO x(e.g. SiO2), carbon-doped SiO2, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, porous dielectric materials, etc.).

[0065] Figure 12K A plurality of trenches 1212 are shown formed (eg, etched) at an upper surface of the third low thermal conductivity dielectric layer 203. In some embodiments, the trenches 1212 may extend partially (eg, approximately halfway) into the third low thermal conductivity dielectric layer 203.

[0066] Figure 12L At least one conductive structure 202 is shown formed (e.g., deposited) to substantially complete the third backside metal layer BM2 and form TCN 101. In some embodiments, at least one conductive structure 202 may be used to connect the conductive structures 202 of the second backside metal layer BM1 and conductors associated with the package of the IC device (e.g., Figure 1 The conductive structure 202 may be provided with a solder bump 123 of the IC device 100 to provide power and / or signal connection. In some embodiments, a planarization operation, such as CMP, may be performed after forming at least one conductive structure 202. In some embodiments, the conductive structure 202 may include a metal (e.g., copper (Cu)), a metal alloy, or another conductive material. In some embodiments, the resulting TCN 101 may be formed with a solder bump 123 of the IC device 100. Figure 12L The cross-sectional view can be compared with Fig. 10A Similar markings correspond to the relevant sections in the figure.

[0067] Fig.13A and Fig. 13B A cross-sectional view of some embodiments of two-step etching of a thermally conductive and electrically insulating structure prior to depositing a plurality of conductive structures according to the present disclosure is shown. In some embodiments, Fig.13A and 13B Depicted with the above Fig. 10B and Fig. 11B More specifically, Fig.13A The removal (e.g., etching) of the trench 1302 of each conductive structure formed in the high thermal conductivity electrically insulating structure 201 in the second back metal layer BM1 is shown. In some embodiments, each trench 1302 may extend partially (e.g., halfway) from the upper surface of the high thermal conductivity electrically insulating structure 201 to the upper surface of the underlying first back metal layer BM0 (e.g., the upper surface of the conductive structure 202 therein). This first trenching step is followed by a second trenching step, such as Fig. 13B As shown, additional trenches 1304 are provided within those previous trenches 1302, wherein vias will be employed to connect the corresponding conductive structures to the conductive structures 202 of the first backside metal layer BM0.

[0068] Fig.14A and Fig. 14BA cross-sectional view of some embodiments of one-step etching of a thermally conductive and electrically insulating structure prior to depositing a plurality of conductive structures according to the present disclosure is shown. Fig.13A and Fig. 13B As in the case of Fig.14A and Fig. 14B It is also possible to depict the above Fig. 10B and Fig. 11B More specifically, Fig.14A A plurality of trenches 1302 are shown removed (e.g., etched) from the high thermal conductivity electrically insulating structure 201 in the second backside metal layer BM1. In some embodiments, a trench 1302 is formed for each conductive structure that is not coupled to the underlying via to connect to the conductive structure 202 of the first backside metal layer BM0. Fig.13A and Fig. 13B As is the case with embodiments of the present invention, in some embodiments, Fig.14A Each of the grooves 1302 may extend from the upper surface of the high thermal conductivity electrical insulation structure 201 to a portion (eg, half) of the upper surface of the first back metal layer BM0 below. Fig. 14B As shown, a separate trench 1306 is etched for each conductive structure and the associated via of the second backside metal layer BM1 that will be connected to the conductive structure 202 of the first backside metal layer BM0. Fig.13A and Fig. 13B Unlike the embodiments of the present invention, each resulting trench associated with the conductive structure in the second backside metal layer BM1 will be formed using a single etching step.

[0069] Fig.15 A method 1500 for forming an IC device according to some embodiments of the present disclosure is shown, and the IC device uses at least one high thermal conductivity electrically insulating structure coupled to multiple conductive structures. Although the method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, these actions may be performed in an order different from that shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0070] In act 1502, a substrate (e.g., Fig. 12A In some embodiments, the device substrate may be a semiconductor substrate, such as a silicon substrate. Fig. 12A A cross-sectional view of some embodiments corresponding to act 1502 is shown.

[0071] In act 1504, a first dielectric layer (eg, Fig. 12B a first dielectric layer 203). Fig. 12B A cross-sectional view of some embodiments corresponding to act 1504 is shown.

[0072] In action 1506, a plurality of conductive structures (eg, conductive structures 202 of the second backside metal layer BM1) and at least one electrically insulating structure (eg, Fig.12I The at least one electrically insulating structure is adjacent to each of the plurality of conductive structures. The thermal conductivity of the at least one electrically insulating structure is greater than the thermal conductivity of the first dielectric layer. FIG. 12E to FIG. 12I Combination Fig. 10B and Fig. 10C A cross-sectional view of some embodiments corresponding to act 1506 is shown.

[0073] Fig.16 A method 1600 of forming an IC device employing a plurality of high thermal conductivity electrically insulating structures coupled with a plurality of electrically conductive structures is shown in accordance with some embodiments of the present disclosure.

[0074] In some embodiments, act 1502 (providing a substrate, such as Fig. 12A device substrate 102) and action 1504 (forming a first dielectric layer (such as Fig. 12B The first dielectric layer 203)) may be Fig.15 The corresponding action Fig.16 same.

[0075] In act 1606, a second dielectric layer (eg, Fig.12E A second dielectric layer 203 above the first backside metal layer BM0). Fig.12E A cross-sectional view of some embodiments corresponding to act 1606 is shown.

[0076] In act 1608, a plurality of trenches (eg, Fig.12F groove 1204). Fig.12F A cross-sectional view of some embodiments corresponding to act 1608 is shown.

[0077] In action 1610, the plurality of trenches and the upper surface of the second dielectric layer are formed by a crystal of an electrically insulating material (e.g., Figure 12G The electrically insulating material may have a thermal conductivity greater than that of the second dielectric layer. Figure 12G A cross-sectional view of some embodiments corresponding to act 1610 is shown.

[0078] In act 1612, particles of electrically insulating material (e.g., Fig.12H A high thermal conductivity electrically insulating material 1208) is grown on the crystals of the dielectric material. Fig.12H A cross-sectional view of some embodiments corresponding to act 1612 is shown.

[0079] In action 1614, grains and crystals not disposed in the plurality of trenches are removed from the upper surface of the second dielectric layer to form a plurality of electrically insulating structures (eg, Fig.12I High thermal conductivity electrical insulation structure 201). Fig.12I A cross-sectional view of some embodiments corresponding to act 1614 is shown.

[0080] In act 1616, a plurality of conductive structures (eg, Fig. 10A and Fig. 10B In some embodiments, the plurality of electrically insulating structures are adjacent to the plurality of electrically conductive structures. In addition, in some embodiments, the thermal conductivity of the plurality of electrically insulating structures is greater than the thermal conductivity of the first dielectric layer. Fig.12I Combination Fig. 10B and Fig. 10C A cross-sectional view of some embodiments corresponding to act 1616 is shown.

[0081] Some embodiments relate to an IC device. The IC device includes a substrate, a plurality of conductive structures disposed on the substrate and separated from each other, and at least one electrically insulating structure disposed above the substrate and directly contacting each of the plurality of conductive structures. The at least one electrically insulating structure has a thermal conductivity greater than 5 watts per meter Kelvin (W / mK).

[0082] In some embodiments, at least one electrically insulating structure comprises diamond.

[0083] In some embodiments, the at least one electrically insulating structure includes at least one of diamond, aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (SiN), boron nitride (BN), or beryllium oxide (BeO).

[0084] In some embodiments, at least one electrically insulating structure contacts a lower surface of each of the plurality of electrically conductive structures.

[0085] In some embodiments, at least one electrically insulating structure contacts a substrate-facing surface of each of the plurality of electrically conductive structures.

[0086] In some embodiments, at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures facing away from the substrate.

[0087] In some embodiments, at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures that faces an adjacent one of the plurality of electrically conductive structures.

[0088] In some embodiments, at least one electrically insulating structure is a single continuous electrically insulating layer.

[0089] In some embodiments, the at least one electrically insulating structure includes a plurality of electrically insulating structures, each of the plurality of electrically insulating structures having a longitudinal major axis extending perpendicular to a longitudinal major axis of each of the plurality of electrically conductive structures.

[0090] In some embodiments, the at least one electrically insulating structure includes a plurality of electrically insulating structures, each of the plurality of electrically insulating structures filling a majority of the space between each of the plurality of electrically conductive structures.

[0091] In some embodiments, the integrated circuit device further includes: at least one first additional conductive structure disposed between the substrate and the plurality of conductive structures; and at least one first conductive via coupling one of the at least one first additional conductive structure to one of the plurality of conductive structures.

[0092] In some embodiments, the integrated circuit device further includes: at least one second additional conductive structure disposed above the plurality of conductive structures opposite to the substrate; and at least one second conductive via coupling one of the at least one second additional conductive structure to one of the plurality of conductive structures.

[0093] Some embodiments relate to another IC device. The IC device includes a substrate, a first dielectric layer disposed on the substrate, a plurality of conductive structures disposed on the first dielectric substrate and separated from each other, and at least one electrically insulating structure disposed on the first dielectric layer and adjacent to each of the plurality of conductive structures. The thermal conductivity of the at least one electrically insulating structure is greater than the thermal conductivity of the first dielectric layer.

[0094] In some embodiments, the at least one electrically insulating structure includes an additional electrically insulating layer in contact with the first dielectric layer.

[0095] In some embodiments, the integrated circuit device also includes: a first additional dielectric layer, disposed above the first dielectric layer and in contact with the first dielectric layer, wherein at least one electrically insulating structure is disposed above the first additional dielectric layer and in contact with the first additional dielectric layer, and the thermal conductivity of the at least one electrically insulating structure is greater than the thermal conductivity of the second additional dielectric layer.

[0096] In some embodiments, the integrated circuit device also includes: a first conductive structure disposed in a first dielectric layer; a first conductive via connecting the first conductive structure to at least one of a plurality of conductive structures; and a second dielectric layer disposed above at least one electrically insulating structure and a plurality of conductive structures; a second conductive structure disposed in the second dielectric layer; and a second conductive via connecting the second conductive structure to at least one of the plurality of conductive structures.

[0097] Some embodiments relate to a method of forming an integrated circuit device. The method includes providing a substrate, forming a first dielectric layer on the substrate, and forming a plurality of conductive structures and at least one electrically insulating structure on the first dielectric layer. The at least one electrically insulating structure is adjacent to each of the plurality of conductive structures, and the thermal conductivity of the at least one electrically insulating structure is greater than the thermal conductivity of the first dielectric layer.

[0098] In some embodiments, at least one electrically insulating structure includes a plurality of electrically insulating structures, and wherein the method further includes: forming a second dielectric layer above the first dielectric layer before forming the plurality of conductive structures and the plurality of electrically insulating structures, wherein forming the plurality of electrically insulating structures includes: etching a plurality of grooves in the second dielectric layer through an upper surface of the second dielectric layer; seeding crystals in the plurality of grooves and the upper surface of the second dielectric layer with an electrically insulating material having a thermal conductivity greater than that of the second dielectric layer; growing grains of the electrically insulating material on the crystals of the electrically insulating material; and removing grains and crystals from the second dielectric layer that are not disposed in the plurality of grooves.

[0099] In some embodiments, chemical mechanical planarization is used to remove grains and crystals that are not disposed in the plurality of trenches.

[0100] In some embodiments, the electrically insulating material includes diamond.

[0101] It should be understood that in this written description and in the claims that follow, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0102] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, comprising: substrate; a plurality of conductive structures disposed above the substrate and separated from each other; as well as At least one electrically insulating structure is disposed over the substrate and directly contacts each of the plurality of electrically conductive structures, the at least one electrically insulating structure having a thermal conductivity greater than 5 Watts per meter Kelvin.

2. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure comprises diamond.

3. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure includes at least one of diamond, aluminum nitride (AlN), silicon carbide (SiC), silicon nitride (SiN), boron nitride (BN), or beryllium oxide (BeO).

4. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure contacts a lower surface of each of the plurality of electrically conductive structures.

5. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures that faces the substrate.

6. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures facing away from the substrate.

7. The integrated circuit device according to claim 1, wherein: The at least one electrically insulating structure contacts a surface of each of the plurality of electrically conductive structures that faces an adjacent one of the plurality of electrically conductive structures.

8. An integrated circuit device comprising: substrate; A first dielectric layer disposed above the substrate; a plurality of conductive structures disposed above the first dielectric layer and separated from each other; as well as At least one electrically insulating structure is disposed over the first dielectric layer and adjacent to each of the plurality of electrically conductive structures, the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer.

9. A method of forming an integrated circuit device, comprising: providing a substrate; forming a first dielectric layer over the substrate; as well as A plurality of electrically conductive structures and at least one electrically insulating structure are formed over the first dielectric layer, the at least one electrically insulating structure abutting each of the plurality of electrically conductive structures, the at least one electrically insulating structure having a thermal conductivity greater than a thermal conductivity of the first dielectric layer.

10. The method according to claim 9, wherein: The at least one electrically insulating structure comprises a plurality of electrically insulating structures, and wherein the method further comprises: Before forming the plurality of conductive structures and the plurality of electrically insulating structures, forming a second dielectric layer over the first dielectric layer, wherein forming the plurality of electrically insulating structures comprises: etching a plurality of trenches in the second dielectric layer through an upper surface of the second dielectric layer; seeding crystals in the plurality of trenches and the upper surface of the second dielectric layer with an electrically insulating material having a thermal conductivity greater than a thermal conductivity of the second dielectric layer; growing grains of electrically insulating material on said crystals of said electrically insulating material; and The grains and the crystals not disposed in the plurality of trenches are removed from the second dielectric layer.

Images