Semiconductor package

Abstract

The invention relates to a semiconductor package. The semiconductor package comprises a package substrate; a connection substrate disposed on the package substrate; a first semiconductor chip disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip; a molding layer disposed on the package substrate and at least partially covering the connection substrate, the first semiconductor chip, and the second semiconductor chip; and a light guide member extending into the molding layer and disposed on the second semiconductor chip.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0098231 filed in the Korean Intellectual Property Office on July 27, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package having an increased light-condensing capability. Background Art

[0003] The demand for portable devices has increased in the recent electronic product market, and thus the reduction in size and weight of electronic components mounted on the portable devices has been continuously required. In order to achieve the reduction in size and weight of electronic components, a technology capable of integrating multiple individual devices into a single package and a technology for reducing the size of each mounted component are required. Summary of the invention

[0004] Some embodiments of the inventive concept provide a semiconductor package having increased light-condensing capability.

[0005] Some embodiments of the inventive concept provide a semiconductor package in which a light guide member is formed to induce total reflection to minimize optical loss and reduce optical noise.

[0006] The objects of the inventive concept are not limited to the above-mentioned objects, and those skilled in the art will clearly understand other objects that have not been mentioned above through the following description.

[0007] According to some embodiments conceived in the present invention, a semiconductor package may include: a packaging substrate; a connecting substrate disposed on the packaging substrate; a first semiconductor chip disposed on the connecting substrate; a second semiconductor chip disposed on the connecting substrate and separated from the first semiconductor chip; a molding layer disposed on the packaging substrate and at least partially covering the connecting substrate, the first semiconductor chip and the second semiconductor chip; and a light guide member extending into the molding layer and disposed on the second semiconductor chip.

[0008] According to some embodiments of the present inventive concept, a semiconductor package may include: a packaging substrate; a connection substrate disposed on the packaging substrate; a first semiconductor chip disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip; a molding layer disposed on the packaging substrate and at least partially covering the first semiconductor chip; and a light guide member extending into the molding layer and contacting a top surface of the second semiconductor chip. A bottom surface of the molding layer may be located on a plane lower than a bottom surface of the light guide member, wherein the packaging substrate defines a base reference plane.

[0009] According to some embodiments of the present invention, a semiconductor package may include: a package substrate; and a connection substrate disposed on the package substrate, the connection substrate including a base substrate, a plurality of upper pads on the top surface of the base substrate, a plurality of lower pads on the bottom surface of the base substrate, and a plurality of through-vias extending into the base substrate and connecting the upper pads to the lower pads. The semiconductor package may also include: a first semiconductor chip disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip in a first direction; a molding layer disposed on the package substrate and at least partially covering the first semiconductor chip, the second semiconductor chip and the connection substrate; a plurality of first connection terminals connecting the upper pad of the connection substrate to the first semiconductor chip and connecting the upper pad of the connection substrate to the second semiconductor chip; a plurality of second connection terminals connecting the package substrate to the lower pad of the connection substrate; and a light guide member penetrating the molding layer and disposed on the second semiconductor chip to guide the path of light. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Simplified plan views showing semiconductor packages according to some embodiments of the inventive concept are shown.

[0011] Figure 2 FIG. 1 shows a semiconductor package according to some embodiments of the present inventive concept. Figure 1 A cross-sectional view of a semiconductor package taken along line AA′.

[0012] Figure 3A Shows the display Figure 2 FIG. 1 is an enlarged cross-sectional view of a portion P of a semiconductor package.

[0013] Figure 3B FIG. 1 shows some embodiments of the present invention. Figure 3A An enlarged cross-sectional view of a modified example of a semiconductor package.

[0014] Figure 4 FIG. 1 shows some embodiments of the present invention. Figure 2 An enlarged cross-sectional view of a second semiconductor chip of a semiconductor package.

[0015] Figures 5 to 7 Cross-sectional views showing semiconductor packages according to some embodiments of the inventive concept are illustrated.

[0016] Figures 8 to 12 Cross-sectional views showing a method of manufacturing a semiconductor package according to some embodiments of the inventive concept are illustrated. DETAILED DESCRIPTION

[0017] Now, some embodiments of the inventive concept will be described below with reference to the accompanying drawings. Throughout the description, like reference numerals may represent like components.

[0018] Figure 1 Simplified plan views showing semiconductor packages according to some embodiments of the inventive concept are shown. Figure 2 FIG. 1 shows a semiconductor package according to some embodiments of the present inventive concept. Figure 1 A cross-sectional view of a semiconductor package taken along line AA′. Figure 3A Shows the display Figure 2 FIG. 1 is an enlarged cross-sectional view of a portion P of a semiconductor package. Figure 3B FIG. 1 shows some embodiments of the present invention. Figure 3A An enlarged cross-sectional view of a modified example of a semiconductor package. Figure 4 FIG. 1 shows some embodiments of the present invention. Figure 2 An enlarged cross-sectional view of a second semiconductor chip of a semiconductor package.

[0019] Reference Figures 1 to 4 In some embodiments, the semiconductor package may include first and second semiconductor chips 100 and 200 , a connection substrate 110 , a light guide member 300 , and a package substrate 500 .

[0020] like Figure 2 As shown in FIG. 1 , the first semiconductor chip 100 and the second semiconductor chip 200 may be disposed on a top surface of the connection substrate 110. The first semiconductor chip 100 and the second semiconductor chip 200 may be connected to the connection substrate 110 through one or more first connection terminals 50.

[0021] In some embodiments, Figure 2 As shown in , the first semiconductor chip 100 may have a plurality of chip pads (pads, or pads) 11 on its bottom surface, and the second semiconductor chip 200 may have a plurality of chip pads 21 on its bottom surface. The first connection terminal 50 may be attached to the chip pads 11 of the first semiconductor chip 100 and the chip pads 21 of the second semiconductor chip 200. The first connection terminal 50 may be one or more of a solder ball, a conductive bump, and a conductive column. The first connection terminal 50 may include at least one metal material selected from copper, tin, and lead.

[0022] The first semiconductor chip 100 may be a logic chip including a processor such as a microelectromechanical system (MEMS) device, an optoelectronic device, a central processing unit (CPU), a graphic processing unit (GPU), a mobile application, or a digital signal processor (DSP).

[0023] like Figure 2As shown in, in some embodiments, the second semiconductor chip 200 may be spaced apart from the first semiconductor chip 100 (e.g., in the first direction) and disposed on the connection substrate 110. Here, the first direction may be a direction parallel to the top surface of the connection substrate 110, but is not limited thereto. The second semiconductor chip 200 may include at least one selected from a light emitting device and a passive device. For example, in some embodiments, when the second semiconductor chip 200 is a light emitting device, the light emitted from the second semiconductor chip 200 may pass through the light guide member 300 and escape from the semiconductor package. Alternatively, in some embodiments, when the second semiconductor chip 200 is a passive device, the light incident on the semiconductor package may pass through the light guide member 300 and converge on the second semiconductor chip 200. The light emitting device may include at least one selected from a light emitting diode (LED), an organic light emitting diode (OLED), and a laser diode. The passive device may include at least one selected from an image sensor (e.g., CIS), a charge coupled device (CCD), a fingerprint sensor, a proximity sensor, an optical sensor, a solar cell, and a light detection sensor.

[0024] In some embodiments, Figure 2 As shown in , the connection substrate 110 can be disposed on the package substrate 500 and connected to the package substrate 500 through one or more second connection terminals 150. The connection substrate 110 may include a chip area and an edge area surrounding the chip area. In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 may be disposed on the chip area of ​​the connection substrate 110.

[0025] Still refer to Figure 2 In some embodiments, the connection substrate 110 may include a base substrate 111 , a plurality of through vias 113 , a redistribution layer including a plurality of connection lines 117 , and a plurality of lower pads 115 and a plurality of upper pads 119 .

[0026] In some embodiments, the base substrate 111 may be a silicon substrate or a silicon on insulator (SOI) substrate. Alternatively, in some embodiments, the base substrate 111 may be a glass substrate, a ceramic substrate, a polymer substrate, or any suitable substrate that can provide appropriate protection and / or interconnection functions. The base substrate 111 may include active electronic devices and / or passive electronic devices. A passivation dielectric layer may be provided on each of the top surface and the bottom surface of the base substrate 111.

[0027] A plurality of through vias 113 may penetrate the base substrate 111 , and the through vias 113 and the connection lines 117 may include a metal material such as tungsten (W), aluminum (Al), or copper (Cu).

[0028] The lower pad 115 may be disposed on the bottom surface of the connection substrate 110, and the upper pad 119 may be disposed on the top surface of the connection substrate 110. The lower pad 115 may be electrically connected to the upper pad 119 through a plurality of through vias 113 and connection lines 117.

[0029] The second connection terminal 150 may be attached to the lower pad 115 of the connection substrate 110. The second connection terminal 150 may be electrically connected to the upper pad 119 through the lower pad 115, the through via 113, and the connection line 117. The second connection terminal 150 may be a solder ball formed of one or more of tin, lead, and copper.

[0030] Similarly, the first connection terminals 50 may be attached to the upper pads 119 of the connection substrate 110. The first connection terminals 50 may connect the upper pads 119 to the first semiconductor chip 100, and may connect the upper pads 119 to the second semiconductor chip 200.

[0031] In some embodiments, Figure 2 As shown in FIG. 1 , a molding layer (or referred to as a molding layer) 120 may be disposed on the package substrate 500. The molding layer 120 may be disposed on the top surface of the connection substrate 110 or on the top surface of the package substrate 500. For example, Figure 2 As shown in , in some embodiments, when the molding layer 120 is disposed on the top surface of the encapsulation substrate 500, the sidewalls of the molding layer 120 may be aligned with the sidewalls of the encapsulation substrate 500. The molding layer 120 may be disposed on the top surface of the encapsulation substrate 500 so as to cover the sidewalls of the connection substrate 110. Therefore, the bottom surface 120b of the molding layer 120 may be in contact with the top surface of the encapsulation substrate 500. In some embodiments, the bottom surface 120b of the molding layer 120 may be positioned lower relative to the bottom surface 300b of the light guide member 300 and the bottom surface of the connection substrate 110.

[0032] In some embodiments, the molding layer 120 may cover the first semiconductor chip 100, and may also cover at least a portion of the connection substrate 110 and at least a portion of the second semiconductor chip 200. A top surface 120a of the molding layer 120 may be coplanar with a top surface 300a of the light guide member 300. In addition, in some embodiments, a bottom surface 120b of the molding layer 120 may contact the top surface of the connection substrate 110, and may be located on a lower plane relative to the bottom surface 300b of the light guide member 300. The molding layer 120 may include a dielectric polymer such as an epoxy molding compound (EMC).

[0033] Still refer to Figure 2In some embodiments, the first bottom filling layer 160 may be disposed between the first semiconductor chip 100 and the connection substrate 110 and between the second semiconductor chip 200 and the connection substrate 110. The first bottom filling layer 160 may be disposed between the first connection terminals 50 and fill the space between the first connection terminals 50 in some embodiments. The first bottom filling layer 160 may include, for example, a heat-curable resin or a photo-curable resin. The first bottom filling layer 160 may also include an inorganic filler or an organic filler. The second bottom filling layer 260 may be disposed between the connection substrate 110 and the encapsulation substrate 500 and fill the space between the connection substrate 110 and the encapsulation substrate 500 in some embodiments. The second bottom filling layer 260 may include a material that is the same as that of the first bottom filling layer 160 or a material that is similar to that of the first bottom filling layer 160.

[0034] In some embodiments, Figure 2 As shown in FIG. 1 , the light guide member 300 may be disposed on the top surface of the second semiconductor chip 200 (see also FIG. 3A to FIG. 3B ), and may be optically transparent. Therefore, light may pass through the light guide member 300 to reach the second semiconductor chip 200. However, the light guide member 300 may converge light incident on the second semiconductor chip 200 from the upper side of the second semiconductor chip 200 or light emitted from the second semiconductor chip 200 toward the upper side of the second semiconductor chip 200.

[0035] Reference Figure 2 , Figure 3A and Figure 4 , in some embodiments, light may move to the second semiconductor chip 200 through the light guide member 300. Light may be incident on the light guide member 300 through the upper surface of the light guide member 300. In some embodiments, the light guide member 300 may have a refractive index greater than that of the mold layer 120, and light in the light guide member 300 may be totally reflected in the light guide member 300. Therefore, most of the light incident on the light guide member 300 may move to the second semiconductor chip 200. For example, in some embodiments, about 80% or more of the light incident on the light guide member 300 may move to the second semiconductor chip 200.

[0036] The light guide member 300 can reduce optical loss by causing total reflection of incident light, and reduce optical noise by fundamentally suppressing diffuse reflection of light caused by other structures.

[0037] like Figure 3A and Figure 3B As shown in FIG. 3 , the light guide member 300 may have a diameter that decreases in a direction from the top surface 300 a toward the bottom surface 300 b (see also FIG. 3 ). Figure 2). For example, in some embodiments, the light guide member 300 may have a tapered shape in which the diameter decreases as the distance from the second semiconductor chip 200 decreases. The diameter W1 of the top surface 300a of the light guide member 300 may be greater than the width W2 of the top surface of the second semiconductor chip 200. The width W2 of the top surface of the second semiconductor chip 200 may refer to a length in a direction parallel to the diameter W1 of the top surface 300a of the light guide member 300. Therefore, the top surface 300a of the light guide member 300 may receive a large amount of external incident light, and the incident light may be transmitted to the second semiconductor chip 200. For example, in some embodiments, the top surface 300a of the light guide member 300 may receive 80% or more of the external incident light that may be transmitted to the second semiconductor chip 200.

[0038] According to some embodiments of the inventive concept, a semiconductor package may have increased light-condensing efficiency.

[0039] The light guide member 300 may include at least one selected from silicon (Si), nitrogen (N), carbon (C), and metal oxide.

[0040] According to some embodiments of the present inventive concept, the light guide member 300 may include a lens. For example, in some embodiments, at least a portion of the light guide member 300 may be formed by a lens. In some embodiments, the path of light may change as the light passes through the lens. In some embodiments, the lens may be formed of glass or plastic, but the present inventive concept is not limited thereto.

[0041] The second semiconductor chip 200 may receive light having passed through the light guide member 300. As discussed above, the second semiconductor chip 200 may include a passive device such as an image sensor (eg, CIS).

[0042] Now refer to Figure 4 In some embodiments, the image sensor (i.e., passive device) of the second semiconductor chip 200 may include a microlens L, a color filter CF, and a photoelectric conversion element PD. The microlens L and the color filter CF may converge and filter incident light, and may provide light to the photoelectric conversion element PD. The photoelectric conversion element PD may be disposed on each of a plurality of pixel regions PR. In the photoelectric conversion element PD, a pn junction may constitute a photodiode, and the photodiode may generate and accumulate photocharges proportional to the intensity of the incident light. According to an embodiment of the inventive concept, the amount of light incident on the microlens L and the color filter CF may be increased.

[0043] Figure 3B According to the embodiment of the present invention Figure 3A2 is an enlarged view of a modified example of a semiconductor package of FIG. 1 , showing a semiconductor package having a light emitting device provided as a second semiconductor chip 200 .

[0044] like Figure 3B As shown in , in some embodiments, when the light emitting device is provided as the second semiconductor chip 200, the light emitting device may be used as a light source. Light emitted from the light emitting device may be incident on the light guide member 300 positioned on the top surface of the second semiconductor chip 200. Figure 3A , in some embodiments, the light guide member 300 may have a higher refractive index than the mold layer 120, and light incident on the light guide member 300 may be totally reflected at the interface between the mold layer 120 and the light guide member 300. In some embodiments, most of the light emitted from the light emitting device may be transmitted to the outside of the semiconductor package. For example, in some embodiments, about 80% or more of the light emitted from the light emitting device may be transmitted to the outside of the semiconductor package.

[0045] Return to reference Figures 1 to 4 In some embodiments, the package substrate 500 may be, for example, a printed circuit board, a flexible substrate, or a carrier substrate. For example, in some embodiments, the package substrate 500 may be one of a flexible printed circuit board, a rigid printed circuit board, and any combination thereof, each board including internal wiring 521 formed therein.

[0046] like Figure 2 As shown in , the package substrate 500 may have a top surface and a bottom surface facing away from each other, and may include a plurality of upper bonding pads 511, a plurality of external bonding pads 513, and internal wiring 521 extending between the plurality of upper bonding pads 511 and the plurality of external bonding pads 513. The upper bonding pads 511 may be arranged on the top surface of the package substrate 500, and the external bonding pads 513 may be arranged on the bottom surface of the package substrate 500. The upper bonding pads 511 may be electrically connected to the corresponding external bonding pads 513 through the internal wiring 521. In some embodiments, external bonding terminals 550 may be attached to the external bonding pads 513. A ball grid array (BGA) may be provided as the external bonding terminal 550.

[0047] Figures 5 to 7 A cross-sectional view of a semiconductor package according to some embodiments of the present invention is shown. Figures 1 to 4 The technical features discussed are the same technical features, and their differences will be described in detail below.

[0048] Reference Figure 5In some embodiments, the first bottom filling layer may be omitted between the connection substrate 110 and the first semiconductor chip 100 and between the connection substrate 110 and the second semiconductor chip 200 (see, for example, Figure 2 160). Alternatively, in some embodiments, the molding layer 120 may be disposed between the connection substrate 110 and the bottom surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200, and in some embodiments fills the space between the connection substrate 110 and the bottom surface of the first semiconductor chip 100 and the bottom surface of the second semiconductor chip 200. In addition, in some embodiments, the second bottom filling layer may be omitted between the connection substrate 110 and the package substrate 500 (see, for example, Figure 2 260). Similarly, in some embodiments, the molding layer 120 may also be disposed between the connection substrate 110 and the packaging substrate 500, and in some embodiments fills the space between the connection substrate 110 and the packaging substrate 500.

[0049] Reference Figure 6 In some embodiments, a first lens 310 may be additionally disposed on the top surface of the light guide member 300. The first lens 310 may be in contact with the top surface of the light guide member 300, and may refract light incident from the outside on the light guide member 300. For example, in some embodiments, light vertically incident on the light guide member 300 may be refracted and converged on the second semiconductor chip 200.

[0050] Reference Figure 7 In some embodiments, a second lens 320 may be additionally disposed on the bottom surface of the light guide member 300. The second lens 320 may be in contact with the bottom surface 300 b of the light guide member 300, and may refract light having passed through the light guide member 300. The second lens 320 may cause the light to be refracted and vertically incident toward the second semiconductor chip 200.

[0051] The first lens 310 and the second lens 320 may have a refractive index different from that of the light guide member 300. For example, in some embodiments, the first lens 310 may have a refractive index smaller than that of the light guide member 300, and the second lens 320 may have a refractive index greater than that of the light guide member 300. Therefore, light may be additionally refracted when passing through the first lens 310 and the second lens 320. In this sense, the first lens 310 and the second lens 320 may focus light incident on the light guide member 300 on the second semiconductor chip 200. The first lens 310 and the second lens 320 may increase the amount of external incident light and may cause a reduction in image distortion. For example, in some embodiments, the first lens 310 and the second lens 320 may increase the external incident light by about 80% or more.

[0052] In some embodiments, the first lens 310 and the second lens 320 may be fixed to the light guide member 300 by an adhesive. The first lens 310 and the second lens 320 may be formed of glass or plastic, but the inventive concept is not limited thereto.

[0053] Figures 8 to 12 Cross-sectional views showing a method of manufacturing a semiconductor package according to some embodiments of the inventive concept are illustrated.

[0054] Reference Figure 8 In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 may be attached to a connection substrate 110 .

[0055] For example, in some embodiments, the first semiconductor chip 100 may include a plurality of chip pads 11 on a bottom surface thereof, and the second semiconductor chip 200 may include a plurality of chip pads 21 on a bottom surface thereof. The first semiconductor chip 100 and the second semiconductor chip 200 may be disposed on the connection substrate 110 to allow the chip pads 11 and 21 to face the top surface of the connection substrate 110. The chip pads 11 of the first semiconductor chip 100 and the chip pads 21 of the second semiconductor chip 200 may be connected to a plurality of upper pads 119 of the connection substrate 110 through one or more first connection terminals 50. After attaching the first semiconductor chip 100 and the second semiconductor chip 200, the first bottom filling layer 160 may fill the space between the first connection terminals 50. In contrast, as Figure 5 As shown in FIG. 1 , in some embodiments, the formation of the first underfill layer 160 may be omitted.

[0056] Reference Fig. 9 In some embodiments, a light guide member 300 may be provided on the second semiconductor chip 200. For example, in some embodiments, the light guide member 300 may include at least one selected from silicon (Si), nitrogen (N), carbon (C), and metal oxides, and may be molded by supplying at least one selected from silicon (Si), nitrogen (N), carbon (C), and metal oxides to a mold frame and curing the material supplied to the mold frame. Alternatively, in some embodiments, the light guide member 300 may be composed of a single integral lens. In this case, the lens may be formed of glass or plastic and may be injection molded into a single object. The light guide member 300 is not limited to what is discussed above, but may be formed by supplying at least one selected from silicon (Si), nitrogen (N), carbon (C), and metal oxides to a mold frame, curing the material supplied to the mold frame, and partially inserting the lens into the cured material.

[0057] The light guide member 300 may be optically transparent, and may allow most of external incident light to pass through the light guide member 300. For example, in some embodiments, the light guide member 300 may allow 80% or more of external incident light to pass through the light guide member 300. In addition, the light guide member 300 may have a tapered structure in which a diameter decreases in a direction from a top surface to a bottom surface of the light guide member 300, and may allow a large amount of light to reach the second semiconductor chip 200. For example, in some embodiments, the light guide member 300 may allow 80% or more of light to reach the second semiconductor chip 200.

[0058] The light guide member 300 may be disposed on the top surface of the second semiconductor chip 200 and may be in contact with the second semiconductor chip 200. For example, in some embodiments, the light guide member 300 and the second semiconductor chip 200 may be attached by an adhesive tape, and the adhesive tape may be optically transparent. The light guide member 300 may be attached and fixed to the second semiconductor chip 200 by the adhesive tape.

[0059] Reference Fig.10 In some embodiments, a molding layer 120' may be formed to cover the first and second semiconductor chips 100 and 200 and the light guide member 300. The molding layer 120' may have a top surface located on a higher plane relative to the light guide member 300. The molding layer 120' may fill a space between the first and second semiconductor chips 100 and 200. The molding layer 120' may include a dielectric polymer such as an epoxy molding compound (EMC).

[0060] Reference Fig.11 In some embodiments, after forming the molding layer 120', the molding layer (see Fig.10 The thinning process may include a grinding process, a chemical mechanical polishing process, or an etching process. After the thinning process, the thinned molding layer 120 may have a top surface that is positioned substantially coplanar with the top surface of the light guide member 300. In addition, the top surface of the light guide member 300 may be exposed outward from the semiconductor package.

[0061] Reference Fig.12 In some embodiments, a first lens 310 may be disposed on the light guide member 300. The first lens 310 may be in contact with a top surface of the light guide member 300 and may be fixed to the top surface of the light guide member 300 by an adhesive.

[0062] According to some embodiments of the inventive concept, a semiconductor package may have increased light-condensing capability.

[0063] According to some embodiments of the inventive concept, a light guide member may be formed to cause total reflection of incident light, thereby minimizing optical loss, and to fundamentally suppress diffuse reflection of light caused by other structures, thereby reducing optical noise.

[0064] Furthermore, the amount of external incident light can be increased, and a reduction in image distortion can be caused.

[0065] As used herein, an element or region that “covers” or “surrounds” or “fills” another element or region may completely or partially cover or surround or fill the other element or region.

[0066] Although the terms (e.g., first, second, or third) may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the disclosed teachings.

[0067] Although the present invention has been described in conjunction with the embodiments of the invention shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and basic features of the present invention. The subject matter disclosed above is considered to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, improvements and other embodiments that fall within the scope of the present invention. Therefore, to the maximum extent permitted by law, the scope is determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the above detailed description.

Claims

1. A semiconductor package, comprising: Package substrate; A connecting substrate is arranged on the packaging substrate; A first semiconductor chip is disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip; A molding layer is disposed on the packaging substrate and at least partially covers the connection substrate, the first semiconductor chip and the second semiconductor chip; as well as The light guide member extends into the molding layer and is disposed on the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein: A diameter of a top surface of the light guide member is greater than a width of a top surface of the second semiconductor chip.

3. The semiconductor package according to claim 1, wherein: The top surface of the light guide member is coplanar with the top surface of the molding layer.

4. The semiconductor package according to claim 1, wherein: A bottom surface of the molding layer is located on a lower plane relative to a bottom surface of the light guide member, wherein the packaging substrate defines a base reference plane.

5. The semiconductor package according to claim 1, wherein: The bottom surface of the molding layer is located on a lower plane relative to the bottom surface of the connection substrate, wherein the package substrate defines a base reference plane.

6. The semiconductor package according to claim 1, wherein: The refractive index of the light guide member is greater than the refractive index of the molded layer.

7. The semiconductor package according to claim 1, wherein: The second semiconductor chip includes a microlens, a color filter, and a photoelectric conversion element.

8. The semiconductor package according to claim 1, wherein: The light guide member includes a lens.

9. The semiconductor package according to claim 1, wherein: The light guiding member includes silicon, nitrogen, carbon and / or metal oxide. 10 . The semiconductor package of claim 1 , further comprising a first lens contacting a top surface of the light guide member. 11 . The semiconductor package of claim 10 , further comprising a second lens between the light guide member and the connection substrate and in contact with a top surface of the second semiconductor chip.

12. The semiconductor package according to claim 1, wherein A bottom surface of the light guide member is in contact with a top surface of the second semiconductor chip.

13. The semiconductor package according to claim 1, wherein: The second semiconductor chip includes a passive device or a light emitting device.

14. A semiconductor package, comprising: Package substrate; A connecting substrate is arranged on the packaging substrate; A first semiconductor chip is disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip; A molding layer, disposed on the packaging substrate and at least partially covering the first semiconductor chip; as well as a light guide member extending into the molding layer and contacting the top surface of the second semiconductor chip, Wherein, a bottom surface of the molding layer is located on a lower plane relative to a bottom surface of the light guide member, and wherein the packaging substrate defines a base reference plane.

15. The semiconductor package according to claim 14, wherein: A diameter of a top surface of the light guide member is greater than a width of a top surface of the second semiconductor chip.

16. The semiconductor package according to claim 14, wherein: The top surface of the light guide member and the top surface of the molding layer are coplanar with each other.

17. The semiconductor package according to claim 14, wherein: The second semiconductor chip includes a passive device or a light emitting device. 18 . The semiconductor package of claim 14 , further comprising a first lens in contact with a top surface of the light guide member. 19 . The semiconductor package of claim 18 , further comprising a second lens between the light guide member and the connection substrate and in contact with a top surface of the second semiconductor chip.

20. A semiconductor package, comprising: Package substrate; a connection substrate disposed on the package substrate, the connection substrate comprising a base substrate, a plurality of upper pads on a top surface of the base substrate, a plurality of lower pads on a bottom surface of the base substrate, and a plurality of through vias extending into the base substrate and connecting the upper pads to the lower pads; A first semiconductor chip is disposed on the connection substrate; a second semiconductor chip disposed on the connection substrate and spaced apart from the first semiconductor chip in the first direction; A molding layer, disposed on the packaging substrate and at least partially covering the first semiconductor chip, the second semiconductor chip and the connection substrate; a plurality of first connection terminals connecting the upper pad of the connection substrate to the first semiconductor chip and connecting the upper pad of the connection substrate to the second semiconductor chip; A plurality of second connection terminals connect the package substrate to the lower pad of the connection substrate; as well as The light guide member penetrates the molding layer and is disposed on the second semiconductor chip to guide a path of light.

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