A drive circuit for adaptively suppressing crosstalk in parallel hybrid Si IGBT and SiC MOSFET

Abstract

The present invention discloses a drive circuit for adaptively suppressing crosstalk in a mixed parallel connection of Si IGBTs and SiC MOSFETs, comprising a bilateral gate drive chip, a differential amplifier circuit, an analog multiplier, and a crosstalk suppression circuit. The present invention extracts the corresponding delayed switch drive signal through the differential amplifier circuit, and then uses the analog multiplier to multiply the delayed switch drive signal with the boosted drive signal of the parallel tube to generate a crosstalk suppression circuit activation signal corresponding to the main power tube that will generate crosstalk, thereby activating the negative crosstalk suppression circuit. Furthermore, the transistor in the positive crosstalk suppression circuit detects the voltage across the drive resistor in real time, and automatically activates the positive crosstalk suppression circuit once a positive crosstalk current flows through the drive resistor. The present invention can effectively eliminate the impact of crosstalk on mixed parallel connections, and has the advantages of being adaptive, fast in response, and good in real time.

Description

Technical Field

[0001] The present invention relates to a crosstalk suppression circuit in which Si IGBT and SiC MOSFET are mixed and connected in parallel. Background Art

[0002] The Si IGBT combines the advantages of both BJTs and MOSFETs, offering high current capacity, low on-state voltage, and fast switching speeds. However, as a bipolar device, it exhibits tail current and high switching losses. Furthermore, due to the limitations of Si material properties, the switching frequency of Si IGBTs has become insufficient to meet the requirements of high-power-density power electronics. SiC MOSFETs, as new third-generation wide-bandgap semiconductors, offer extremely low on-state resistance and higher switching frequencies, significantly increasing the power density of power electronics. However, they are expensive, and the current handling capacity of a single SiC MOSFET is limited.

[0003] A hybrid Si IGBT and SiC MOSFET parallel connection typically consists of a discrete Si IGBT and a discrete SiC MOSFET connected in parallel. Combining the advantages of both Si IGBTs and SiC MOSFETs, it offers both high current handling and low switching losses. Currently, a common driving strategy is to switch the SiC MOSFET on first, then off, followed by the Si IGBT on last, then off. This effectively eliminates the effects of IGBT tail current and reduces device switching losses. Furthermore, a driving strategy that switches the SiC MOSFET on last, then off, followed by the Si IGBT on first, then off, ensures the reliability of the SiC MOSFET.

[0004] However, when the SiC MOSFET (IGBT) is turned on early, the parallel device V DS (V CE ) will suddenly drop from the bus voltage to zero, which will generate a negative crosstalk current flowing through the IGBT (SiC MOSFET) drive resistor, causing a negative voltage to be generated at the gate emitter (gate source) of the IGBT (SiC MOSFET), which will cause great damage to the Si IGBT (SiC MOSFET) device. At the same time, when the SiC MOSFET (IGBT) is turned off later, the parallel device V DS (V CE ) will suddenly change from zero to the bus voltage, which will generate a forward crosstalk current flowing through the Si IGBT (SiC MOSFET) drive resistor, causing a forward voltage to be generated at the gate-emitter (gate-source) of the Si IGBT (SiC MOSFET), which may cause the Si IGBT (SiC MOSFET) to be turned on incorrectly, seriously affecting the reliability of the device and the power electronic conversion device.

[0005] Existing research on crosstalk suppression rarely includes solutions specifically applied to the mixed parallel connection of Si IGBTs and SiC MOSFETs. Therefore, it is extremely important to propose a solution specifically applied to solving the crosstalk problem of the mixed parallel connection of Si IGBTs and SiC MOSFETs. Summary of the Invention

[0006] Purpose of the invention: In view of the above-mentioned existing technologies, a drive circuit is proposed to adaptively suppress crosstalk in mixed parallel connection of Si IGBT and SiC MOSFET, solve the crosstalk problem caused by inconsistent switching timing, and improve the reliability of the device.

[0007] Technical solution: A drive circuit that adaptively suppresses crosstalk in mixed parallel Si IGBTs and SiC MOSFETs, including a bilateral gate drive chip, a differential amplifier circuit, an analog multiplier, and a crosstalk suppression circuit;

[0008] The differential amplifier circuit extracts the delayed switching portion of the drive signal. When the switching timings of the SiC MOSFET and SiIGBT are inconsistent, the operational amplifier will output the delayed switching portion of the switching timing, and the output signal will be connected to the analog multiplier.

[0009] In the analog multiplier part, since the turn-off voltage in the SiC MOSFET and Si IGBT driving signal is generally negative, the driving voltage is first raised to zero by a voltage boosting circuit. The SiC MOSFET analog multiplier multiplies the output signal of the differential amplifier circuit with the Si IGBT drive signal after passing through the voltage boost circuit. If the SiC MOSFET is turned on first and off last, no crosstalk will occur on the SiC MOSFET. The result PWM1 of the multiplication of the multiplier is zero, and the crosstalk suppression circuit will not be triggered to turn on. If the SiC MOSFET is turned on last and off first, crosstalk will occur on the SiC MOSFET. The output result PWM1 of the multiplier is non-zero, and the crosstalk suppression circuit will be turned on during the delay switching portion. The Si IGBT analog multiplier multiplies the output signal of the differential amplifier circuit with the SiC MOSFET drive signal after passing through the voltage boost circuit. If the Si IGBT is turned on first and off last, no crosstalk will occur on the Si IGBT. The result PWM2 of the multiplication of the multiplier is zero, and the crosstalk suppression circuit will not be triggered to turn on. If the Si IGBT is turned on last and off first, crosstalk will occur on the Si IGBT. The output result PWM2 of the multiplier is non-zero, and the crosstalk suppression circuit will be turned on during the delay switching portion.

[0010] The crosstalk suppression circuit is divided into a forward crosstalk suppression circuit and a reverse crosstalk suppression circuit. When forward crosstalk occurs, a forward crosstalk current flows through the driving resistor and generates a voltage difference across the driving resistor. This voltage difference is applied to the base-emitter terminals of the PNP transistor, turning on the transistor and allowing the forward crosstalk current to flow through the transistor and into the RC parallel circuit, thereby bypassing the driving resistor of the main power transistor and avoiding the occurrence of forward crosstalk. When negative crosstalk occurs, a negative crosstalk current flows. At this time, the analog multiplier outputs a corresponding suppression circuit turn-on signal, turning on the N-channel MOSFET. At this time, the negative crosstalk current passes through the N-channel MOSFET and is quickly conducted out of the RC parallel branch, thereby suppressing the occurrence of negative crosstalk.

[0011] Beneficial effect: Due to inconsistent switching timing, when SiC MOSFET (Si IGBT) is turned on early, the parallel device V DS (V CE ) will suddenly drop from the bus voltage to zero, which will generate a negative crosstalk current flowing through the Si IGBT (SiC MOSFET) drive resistor, causing a negative voltage to be generated at the gate emitter (gate source) of the Si IGBT (SiC MOSFET), which will cause great damage to the Si IGBT (SiC MOSFET) device. When the SiC MOSFET (Si IGBT) is turned off later, the parallel device V DS (V CE ) will suddenly change from zero to the bus voltage, which will generate a positive crosstalk current flowing through the Si IGBT (SiC MOSFET) driving resistor, causing the SiIGBT (SiC MOSFET) gate emitter (gate source) to generate a positive voltage, which may cause the Si IGBT (SiC MOSFET) to be turned on incorrectly. However, there are currently few methods used to specifically solve the crosstalk problem existing in mixed parallel connections. The present invention extracts the corresponding delayed switch driving signal through a differential amplifier circuit, and then multiplies the delayed switch driving signal with the parallel tube after the driving signal is raised by an analog multiplier to generate a crosstalk suppression circuit opening signal corresponding to the main power tube that will generate crosstalk, and turns on the negative crosstalk suppression circuit. In addition, the transistor in the positive crosstalk suppression circuit will detect the voltage across the driving resistor in real time. Once the positive crosstalk current flows through the driving resistor, the positive crosstalk suppression circuit will be automatically turned on. The present invention can effectively eliminate the influence of crosstalk on mixed parallel connections, has the advantages of adaptability, fast response speed and good real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a topological structure diagram of the present invention;

[0013] Figure 2The driving voltage differential amplifier circuit diagram, where (a) corresponds to SiC MOSFET and (b) corresponds to Si IGBT;

[0014] Figure 3 The analog multiplier circuit diagram, where (a) corresponds to SiC MOSFET and (b) corresponds to Si IGBT;

[0015] Figure 4 The crosstalk suppression circuit diagram, where (a) corresponds to SiC MOSFET and (b) corresponds to Si IGBT;

[0016] Figure 5 Schematic diagram of the crosstalk current flow when crosstalk occurs in SiC MOSFET, where (a) corresponds to positive crosstalk and (b) corresponds to negative crosstalk;

[0017] Figure 6 Schematic diagram of the crosstalk current flow when crosstalk occurs in Si IGBT, where (a) corresponds to positive crosstalk and (b) corresponds to negative crosstalk;

[0018] Figure 7 Schematic diagram of the crosstalk suppression circuit when crosstalk occurs in SiC MOSFET, where (a) corresponds to positive crosstalk and (b) corresponds to negative crosstalk;

[0019] Figure 8 Schematic diagram of the crosstalk suppression circuit when crosstalk occurs in Si IGBT, where (a) corresponds to positive crosstalk and (b) corresponds to negative crosstalk;

[0020] Figure 9 Schematic diagram of Si IGBT gate-emitter voltage without and with crosstalk suppression measures, where (a) corresponds to when it is turned on and (b) corresponds to when it is turned off;

[0021] Figure 10 Schematic diagram of the gate-source voltage of Si MOSFET with and without crosstalk suppression measures, where (a) corresponds to when it is turned on and (b) corresponds to when it is turned off. DETAILED DESCRIPTION

[0022] The present invention will be further explained below with reference to the accompanying drawings.

[0023] like Figure 1 As shown, a driving circuit for adaptively suppressing crosstalk in a mixed parallel connection of Si IGBTs and SiC MOSFETs includes a Si IGBT Q, a SiC MOSFET M, a bilateral gate driver chip, a differential amplifier circuit, an analog multiplier, and a crosstalk suppression circuit.

[0024] The bilateral gate driver chip outputs a set of PWM signals with adjustable duty cycle as the driving signals for Si IGBT and SiC MOSFET.

[0025] The SiC MOSFET differential amplifier circuit extracts the delayed switching portion of the Si IGBT drive signal relative to the SiC MOSFET at different drive timings. This output is connected to the input of the SiC MOSFET analog multiplier. Since the off-state voltage of the SiC MOSFET and Si IGBT drive signals is generally negative, a voltage boost circuit is first used to boost the drive voltage to zero. The boosted Si IGBT drive signal is then connected to the other input of the SiC MOSFET analog multiplier, where the two are multiplied. If the SiC MOSFET switches on before the Si IGBT, crosstalk will not occur, and the analog multiplier output will be zero. If the SiC MOSFET switches on before the Si IGBT, crosstalk will occur, and the analog multiplier will output the PWM1 drive signal, activating the crosstalk suppression circuit. The Si IGBT differential amplifier circuit extracts the delayed switching portion of the SiC MOSFET drive signal relative to the Si IGBT at different drive timings. This output is connected to the input of the Si IGBT analog multiplier. At the same time, the SiC MOSFET drive signal, which has passed through the voltage boost circuit, is connected to the other input of the Si IGBT analog multiplier, and the two are multiplied. If the Si IGBT switches on before the SiC MOSFET, crosstalk will not occur, and the analog multiplier outputs zero. If the Si IGBT switches on before the SiC MOSFET, crosstalk will occur, and the analog multiplier will output the PWM2 drive signal, activating the crosstalk suppression circuit. When the crosstalk suppression circuit begins operating, the PNP transistor in the crosstalk suppression circuit turns on, and the positive crosstalk current flows through the transistor and is discharged from the RC parallel branch. The N-channel MOSFET in the crosstalk suppression circuit turns on, and the negative crosstalk current flows through the N-channel MOSFET and is quickly discharged from the RC parallel branch, thereby suppressing the occurrence of negative crosstalk.

[0026] like Figure 2 As shown in (a), the SiC MOSFET differential amplifier circuit includes an operational amplifier U1 and resistors R3 to R6; one end of the resistor R3 is connected to the Si IGBT drive signal OUT2, and the other end is connected to the non-inverting input terminal of the operational amplifier U1 and one end of the resistor R5, and the other end of the resistor R5 is grounded; one end of the resistor R4 is connected to the SiC MOSFET drive signal OUT1, and the other end is connected to the inverting input terminal of the operational amplifier U1 and one end of the resistor R6, and the other end of the resistor R6 is connected to the output terminal of the operational amplifier U1; the power supply terminals of the operational amplifier are respectively connected to the positive voltage V cc and negative voltage Vss .

[0027] like Figure 2 As shown in (b), the Si IGBT differential amplifier circuit includes an operational amplifier U2, R 12 ~R 15 ;Resistor R 12 One end is connected to the SiC MOSFET drive signal OUT1, and the other end is connected to the operational amplifier U2 non-inverting input and resistor R 14 One end, resistor R 14 The other end is grounded; the resistor R 13 One end is connected to the Si IGBT drive signal OUT2, and the other end is connected to the inverting input of the operational amplifier U1 and the resistor R 15 One end, resistor R 15 The other end is connected to the output of the operational amplifier U2; the power supply end of the operational amplifier is connected to the positive voltage V cc and negative voltage V ss .

[0028] like Figure 3 As shown in (a), the SiC MOSFET analog multiplier includes resistors R7 to R 11 、R f1 ~R f3 , operational amplifier U3, NPN transistors Q5~Q7; one end of resistor R7 is connected to the output of operational amplifier U1, and the other end is connected to the base of transistor Q5. The collector of transistor Q5 is connected to one end of resistor R9, and the output signal PWM1 is derived from this. The other end of resistor R9 is connected to the positive voltage V cc , the emitter of transistor Q5 is connected to the emitter of transistor Q6 and the collector of transistor Q7, the base of transistor Q6 is grounded, and the collector is connected to resistor R 10 One end, resistor R 10 The other end is connected to a positive voltage V cc , the emitter of transistor Q7 is connected to resistor R 11 One end, resistor R 11 The other end is grounded, and the base of transistor Q7 is connected to the output of operational amplifier U3 and resistor R f3 One end, resistor R f3 The other end is connected to the inverting input of the operational amplifier U3, and the power supply end of the operational amplifier U3 is connected to the positive voltage V cc and negative voltage V ss , the operational amplifier U3 non-inverting input terminal is connected to one end of the resistor R8 and the resistor R f1 , resistor R f2 One end, the other end of the resistor R8 is connected to the Si IGBT drive signal OUT2, the resistor R f1 The other end is connected to a positive voltage V cc , resistor R f2 The other end is grounded.

[0029] like Figure 3 As shown in (b), the Si IGBT analog multiplier includes a resistor R 16 ~R 20 、R f4 ~R f6 , operational amplifier U4, NPN transistor Q8 ~ Q 10 ;Resistor R 16 One end is connected to the output of operational amplifier U2, the other end is connected to the base of transistor Q8, and the collector of transistor Q8 is connected to resistor R 18 One end, and the output signal PWM2 is drawn here, R 18 The other end is connected to a positive voltage V cc , the emitter of transistor Q8 is connected to the emitter of transistor Q9 and transistor Q 10 The collector of transistor Q9 is connected to the ground, and the collector is connected to the resistor R 19 One end, resistor R 19 The other end is connected to a positive voltage V cc , transistor Q 10 The emitter is connected to the resistor R 20 One end, resistor R 20 The other end is grounded, transistor Q 10 The base of is connected to the output of operational amplifier U4 and resistor R f6 One end, resistor R f6 The other end is connected to the inverting input of the operational amplifier U4, and the power supply end of the operational amplifier U4 is connected to the positive voltage V cc and negative voltage V ss , operational amplifier U4 non-inverting input terminal connected to resistor R 17 One end and resistor R f4 , resistor R f5 One end, resistor R 17 The other end is connected to the Si MOSFET drive signal OUT1, and the resistor R f4 The other end is connected to a positive voltage V cc , resistor R f5 The other end is grounded.

[0030] like Figure 4 As shown in (a), the SiC MOSFET crosstalk suppression circuit includes a resistor R1, a capacitor C1, a PNP transistor Q1, an N-channel MOSFET Q3, and a diode D1; the base of the transistor Q1 is connected to the SiC MOSFET drive resistor R g_MOS One end and SiCMOSFET drive signal OUT1, the emitter of transistor Q1 is connected to SiC MOSFET drive resistor R g_MOSThe other end and the cathode of the diode D1 and the source of the SiC MOSFET, the collector of the transistor Q1 are connected to the source of the MOSFET Q3 and the resistor R1 and one end of the capacitor C1, the other ends of the resistor R1 and the capacitor C1 are grounded, the gate of the MOSFET Q3 is connected to the SiC MOSFET analog multiplier output signal PWM1, and the drain of the MOSFET Q3 is connected to the anode of the diode D1.

[0031] like Figure 4 As shown in (b), the Si IGBT crosstalk suppression circuit includes a resistor R2, a capacitor C2, a PNP transistor Q2, an N-channel MOSFET Q4, and a diode D2; the base of the transistor Q2 is connected to the Si IGBT drive resistor R g_IGBT One end and Si IGBT drive signal OUT2, the emitter of transistor Q2 is connected to Si IGBT drive resistor R g_IGBT The other end and the cathode of the diode D2 and the source of the SiIGBT, the collector of the transistor Q2 are connected to the source of the MOSFET Q4 and the resistor R2 and one end of the capacitor C2, the other ends of the resistor R2 and the capacitor C2 are grounded, the gate of the MOSFET Q4 is connected to the Si IGBT analog multiplier output signal PWM2, and the drain of the MOSFET Q4 is connected to the anode of the diode D2.

[0032] To analyze the working principle of the circuit, the following definitions are made: V OUT_MOS is the output of the SiC MOSFET differential amplifier circuit, namely U1; V OUT_IGBT is the output of the Si IGBT differential amplifier circuit, namely U2; V drive_MOS is the SiC MOSFET driving voltage, which is OUT1; V drive_IGBT is the Si IGBT driving voltage, which is OUT2; V drive_up is the driving signal after passing through the voltage boost circuit; V PWM1 is the N-channel MOSFET driving signal in the SiC MOSFET crosstalk suppression circuit, namely PWM1, V PWM2 is the N-channel MOSFET driving signal in the Si IGBT crosstalk suppression circuit, namely PWM2; I gd_MOS+ is the forward crosstalk current when the SiC MOSFET has forward crosstalk, I gd_MOS- is the negative crosstalk current when SiC MOSFET has negative crosstalk, I gc_IGBT+ is the forward crosstalk current when the Si IGBT has forward crosstalk, I gc_IGBT- is the negative crosstalk current when negative crosstalk occurs in Si IGBT; C gd is the Miller capacitance of SiCMOSFET, C gsis the gate-source capacitance of SiC MOSFET, C ds is the drain-source capacitance of SiC MOSFET, C gc is the Miller capacitance of SiIGBT, C ge is the gate-emitter capacitance of Si IGBT, C ce is the collector-emitter capacitance of Si IGBT.

[0033] like Figure 2 The differential amplifier circuit shown in FIG. 1 forms a difference circuit through an operational amplifier. Figure 2 The SiC MOSFET differential amplifier circuit shown in (a) takes the difference between the Si IGBT drive signal and the SiC MOSFET drive signal and outputs the delayed switching portion of the two drive signals, as shown in the following formula:

[0034]

[0035] Generally, R3=R4, R5=R6, then the above formula can be simplified to:

[0036]

[0037] like Figure 2 The Si IGBT differential amplifier circuit shown in (b) takes the difference between the SiC MOSFET drive signal and the Si IGBT drive signal and outputs the delayed switching portion of the two drive signals, as shown in the following formula:

[0038]

[0039] Generally take R 12 =R 13 , R 14 =R 15 , then the above formula can be simplified to:

[0040]

[0041] like Figure 3 The analog multiplier shown multiplies the output of the differential amplifier circuit with the boosted drive signal of another switch tube in the hybrid parallel connection (if it is a SiC MOSFET analog multiplier, the tube is a Si IGBT; if it is a Si IGBT analog multiplier, the tube is a SiMOSFET) for adaptive judgment of the crosstalk suppression circuit switch. The boosted voltage is shown in the following formula:

[0042]

[0043] Generally, R8=R f1 =R 17 =R f4 =R, Rf3 =R f6 =R f , V drive It is the driving signal of SiC MOSFET or Si IGBT.

[0044] like Figure 3 The SiC MOSFET analog multiplier shown in (a) multiplies the boosted Si IGBT drive signal by the output of the SiC MOSFET differential amplifier circuit to output the drive signal for the N-channel MOSFET in the crosstalk suppression circuit. The output is shown in the following formula:

[0045]

[0046] Among them, R9=R 10 , U T1 is the collector-emitter voltage on Q5 and Q6 on the single differential transistor. When the SiC MOSFET switches on last and off first relative to the Si IGBT, crosstalk occurs in the SiC MOSFET. At this point, the output signal of the analog multiplication circuit turns on the N-channel MOSFET in the SiC MOSFET crosstalk suppression circuit. When the SiC MOSFET switches on first and off last relative to the Si IGBT, crosstalk does not occur in the SiC MOSFET. The output signal of the analog multiplication circuit is zero, and the N-channel MOSFET in the SiC MOSFET crosstalk suppression circuit does not conduct.

[0047] like Figure 3 The Si IGBT analog multiplier shown in (b) multiplies the boosted SiC MOSFET drive signal by the output of the Si IGBT differential amplifier circuit to output the drive signal for the N-channel MOSFET in the crosstalk suppression circuit. The output is shown in the following formula:

[0048]

[0049] Among them, R is generally taken 18 =R 19 , U T2 is the collector-emitter voltage across Q8 and Q9 on a single differential transistor. When the Si IGBT switches on last and off first relative to the SiC MOSFET, crosstalk occurs between the Si IGBTs. At this point, the output signal from the analog multiplication circuit turns on the N-channel MOSFET in the Si IGBT crosstalk suppression circuit. When the Si IGBT switches on first and off last relative to the SiC MOSFET, crosstalk does not occur between the Si IGBTs. The output signal from the analog multiplication circuit is zero, and the N-channel MOSFET in the Si IGBT crosstalk suppression circuit is off.

[0050] like Figure 4 The crosstalk suppression circuit shown in the figure implements positive crosstalk suppression and negative crosstalk suppression respectively through an auxiliary transistor and an RC parallel branch, as well as an N-channel MOSFET and an RC parallel branch, and conducts the crosstalk current through the suppression circuit.

[0051] like Figure 5 (a) shows the direction of crosstalk current flow when the SiC MOSFET has forward crosstalk. At this time, the SiC MOSFET is turned off in advance. When the Si IGBT is turned off, the voltage of the parallel device rises rapidly from zero to the bus voltage. The drain-source voltage V DS Rapidly rises due to the Miller capacitance C between the gate and drain gd , will generate Miller current I gd_MOS+ , which is the forward crosstalk current, which will give the gate-source capacitance C gs Charging causes a forward voltage spike in the gate-source voltage, which may cause misleading turn-on.

[0052] like Figure 5 (b) shows the direction of crosstalk current flow when negative crosstalk occurs on the SiC MOSFET. At this time, the Si IGBT is turned on early. At this time, the voltage of the parallel device drops rapidly from the bus voltage to near zero, and the drain-source voltage V DS Rapidly decreases due to the Miller capacitance C between the gate and drain gd , will generate Miller current I gd_MOS- , at this time the current is a negative crosstalk current, which will give the gate-source capacitance C gs Discharge causes a reverse voltage spike in the gate-source voltage, which may cause the switch tube to break down.

[0053] like Figure 6 (a) shows the crosstalk current flow direction when the Si IGBT has forward crosstalk. At this time, the Si IGBT is turned off early. When the SiC MOSFET is turned off, the voltage of the parallel device rises rapidly from zero to the bus voltage. The collector-emitter voltage V ce Rapidly rises due to the Miller capacitance C between the gate and collector gc , will generate Miller current I gc_IGBT+ , which is the forward crosstalk current, which will give the gate-emitter capacitance C ge Charging causes a forward voltage spike in the gate-emitter voltage, which may cause misleading conduction.

[0054] like Figure 6 (b) shows the crosstalk current flow direction when negative crosstalk occurs in the Si IGBT. At this time, the SiC MOSFET is turned on in advance. At this time, the voltage of the parallel device drops rapidly from the bus voltage to near zero, and the collector-emitter voltage Vce Rapidly decreases due to the Miller capacitance C between the gate and collector gc , will generate Miller current I gc_IGBT- , at this time the current is a negative crosstalk current, which will give the gate-emitter capacitance C ge Discharge causes a reverse voltage spike in the gate-emitter voltage, which may cause the switching tube to break down.

[0055] like Figure 7 The figure shows the working diagram of the crosstalk suppression circuit when positive and negative crosstalk occur in the SiC MOSFET. The crosstalk suppression circuit derives positive crosstalk current and negative crosstalk current by turning on the PNP transistor and the N-channel MOSFET, respectively, thereby suppressing the crosstalk.

[0056] like Figure 7 (a) shows the working process of the crosstalk suppression circuit when the SiC MOSFET has forward crosstalk, and the forward crosstalk current I gd_MOS+ When forward crosstalk occurs, the driving resistor R g_MOS The voltage at both ends changes, causing transistor Q1 to conduct, and the crosstalk current I gd_MOS+ The current flows through the transistor and is led out from the RC parallel branch, so that it will not flow to the gate-source capacitance C gs Charging, no forward voltage spike is generated on the gate-source, and forward crosstalk is suppressed.

[0057] like Figure 7 (b) shows the working process of the crosstalk suppression circuit when the SiC MOSFET has negative crosstalk, and the negative crosstalk current I gd_MOS- When negative crosstalk occurs, the analog multiplier will output the Q3 turn-on signal, so that MOSFET Q3 is turned on, and the negative crosstalk current will no longer flow through the gate-source capacitance C gs , gate-source capacitance C gs It will not discharge, but will be derived from the RC parallel branch. No reverse voltage spike will be generated on the gate-source, and negative crosstalk will be suppressed.

[0058] like Figure 8 The crosstalk suppression circuit shown in FIG. 1 is a schematic diagram illustrating the operation of the crosstalk suppression circuit when positive and negative crosstalk occur in the Si IGBT. The crosstalk suppression circuit derives positive and negative crosstalk currents by turning on the PNP transistor and the N-channel MOSFET, respectively, thereby suppressing the crosstalk.

[0059] like Figure 8 (a) shows the working process of the crosstalk suppression circuit when the Si IGBT has forward crosstalk, and the forward crosstalk current I gc_IGBT+ When forward crosstalk occurs, the driving resistor R g_IGBT The voltage at both ends changes, causing transistor Q2 to conduct, and the crosstalk current Igc_IGBT+ The current flows through the transistor and is led out from the RC parallel branch, so that it will not flow to the gate-emitter capacitance C ge Charging, no forward voltage spike will be generated on the gate emitter, and forward crosstalk will be suppressed.

[0060] like Figure 8 (b) shows the working process of the crosstalk suppression circuit when the Si IGBT has negative crosstalk, and the negative crosstalk current I gc_IGBT- When negative crosstalk occurs, the analog multiplier will output the Q4 turn-on signal, so that MOSFET Q4 is turned on, and the negative crosstalk current will no longer flow through the gate-emitter capacitance C ge , gate-emitter capacitance C ge There will be no discharge, no reverse voltage spike will be generated on the gate emitter, and negative crosstalk will be suppressed.

[0061] This invention mainly addresses the crosstalk problem caused by the different switching timings of Si IGBT and SiC MOSFET. To better illustrate the working principle of the suppression circuit, in one switching cycle, it is assumed that SiC MOSFET is turned on first and then turned off compared to Si IGBT. The forward crosstalk current is I gc_IGBT+ , the negative crosstalk current is I gc_IGBT- .

[0062] Opening process:

[0063] State 1: SiC MOSFET starts to turn on, at this time Si IGBT is not turned on, the voltage across the parallel devices drops rapidly due to the turn-on of SiC MOSFET, and the collector-emitter voltage V ce When the bus voltage drops to nearly zero, due to the Miller capacitance C between the gate and collector gc , a negative Miller current I gc_IGBT- .

[0064] State 2: The Si IGBT differential amplifier circuit calculates the difference between the SiC MOSFET and Si IGBT drive signals to obtain the drive signal between the time the SiC MOSFET is turned on and the time the Si IGBT is not turned on. This signal is fed into the Si IGBT analog multiplier and multiplied by the SiC MOSFET drive signal after passing through the voltage boost circuit. The drive signal timing remains unchanged, but the voltage amplitude changes according to the multiplier's coefficient. Simultaneously, the SiC MOSFET differential amplifier circuit calculates the difference between the Si IGBT and SiC MOSFET drive signals to obtain the drive signal between the time the SiC MOSFET is turned on and the time the Si IGBT is not turned on. This signal is fed into the SiC MOSFET analog multiplier and multiplied by the Si IGBT drive signal after the boost circuit, maintaining the output voltage at zero.

[0065] State 3: Si IGBT analog multiplier output voltage turns on Q4 in the Si IGBT negative crosstalk suppression circuit, and the Miller current I gc_IGBT- Through Q4 and the RC parallel branch, the current no longer flows through the gate-emitter capacitor C ge , gate-emitter capacitance C ge There is no discharge, no reverse voltage spike is generated on the gate emitter, and negative crosstalk is suppressed. However, Q3 in the SiC MOSFET will not conduct because the output of the SiC MOSFET analog multiplier is zero.

[0066] State 4: The Si IGBT is turned on, the SiC MOSFET remains on, the output voltage of the Si IGBT analog multiplier turns to zero, Q4 is turned off, the negative crosstalk suppression circuit stops working, and the Si IGBT is turned on normally.

[0067] Shutdown process:

[0068] State 1: Si IGBT turns off prematurely, and SiC MOSFET starts to turn off after a delay. The voltage across the parallel devices rises rapidly due to the turn-off of SiC MOSFET, and the collector-emitter voltage V ce From zero to bus voltage, due to the Miller capacitance C between the gate and collector gc , will generate a forward Miller current I gc_IGBT+ .

[0069] State 2: Forward Miller current I gc_IGBT+ Flowing through the Si IGBT drive resistor R g_IGBT At this time, the V of the PNP transistor Q2 be <0 and V bc >0, Q2 is turned on.

[0070] State 3: Miller current I gc_IGBT+ Through Q2 and the RC parallel branch, the current no longer flows through the gate-emitter capacitor C ge , gate-emitter capacitance C ge There will be no further charging, no forward voltage spike will be generated on the gate emitter, and forward crosstalk will be suppressed.

[0071] State 4: Miller current I gc_IGBT+ Elimination, Q2's V be When the voltage is no longer less than zero, Q2 turns off naturally, the forward crosstalk suppression circuit stops working, and both the SiC MOSFET and the Si IGBT wait for the next switching cycle.

[0072] Figure 9(a) and (b) are schematic diagrams of SiIGBT gate-emitter voltage when turning on and off without and with crosstalk suppression measures, respectively; Figure 10 (a) and (b) are schematic diagrams of the gate-source voltage of Si MOSFET when it is turned on and off without and with crosstalk suppression measures. Figure 9 (a) Gate-emitter voltage comparison when turned on Figure 10 By comparing the gate-source voltage when the device is turned on (a), it can be found that the drive circuit for adaptively suppressing the crosstalk of Si IGBT and SiC MOSFET in parallel has a significant effect on suppressing the negative crosstalk problem that occurs during the turn-on process of Si IGBT and SiC MOSFET. Figure 9 (b) Gate-emitter voltage comparison when turned off and Figure 10 From the comparison of gate-source voltage at turn-off (b), it can be found that the drive circuit for adaptively suppressing crosstalk between Si IGBT and SiC MOSFET in parallel proposed in the present invention also has a significant effect on suppressing the forward crosstalk problem occurring during the turn-off process of Si IGBT and SiC MOSFET.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A driving circuit for adaptively suppressing crosstalk in a mixed parallel connection of Si IGBT and SiC MOSFET, characterized in that: Includes bilateral gate driver chip, crosstalk suppression circuit, differential amplifier circuit and analog multiplier; The bilateral gate driver chip is used to output drive signals for the hybrid parallel Si IGBT and SiC MOSFET; The differential amplifier circuit includes a SiC MOSFET differential amplifier circuit and a Si IGBT differential amplifier circuit; the SiC MOSFET differential amplifier circuit connects the Si IGBT drive signal to the non-inverting input terminal of the operational amplifier, and the SiC MOSFET drive signal to the inverting input terminal of the operational amplifier. After the two signals are differentially amplified, a drive signal including only the delayed switch part is generated; the Si IGBT differential amplifier circuit connects the SiC MOSFET drive signal to the non-inverting input terminal of the operational amplifier, and the Si IGBT drive signal to the inverting input terminal of the operational amplifier. After the two signals are differentially amplified, a drive signal including only the delayed switch part is generated; The analog multiplier includes a SiC MOSFET analog multiplier and a Si IGBT analog multiplier; the SiC MOSFET analog multiplier multiplies the output of the SiC MOSFET differential amplifier circuit by the Si IGBT drive signal after voltage boosting to generate PWM1; If the SiC MOSFET drive signal is turned on last and turned off first relative to the Si IGBT drive signal at this time, the PWM1 signal is output; the Si IGBT analog multiplier multiplies the output of the Si IGBT drive signal differential amplifier circuit with the boosted SiC MOSFET drive signal to generate the Si IGBT negative crosstalk suppression circuit turn-on signal PWM2. If the Si IGBT drive signal is turned on last and turned off first at this time, the PWM2 signal is output; The hybrid parallel SiC MOSFET and Si IGBT are each connected to a set of crosstalk suppression circuits; the crosstalk suppression circuit includes a positive crosstalk suppression circuit and a negative crosstalk suppression circuit; the positive crosstalk circuit includes a PNP transistor and an RC parallel branch, the base and emitter of the PNP transistor are respectively connected to the two ends of the driving resistor. When positive crosstalk occurs, the PNP transistor is turned on, and the positive crosstalk current passes through the PNP transistor and flows into the RC parallel branch, thereby suppressing the occurrence of positive crosstalk; the negative crosstalk suppression circuit includes an N-channel MOSFET and an RC parallel branch, and the RC parallel branch reuses the RC parallel branch part in the positive crosstalk suppression circuit. When negative crosstalk occurs in Si IGBT Q or SiC MOSFET M, the PWM signal connected to the gate of the N-channel MOSFET will turn it on, and the reverse crosstalk current passes through the N-channel MOSFET and is derived from the RC parallel branch, thereby suppressing the occurrence of negative crosstalk.

2. The driving circuit for adaptively suppressing crosstalk in mixed parallel connection of Si IGBT and SiC MOSFET according to claim 1, characterized in that: The SiC MOSFET differential amplifier circuit includes an operational amplifier U1, a resistor R 3~ R 6. Resistance R 3 One end is connected to Si IGBT drive signal OUT2, and the other end is connected to the operational amplifier U1 non-inverting input and resistor R 5 one end, resistor R 5The other end is grounded; the resistor R 4 One end is connected to the SiC MOSFET drive signal OUT1, and the other end is connected to the inverting input of the operational amplifier U1 and the resistor R 6 one end, resistor R 6 The other end is connected to the output of the operational amplifier U1; the power supply end of the operational amplifier is connected to the positive voltage V cc and negative voltage V ss ; The Si IGBT differential amplifier circuit includes an operational amplifier U2, R 12 ~ R 15 ;resistance R 12 One end is connected to the SiC MOSFET drive signal OUT1, and the other end is connected to the operational amplifier U2 non-inverting input and the resistor R 14 One end, resistor R 14 The other end is grounded; the resistor R 13 One end is connected to the Si IGBT drive signal OUT2, and the other end is connected to the operational amplifier U1 inverting input and the resistor R 15 One end, resistor R 15 The other end is connected to the output of the operational amplifier U2; the power supply end of the operational amplifier is connected to the positive voltage V cc and negative voltage V ss .

3. The driving circuit for adaptively suppressing crosstalk in mixed parallel connection of Si IGBT and SiC MOSFET according to claim 1, characterized in that: The SiC MOSFET analog multiplier includes resistors R 7 ~R 11 、 R f1 ~R f3 , operational amplifier U3, NPN transistors Q5~Q7; resistors R 7. One end is connected to the output of operational amplifier U1, the other end is connected to the base of transistor Q5, and the collector of transistor Q5 is connected to the resistor. R 9 one end, and the output signal PWM1 is drawn here, the resistor R 9The other end is connected to a positive voltage V cc , the emitter of transistor Q5 is connected to the emitter of transistor Q6 and the collector of transistor Q7, the base of transistor Q6 is grounded, and the collector is connected to the resistor R 10 One end, resistor R 10 The other end is connected to a positive voltage V cc , the emitter of transistor Q7 is connected to the resistor R 11 One end, resistor R 11 The other end is grounded, and the base of transistor Q7 is connected to the output of operational amplifier U3 and resistor R f3 One end, resistor R f3 The other end is connected to the inverting input of the operational amplifier U3, and the power supply end of the operational amplifier U3 is connected to the positive voltage V cc and negative voltage V ss , operational amplifier U3 non-inverting input termination resistor R 8 one end and resistor R f1 ,resistance R f2 One end, resistor R 8The other end is connected to Si IGBT drive signal OUT2, resistor R f1 The other end is connected to a positive voltage V cc ,resistance R f2 The other end is grounded; The Si IGBT analog multiplier includes resistors R 16 ~R 20 、 R f4 ~R f6 , operational amplifier U4, NPN transistor Q8~Q 10 ;resistance R 16 One end is connected to the output of operational amplifier U2, the other end is connected to the base of transistor Q8, and the collector of transistor Q8 is connected to the resistor R 18 One end, and the output signal PWM2 is drawn here, R 18 The other end is connected to a positive voltage V cc , the emitter of transistor Q8 is connected to the emitter of transistor Q9 and transistor Q 10 The collector of transistor Q9 is grounded, and the collector is connected to the resistor R 19 One end, resistor R 19 The other end is connected to a positive voltage V cc , transistor Q 10 The emitter is connected to a resistor R 20 One end, resistor R 20 The other end is grounded, transistor Q 10 The base of the operational amplifier U4 output and the resistor R f6 One end, resistor R f6 The other end is connected to the inverting input of the operational amplifier U4, and the power supply end of the operational amplifier U4 is connected to the positive voltage V cc and negative voltage V ss , operational amplifier U4 non-inverting input termination resistor R 17 One end and resistor R f4 ,resistance R f5 One end, resistor R 17 The other end is connected to the Si MOSFET drive signal OUT1, and the resistor R f4 The other end is connected to a positive voltage V cc ,resistance R f5 The other end is grounded.

4. The driving circuit for adaptively suppressing crosstalk in mixed parallel connection of Si IGBT and SiC MOSFET according to claim 1, characterized in that: The crosstalk suppression circuit of SiC MOSFET includes resistors R 1. Capacitor C 1. PNP transistor Q1, N-channel MOSFET Q3, diode D1; the base of transistor Q1 is connected to the SiC MOSFET drive resistor R g_MOS One end and SiC MOSFET drive signal OUT1, the emitter of transistor Q1 is connected to SiC MOSFET drive resistor R g_MOS The other end and the cathode of diode D1, the source of SiC MOSFET, and the collector of transistor Q1 are connected to the source of MOSFET Q3 and the resistor R 1. Capacitor C 1 one end, resistor R 1 and capacitor C 1 The other end is grounded, the gate of MOSFET Q3 is connected to the SiC MOSFET analog multiplier output signal PWM1, and the drain of MOSFET Q3 is connected to the anode of diode D1; The crosstalk suppression circuit of Si IGBT includes resistors R 2. Capacitor C 2. PNP transistor Q2, N-channel MOSFET Q4, diode D2; the base of transistor Q2 is connected to the Si IGBT drive resistor R g_IGBT One end and Si IGBT drive signal OUT2, the emitter of transistor Q2 is connected to Si IGBT drive resistor R g_IGBT The other end and the cathode of diode D2, the source of Si IGBT, and the collector of transistor Q2 are connected to the source of MOSFET Q4 and resistor R 2. Capacitor C 2 one end, resistor R 2 and capacitor C 2 The other end is grounded, the gate of MOSFET Q4 is connected to the Si IGBT analog multiplier output signal PWM2, and the drain of MOSFET Q4 is connected to the anode of diode D2.

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