High-voltage integrated circuit integrated with stepped self-adaptive dead zone function

Abstract

The invention relates to the technical field of high-voltage integrated circuits, and provides a high-voltage integrated circuit integrated with a stepped self-adaptive dead zone function. Comprising a first input stage circuit, a time delay circuit, a second input stage circuit, a dynamic dead zone generation circuit, a pulse generation circuit, a level shift circuit, a first amplifier, a negative voltage detection circuit, a low-side time delay circuit, a second amplifier and a converter circuit. The output end of the low-side delay circuit is connected with the input end of the second amplifier, the output end of the second amplifier is connected with the second input end of the converter circuit, and the output end of the converter circuit is used for being connected with a load; and the negative voltage detection circuit is used for detecting a delay signal of the converter circuit and feeding back the delay signal to the dynamic dead zone generation circuit so as to adjust the dead zone time in real time. According to the invention, the HVIC can work in the optimal dead time, and the reliability of the HVIC is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a high-voltage integrated circuit with an integrated step-type adaptive dead zone function. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.

[0003] The traditional HVIC anti-shoot-through dead zone technology inserts a fixed dead zone time between the high and low voltage side outputs to prevent shoot-through on the high and low voltage sides. The high and low voltage side input signals are logically completely complementary signals. After being processed by the input logic module, they enter the fixed dead zone time generation module. A certain dead zone is produced between the HO and LO output after passing through the high and low voltage side channels, avoiding the shoot-through problem caused by the simultaneous opening of the high and low voltage side power tubes. In actual applications, the opening and closing time of the power tube will change with the changes in input voltage, temperature, and load current, so the setting of the fixed dead zone time is based on the worst case shoot-through. Therefore, in general conditions, the dead zone time often has a sufficiently long margin. If the dead zone time is set too short, it may cause shoot-through as the system application environment changes, affecting the reliability of the system. If the dead time is set too long, a brief current blank period will occur in the circuit when the switch tube is switched. During this period, both the voltage and power are in a no-load state, which will cause a certain amount of power loss, reduce the efficiency of the circuit, the quality of the output waveform, increase power loss, and possibly damage the switch tube, affecting the stability of the circuit.

[0004] Therefore, the above-mentioned high-voltage integrated circuit has large power loss, low efficiency, poor quality of output waveform when working, and may damage the switch tube, affecting the stability of the circuit. Summary of the invention

[0005] The present invention provides a high-voltage integrated circuit with an integrated step-type adaptive dead zone function, aiming to solve the problems of large power loss, low efficiency, poor quality of output waveform, possible damage to switch tubes and influence on circuit stability of existing high-voltage integrated circuits during operation.

[0006] An embodiment of the present invention provides a high-voltage integrated circuit with an integrated step-type adaptive dead zone function, comprising: a first input stage circuit, a delay circuit, a second input stage circuit, a dynamic dead zone generating circuit, a pulse generating circuit, a level shifting circuit, a first amplifier, a negative voltage detection circuit, a low-side delay circuit, a second amplifier, and a converter circuit; the input end of the first input stage circuit is connected to the input end of the second input stage circuit and is commonly used to connect a signal input end, the output end of the first input stage circuit and the output end of the second input stage circuit are respectively connected to the input end of the dynamic dead zone generating circuit, and the output end of the dynamic dead zone generating circuit is respectively connected to the pulse generating circuit. The input end of the circuit and the input end of the low-side delay circuit, the output end of the pulse generating circuit is connected to the input end of the level shifting circuit, the output end of the level shifting circuit is connected to the input end of the first amplifier, and the output end of the first amplifier is connected to the first input end of the converter circuit; the output end of the low-side delay circuit is connected to the input end of the second amplifier, the output end of the second amplifier is connected to the second input end of the converter circuit, and the output end of the converter circuit is used to connect a load; the negative voltage detection circuit is used to detect the delay signal of the converter circuit and feed it back to the dynamic dead zone generating circuit, so as to adjust the dead time in real time; The converter circuit includes a first transistor, a second transistor, a first resistor, a first capacitor and a first inductor; the gate of the first transistor serves as the first input end of the converter circuit, the drain of the first transistor is used to connect to a power supply, the source of the first transistor is respectively connected to the negative voltage detection circuit, the drain of the second transistor and the first end of the first inductor, the gate of the second transistor serves as the second input end of the converter circuit, and the source of the second transistor is grounded; the second end of the first inductor is respectively connected to the first end of the first capacitor and the first end of the first resistor, the second end of the first capacitor is connected to the second end of the first resistor and is grounded; the second end of the first inductor also serves as the output end of the converter circuit.

[0007] Preferably, the delay circuit includes a first dynamic delay unit and a second dynamic delay unit; the input end of the first dynamic delay unit and the input end of the second dynamic delay unit are connected and serve together as the input end of the delay circuit; the output end of the first dynamic delay unit and the output end of the second dynamic delay unit respectively serve as the output end of the delay circuit.

[0008] Preferably, the dynamic dead zone generating circuit comprises: a first NOT gate, a first NAND gate, a first NOR gate, a second NOT gate, a second NAND gate and a second NOR gate; The input end of the first NOT gate is connected to the input end of the first dynamic delay unit, the output end of the first NOT gate is respectively connected to the first end of the first NAND gate and the first end of the first NOR gate, and the second end of the first NAND gate is connected to the output end of the first dynamic delay unit as the first input end of the dynamic dead zone generating circuit; The input end of the second NOT gate is connected to the input end of the second dynamic delay unit, the output end of the second NOT gate is respectively connected to the first end of the second NAND gate and the first end of the second NOR gate, and the second end of the second NOT gate is connected to the output end of the second dynamic delay unit as the second input end of the dynamic dead zone generating circuit; The output end of the first NAND gate is connected to the second end of the second NOR gate, the output end of the second NAND gate is connected to the second end of the first NOR gate, the output end of the first NOR gate is connected to the input end of the pulse generating circuit, and the output end of the second NOR gate is connected to the input end of the low-side delay circuit.

[0009] Preferably, the circuit structure of the first dynamic delay unit is the same as that of the second dynamic delay unit.

[0010] Preferably, the first dynamic delay unit comprises: a trigger, a two-to-one data selector, an up-down counter, a binary delay line, an AND gate, a third NAND gate, a third NOR gate, a fourth NOR gate and a NOT gate; The input end of the trigger is used to connect the output end of the negative voltage detection circuit, the output end of the trigger is connected to the X1 input end of the two-to-one data selector, the output end of the two-to-one data selector is connected to the control end of the add-subtract counter, the output end of the add-subtract counter is connected to the input end of the binary delay line, and the output end of the binary delay line serves as the output end of the first dynamic delay unit; the input end of the binary delay line is connected to the input end of the third NOT gate and serves as the input end of the first dynamic delay unit; The output end of the third NOT gate is connected to the CLK port of the up-down counter, the input end of the third NOR gate is used to connect to the signal input end, the output end of the third NOR gate is respectively connected to the first input end of the fourth NOR gate and the first input end of the third NAND gate, the output end of the fourth NOR gate is respectively connected to the second input end of the first NAND gate and the S input end of the two-to-one data selector; the output end of the third NAND gate is connected to the X0 input end of the two-to-one data selector; the input end of the AND gate is used to connect to the signal input end, and the output end of the AND gate is connected to the second input end of the fourth NOR gate.

[0011] Preferably, the binary delay line comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a second capacitor; The drain of the first PMOS tube is used to connect to the power supply, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and serves as the input end of the binary delay line, and the drain of the first NMOS tube is respectively connected to the first end of the first resistor and the source of the second NMOS tube and serves as the output end of the binary delay line; The source of the first NMOS transistor is connected to the first end of the second capacitor and is grounded, and the second end of the second capacitor is connected to the drain of the first NMOS transistor; The drain of the second NMOS tube is respectively connected to the second end of the first resistor, the first end of the second resistor and the source of the third NMOS tube; the drain of the third NMOS tube is respectively connected to the second end of the second resistor, the first end of the third resistor and the source of the fourth NMOS tube; the drain of the fourth NMOS tube is respectively connected to the second end of the third resistor, the first end of the fourth resistor and the source of the fifth NMOS tube; the drain of the fifth NMOS tube is respectively connected to the second end of the fourth resistor, the first end of the fifth resistor and the source of the sixth NMOS tube; the drain of the sixth NMOS tube is respectively connected to the second end of the fifth resistor and the source of the first PMOS tube; The gate of the second NMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are respectively connected to the input end of the third NOR gate.

[0012] Preferably, the up-down counter comprises: a D flip-flop, four JK flip-flops and a plurality of logic gate circuits; the CLK terminal of the D flip-flop is respectively connected to the CLK terminals of the four JK flip-flops, the Reset terminal of the D flip-flop is respectively connected to the Reset terminals of the four JK flip-flops, and the Q terminal of the D flip-flop is respectively connected to the Q terminals of the four JK flip-flops; The logic gate circuit includes: a fourth NAND gate, an OR gate and a fifth NAND gate; The output end of the fourth NAND gate is connected to the J end and the K end of the JK flip-flop respectively; the first input end of the fourth NAND gate is connected to the output end of the OR gate, and the second input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; The first input terminal of the OR gate is connected to the first input terminal of the fifth NAND gate and connected to the D terminal of the D flip-flop, and the second input terminal of the OR gate is connected to the second input terminal of the fifth NAND gate and connected to the signal input terminal.

[0013] Compared with the prior art, the beneficial effect of the present invention lies in that, by connecting the input end of the first input stage circuit with the input end of the second input stage circuit and jointly using them to connect the signal input end, the output end of the first input stage circuit and the output end of the second input stage circuit are respectively connected to the input end of the dynamic dead zone generating circuit, the output end of the dynamic dead zone generating circuit is respectively connected to the input end of the pulse generating circuit and the input end of the low-side delay circuit, the output end of the pulse generating circuit is connected to the input end of the level shifting circuit, the output end of the level shifting circuit is connected to the input end of the first amplifier, and the output end of the first amplifier is connected to the first input end of the converter circuit; the output end of the low-side delay circuit is connected to the input end of the second amplifier, the output end of the second amplifier is connected to the second input end of the converter circuit, and the output end of the converter circuit is used to connect the load; the negative voltage detection circuit is used to detect the delay signal of the converter circuit and feed it back to the dynamic dead zone generating circuit, thereby adjusting the dead zone time in real time. In this way, the negative voltage detection circuit is used to monitor the state of the Vs terminal voltage through the step-type adaptive dead zone circuit to determine the adjustment direction of the internal delay time used to generate the dead zone, and the delayed signal HO' of LO and OUT_H is used as the clock to read and latch the output signal of the negative voltage detection circuit, so as to adjust the dead zone time in real time. The HVIC works with the best dead zone time, thereby improving the reliability of the HVIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings: Figure 1 is a circuit diagram of a high-voltage integrated circuit with an integrated step-type adaptive dead zone function provided by an embodiment of the present invention; Figure 2 is a circuit diagram of a dynamic dead zone generating circuit provided by an embodiment of the present invention; Figure 3 is a waveform diagram of each node of the dynamic dead zone generating circuit provided by an embodiment of the present invention; Figure 4 is a circuit diagram of a first dynamic delay unit provided by an embodiment of the present invention; Figure 5 is a schematic diagram of the working process of the dynamic delay unit provided by an embodiment of the present invention; Figure 6 is a circuit diagram of a binary delay line provided by an embodiment of the present invention; Figure 7is a circuit diagram of an up-down counter provided by an embodiment of the present invention; Figure 8 It is a schematic diagram of simulation results of the dynamic delay unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0016] Combined with Figure 1-Figure 8 As shown, an embodiment of the present invention provides a high-voltage integrated circuit with an integrated step-type adaptive dead zone function, including: a first input stage circuit 1, a delay circuit 2, a second input stage circuit 3, a dynamic dead zone generating circuit 4, a pulse generating circuit 5, a level shifting circuit 6, a first amplifier 7, a negative voltage detecting circuit 8, a low-side delay circuit 9, a second amplifier 10 and a converter circuit 11; the input end of the first input stage circuit 1 is connected to the input end of the second input stage circuit 3 and is commonly used to connect the signal input end, the output end of the first input stage circuit 1 and the output end of the second input stage circuit 3 are respectively connected to the input end of the dynamic dead zone generating circuit 4, and the output end of the dynamic dead zone generating circuit 4 is respectively connected to the pulse generating circuit 8. The input end of the circuit 5 and the input end of the low-side delay circuit 9, the output end of the pulse generating circuit 5 is connected to the input end of the level shifting circuit 6, the output end of the level shifting circuit 6 is connected to the input end of the first amplifier 7, and the output end of the first amplifier 7 is connected to the first input end of the converter circuit 11; the output end of the low-side delay circuit 9 is connected to the input end of the second amplifier 10, the output end of the second amplifier 10 is connected to the second input end of the converter circuit 11, and the output end of the converter circuit 11 is used to connect the load; the negative voltage detection circuit 8 is used to detect the delay signal of the converter circuit 11 and feed it back to the dynamic dead zone generating circuit 4, so as to adjust the dead time in real time.

[0017] The first input stage circuit 1 and the second input stage circuit 3 are the same, and generally include an RC filter, a Schmitt circuit, a filter, a level conversion circuit, etc. connected in sequence.

[0018] The converter circuit 11 includes a first transistor Q1, a second transistor Q2, a first resistor R1, a first capacitor C1 and a first inductor L1; the gate of the first transistor Q1 serves as the first input terminal of the converter circuit 11, the drain of the first transistor Q1 is used to connect to a power supply, the source of the first transistor Q1 is respectively connected to the negative voltage detection circuit 8, the drain of the second transistor Q2 and the first end of the first inductor L1, the gate of the second transistor Q2 serves as the second input terminal of the converter circuit 11, and the source of the second transistor Q2 is grounded; the second end of the first inductor L1 is respectively connected to the first end of the first capacitor C1 and the first end of the first resistor R1, the second end of the first capacitor C1 is connected to the second end of the first resistor R1 and is grounded; the second end of the first inductor L1 also serves as the output terminal of the converter circuit 11. In this way, the negative voltage detection circuit 8 is used to monitor the state of the Vs terminal voltage through the step-type adaptive dead zone circuit to determine the adjustment direction of the internal delay time for generating the dead zone, and the delayed signal HO' of LO and OUT_H is used as the clock for reading and latching the output signal of the negative voltage detection circuit 8, so as to adjust the dead zone time in real time. The HVIC works with the best dead zone time, thereby improving the reliability of the HVIC.

[0019] Among them, the adaptive dead time circuit is composed of a dynamic dead time generating circuit 4, a delay circuit 2 and a VS negative voltage detecting circuit 8. The negative voltage detecting circuit 8 is used to monitor the state of the Vs terminal voltage to determine the adjustment direction of the internal delay time used to generate the dead time. The delay signal HO' of LO and OUT_H is used as a clock to read and latch the output signal of the negative voltage detecting circuit 8, so as to perform real-time dead time adjustment.

[0020] The first transistor Q1 and the second transistor Q2 are switching devices of a basic Buck converter, and the first inductor L1, the first capacitor C1, and the first resistor R1 are loads of the Buck converter.

[0021] In this embodiment, the delay circuit 2 includes a first dynamic delay unit 0304 and a second dynamic delay unit 0305; the input end of the first dynamic delay unit 0304 and the input end of the second dynamic delay unit 0305 are connected and serve as the input end of the delay circuit 2; the output end of the first dynamic delay unit 0304 and the output end of the second dynamic delay unit 0305 serve as the output end of the delay circuit 2 respectively.

[0022] In this embodiment, the dynamic dead zone generating circuit 4 includes: a first NOT gate 0301, a first NAND gate 0302, a first NOR gate 0303, a second NOT gate 0306, a second NAND gate 0307 and a second NOR gate 0308; The input end of the first NOT gate 0301 is connected to the input end of the first dynamic delay unit 0304, the output end of the first NOT gate 0301 is respectively connected to the first end of the first NAND gate 0302 and the first end of the first NOR gate 0303, and the second end of the first NAND gate 0302 is connected to the output end of the first dynamic delay unit 0304 as the first input end of the dynamic dead zone generating circuit 4; The input end of the second NOT gate 0306 is connected to the input end of the second dynamic delay unit 0305, the output end of the second NOT gate 0306 is respectively connected to the first end of the second NAND gate 0307 and the first end of the second NOR gate 0308, and the second end of the second NOT gate 0306 is connected to the output end of the second dynamic delay unit 0305 as the second input end of the dynamic dead zone generating circuit 4; The output end of the first NAND gate 0302 is connected to the second end of the second NOR gate 0308, the output end of the second NAND gate 0307 is connected to the second end of the first NOR gate 0303, the output end of the first NOR gate 0303 is connected to the input end of the pulse generating circuit 5, and the output end of the second NOR gate 0308 is connected to the input end of the low-side delay circuit 9.

[0023] Specifically, IN_H is connected to the input of the first NOT gate 0301 and the input IN of the first dynamic delay unit 0304 at the same time, and the output of the first NOT gate 0301, one input of the first NAND gate 0302 and the input of the first NOR gate 0303 are connected, which is denoted as A.

[0024] The output terminal OUT of the first dynamic delay unit 0304 is connected to the other input terminal of the first NAND gate 0302 , which is denoted as C1 .

[0025] The output terminal of the first NOR gate 0303 is OUT_H.

[0026] An output terminal of the first NAND gate 0302 is connected to an input terminal of the second NOR gate 0308, which is denoted as A1.

[0027] IN_L is connected to the input end of the second NOT gate 0306 and the input end IN of the second dynamic delay unit 0305 at the same time. The output end of the second NOT gate 0306, an input end of the second NAND gate 0307 and the input end of the second NOR gate 0308 are connected, which is denoted as B.

[0028] The output terminal OUT of the second dynamic delay unit 0305 is connected to the other input terminal of the second NAND gate 0307, ​​which is denoted as C2.

[0029] An output terminal of the second NAND gate 0307 is connected to an input terminal of the first NOR gate 0303, which is denoted as B1.

[0030] The output terminal of the second NOR gate 0308 is OUT_L.

[0031] The input terminal A of the first dynamic delay unit 0304 and the input terminal A of the second dynamic delay unit 0305 are connected to the output signal ND of the Vs negative voltage sampling detection circuit; the CLK input terminal of the first dynamic delay unit 0304 is connected to HO`; and the CLK input terminal of the second dynamic delay unit 0305 is connected to LO.

[0032] The following will be combined Figure 3 The waveforms of each node shown in the figure illustrate the working principle of the adaptive dead zone circuit. First, if the input signals of the two input terminals IN_H and IN_L of the chip overlap, the dead zone circuit will force the two signals OUT_H and OUT_L to zero in the overlapping area to ensure the normal output signal. In addition, a certain dead zone time will be superimposed. To make it clearer, the input signals IN_H and IN_L here are two interlaced square wave signals. The C1 signal is the output signal of IN_H after passing through the dynamic delay unit. The dynamic delay unit only delays the falling edge of the input signal and outputs an inverted signal. Therefore, the falling edge of IN_H is delayed, and the output is the A1 signal, which is used to control the opening time of the low-voltage side channel. Similarly, B1 is the falling edge delayed output signal of IN_L, which is used to control the opening time of the high-voltage side channel. Finally, the inverted signal A and B1 or the non-rear output signal of IN_H turns on the high-voltage side power tube Q1, and forms a dead time between the low-voltage side power device Q2 being turned off and the high-voltage side power device Q1 being turned on, while the inverted signal B and A1 or the non-rear output signal of IN_L turns on the low-voltage side power device Q2, and forms a dead time between the high-voltage side power device Q1 being turned off and the low-voltage side power device Q2 being turned on.

[0033] In this embodiment, the circuit structures of the first dynamic delay unit 0304 and the second dynamic delay unit 0305 are the same.

[0034] In this embodiment, the first dynamic delay unit 0304 includes: a trigger 12, a two-to-one data selector 13, an up-down counter 14, a binary delay line 15, an AND gate AND1, a third NAND gate NAND1, a third NOR gate NOR1, a fourth NOR gate NOR2 and a third IN gate INV1; The input end of the trigger 12 is used to connect the output end of the negative voltage detection circuit 8, the output end of the trigger 12 is connected to the X1 input end of the two-to-one data selector 13, the output end of the two-to-one data selector 13 is connected to the control end of the add-subtract counter 14, the output end of the add-subtract counter 14 is connected to the input end of the binary delay line 15, and the output end of the binary delay line 15 serves as the output end of the first dynamic delay unit 0304; the input end of the binary delay line 15 is connected to the input end of the NOT gate and serves together as the input end of the first dynamic delay unit 0304; The output end of the third NOT gate INV1 is connected to the CLK port of the up-down counter 14, the input end of the third NOR gate NOR1 is used to connect to the signal input end, the output end of the third NOR gate NOR1 is respectively connected to the first input end of the fourth NOR gate NOR2 and the first input end of the third NAND gate NAND1, the output end of the fourth NOR gate NOR2 is respectively connected to the second input end of the first NAND gate 0302 and the S input end of the two-to-one data selector 13; the output end of the third NAND gate NAND1 is connected to the X0 input end of the two-to-one data selector 13; the input end of the AND gate AND1 is used to connect to the signal input end, and the output end of the AND gate AND1 is connected to the second input end of the fourth NOR gate NOR2.

[0035] Specifically, the step-type dynamic delay unit is the core component of the entire adaptive dead-zone circuit, and its dynamic adjustment process determines the adaptability of the dead-zone time as the working state changes. Figure 4 Detailed circuit diagram of the dynamic delay unit is shown in FIG. 1 , including a D flip-flop 12 , a two-to-one data selector 13 , a 5-bit up-down counter 14 , a binary delay line 15 and logic circuits.

[0036] The D input terminal of the D flip-flop 12 is the input terminal A of the dynamic delay unit. Figure 2 The output signal ND of the negative voltage sampling detection circuit of Vs is connected; the output terminal Q of the D flip-flop 12 is connected to the X1 input terminal of the two-to-one data selector MUX1; the input CLK of the D flip-flop 12 is connected to the X1 input terminal of the two-to-one data selector MUX1; Figure 2 LO and HO` among them; the 5 input ends of the 5 NOR gates NOR1 are connected to Q0, Q1, Q2, Q3, and Q4 respectively; the 5 input ends of the 5 AND gates AND1 are connected to Q0, Q1, Q2, Q3, and Q4 respectively; the output end of the 5 NOR gates NOR1 and one input end of the NOR gate NOR2 are connected to the input end of the NAND gate NAND1; the output end of the 5 AND gates AND1 is connected to the other input end of the NOR gate NOR2; the output end of the NOR gate NOR2 and one input end of the NAND gate NAND1 are connected to the S input end of the two-to-one data selector MUX1.

[0037] The output end of the NAND gate NAND1 is connected to the X0 input end of the two-to-one data selector MUX1; the output end OUT of the two-to-one data selector MUX1 is connected to the up / down of the add-subtract counter; the input end IN of the dynamic delay unit is connected to the input end of the NOT gate INV1 and the input end of the binary delay line; the output end of the NOT gate INV1 is connected to the CLK of the add-subtract counter; the output end of the add-subtract counter is connected to the binary delay line; the output end of the binary delay line is the output end of the dynamic delay unit; Figure 5 The workflow diagram in the figure introduces the workflow of the dynamic delay unit in detail. First, after the chip is powered on, the add-subtract counter is reset, and the output is 00000, so that all switches in the binary delay line are closed, and the dead time is set to the maximum value of the adjustment range. This ensures that the circuit will not be directly connected due to the lack of initial judgment basis for the VS voltage after normal power-on. Then the circuit will determine whether the working state of the counter is 00000 or 11111. If the counter state is 00000, the logic circuit composed of NOR1, AND1, NOR2, NAND1 and the two-choice data selector MUX1 will force the input add-subtract control signal to be 0, so that the add-subtract counter is forced to add 1, and the circuit shields the input signal to directly read the delay of the binary delay line 15, and forms the dead time. Similarly, when the state of the counter is 11111, the logic circuit will force the input add-subtract control signal 1, so that the add-subtract counter 14 is forced to subtract 1, and the circuit will also shield the input signal and directly read the delay of the binary delay line 15, and form the dead time. The purpose of this function is the following two points: First, to prevent the add-subtract counter 14 from jumping directly from 11111 to 00000 when a long dead time is required during circuit operation, so that the dead time will be sharply reduced and cause circuit failure. Second, to prevent the circuit from jumping directly from the 00000 state to the 11111 state when a very small dead zone is required during circuit operation, thereby causing a long period of reverse conduction loss. If the output value of the add-subtract counter 14 is not the highest value or the lowest value, the chip will enter the waiting state. When the rising edge of the clk signal arrives (the high-voltage side channel delay in the chip is controlled by LO and affects the low-voltage side opening time; the low-voltage side channel delay is provided by the delay signal of OUT_H and affects the opening time of the high-voltage side channel), the value of the negative voltage detection circuit 8 is read. The voltage value at the VS end when the power tube is turned on can be used to determine whether the power device is in the reverse conduction stage. The main part of the negative voltage detection circuit 8 adopts Figure 1The structure introduced in the above is different in that the negative voltage detection circuit 8 used here has an inverted output and needs to add a short filtering time to prevent abnormal circuit state. The two dead zones of the Buck converter switching process respectively introduce the working state of the circuit: the first stage is the dead zone stage in which the working state of the Buck converter is the high-voltage side power tube Q1 to be turned off and the low-voltage side power tube Q2 to be turned on. When the output of the negative voltage detection circuit 8 is zero, it means that when the power tube Q2 is turned on, the power tube has already started to flow, indicating that Q2 is turned on late, so it is judged that the dead zone time is too large. After this signal enters the add-subtract counter, the value of the counter will be increased by 1, thereby reducing the dead zone time by one step; similarly, if the output of the negative voltage detection circuit 8 is 1 at this time, it means that the power tube Q2 has not entered the flow stage, and VS has not yet dropped to zero, the high-voltage side power device Q1 has not been completely turned off, and Q2 is turned on early. At this time, if the low-voltage side power tube is turned on, it will cause a large direct loss, so the dead time is too small. After the detection signal enters the add-subtract counter, its output value is reduced by one bit, thereby increasing the dead time by one step; the second stage is the dead stage in which the working state of the Buck converter is that the low-voltage side power tube Q2 is about to be turned off and the high-voltage side power tube Q1 is about to be turned on. It should be noted in advance that the delay time from OUT_H to HO' is the same as the delay time from OUT_H to HO. Therefore, when the gate signal of Q1 is applied with the turn-on signal, if the negative voltage detection circuit 8 outputs 0, it means that the low-voltage side power tube Q2 has been turned off and has entered the freewheeling stage. At this time, it is judged that the dead time is too long, and the control signal makes the value of the add-subtract counter plus 1, thereby controlling the binary delay line to reduce the dead time by one step. If the output of the negative voltage detection circuit 8 is 1, there are two situations. One is that Q2 has not been completely turned off, and a dead zone needs to be added at this time. Another situation is that the circuit works in DCM mode, the low-voltage side power tube is turned off and does not continue current. In this case, increasing the dead time does not increase system losses.

[0038] In this embodiment, the binary delay line includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6 and a second capacitor C2; The drain of the first PMOS transistor MP1 is used to connect to the power supply VCC, the gate of the first PMOS transistor MP1 is connected to the gate of the first NMOS transistor MN1 and serves as the input end of the binary delay line, and the drain of the first NMOS transistor MN1 is respectively connected to the first end of the first resistor R1R1 and the source of the second NMOS transistor MN2 and serves as the output end of the binary delay line; The source of the first NMOS transistor MN1 is connected to the first end of the second capacitor C2 and grounded, and the second end of the second capacitor C2 is connected to the drain of the first NMOS transistor MN1; The drain of the second NMOS transistor MN2 is respectively connected to the second end of the first resistor R1R1, the first end of the second resistor R2 and the source of the third NMOS transistor MN3; the drain of the third NMOS transistor MN3 is respectively connected to the second end of the second resistor R2, the first end of the third resistor R3 and the source of the fourth NMOS transistor MN4; the drain of the fourth NMOS transistor MN4 is respectively connected to the second end of the third resistor R3, the first end of the fourth resistor R4 and the source of the fifth NMOS transistor MN5; the drain of the fifth NMOS transistor MN5 is respectively connected to the second end of the fourth resistor R4, the first end of the fifth resistor R5 and the source of the sixth NMOS transistor MN6; the drain of the sixth NMOS transistor MN6 is respectively connected to the second end of the fifth resistor R5 and the source of the first PMOS transistor MP1; The gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are respectively connected to the input end of the third NOR gate.

[0039] Specifically, the binary delay line 15 uses an NMOS tube as a control device for the resistance short circuit.

[0040] The input terminal IN is connected to the G poles of MOS tubes MP1 and MN1; The D pole of MOS tube MP1 is connected to the power supply VCC; The S pole of the MOS tube MP1, the D pole of the MOS tube MN6 are connected to one end of the resistor R5; The S pole of the MOS tube MN6, the D pole of the MOS tube MN5, the other end of the resistor R5 and one end of the resistor R4 are connected; The S pole of the MOS tube MN5, the D pole of the MOS tube MN4, the other end of the resistor R4 and one end of the resistor R3 are connected; The S pole of the MOS tube MN4, the D pole of the MOS tube MN3, the other end of the resistor R3 and one end of the resistor R2 are connected; The S pole of the MOS tube MN3, the D pole of the MOS tube MN2, the other end of the resistor R2 and one end of the resistor R1 are connected; The S pole of the MOS tube MN2, the D pole of the MOS tube MN1, the other end of the resistor R1 and one end of the capacitor C are connected to serve as the output end OUT; The S pole of the MOS tube MN1 and the other end of the capacitor C are grounded; The G poles of MOS tubes MN2, MN3, MN4, MN5 and MN6 are connected to Q0, Q1, Q2, Q3 and Q4 respectively; When the power is on, the timer resets and MN2~MN6 are all turned off. The delay of the entire circuit to the falling edge of the IN signal can be expressed as follows: Delay max. =C*V th.NAND (VCC / (R1+R2+R3+R4+R5)); Where C is the capacitance value of the capacitor, and Vth,NAND represents the threshold voltage of the NAND gate connected to the back stage of the binary delay line. The resistance values ​​of the five controlled resistors increase exponentially. The delay shown in the above formula is also the maximum delay that the binary delay line can provide. When Q0~Q4 are all turned on, the delay of the binary delay line is the smallest: Delay min. =C*V th.NAND / VCC; As the output value of the binary up-down counter increases, the delay will decrease in a step-like manner. It is worth noting that the delay circuit 2 here only delays the falling edge of the IN signal. When IN changes from a low level to a high level, MN1 is turned on and the charge on C is quickly released.

[0041] In this embodiment, the up-down counter 14 includes: a D flip-flop 0801, four JK flip-flops (0802, 0803, 0804, 0805) and a plurality of logic gate circuits; the CLK terminal of the D flip-flop 0801 is respectively connected to the CLK terminals of the four JK flip-flops, the Reset terminal of the D flip-flop 0801 is respectively connected to the Reset terminals of the four JK flip-flops, and the Q terminal of the D flip-flop 0801 is respectively connected to the Q terminals of the four JK flip-flops; The logic gate circuit includes: a fourth NAND gate 0806, an OR gate 0807 and a fifth NAND gate 0808; The output end of the fourth NAND gate 0806 is connected to the J end and the K end of the JK flip-flop respectively; the first input end of the fourth NAND gate 0806 is connected to the output end of the OR gate 0807, and the second input end of the fourth NAND gate 0806 is connected to the output end of the fifth NAND gate 0808; The first input terminal of the OR gate 0807 is connected to the first input terminal of the fifth NAND gate 0808 and connected to the D terminal of the D flip-flop 0801, and the second input terminal of the OR gate 0807 is connected to the second input terminal of the fifth NAND gate 0808 and connected to the signal input terminal.

[0042] Specifically, the CLK of the D flip-flop 0801 and the CLK of the four JK flip-flops are connected together to the external CLK; The Reset of the D flip-flop 0801 and the Reset of four JK flip-flops are connected together to connect to the external Reset; The Q of the D flip-flop 0801 and the Q of the four JK flip-flops are Q0, Q1, Q2, Q3, and Q4 respectively; The input signal A is connected to one input terminal of the OR gate 0807 and one input terminal of the NAND gate 0808 at the same time; Another input terminal of the OR gate 0807 and another input terminal of the NAND gate 0808 are connected to the D and / Q of the D flip-flop 0801; An output terminal of the OR gate 0807, an input terminal of the NAND gate 0806, an input terminal of the OR gate 0809, and an input terminal of the NAND gate 0810 are connected; The output terminal of the NAND gate 0808 and the other input terminal of the NAND gate 0806 are connected; The output of NAND gate 0806 is connected to J and K of JK flip-flop 0802; Another input terminal of the OR gate 0809 and another input terminal of the NAND gate 0810 are connected to / Q of the JK flip-flop 0802; An output terminal of the OR gate 0809, an input terminal of the NAND gate 0811 and an input terminal of the OR gate 0813 are connected; The output terminal of the NAND gate 0810, the other input terminal of the NAND gate 0811 and one input terminal of the NAND gate 0814 are connected; Another output terminal of the OR gate 0813 and another input terminal of the NAND gate 0814 are connected to / Q of the JK flip-flop 0803; The output terminal of the NAND gate 0811 is connected to the J and K of the JK flip-flop 0803; An output terminal of the OR gate 0813, an input terminal of the NAND gate 0812 and an input terminal of the OR gate 0816 are connected; The output terminal of the NAND gate 0814, the other input terminal of the NAND gate 0812 and one input terminal of the NAND gate 0817 are connected; Another input terminal of the OR gate 0816 and another input terminal of the NAND gate 0817 are connected to / Q of the JK flip-flop 0804; The output terminal of the NAND gate 0815 is connected to the J and K of the JK flip-flop 0805; Reset is the reset port of the D flip-flop. When the chip is started, the counter is reset. When A is equal to 0, the counter value increases by one bit when the clock signal comes; and when A=1, the counter value decreases by one bit when the clock signal comes. Its combination with the logic circuit can effectively avoid direct jumps between 00000 and 11111. Figure 8The figure shows the simulation results of the entire dynamic delay unit, and the figure shows the waveforms of the CLK signal, ND input signal, and Q4~Q0. It can be seen that after the initial state counter is cleared, the ND signal remains at a low level, and the counter increments. When the counter value reaches the maximum, its state fluctuates between 11111 and 11110, and will not jump to 00000. Similarly, when the ND input signal becomes a high level, the counter enters the decrement process. When the counter reaches the minimum value, its state fluctuates between 00000 and 00001, and will not increase and jump to the 11111 state. During the operation of the counter, as the ND signal changes, the counter can realize the free addition and subtraction counting function without causing any misoperation.

[0043] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0044] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high voltage integrated circuit with a step-type adaptive dead zone function, characterized in that: include: A first input stage circuit, a delay circuit, a second input stage circuit, a dynamic dead zone generating circuit, a pulse generating circuit, a level shift circuit, a first amplifier, a negative voltage detection circuit, a low-side delay circuit, a second amplifier and a converter circuit; the input end of the first input stage circuit is connected to the input end of the second input stage circuit and is used to connect the signal input end together, the output end of the first input stage circuit and the output end of the second input stage circuit are respectively connected to the input end of the dynamic dead zone generating circuit, the output end of the dynamic dead zone generating circuit is respectively connected to the input end of the pulse generating circuit and the input end of the low-side delay circuit, the output end of the pulse generating circuit is connected to the input end of the level shift circuit, the output end of the level shift circuit is connected to the input end of the first amplifier, and the output end of the first amplifier is connected to the first input end of the converter circuit; the output end of the low-side delay circuit is connected to the input end of the second amplifier, the output end of the second amplifier is connected to the second input end of the converter circuit, and the output end of the converter circuit is used to connect a load; the negative voltage detection circuit is used to detect the delay signal of the converter circuit and feed it back to the dynamic dead zone generating circuit, so as to adjust the dead zone time in real time; The converter circuit includes a first transistor, a second transistor, a first resistor, a first capacitor and a first inductor; the gate of the first transistor serves as the first input end of the converter circuit, the drain of the first transistor is used to connect to a power supply, the source of the first transistor is respectively connected to the negative voltage detection circuit, the drain of the second transistor and the first end of the first inductor, the gate of the second transistor serves as the second input end of the converter circuit, and the source of the second transistor is grounded; the second end of the first inductor is respectively connected to the first end of the first capacitor and the first end of the first resistor, the second end of the first capacitor is connected to the second end of the first resistor and is grounded; the second end of the first inductor also serves as the output end of the converter circuit.

2. The high voltage integrated circuit with integrated step-type adaptive dead zone function as claimed in claim 1, characterized in that: The delay circuit includes a first dynamic delay unit and a second dynamic delay unit; the input end of the first dynamic delay unit and the input end of the second dynamic delay unit are connected and serve as the input end of the delay circuit; the output end of the first dynamic delay unit and the output end of the second dynamic delay unit serve as the output end of the delay circuit respectively.

3. The high voltage integrated circuit with a step-type adaptive dead zone function as claimed in claim 2, characterized in that: The dynamic dead zone generating circuit comprises: a first NOT gate, a first NAND gate, a first NOR gate, a second NOT gate, a second NAND gate and a second NOR gate; The input end of the first NOT gate is connected to the input end of the first dynamic delay unit, the output end of the first NOT gate is respectively connected to the first end of the first NAND gate and the first end of the first NOR gate, and the second end of the first NAND gate is connected to the output end of the first dynamic delay unit as the first input end of the dynamic dead zone generating circuit; The input end of the second NOT gate is connected to the input end of the second dynamic delay unit, the output end of the second NOT gate is respectively connected to the first end of the second NAND gate and the first end of the second NOR gate, and the second end of the second NOT gate is connected to the output end of the second dynamic delay unit as the second input end of the dynamic dead zone generating circuit; The output end of the first NAND gate is connected to the second end of the second NOR gate, the output end of the second NAND gate is connected to the second end of the first NOR gate, the output end of the first NOR gate is connected to the input end of the pulse generating circuit, and the output end of the second NOR gate is connected to the input end of the low-side delay circuit.

4. The high voltage integrated circuit with integrated step-type adaptive dead zone function as claimed in claim 3, characterized in that: The circuit structure of the first dynamic delay unit is the same as that of the second dynamic delay unit.

5. The high voltage integrated circuit with integrated step-type adaptive dead zone function as claimed in claim 4, characterized in that: The first dynamic delay unit includes: a trigger, a two-to-one data selector, an up-down counter, a binary delay line, an AND gate, a third NAND gate, a third NOR gate, a fourth NOR gate and a third NOT gate; The input end of the trigger is used to connect the output end of the negative voltage detection circuit, the output end of the trigger is connected to the X1 input end of the two-to-one data selector, the output end of the two-to-one data selector is connected to the control end of the add-subtract counter, the output end of the add-subtract counter is connected to the input end of the binary delay line, and the output end of the binary delay line serves as the output end of the first dynamic delay unit; the input end of the binary delay line is connected to the input end of the third NOT gate and serves as the input end of the first dynamic delay unit; The output end of the third NOT gate is connected to the CLK port of the up-down counter, the input end of the third NOR gate is used to connect to the signal input end, the output end of the third NOR gate is respectively connected to the first input end of the fourth NOR gate and the first input end of the third NAND gate, the output end of the fourth NOR gate is respectively connected to the second input end of the first NAND gate and the S input end of the two-to-one data selector; the output end of the third NAND gate is connected to the X0 input end of the two-to-one data selector; the input end of the AND gate is used to connect to the signal input end, and the output end of the AND gate is connected to the second input end of the fourth NOR gate.

6. The high voltage integrated circuit with integrated step-type adaptive dead zone function as claimed in claim 5, characterized in that: The binary delay line comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a second capacitor; The drain of the first PMOS tube is used to connect to the power supply, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and serves as the input end of the binary delay line, and the drain of the first NMOS tube is respectively connected to the first end of the first resistor and the source of the second NMOS tube and serves as the output end of the binary delay line; The source of the first NMOS transistor is connected to the first end of the second capacitor and is grounded, and the second end of the second capacitor is connected to the drain of the first NMOS transistor; The drain of the second NMOS tube is respectively connected to the second end of the first resistor, the first end of the second resistor and the source of the third NMOS tube; the drain of the third NMOS tube is respectively connected to the second end of the second resistor, the first end of the third resistor and the source of the fourth NMOS tube; the drain of the fourth NMOS tube is respectively connected to the second end of the third resistor, the first end of the fourth resistor and the source of the fifth NMOS tube; the drain of the fifth NMOS tube is respectively connected to the second end of the fourth resistor, the first end of the fifth resistor and the source of the sixth NMOS tube; the drain of the sixth NMOS tube is respectively connected to the second end of the fifth resistor and the source of the first PMOS tube; The gate of the second NMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are respectively connected to the input end of the third NOR gate.

7. The high voltage integrated circuit with integrated step-type adaptive dead zone function as claimed in claim 5, characterized in that: The up-down counter comprises: a D flip-flop, four JK flip-flops and a plurality of logic gate circuits; the CLK terminal of the D flip-flop is respectively connected to the CLK terminals of the four JK flip-flops, the Reset terminal of the D flip-flop is respectively connected to the Reset terminals of the four JK flip-flops, and the Q terminal of the D flip-flop is respectively connected to the Q terminals of the four JK flip-flops; The logic gate circuit includes: a fourth NAND gate, an OR gate and a fifth NAND gate; The output end of the fourth NAND gate is connected to the J end and the K end of the JK flip-flop respectively; the first input end of the fourth NAND gate is connected to the output end of the OR gate, and the second input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; The first input terminal of the OR gate is connected to the first input terminal of the fifth NAND gate and connected to the D terminal of the D flip-flop, and the second input terminal of the OR gate is connected to the second input terminal of the fifth NAND gate and connected to the signal input terminal.

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