Multi-level power factor correction circuit and control method thereof

Abstract

The invention relates to a multi-level power factor correction circuit and a control method thereof, and a control unit triggers the multi-level power factor correction circuit to enter a surge protection mode when an input voltage generates a surge condition, and controls two first switches, two second switches, a first polarity switch and a second polarity switch to be turned off. According to the multi-level power factor correction circuit, the input current received by the multi-level power factor correction circuit does not flow through the flying capacitor, so that the voltage on the flying capacitor is very stable and is not overcharged, and the safety of the multi-level power factor correction circuit is relatively high.

Description

Technical Field

[0001] This case relates to a power factor correction circuit, and in particular to a multi-level power factor correction circuit and a control method thereof. Background Art

[0002] The two-level power factor correction circuit includes a polarity switch and a power switch. When the input voltage or input current generates a surge, the polarity switch is controlled to be turned off to prevent the surge from damaging the two-level power factor correction circuit. However, in addition to the polarity switch and the power switch, the multi-level power factor correction circuit also includes a flying capacitor. When the input voltage or input current generates a surge, even if the polarity switch is turned off, the surge current generated by the input voltage may still flow through the flying capacitor of the multi-level power factor correction circuit, causing the multi-level flying capacitor to be overcharged and discharged, which will damage the multi-level power factor correction circuit, making the traditional multi-level power factor correction circuit less safe.

[0003] Therefore, it is necessary to develop a multi-level power factor correction circuit and a control method thereof to solve the problems faced by the prior art. Summary of the invention

[0004] The purpose of this case is to provide a multi-level power factor correction circuit and a control method thereof. When a surge occurs in the input voltage, the control unit triggers the multi-level power factor correction circuit to enter a surge protection mode, and controls the two first switches, the two second switches, the first polarity switch and the second polarity switch to remain off. The input current received by the multi-level power factor correction circuit of this case will not flow through the flying capacitor, so that the voltage on the flying capacitor is very stable and not overcharged. Therefore, the multi-level power factor correction circuit of this case has a higher safety.

[0005] To achieve the above-mentioned purpose, a preferred embodiment of the present case is to provide a multi-level power factor correction circuit, wherein the number of levels of the multi-level power factor correction circuit is N, N is an integer greater than or equal to 3, and the multi-level power factor correction circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, an inductor, (N-1) first switches, (N-1) second switches, (N-2) flying capacitors, a first polarity switch, a second polarity switch and a control unit. The first input terminal and the second input terminal are configured to receive an input voltage. The first output terminal and the second output terminal are configured to provide an output voltage. The inductor includes a first terminal and a second terminal, and the first terminal of the inductor is connected to the second input terminal. The (N-1) first switches are connected in series in sequence between the second terminal of the inductor and the second output terminal. The (N-1) second switches are connected in series in sequence between the second terminal of the inductor and the first output terminal. The kth flying capacitor is connected across the common connection point between the kth first switch and the k+1th first switch and the common connection point between the kth second switch and the k+1th second switch, where k is a positive integer less than or equal to (N-2). The first polarity switch is coupled between the first input terminal and the first output terminal. The second polarity switch is coupled between the first input terminal and the second output terminal. The control unit is used to control the working state of the multi-level power factor correction circuit according to the state of the input voltage, wherein the control unit triggers the multi-level power factor correction circuit to enter a surge protection mode when a surge occurs in the input voltage, and controls the first polarity switch, the second polarity switch, the (N-1) first switches and the (N-1) second switches to be turned off.

[0006] To achieve the above-mentioned purpose, another preferred embodiment of the present invention is to provide a surge protection control method for a multi-level power factor correction circuit, wherein the number of levels of the multi-level power factor correction circuit is N, N is an integer greater than or equal to 3, and the multi-level power factor correction circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, an inductor, (N-1) first switches, (N-1) second switches, (N-2) flying capacitors, a first polarity switch and a second polarity switch, wherein the first input terminal and the second input terminal are configured to receive an input voltage, and the first output terminal and the second output terminal are configured to provide an output voltage. The first end of the inductor is connected to the second input end, (N-1) first switches are connected in series between the second end of the inductor and the second output end, (N-1) second switches are connected in series between the second end of the inductor and the first output end, the kth flying capacitor is connected between the common connection point of the kth first switch and the k+1th first switch and the common connection point of the kth second switch and the k+1th second switch, wherein k is a positive integer less than or equal to (N-2), the first polarity switch is connected between the first input end and the first output end, and the second polarity switch is connected between the first input end and the second output end. The surge protection control method comprises the following steps: controlling the working state of the multi-level power factor correction circuit according to the state of the input voltage, and triggering the multi-level power factor correction circuit to enter the surge protection mode when the input voltage generates a surge, and controlling the first polarity switch, the second polarity switch, the (N-1) first switches and the (N-1) second switches to be turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 The circuit topology diagram of the multi-level power factor correction circuit in this case;

[0008] Figure 2A and Figure 2B They are respectively the charging and discharging path diagrams of the flying capacitor of the multi-level power factor correction circuit;

[0009] Figure 3 A current path diagram of the multi-level power factor correction circuit of the present invention when a surge occurs in the input voltage;

[0010] Figure 4 for Figure 1 A block diagram of a control unit of a first embodiment of a multi-level power factor correction circuit shown;

[0011] Figure 5 for Figure 1 A detailed topological diagram of a control unit of a second embodiment of a multi-level power factor correction circuit shown;

[0012] Fig. 6A for Figure 1A detailed topological diagram of a control unit of a third embodiment of the multi-level power factor correction circuit shown;

[0013] Figure 6B for Figure 1 A detailed topological diagram of a control unit of a fourth embodiment of a multi-level power factor correction circuit shown;

[0014] Figure 7 for Figure 1 A flow chart of a control method of a multi-level power factor correction circuit shown;

[0015] Figure 8 A circuit topology diagram of a multi-level power factor correction circuit according to a fifth embodiment of the present invention;

[0016] Fig. 9 A circuit topology diagram of a multi-level power factor correction circuit according to a sixth embodiment of the present invention; and

[0017] Fig.10 FIG. 4 is a circuit topology diagram of a multi-level power factor correction circuit according to the seventh embodiment of the present invention.

[0018] The reference numerals are described as follows:

[0019] 1, 1d, 1e, 1f: Multi-level power factor correction circuit

[0020] 2: AC power supply

[0021] 31: First input terminal

[0022] 32: Second input terminal

[0023] 33: First output terminal

[0024] 34: Second output terminal

[0025] L1: First inductor

[0026] 51: First End

[0027] 52: Second End

[0028] S1, S3: First switch

[0029] A1: First common connection point

[0030] S2, S4: Second switch

[0031] A2: Second common connection point

[0032] Cfly1: Flying capacitor

[0033] Sa: First polarity switch

[0034] Sb: Second polarity switch

[0035] 4.4a,4b: Control unit

[0036] 41: Inrush current sampling module

[0037] 41a: Voltage shaping circuit

[0038] 411: First sampling output terminal

[0039] 412: Second sampling output terminal

[0040] 413: Sampling Circuit

[0041] D3: The first rectifier diode

[0042] D4: Second rectifier diode

[0043] D5: The third rectifier diode

[0044] D6: The fourth rectifier diode

[0045] L3: Secondary winding

[0046] C1: First sampling capacitor

[0047] R1: The first sampling resistor

[0048] R2: Second sampling resistor

[0049] C2: Second sampling capacitor

[0050] D7: diode

[0051] 42: Surge judgment module

[0052] 43: False trigger module

[0053] Err: False trigger signal

[0054] 44: Shielding module

[0055] S5: Shielding switch element

[0056] Cbulk: output capacitance

[0057] Vi: Inrush current sampling signal

[0058] Vt: Surge protection threshold

[0059] 6: Bypass unit

[0060] Ds1: The first diode

[0061] Ds2: Second diode

[0062] Y: Polarity switch midpoint

[0063] Z: diode midpoint

[0064] L2: Primary winding

[0065] M1-M4: Steps DETAILED DESCRIPTION

[0066] Some typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different implementations without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0067] See also Figure 1 , Figure 1 The circuit topology diagram of the multi-level power factor correction circuit of the present case. As shown in the figure, the multi-level power factor correction circuit 1 of the present embodiment is a three-level power factor correction circuit, that is, the number of levels of the multi-level power factor correction circuit 1 of the present embodiment is 3. The multi-level power factor correction circuit 1 of the present embodiment receives the input voltage provided by the AC power supply 2 and provides electrical energy to the load (not shown), and the multi-level power factor correction circuit 1 includes a first input terminal 31, a second input terminal 32, a first output terminal 33, a second output terminal 34, a first inductor L1, two first switches S1, S3, two second switches S2, S4, a flying capacitor Cfly1, a first polarity switch Sa, a second polarity switch Sb, a control unit 4 and an output capacitor Cbulk.

[0068] The first input terminal 31 and the second input terminal 32 are respectively connected to two ends of the AC power source 2, and are configured to receive an input voltage provided by the AC power source 2. The first output terminal 33 and the second output terminal 34 are configured to provide an output voltage to a load. The first inductor L1 includes a first terminal 51 and a second terminal 52, and the first terminal 51 of the first inductor L1 is connected to the second output terminal 32.

[0069] The two first switches S1 and S3 are connected in series between the second end 52 of the first inductor L1 and the second output end 34, wherein the first switch S1 is connected to the second end 52 of the first inductor L1, the first switch S3 is connected to the second output end 34, and the connection between the first switches S1 and S3 constitutes a first common connection point A1. The two second switches S2 and S4 are connected in series between the second end 52 of the first inductor L1 and the first output end 33, the second switch S2 is connected to the second end 52 of the first inductor L1, the second switch S4 is connected to the first output end 33, and the connection between the second switches S2 and S4 constitutes a second common connection point A2. In other words, the second switch S4, the second switch S2, the first switch S1 and the first switch S3 are connected in series between the first output end 33 and the second output end 34 in sequence. The flying capacitor Cfly1 is connected across the first common connection point A1 and the second common connection point A2. In this embodiment, the first switches S1 and S3 and the second switches S2 and S4 are all controlled to operate in a PWM switching state, wherein the driving signals received by the first switch S1 and the second switch S4 are the same, namely, the first driving signal; the driving signals received by the first switch S2 and the second switch S3 are the same, namely, the second driving signal; and the first driving signal and the second driving signal are complementary.

[0070] The first polarity switch Sa is connected between the first input terminal 31 and the first output terminal 33, wherein the first polarity switch Sa is turned on when the input voltage provided by the AC power supply 2 is in the positive half cycle. The second polarity switch Sb is connected between the first input terminal 31 and the second output terminal 34, wherein the second polarity switch Sb is turned on when the input voltage provided by the AC power supply 2 is in the negative half cycle. In summary, the switching frequency of the first polarity switch Sa and the second polarity switch Sb is much lower than that of the first switch S1, S3 and the second switch S2, S4, so they are also called slow switches (tubes). According to the setting positions of the first polarity switch Sa and the second polarity switch Sb, when the potential of the first input terminal 31 is lower than the potential of the second input terminal 32, the second polarity switch Sb is turned on; when the potential of the first input terminal 31 is higher than the second input terminal 32, the first polarity switch Sa is turned on. The output capacitor Cbulk is connected between the first output terminal 33 and the second output terminal 34.

[0071] It should be understood that the first switches S1, S3 and the second switches S2, S4 as well as the first polarity switch Sa and the second polarity switch Sb can all be power transistors such as JFETs, MOSFETs, IGBTs, etc. with anti-parallel diodes. Of course, in some cases, some power transistors have built-in body diodes. This case is explained by taking MOSFETs as an example.

[0072] The control unit 4 is used to control the working state of the overall multi-level power factor correction circuit 1 according to the state of the input voltage received by the first input terminal 31 and the second input terminal 32, wherein when a surge occurs in the input voltage provided by the AC power source 2, for example, when the input voltage exceeds the instantaneous overvoltage that the multi-level power factor correction circuit 1 can withstand, the control unit 4 triggers the multi-level power factor correction circuit 1 to enter a surge protection mode, so that the control unit 4 controls the two first switches S1, S3, the two second switches S2, S4, the first polarity switch Sa and the second polarity switch Sb to remain off.

[0073] Please continue reading Figure 1 In this embodiment, the multi-level power factor correction circuit 1 further includes a bypass unit 6, which is connected between the first output terminal 33 and the second output terminal 34, and includes a first diode Ds1 and a second diode Ds2, which are sequentially connected between the first output terminal 33 and the second output terminal 34, wherein the cathode of the first diode Ds1 is connected to the first output terminal 33, the cathode of the second diode Ds2 is connected to the anode of the first diode Ds1, and the anode of the second diode Ds2 is connected to the second output terminal 34, wherein the connection point between the cathode of the second diode Ds2 and the anode of the first diode Ds1 constitutes a diode midpoint Z, and the diode midpoint Z is connected to the second input terminal 32 (i.e., the first end 51 of the first inductor L1). When a surge occurs, since the surge voltage has a very high peak, the input voltage will be greater than the voltage of the output capacitor Cbulk. Therefore, at the moment when a positive surge voltage is generated, the surge current loop is the first diode Ds1-output capacitor Cbulk-second polarity switch Sb, and at the moment when a negative surge voltage is generated, the surge current loop is the first polarity switch Sa-output capacitor Cbulk-second diode Ds2, without passing through the first switch S1, S3 and the second switch S2, S4, thereby avoiding damage to the switches.

[0074] See also Figure 2A and Figure 2B ,in Figure 2A and Figure 2B 1 and 2 are respectively a charging and discharging path diagram of the flying capacitor of the multi-level power factor correction circuit. In the case of normal operation, the potential of the first input terminal 31 is lower than the potential of the second input terminal 32. When the AC power supply 2 charges the flying capacitor Cfly1, as shown in FIG. Figure 2A As shown, the AC current provided by the AC power source 2 will flow through the first inductor L1, the second switch S2, the flying capacitor Cfly1, the first switch S3, and the second polarity switch Sb in sequence; and when the flying capacitor Cfly1 is discharged, as shown in FIG. Figure 2BAs shown, the current provided by the flying capacitor Cfly1 will flow through the second switch S4, the output capacitor Cbulk, the second polarity switch Sb, the first inductor L1 and the first switch S1 in sequence. When a positive surge voltage arrives, the peak of the surge voltage only lasts for a moment, but because the current it generates lasts for a long time, when the surge voltage ends, the input current is still relatively large. At this time, if the traditional power factor correction circuit is still continued to only control the polarity switch to turn off, the input current will still pass through the body diode (or anti-parallel diode) of the second polarity switch Sb, and the current path has not changed, so that the larger input current will over-charge and discharge the flying capacitor Cfly1, resulting in an increase in the withstand voltage of the switch, and then there is a risk of damage.

[0075] Therefore, in order to avoid damage to the switch, the multi-level power factor correction circuit in this case uses the surge protection mode to achieve the effect of changing the current path. Figure 3 , which is a current path diagram of the multi-level power factor correction circuit of the present invention when the input voltage generates a surge. When the input voltage generates a surge, the control unit 4 of the multi-level power factor correction circuit 1 of the present invention triggers the multi-level power factor correction circuit 1 to enter the surge protection mode, and controls the two first switches S1, S3, the two second switches S2, S4, the first polarity switch Sa and the second polarity switch Sb to remain off, so that when the above-mentioned Figure 2A and Figure 2B When a surge occurs in the circuit, after adopting the control method proposed in this case, the input current sequentially flows through the first inductor L1, the body diode (or anti-parallel diode) of the second switch S2 and S4, the output capacitor Cbulk, and the body diode (or anti-parallel diode) of the second polarity switch Sb, or the input current sequentially flows through the first inductor L1, the body diode (or anti-parallel diode) of the first switch S1 and S3, the output capacitor Cbulk, and the body diode (or anti-parallel diode) of the first polarity switch Sa. Compared with the traditional power factor correction circuit that only controls the polarity switch to be turned off, the input current of the multi-level power factor correction circuit 1 of this case will not flow through the flying capacitor Cfly1, so that the voltage on the flying capacitor Cfly1 is very stable and not over-charged or over-discharged, so the multi-level power factor correction circuit 1 of this case is safer.

[0076] It should be understood that this embodiment only takes the case where the potential of the first input terminal 31 is lower than the potential of the second input terminal 32 and a positive surge voltage arrives as an example for explanation. Other situations are similar to the above situations, and ordinary technicians in this field can deduce them based on the above description, so they will not be repeated here.

[0077] See also Figure 4 And cooperate Figure 1 ,in Figure 4 for Figure 1The block diagram of the control unit of the first embodiment of the multi-level power factor correction circuit shown in FIG. As shown in the figure, in this embodiment, the control unit 4 includes a surge current sampling module 41 and a surge judgment module 42. As described above, the surge current flows to the output capacitor Cbulk via the first diode Ds1 or the second diode Ds2 of the bypass unit 6, and the surge current sampling module 41 is used to sample the surge current and generate a surge current sampling signal Vi according to the surge current. Therefore, one end of the surge current sampling module 41 is connected to the diode midpoint Z between the first diode Ds1 and the second diode Ds2, and the other end of the surge current sampling module 41 is connected to the second input terminal 32. Specifically, the surge current sampling module 41 includes a current transformer or a resistor. The surge judgment module 42 has a preset surge protection threshold value Vt, and the surge judgment module 42 receives the surge current sampling signal Vi generated by the surge current sampling module 41, wherein when the surge judgment module 42 judges that the surge situation is that the surge current sampling signal Vi is greater than the surge protection threshold value Vt, a trigger signal is generated to trigger the multi-level power factor correction circuit 1 to enter the surge protection mode, so that the driving module (not shown) in the control unit 4 controls the two first switches S1, S3, the two second switches S2, S4, the first polarity switch Sa and the second polarity switch Sb to remain turned off.

[0078] Figure 5 for Figure 1 Detailed topology diagram of the control unit of the second embodiment of the multi-level power factor correction circuit shown in FIG. Figure 5 , Figure 4 and Figure 1As shown, the surge current sampling module 41 also includes a sampling circuit 413 and a voltage shaping circuit 41a. The sampling circuit 413 samples the surge current and outputs the sampled current information to the voltage shaping circuit 41a, and the voltage shaping circuit 41a outputs the surge current sampling signal Vi according to the current information. In this embodiment, the sampling circuit 413 is described by taking a current transformer as an example. The current transformer includes a primary winding L2 and a secondary winding L3, and the primary winding L2 is connected in series between the midpoint Z of the diode and the second input terminal 32, so that the surge current flows through the primary winding L2, thereby generating an induced current on the secondary winding L3. The voltage shaping circuit 41a is connected to the secondary winding L3 in the current transformer to shape the electrical signal induced by the secondary winding L3 to obtain the surge current sampling signal Vi. Specifically, the voltage shaping circuit 41a includes a rectifier unit, a filter circuit, a first sampling output terminal 411 and a second sampling output terminal 412, so that the electrical signal induced by the secondary winding L3 is rectified by the rectifier unit to obtain an electrical signal in a DC form, and then converted into the surge current sampling signal Vi through the filter circuit. Specifically, the rectifier unit includes a first rectifier diode D3, a second rectifier diode D4, a third rectifier diode D5 and a fourth rectifier diode D6, wherein the first rectifier diode D3, the second rectifier diode D4, the third rectifier diode D5 and the fourth rectifier diode D6 constitute a rectifier bridge, wherein one end of the secondary winding L3 is connected to the midpoint between the first rectifier diode D3 and the second rectifier diode D4, and the other end of the secondary winding L3 is connected to the midpoint between the third rectifier diode D5 and the fourth rectifier diode D6. The filter circuit includes a first sampling capacitor C1, a first sampling resistor R1, a second sampling resistor R2 and a second sampling capacitor C2, wherein the first sampling capacitor C1 and the first sampling resistor R1 constitute an RC parallel filter circuit, and the second sampling resistor R2 and the second sampling capacitor C2 constitute an RC series filter circuit. The first sampling output terminal 411 is connected to the common node of the second sampling resistor R2 and the second sampling capacitor C2, and the second sampling output terminal 412 is used for grounding. In addition, the surge current sampling module 41 also includes a diode D7, which is connected to the common node of the first sampling resistor R1 and the second sampling resistor R2, and the cathode of the diode D7 receives the maximum voltage allowed by the surge current sampling module 41, for example, 3.3V. The second sampling resistor R2 is connected to the first sampling output terminal 411, and the second sampling capacitor C2 is connected between the first sampling output terminal 411 and the second sampling output terminal 412. It should be understood that the sampling circuit 413 can also be implemented using a resistor, with both ends of the resistor being respectively connected between the midpoint Z of the diode and the second input terminal 32, and both ends of the resistor being respectively connected to the input terminal of the voltage shaping circuit 41a (i.e., one end of the resistor is connected to the midpoint between the first rectifier diode D3 and the second rectifier diode D4, and the other end is connected to the midpoint between the third rectifier diode D5 and the fourth rectifier diode D6).The surge determination module 42 includes a comparator, wherein a first input terminal of the comparator is connected to the first sampling output terminal 411 of the surge current sampling module 41 , a second input terminal of the comparator is used to receive a surge protection threshold Vt, and an output terminal of the comparator outputs a trigger signal.

[0079] In some special cases, when a surge condition is generated and then the normal condition is restored, the control unit 4 still continues to believe that the surge condition is still occurring and continues to be in the surge protection mode. In some embodiments, the control unit 4 further determines whether the surge protection mode is a false trigger condition, and when the surge protection mode is determined to be a false trigger condition, the multi-level power factor correction circuit 1 is controlled to exit the surge protection mode. The following will further explain how the control unit 4 determines whether the surge protection mode is in a surge condition or a false trigger condition.

[0080] See also Fig. 6A , which is the case Figure 1 The detailed topology diagram of the control unit of the third embodiment of the multi-level power factor correction circuit shown in FIG. Figure 5The control unit 4 shown only includes an inrush current sampling module 41 and a surge judgment module 42. The control unit 4a of this embodiment also includes a false trigger module 43 and a shielding module 44. The false trigger module 43 is used to receive the inrush current sampling signal Vi generated by the inrush current sampling module 41 (and / or directly receive the input voltage sampling signal provided by the AC power source 2), and determine whether the surge protection mode is a false trigger situation according to the inrush current sampling signal Vi and / or the input voltage sampling signal. For example, the false trigger module 43 confirms whether the inrush current sampling signal Vi and / or the input voltage sampling signal are within a preset threshold range to determine whether the current surge protection mode is a false trigger situation. When the inrush current sampling signal Vi and / or the input voltage sampling signal are within the preset threshold range, the current surge protection mode is determined to be a false trigger situation, and the false trigger module 43 generates a false trigger signal Err when the current surge protection mode is a false trigger situation. When the inrush current sampling signal Vi and / or the input voltage sampling signal are not within the preset threshold range, the current surge protection mode is determined not to be a false trigger situation. In some embodiments, in order to more accurately confirm whether the surge protection mode is a false trigger, the false trigger module 43 not only confirms whether the surge protection mode is a false trigger based on the surge current sampling signal Vi and / or the input voltage sampling signal received once, but can also more accurately determine whether it is a false trigger based on multiple consecutive confirmations. For example, the false trigger module 43 determines that the current surge protection mode is a false trigger when the input voltage sampling signal or surge current sampling signal received M times in succession is within the preset threshold range. When the input voltage sampling signal or surge current sampling signal received M times in succession is not all within the preset threshold range, it is determined that the current surge protection mode is not a false trigger, where M≥2.

[0081] Please continue reading Fig. 6A , the shielding module 44 is connected to the false triggering module 43, and is arranged between the surge current sampling module 41 and the surge judging module 42, wherein when the shielding module 44 receives the false triggering signal Err generated by the false triggering module 43, the shielding module 44 is used to shield the surge current sampling signal Vi provided by the surge current sampling module 41, so that the surge current sampling signal Vi is less than the surge protection threshold Vt, thereby invalidating the trigger signal output by the surge judging module 42, so that the multi-level power factor correction circuit 1 exits the surge protection mode, and then the two first switches S1, S3, the two second switches S2, S4, the first polarity switch Sa and the second polarity switch Sb resume normal working state. It should be understood that "shielding" in this article refers to making the signal invalid (for example, low level), or the signal does not work.

[0082] In some embodiments, the shielding module 44 includes a driving circuit 45 and a shielding switch element S5. The shielding switch element S5 is connected between the output end of the surge current sampling module 41 and the ground. The control end of the shielding switch element S5 receives the false trigger signal Err generated by the false trigger module 43 via the driving circuit 45. When the false trigger signal Err is valid (for example, a high level), it controls the shielding switch element S5 to turn on, thereby pulling down the surge current sampling signal Vi to make it less than the surge protection threshold Vt. The setting position of the shielding module 44 can be adjusted according to needs, please refer to Figure 6B , which is Figure 1 The detailed topology diagram of the control unit of the fourth embodiment of the multi-level power factor correction circuit shown in FIG. Fig. 6A The control unit 4a shown in the figure, the shielding module 44 of the control unit 4b of this embodiment is arranged between the output end of the surge judgment module 42 and the ground to shield the trigger signal generated by the surge judgment module 42, so that the multi-level power factor correction circuit exits the surge protection mode. The principle is the same as Fig. 6A The same is not described here. In other embodiments, the shielding module 44 can also be directly set at the output end of the driving module (not shown) for driving the switch to directly shield the driving signal generated by the driving module. Alternatively, in some embodiments, the control unit can also be implemented in a pure software manner, or any method that can shield the trigger signal can be used to achieve the purpose of exiting the surge protection mode. In some embodiments, the sampling circuit 413 includes a sampling resistor, and sampling is performed through the sampling resistor.

[0083] See also Figure 7 And cooperate Figure 1 and Figure 2, where Figure 7 for Figure 1 Flow chart of the control method of the multi-level power factor correction circuit shown. First, execute step M1 to control the working state of the multi-level power factor correction circuit 1 according to the state of the input voltage, and trigger the multi-level power factor correction circuit 1 to enter the surge protection mode when the input voltage generates a surge, and control the first polarity switch Sa, the second polarity switch Sb, (N-1) first switches S1, S3 and (N-1) second switches S2, S4 to be turned off. In some embodiments, the control method further includes step M2, judging whether the surge protection mode is a false triggering situation, when the judgment result of step M2 is yes, execute step M3, control the multi-level power factor correction circuit 1 to exit the surge protection mode, and when the judgment result of step M2 is no, re-execute step M1.

[0084] In some embodiments, the multi-level power factor correction circuit 1 can also use the method of adjusting the surge protection threshold Vt to avoid false triggering. For example, when the input voltage is a DC voltage, if the input voltage suddenly loses power, the output capacitor Cbulk voltage will decrease. Then when the input voltage is restored, the voltage on the output capacitor Cbulk (i.e., the output voltage) is lower than the input voltage, and most of the current will flow to the output side through the primary winding L2, so that the surge current sampling signal Vi induced by the secondary winding L3 is also greater than the surge protection threshold Vt, causing the surge protection mode to be falsely triggered, and thus continue to be in the surge protection mode, resulting in the output voltage being unable to rise normally. In order to avoid this situation, the control unit 4 can set the false trigger threshold Vsft according to the output current peak value when the multi-level power factor correction circuit 1 is working normally, so that the set surge protection threshold Vt is greater than the false trigger threshold Vsft. For example, the calculation equation of the false trigger threshold Vsft is as shown in formula (1),

[0085]

[0086] Among them, V sft is the preset false trigger threshold, I out_peak is the output current peak value when the multi-level power factor correction circuit 1 works normally, N s is the coil turns ratio between the primary winding L2 and the secondary winding L3, and R1 is the resistance value of the first sampling resistor.

[0087] In some embodiments, the location of the inrush current sampling module 41 of the control unit 4 can be adjusted according to the requirements. Figure 8 , which is a circuit topology diagram of a multi-level power factor correction circuit of the fifth embodiment of the present invention. As shown in the figure, compared with Figure 1 In the multi-level power factor correction circuit 1 shown in the figure, the surge current sampling module 41 of the control unit 4 of the multi-level power factor correction circuit 1d of this embodiment is arranged between the second input terminal 32 and the first end 51 of the first inductor L1, and is arranged between the second input terminal 32 and the midpoint Z of the diode. In this embodiment, the first end 51 of the first inductor L1 and the midpoint Z of the diode are connected to each other.

[0088] See also Fig. 9 , which is a circuit topology diagram of a multi-level power factor correction circuit of the sixth embodiment of the present invention. As shown in the figure, compared with Figure 1In the multi-level power factor correction circuit 1 shown in the embodiment, one end of the inrush current sampling module 41 of the control unit 4 of the multi-level power factor correction circuit 1e of the embodiment is connected to the first input terminal 31, and the other end of the inrush current sampling module 41 is connected to the polarity switch midpoint Y between the first polarity switch Sa and the second polarity switch Sb. In the embodiment, the first end 51 of the first inductor L1 and the midpoint Z of the diode are connected to each other.

[0089] In some embodiments, the number of levels of the multi-level power factor correction circuit may not only be three, but may be an integer greater than three. Fig.10 , which is a circuit topology diagram of the multi-level power factor correction circuit of the seventh embodiment of the present case. Figure 1 The multi-level power factor correction circuit 1 shown in the embodiment has a level number of N, where N is an integer greater than three. The number of first switches in the embodiment is (N-1), which are S1, S3..., S(2N-3), the number of second switches is (N-1), which are S2, S4..., S(2N-2), the number of flying capacitors is (N-2), which are Cfly1, Cfly2..., Cfly(N-2), wherein the kth flying capacitor is connected across the common connection point between the kth first switch and the k+1th first switch and the common connection point between the kth second switch and the k+1th second switch, wherein k is a positive integer less than or equal to (N-2). The circuit topology and control method are similar to those of the first embodiment, so they are not repeated here.

[0090] In summary, the control unit of the multi-level power factor correction circuit of the present invention triggers the multi-level power factor correction circuit to enter the surge protection mode when the input voltage generates a surge, and controls the two first switches, the two second switches, the first polarity switch and the second polarity switch to remain off. Compared with the traditional power factor correction circuit that only controls the polarity switch to be turned off, the input current received by the multi-level power factor correction circuit of the present invention will not flow through the flying capacitor, so that the voltage on the flying capacitor is very stable and not overcharged, so the multi-level power factor correction circuit of the present invention is safer.

Claims

1. A multi-level power factor correction circuit, wherein the number of levels of the multi-level power factor correction circuit is N, N is an integer greater than or equal to 3, and the multi-level power factor correction circuit comprises: a first input terminal; a second input terminal, wherein the first input terminal and the second input terminal are configured to receive an input voltage; a first output terminal; a second output terminal, wherein the first output terminal and the second output terminal are configured to provide an output voltage; an inductor comprising a first end and a second end, wherein the first end of the inductor is connected to the second input end; (N-1) first switches are sequentially connected in series between the second end of the inductor and the second output end; (N-1) second switches are connected in series between the second end of the inductor and the first output end; (N-2) flying capacitors, wherein the kth flying capacitor is connected between a common connection point between the kth first switch and the k+1th first switch and a common connection point between the kth second switch and the k+1th second switch, wherein k is a positive integer less than or equal to (N-2); a first polarity switch coupled between the first input terminal and the first output terminal; a second polarity switch coupled between the first input terminal and the second output terminal; and A control unit is used to control the working state of the multi-level power factor correction circuit according to the state of the input voltage, wherein the control unit triggers the multi-level power factor correction circuit to enter a surge protection mode when the input voltage generates a surge condition, and controls the first polarity switch, the second polarity switch, the (N-1) first switches and the (N-1) second switches to be turned off.

2. The multi-level power factor correction circuit as described in claim 1, wherein the control unit includes a surge current sampling module and a surge judgment module, the surge current sampling module samples a surge current to generate a surge current sampling signal when the surge condition occurs, and the surge judgment module receives the surge current sampling signal and generates a trigger signal to trigger the surge protection mode when it is determined that the surge condition is that the surge current sampling signal is greater than a surge protection threshold.

3. A multi-level power factor correction circuit as described in claim 2, wherein the multi-level power factor correction circuit includes a bypass unit, and in the surge condition, the surge current forms a loop through the bypass unit and the second polarity switch, or forms a loop through the bypass unit and the first polarity switch.

4. A multi-level power factor correction circuit as described in claim 3, wherein the bypass unit includes a first diode and a second diode, the first diode and the second diode are connected between the first output terminal and the second output terminal in sequence, and a diode midpoint between the first diode and the second diode is coupled to the first end of the inductor. 5 . The multi-level power factor correction circuit as claimed in claim 4 , wherein the midpoint of the diode is connected to the first end of the inductor via the surge current sampling module.

6. The multi-level power factor correction circuit as claimed in claim 4, wherein the surge current sampling module is connected between a midpoint between the first polarity switch and the second polarity switch and the first input terminal or between the second input terminal and the first terminal of the inductor.

7. The multi-level power factor correction circuit as claimed in claim 2, wherein the control unit controls the multi-level power factor correction circuit to exit the surge protection mode when the control unit determines that the surge protection mode is a false triggering situation.

8. A multi-level power factor correction circuit as described in claim 7, wherein the control unit has a false trigger threshold, wherein the false trigger threshold is set according to an output current peak value when the multi-level power factor correction circuit is working normally, and wherein the control unit adjusts the surge protection threshold to be greater than the false trigger threshold.

9. The multi-level power factor correction circuit as described in claim 7, wherein the multi-level power factor correction circuit includes a false trigger module for determining whether the surge protection mode is the false trigger condition, and generating a false trigger signal when the surge protection mode is the false trigger condition.

10. The multi-level power factor correction circuit as described in claim 9, wherein the false trigger module determines whether the current surge protection mode is the false trigger situation according to whether an input voltage sampling signal and / or the surge current sampling signal of the multi-level power factor correction circuit are between a preset threshold range.

11. The multi-level power factor correction circuit as described in claim 10, wherein the false trigger module determines that the current surge protection mode is the false trigger situation when the input voltage sampling signal or the surge current sampling signal received M times in succession is within the preset threshold range, and when the input voltage sampling signal or the surge current sampling signal received M times in succession is not all within the preset threshold range, it determines that the current surge protection mode is not the false trigger situation, wherein M≥2.

12. A multi-level power factor correction circuit as described in claim 7, wherein the multi-level power factor correction circuit includes a shielding module, which is arranged between the surge current sampling module and the surge judgment module to shield the surge current sampling signal when receiving the false trigger situation of the surge protection mode to exit the surge protection mode.

13. A multi-level power factor correction circuit as described in claim 7, wherein the multi-level power factor correction circuit includes a shielding module, which is arranged at the output end of the surge judgment module to shield the surge current sampling signal when receiving the false trigger situation of the surge protection mode to exit the surge protection mode.

14. A multi-level power factor correction circuit as described in claim 12 or 13, wherein the shielding module includes a driving circuit and a shielding switch element, the shielding switch element receives a false trigger signal via the driving circuit, and when the false trigger signal is valid, the shielding switch element is controlled to be turned on, thereby pulling down the surge current sampling signal, so that the surge current sampling signal is less than the surge protection threshold to shield the trigger signal, thereby causing the multi-level power factor correction circuit to exit the surge protection mode.

15. The multi-level power factor correction circuit as claimed in claim 3, wherein the surge current sampling module comprises a sampling circuit and a voltage shaping circuit, the sampling circuit samples the surge current and outputs a current information obtained by sampling to the voltage shaping circuit, and the voltage shaping circuit outputs the surge current sampling signal according to the current information, wherein the sampling circuit comprises a current transformer or a sampling resistor.

16. A multi-level power factor correction circuit as described in claim 15, wherein the current transformer comprises a primary winding and a secondary winding, wherein the primary winding is connected in series between the bypass unit and the first input terminal, or between the bypass unit and the second input terminal, and the electrical signal induced on the secondary winding is processed by the rectifying unit and the filtering unit included in the voltage shaping circuit to obtain the surge current sampling signal.

17. A surge protection control method for a multi-level power factor correction circuit, wherein the number of levels of the multi-level power factor correction circuit is N, N is an integer greater than or equal to 3, and the multi-level power factor correction circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, an inductor, (N-1) first switches, (N-1) second switches, (N-2) flying capacitors, a first polarity switch and a second polarity switch, wherein the first input terminal and the second input terminal are configured to receive an input voltage, the first output terminal and the second output terminal are configured to provide an output voltage, and the first end of the inductor is connected to the second input terminal. The (N-1) first switches are sequentially connected in series between the second end of the inductor and the second output end, the (N-1) second switches are sequentially connected in series between the second end of the inductor and the first output end, the kth flying capacitor is connected across a common connection point between the kth first switch and the k+1th first switch and a common connection point between the kth second switch and the k+1th second switch, wherein k is a positive integer less than or equal to (N-2), the first polarity switch is connected between the first input end and the first output end, and the second polarity switch is connected between the first input end and the second output end, wherein the surge protection control method comprises: The working state of the multi-level power factor correction circuit is controlled according to the state of the input voltage, and when a surge occurs in the input voltage, the multi-level power factor correction circuit is triggered to enter a surge protection mode, and the first polarity switch, the second polarity switch, the (N-1) first switches and the (N-1) second switches are controlled to be turned off.

18. The surge protection control method as claimed in claim 17, wherein the surge protection control method further comprises, when the surge condition occurs, sampling a surge current to generate a surge current sampling signal, and when it is determined that the surge condition is that the surge current sampling signal is greater than a surge protection threshold, generating a trigger signal to trigger the surge protection mode.

19. The surge protection control method as claimed in claim 18, wherein the surge protection control method further comprises generating a false trigger signal when determining that the surge protection mode is a false trigger situation, and controlling the multi-level power factor correction circuit to exit the surge protection mode.

20. The surge protection control method as described in claim 19, wherein the surge protection control method further comprises determining whether the current surge protection mode is the false triggering condition according to whether an input voltage sampling signal and / or the surge current sampling signal of the multi-level power factor correction circuit are within a preset threshold range.

21. The surge protection control method as described in claim 20, wherein the surge protection control method further comprises: when the input voltage sampling signal or the surge current sampling signal received M times in succession are both within the preset threshold range, then judging that the current surge protection mode is the false triggering situation; when the input voltage sampling signal or the surge current sampling signal received M times in succession are not all within the preset threshold range, then judging that the current surge protection mode is not the false triggering situation, wherein M≥2.

22. The surge protection control method as claimed in claim 19, wherein the surge protection control method further comprises adjusting the surge protection threshold to be greater than a false trigger threshold, wherein the false trigger threshold is set according to an output current peak value when the multi-level power factor correction circuit works normally.

23. The surge protection control method as claimed in claim 19, wherein the surge protection control method further comprises providing a shielding module to shield the surge current sampling signal when receiving the false trigger signal indicating that the surge protection mode is the false trigger signal, so as to exit the surge protection mode.

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