Low-noise amplifier structure adopting multi-inductor coupling and current multiplexing

Abstract

The invention discloses a low-noise amplifier structure adopting multi-inductor coupling and current multiplexing, which comprises a multi-inductor coupling network and a full-nmos current multiplexing technology network, the multi-inductor coupling network is connected with the full-nmos current multiplexing technology network, the full-nmos current multiplexing technology network is used for enabling the same current to flow through a multi-stage amplifier, and the multi-stage amplifier is connected with the full-nmos current multiplexing technology network. The multi-stage amplifiers share the same power supply voltage; and the multi-inductance coupling network is used for realizing broadband maximum power transmission matching and noise coefficient matching at an input node so as to realize high power transmission and low noise coefficient. According to the invention, broadband input matching and noise matching can be realized at the same time. The invention can be widely applied to the field of radio frequency receiver front ends.

Description

Technical Field

[0001] The invention relates to the field of radio frequency receiver front ends, and in particular to a low noise amplifier structure using multi-inductor coupling and current multiplexing. Background Art

[0002] The rapid progress of wireless communication technology has put forward higher requirements for receiver performance, especially in terms of signal amplification and sensitivity. In the receiver architecture, the low noise amplifier (LNA) is a key module after the antenna, responsible for effectively amplifying weak RF signals. The noise factor of LNA has become an important indicator to measure its performance. A high noise factor will significantly reduce the receiver's ability to capture weak signals. In addition, traditional LNA designs often focus on the optimal performance of a specific frequency band, which makes the bandwidth a major bottleneck when facing ultra-wideband signals, limiting its wide application in wide-band application scenarios. In advanced processes, LNA is also limited by power supply voltage. In advanced processes such as 65nm CMOS, the operating voltage of transistors is generally reduced to 1.2V or lower in order to pursue higher energy efficiency. However, higher voltage power supplies are widely used in current commercial systems, which poses a challenge to the widespread application of LNA. Therefore, how to overcome bandwidth limitations and adapt to different power supply voltage environments while maintaining a low noise factor has become a key issue that needs to be solved in the field of LNA design. Summary of the invention

[0003] In view of this, in order to solve the technical problem that the existing low noise amplifier cannot meet the bandwidth requirements of the scene while maintaining a low noise figure, the present invention proposes a low noise amplifier structure using multi-inductor coupling and current multiplexing, including a multi-inductor coupling network and a full NMOS current multiplexing technology network, wherein the multi-inductor coupling network and the full NMOS current multiplexing technology network are connected, wherein:

[0004] A multi-inductor coupling network, used to achieve broadband maximum power transmission matching and noise figure matching at the input node to achieve high power transmission and low noise figure, including an input transistor gate terminal series inductor, an input transistor gate terminal shunt inductor, an input transistor source terminal series inductor, and an input transistor gate-source capacitor, wherein the input transistor gate terminal series inductor, the input transistor gate terminal shunt inductor, and the input transistor source terminal series inductor are coupled in pairs;

[0005] A full-NMOS current multiplexing technology network, used to make the same current flow through multi-stage amplifiers, so that the multi-stage amplifiers share the same power supply voltage, including a full-NMOS cascode amplifier stage module, a full-NMOS stack structure amplifier stage module, an inter-stage matching network, an output matching network and a voltage bias module, wherein the full-NMOS cascode amplifier stage module, the full-NMOS stack structure amplifier stage module, the inter-stage matching network and the output matching network are connected in sequence, and the voltage bias module is used to control the transistor gate terminal DC voltage and drain-source DC voltage of the full-NMOS cascode amplifier stage module and the full-NMOS stack structure amplifier stage module;

[0006] In some embodiments, the substrate and source of the nmos transistor in the cascode amplifier module are also connected to an anti-breakdown resistor; the substrate and source of the nmos transistor in the stack structure amplifier module are also connected to an anti-breakdown resistor. This can make the DC potential of the substrate and the source as close as possible to prevent the nmos transistor from breaking down due to a large voltage difference between the substrate and the source.

[0007] Based on the above scheme, the present invention provides a low noise amplifier structure using multi-inductor coupling and current multiplexing: the present invention supports the simultaneous realization of broadband input matching and noise matching, supports the use of an LNA composed of all-NMOS to adapt to the power supply voltage of a commercial system, and through multiple inductor couplings, improves the equivalent Q value of some inductors of the input matching network, improves the design freedom of the input matching network, changes the impedance required to achieve noise figure matching within the target broadband frequency, and can simultaneously achieve broadband input matching and noise matching. The power supply voltage of the commercial system is adapted through the full-NMOS current multiplexing technology, reducing the sensitivity requirements of high-performance receivers and the limitations of the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a framework of a low noise amplifier structure using multi-inductor coupling and current multiplexing of the present invention;

[0009] Figure 2 is a schematic diagram of a cascode amplifier stage module and a multi-inductor coupling network according to a specific embodiment of the present invention;

[0010] Figure 3 It is a schematic diagram of a stack structure amplifier stage module and an inter-stage matching network in a specific embodiment of the present invention;

[0011] Figure 4 is a S11 parameter simulation curve diagram of a low noise amplifier structure according to a specific embodiment of the present invention;

[0012] Figure 5is a S22 parameter simulation curve diagram of a low noise amplifier structure according to a specific embodiment of the present invention;

[0013] Figure 6 is a simulation curve diagram of the S21 parameter of the low noise amplifier structure of a specific embodiment of the present invention;

[0014] Figure 7 is a noise coefficient simulation curve diagram of a low noise amplifier structure according to a specific embodiment of the present invention;

[0015] Figure 8 It is a simulation curve diagram of the K parameter stability factor of the low noise amplifier structure of a specific embodiment of the present invention.

[0016] Figure symbols: M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; L1, first inductor; L2, second inductor; L3, third inductor; L4, fourth inductor; L5, fifth inductor; L6, sixth inductor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; C6, sixth capacitor; C7, seventh capacitor; C8, eighth capacitor. DETAILED DESCRIPTION

[0017] In order to increase the bandwidth of LNA, predecessors have introduced a variety of topologies in LNA. Including dual-resonant cavity transformers, high-order matching networks, and some pole tuning techniques. However, most reported LNAs prefer to use multi-cascade resonant cavities with different resonant frequencies to expand the bandwidth, which may reduce the NF. In order to make the LNA made with advanced technology adapt to higher voltage power supplies, it is generally necessary to use LDO or dc-dc circuits to reduce the voltage. Among them, the efficiency of dc-dc can reach 95%, but the residual ripple in dc-dc will affect the RF signal-to-noise ratio through its harmonic terms and reduce performance. LDO can suppress ripple, but the efficiency is low, which will lead to energy waste. In summary, the existing LNA still cannot meet actual needs.

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] It should be noted that, for the convenience of description, only the parts related to the relevant invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other.

[0020] It should be understood that the "system", "device", "unit" and / or "module" used in this application is a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.

[0021] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not refer to the singular, but also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements. The elements defined by the sentence "includes a..." do not exclude the existence of other identical elements in the process, method, commodity or device that includes the elements.

[0022] In the description of the embodiments of the present application, "plurality" means two or more than two. The following terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0023] In addition, flow charts are used in the present application to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed accurately in order. On the contrary, the various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes, or a certain step or several steps of operations may be removed from these processes.

[0024] Reference Figure 1 and Figure 2 , is a schematic diagram of an optional example of a low noise amplifier structure using multi-inductor coupling and current multiplexing proposed by the present invention. The LNA proposed in this embodiment may include but is not limited to the following structure:

[0025] A multi-inductor coupling network, comprising a first inductor, a second inductor, a third inductor and a first capacitor, wherein a first end of the first inductor is connected to a second end of the second inductor; a first end of the second inductor is connected to a first end of the first capacitor; a second end of the first inductor and a first end of the third inductor are respectively connected to the full NMOS current multiplexing technology network;

[0026] The first end of the first inductor is also connected to the cascode amplifier module; the second end of the first capacitor is grounded; the second end of the third inductor is grounded;

[0027] A full NMOS current multiplexing technology network, comprising a cascode amplifier stage module, a stack structure amplifier stage module, an interstage matching network, an output matching network and a voltage bias module, wherein the cascode amplifier stage module, the stack structure amplifier stage module, the interstage matching network and the output matching network are connected in sequence, and the voltage bias module is used to control the transistor gate terminal DC voltage and drain-source DC voltage of the cascode amplifier stage module and the stack structure amplifier stage module, and the cascode amplifier stage module is also connected to a multi-inductor coupling network;

[0028] Wherein, the transistors used in the cascode amplifier stage module and the stack structure amplifier stage module are both noms transistors.

[0029] The above-mentioned full-nmos cascode amplifier stage module, full-nmos stack structure amplifier stage module, interstage matching network, output matching network and voltage bias module jointly realize the full-nmos current reuse technology network. The full-nmos cascode amplifier stage module, interstage matching network, full-nmos stack structure amplifier stage module and output matching network are connected in sequence to provide a DC path from power supply to ground for LNA. The size of the transistors of the full-nmos cascode amplifier stage module and the full-nmos stack structure amplifier stage module and the voltage control module realize the reasonable distribution of DC voltage for the transistors of LNA, so that the transistors of LNA using full-nmos current reuse technology reduce the risk of breakdown. The full-nmos stack structure amplifier stage module can also control the gate-source voltage of the transistors at this stage, further reducing the risk of breakdown of the transistors. The inter-stage matching network provides a suitable AC ground for the full-NMOS stack structure amplifier stage module and the full-NMOS cascode amplifier stage module without affecting the transmission of DC signals, so that the DC current provided by the same power supply voltage can flow through the full-NMOS cascode amplifier stage module and the full-NMOS stack structure amplifier stage module at the same time, realizing current multiplexing.

[0030] In some embodiments, the cascode amplifier stage module includes a first nmos transistor, a second nmos transistor, a second capacitor, a first resistor and a second resistor, wherein:

[0031] The gate of the first nmos transistor is connected to the second end of the first inductor, the source of the first nmos transistor is connected to the first end of the third inductor, the drain of the first nmos transistor is connected to the source of the second nmos transistor, the gate of the second nmos transistor, the first end of the second resistor and the first end of the second capacitor are connected, and the first end of the first resistor is connected to the first end of the first inductor.

[0032] The second end of the first resistor is connected to the VG1 signal end, the second end of the second resistor is connected to the VG2 signal end, and the first end of the first resistor serves as the input end of the overall LNA.

[0033] The active NMOS transistor connected in the form of cascode is used to amplify the input signal and output the amplified signal to the next stage, reuse the same current with the full NMOS stack structure amplifier stage, and achieve reasonable distribution of transistor drain-source voltage by using transistor sizes similar to the full NMOS stack structure amplifier stage, thereby reducing the risk of transistor breakdown;

[0034] The connection resistance between the substrate and the source end of the nmos transistor makes the DC potential of the substrate and the source end as close as possible, preventing the nmos transistor from breaking down due to a large voltage difference between the substrate and the source end.

[0035] In some embodiments, reference Figure 3 , the inter-stage matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, and the stack structure amplifier stage module includes a third transistor, a fourth transistor, a third resistor, a fourth resistor, a seventh capacitor and an eighth capacitor, wherein:

[0036] The first end of the fourth inductor, the first end of the third capacitor, the first end of the third resistor and the gate of the third transistor are connected, the second end of the third resistor is connected to the VG3 signal terminal, the second end of the fourth inductor, the second end of the third capacitor and the first end of the fourth capacitor are connected, the second end of the fifth inductor, the second end of the sixth inductor, the first end of the fifth capacitor and the first end of the sixth capacitor are connected, the first end of the sixth inductor and the second end of the fifth capacitor are connected and connected to the previous module, the second end of the sixth capacitor is grounded, the source of the third transistor is connected to the first end of the fifth inductor, the drain of the third transistor and the second end of the eighth capacitor are connected to the source of the fourth transistor, the gate of the fourth transistor, the first end of the eighth capacitor, the first end of the seventh capacitor and the first end of the fourth resistor are connected, the second end of the fourth resistor is connected to the VG4 signal terminal, the second end of the seventh capacitor is grounded, and the drain of the fourth transistor is connected to the next module.

[0037] Active NMOS transistors connected in stack form are used to amplify the input signal from the upper amplifier and output the amplified signal. They are used to control the gate-source voltage of the NMOS transistor to prevent the gate-source voltage difference from being too large and causing the transistor to break down. They reuse the same current with the full NMOS cascode structure amplifier stage. By using transistors of similar size to the full NMOS cascode structure amplifier stage, the transistor drain-source voltage is reasonably distributed, reducing the risk of transistor breakdown.

[0038] The connection resistance between the substrate and the source end of the nmos transistor makes the DC potential of the substrate and the source end as close as possible, preventing the nmos transistor from breaking down due to a large voltage difference between the substrate and the source end.

[0039] The drain-end series inductor of the output transistor of the full-NMOS cascode structure amplifier stage module and the source-end series inductor of the input transistor of the full-NMOS stack structure amplifier stage module are connected to the AC-to-ground capacitor at the node, which is used to provide an AC ground for the inter-stage matching network at the node without interfering with the DC current flowing from the rear stage to the front stage, thereby realizing DC current multiplexing.

[0040] The gate-end parallel inductance, gate-end parallel capacitance, source-end series inductance of the input transistor of the full-NMOS stack structure amplifier stage module, the drain-end series inductance and parallel capacitance of the output transistor of the full-NMOS cascode structure amplifier stage module, together with the above-mentioned AC-to-ground capacitance, realize inter-stage conjugate matching to avoid power reflection.

[0041] Similarly, the substrate and source end of the nmos transistor in this embodiment are connected with resistors to make the DC potentials of the substrate and the source end as close as possible to prevent the nmos transistor from breaking down due to a large voltage difference between the substrate and the source end.

[0042] In some embodiments, the voltage bias module specifically includes:

[0043] The drain power supply voltage of the output stage nmos transistor is used as the only power supply of the current multiplexing LNA. The DC current flowing out of this power supply passes through the cascode amplifier stage module and the stack structure amplifier stage module at the same time to realize current multiplexing.

[0044] The gate bias voltage of the nmos transistor sets a suitable DC voltage for the gate of each level of transistors, so that the drain-source voltage of each transistor is approximately equal, reducing the breakdown risk of transistors that reuse DC current.

[0045] Based on the above scheme, the coupling of the series inductor at the gate terminal of the input transistor and the series inductor at the source terminal improves the Q value of the series inductor at the gate terminal, the coupling of the parallel inductor at the gate terminal of the input transistor and the series inductor at the source terminal improves the Q value of the parallel inductor at the gate terminal, and the coupling of the parallel inductor at the gate terminal of the input transistor and the series inductor at the gate terminal improves the Q value of the parallel inductor at the gate terminal, reduces the signal leakage caused by the parasitic resistance of the parallel inductor at the gate terminal, and improves the noise coefficient; the coupling of the parallel inductor at the gate terminal of the input transistor and the series inductor at the gate terminal changes the real and imaginary impedances of the parallel inductor at the gate terminal, so that the impedance required to achieve noise coefficient matching and the impedance required to achieve conjugate matching within the target broadband frequency are close.

[0046] Figure 4 FIG. 1 is a simulation curve diagram of the S11 parameters of the low noise amplifier provided by the specific embodiment of the present invention, referring to FIG. Figure 4 It can be seen that the S11 input matching curve is below -10 dB in the frequency range of 9.4 GHz-15 GHz. The results show that the low noise amplifier provided by the specific embodiment of the present invention has good input matching in the frequency range of 9.4 GHz-15 GHz.

[0047] Figure 5 FIG. 1 is a simulation curve diagram of the S22 parameter of the low noise amplifier provided by the specific embodiment of the present invention, referring to FIG. Figure 5 It can be seen that the S22 input matching curve is below -10 dB in the frequency range of 11 GHz-13.5 GHz. The results show that the low noise amplifier provided by the specific embodiment of the present invention has good output matching in the frequency range of 11 GHz-13.5 GHz.

[0048] Figure 6 FIG. 1 is a simulation curve diagram of the S21 parameters of the low noise amplifier provided by the specific embodiment of the present invention, referring to FIG. Figure 6 It can be seen that the S21 gain curve has only 2 dB ripple in the frequency range of 10 GHz-14 GHz. The results show that the low noise amplifier provided by the specific embodiment of the present invention has a flat gain curve in the frequency range of 10 GHz-14 GHz.

[0049] Figure 7 FIG. 1 is a noise figure simulation curve diagram of a low noise amplifier provided by a specific embodiment of the present invention, referring to FIG. Figure 7 It can be seen that the noise figure simulation curve is below 2dB in the frequency range of 9.5GHz-15GHz. The results show that the low noise amplifier provided by the specific embodiment of the present invention has good noise figure matching and low noise figure in the frequency range of 9.5GHz-15GHz.

[0050] Figure 8 FIG. 1 is a simulation curve diagram of the K parameter stability factor of the low noise amplifier provided by the specific embodiment of the present invention, referring to FIG. Figure 8 It can be seen that the K parameter stability factor simulation curve is basically above 10 in the frequency range of 9 GHz-15 GHz, which is much greater than 1. The results show that the low noise amplifier provided by the specific embodiment of the present invention has good stability in the frequency range of 9 GHz-15 GHz.

[0051] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A low noise amplifier structure using multi-inductor coupling and current multiplexing, characterized in that: It includes a multi-inductor coupling network and a full-NMOS current multiplexing technology network, wherein the multi-inductor coupling network and the full-NMOS current multiplexing technology network are connected, wherein: A multi-inductor coupling network, comprising a first inductor, a second inductor, a third inductor and a first capacitor, wherein a first end of the first inductor is connected to a second end of the second inductor; a first end of the second inductor is connected to a first end of the first capacitor; a second end of the first inductor and a first end of the third inductor are respectively connected to the full NMOS current multiplexing technology network; A full NMOS current multiplexing technology network, comprising a cascode amplifier stage module, a stack structure amplifier stage module, an interstage matching network, an output matching network and a voltage bias module, wherein the cascode amplifier stage module, the stack structure amplifier stage module, the interstage matching network and the output matching network are connected in sequence, and the voltage bias module is used to control the transistor gate terminal DC voltage and drain-source DC voltage of the cascode amplifier stage module and the stack structure amplifier stage module; The transistors used in the cascode amplifier stage module and the stack structure amplifier stage module are both noms transistors.

2. A low noise amplifier structure using multi-inductor coupling and current multiplexing according to claim 1, characterized in that: The cascode amplifier stage module includes a first nmos transistor, a second nmos transistor, a second capacitor, a first resistor and a second resistor, wherein: The gate of the first nmos transistor is connected to the second end of the first inductor, the source of the first nmos transistor is connected to the first end of the third inductor, the drain of the first nmos transistor is connected to the source of the second nmos transistor, the gate of the second nmos transistor, the first end of the second resistor and the first end of the second capacitor are connected, and the first end of the first resistor is connected to the first end of the first inductor.

3. A low noise amplifier structure using multi-inductor coupling and current multiplexing according to claim 2, characterized in that: The inter-stage matching network includes a fourth inductor, a fifth inductor, a sixth inductor, a third capacitor, a fourth capacitor, a fifth capacitor and a sixth capacitor, wherein: The first end of the fourth inductor is connected to the first end of the third capacitor, the second end of the fourth inductor, the second end of the third capacitor and the first end of the fourth capacitor are connected, the second end of the fifth inductor, the second end of the sixth inductor, the first end of the fifth capacitor and the first end of the sixth capacitor are connected, and the first end of the sixth inductor is connected to the second end of the fifth capacitor.

4. A low noise amplifier structure using multi-inductor coupling and current multiplexing according to claim 3, characterized in that: The stack structure amplifier stage module includes a third transistor, a fourth transistor, a third resistor, a fourth resistor, a seventh capacitor and an eighth capacitor, wherein: The gate of the third transistor, the first end of the fourth inductor and the first end of the third resistor are connected, the source of the third transistor is connected to the first end of the fifth inductor, the drain of the third transistor, the second end of the eighth capacitor and the source of the fourth transistor are connected, and the gate of the fourth transistor, the first end of the eighth capacitor, the first end of the seventh capacitor and the first end of the fourth resistor are connected.

5. The low noise amplifier structure using multi-inductor coupling and current multiplexing according to claim 1, characterized in that: The NMOS transistor substrate and source end in the cascode amplifier module are also connected to an anti-breakdown resistor.

6. A low noise amplifier structure using multi-inductor coupling and current multiplexing according to claim 1, characterized in that: The NMOS transistor substrate and source end in the stack structure amplifier module are also connected to an anti-breakdown resistor.

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