A device and method for detecting a loran c key signal

Abstract

The application discloses a device for detecting a Loran C key signal, which comprises an input circuit, a counter, a state flag register and an abnormality detecting circuit, and provides a method for detecting the Loran C key signal. The rising edge of a serial data signal SERDA is detected by the input circuit to control the counter and the abnormality detecting circuit. The abnormality detecting circuit detects the count value output by the counter to detect whether the serial data signal SERDA comprises four single pulses, i.e. a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig and a magnetic pulse reference pulse MEG_REF in sequence, and the count values of the four single pulses correspond to the time intervals in the count value threshold interval of each single pulse, so that the integrity of the serial data signal SERDA is judged. The application effectively solves the monitoring problem of the SERDA signal in a Loran wave emission control system, and guarantees the normal operation of the emission control system.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, in particular to a device for detecting a Loran C key signal, and also to a method for detecting a Loran C key signal. Background Art

[0002] The Loran-C navigation system is a large-scale, long-range, high-precision radio navigation system with a range of up to 2,000 kilometers and an operating frequency of 100 kHz. The system's basic components include ground infrastructure, user equipment, and transmission media. The ground infrastructure consists of a transmitter station, a work area monitoring station, and a station chain control center. The transmitter station transmits the radio navigation signal, while the work area monitoring station and the station chain control center ensure that the signal meets system requirements. Although satellite navigation systems are widely used, their low interference resistance makes sole reliance on satellite navigation systems unreliable. In contrast, the Loran-C system, with its high signal power and interference resistance, has become a familiar and reliable navigation method. Many countries use the Loran-C system as a backup system for their satellite navigation systems to ensure continuous navigation services for transportation. The Loran-C system is also widely used in national timing systems, and through continuous technical improvements, its timing functions and performance have been further improved.

[0003] The serial data signal (SERDA) is generated by the timing pulse control unit in the Roland C control cabinet. It contains all the timing and amplitude control information required by the half-cycle power generation unit (HCG) of the Roland C transmitter. In the entire broadcast control system, there are four serial data signals SERDA with exactly the same signal format. Figure 1 Shown is a waveform of a serial data signal SERDA.

[0004] All pulses and data bits in the serial data signal SERDA are 5μs long. The start pulse (STP) is the first single pulse of the serial data signal SERDA. The charge trigger pulse (CHARGE) is the second single pulse of the serial data signal SERDA, which occurs after the start pulse STP and initiates charging of the HCG half-cycle power generation unit. The eight-bit digital amplitude reference (DAR) is 8 bits of data delayed 60μs relative to the start pulse STP. The eight-bit digital amplitude reference DAR controls the charging time of the HCG half-cycle power generation unit capacitors, thereby controlling the voltage of the HCG half-cycle power generation unit storage capacitors and, in turn, the amplitude of the half-cycle pulses generated by each HCG half-cycle power generation unit. The seven-bit amplitude compensation delay (ACD) is delayed 160μs relative to the start pulse STP. It is a signal in the timing control loop of the HCG half-cycle power generation unit and is used to adjust the timing of the half-cycle pulses. The single-bit A-rate phase code (φA) following the seven-bit amplitude compensation delay (ACD) is controlled by the phase-encoding square wave of the timing logic. This bit is positive when the signal is a positive A-rate phase-encoding square wave; otherwise, it is negative. The discharge trigger pulse (DC_Trig) and the magnetic pulser reference pulse (MEG_REF) are delayed by 375μs and 405μs, respectively, relative to the start pulse STP. The magnetic pulser reference pulse (MEG_REF) corrects the timing of the discharge trigger pulse in the serial data signal SERDA, ensuring that the same serial data signal SERDA triggers the same half-cycle pulses generated by the HCG half-cycle power generation unit.

[0005] The serial data signal SERDA is a key signal that controls the subsequent transmitter to generate and transmit the Loran waveform, playing a crucial role in the entire Loran-C system. Errors in the SERDA signal can damage the subsequent transmitter and even affect Loran-C users. Therefore, monitoring the SERDA signal is essential. However, currently, there are no methods or devices for monitoring the SERDA signal. Summary of the Invention

[0006] The purpose of the present invention is to address the deficiencies of existing key signal detection technology and provide a device for detecting Loran C key signals. It also provides a method for detecting Loran C key signals. The method can measure the relative phase of four single pulses in the serial data signal SERDA and can sample two eight-bit data values ​​at the same time to monitor the serial data signal SERDA.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A device for detecting a Roland C key signal includes an input circuit, wherein the input circuit captures a serial data signal SERDA, and when the input circuit detects the first rising edge of the serial data signal SERDA, the input circuit sends a count enable signal to a counter; and each time the input circuit detects a rising edge of the serial data signal SERDA, the input circuit sends a detection enable signal to an abnormality detection circuit.

[0009] The counter receives a clock signal and a count enable signal from a clock source. When the counter receives the count enable signal, it starts counting continuously and sends the count value count1 to the abnormality detection circuit in sequence.

[0010] The abnormality detection circuit determines, based on the received detection enable signal and the count value count1, whether the serial data signal SERDA includes four single pulses, namely, a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig, and a magnetic pulser reference pulse MEG_REF, in sequence, and whether the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse. Based on the judgment result, the abnormality detection circuit outputs a flag bit setting signal corresponding to each single pulse and a flag bit setting signal corresponding to the integrity error flag SERDA_Integrity_Error to the status flag register, thereby setting the flag bit corresponding to the single pulse and the integrity error flag SERDA_Integrity_Error.

[0011] The reset control circuit selects whether to send a reset execution signal to the counter and the status flag register according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register;

[0012] The external monitoring control unit controls the link switch between the input circuit and the HCG half-cycle power generation unit according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register.

[0013] As mentioned above, the counting value threshold intervals corresponding to each single pulse include:

[0014] The charge trigger pulse counting threshold interval Charge_thr represents the time limit of the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge;

[0015] The discharge trigger pulse counting threshold interval DC_Trig_thr represents the time limit of the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig;

[0016] The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF;

[0017] The flag bits corresponding to each single pulse in the serial data signal SERDA include:

[0018] The start pulse flag Find_STP_Flag corresponds to the start pulse STP;

[0019] The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge;

[0020] The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig;

[0021] The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF.

[0022] As mentioned above, the input circuit adopts a three-stage shift register structure.

[0023] The device for detecting a Loran C key signal as described above further includes a sampling circuit and an output circuit.

[0024] The sampling circuit receives the clock signal from the clock source and, based on the flag bits corresponding to the start pulse STP and the charge trigger pulse Charge, selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase code φA.

[0025] The output circuit reads the flag bits corresponding to each single pulse in the status flag register and the value of the integrity error flag bit SERDA_Integrity_Error, and selects whether to transmit the data temporarily stored in the counter, sampling circuit and status flag register to the external monitoring control unit;

[0026] The data temporarily stored in the counter are: the count value count1 corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF;

[0027] The data temporarily stored in the sampling circuit are: eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD and one-bit A-rate phase code φA;

[0028] The data temporarily stored in the status flag register are: the flag bits corresponding to each single pulse and the value of the integrity error flag bit SERDA_Integrity_Error;

[0029] The reset control circuit selects whether to send a reset execution signal to the sampling circuit according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register.

[0030] A method for detecting a Loran-C key signal, using the device for detecting a Loran-C key signal as described above, is characterized by comprising the following steps:

[0031] Step 1: Set the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit, and set the preset sampling time point in the sampling circuit;

[0032] Step 2: Set the link switch to off;

[0033] Step 3: Reset and initialize the count value count1 in the counter, the register of the sampling circuit, and all the flag bits in the status flag register through the reset control circuit;

[0034] Step 4: The input circuit captures the serial data signal SERDA and detects the rising edge in the serial data signal SERDA. The counter starts counting. The abnormality detection circuit detects the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig, and the magnetic pulser reference pulse MEG_REF in the serial data signal SERDA through the count value count1 output by the counter, and determines whether the serial data signal SERDA is complete. If the serial data signal SERDA is complete, that is, the serial data signal SERDA includes four single pulses, namely the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig, and the magnetic pulser reference pulse MEG_REF, in sequence, and the time corresponding to the count value count1 of the four single pulses is within the count value threshold interval corresponding to each single pulse, then step 5 is executed. If any of the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig, and the magnetic pulser reference pulse MEG_REF is not detected, then the circuit returns to step 3.

[0035] Step 5: The external monitoring control unit turns on the link switch so that the complete and normal serial data signal SERDA in the input circuit is input into the HCG half-cycle power generation unit of the corresponding Loran C transmitter, and then returns to step 2.

[0036] As described above in step 1, the maximum count value threshold value count_max is set to the maximum interval time between the two preceding and following serial data signals SERDA of the same channel.

[0037] As mentioned above in step 1,

[0038] Set the lower limit of the charge trigger pulse count threshold interval Charge_thr_l in the charge trigger pulse count threshold interval Charge_thr to be greater than 5μs, and the upper limit of the charge trigger pulse count threshold interval Charge_thr_h to be less than 60μs;

[0039] The discharge trigger pulse count threshold interval lower limit DC_Trig_thr_l in the discharge trigger pulse count threshold interval DC_Trig_thr is greater than 200 μs, and the discharge trigger pulse count threshold interval upper limit DC_Trig_thr_h is less than 405 μs;

[0040] The magnetic pulser reference pulse count threshold interval lower limit MEG_REF_thr_l in the magnetic pulser reference pulse count threshold interval MEG_REF_thr is greater than or equal to 405 μs, and the magnetic pulser reference pulse count threshold interval upper limit MEG_REF_thr_h is less than 425 μs.

[0041] The above-mentioned step 4 specifically includes the following steps:

[0042] Step 4.1, the serial data signal SERDA is captured by the input circuit;

[0043] Step 4.2: When the input circuit detects the first rising edge, the count value count1 output by the counter starts counting from 0. The abnormality detection circuit receives the first detection enable signal sent by the input circuit. The abnormality detection circuit outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register, setting the start pulse flag Find_STP_Flag in the status flag register. After the counter starts counting, it continuously sends the count value count1 corresponding to each moment to the abnormality detection circuit.

[0044] Step 4.3: The input circuit continues to detect the rising edge of the serial data signal SERDA, and the counter continues to count;

[0045] At the same time, the abnormality detection circuit judges the count value count1:

[0046] If the input circuit still does not detect the second rising edge when the count value count1 output by the counter reaches the maximum count value threshold value count_max, return to step 3;

[0047] If the count value countl outputted by the counter does not reach the maximum count value threshold count_max, the input circuit monitors the second rising edge, the anomaly detection circuit receives the second detection enable signal sent by the input circuit, and the register of the counter temporarily stores the count value countl corresponding to the second rising edge; the anomaly detection circuit takes the time corresponding to the count value countl corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase and judges whether the charge trigger pulse phase difference delta_Charge_phase is within the set charge trigger pulse count threshold interval Charge_thr, if the charge trigger pulse phase difference delta_Charge_phase is within the charge trigger pulse count threshold interval Charge_thr, the anomaly detection circuit sets the charge trigger pulse flag bit Find_Charge_Flag in the state flag register, and then executes step 4.4; otherwise, returns to step 3.

[0048] Step 4.4, the counter continues to count, after the sampling circuit identifies that the charge trigger pulse flag bit Find_Charge_Flag is 1, the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A rate phase encoding φA are sequentially sampled according to the preset sampling time point, and the sampling results are temporarily stored in the register of the sampling circuit;

[0049] During the sampling process, the anomaly detection circuit does not judge the count value countl;

[0050] Step 4.5, the input circuit continues to detect the rising edge in the serial data signal SERDA, and the counter continues to count;

[0051] At the same time, the anomaly detection circuit judges the count value countl:

[0052] If the count value countl outputted by the counter reaches the maximum count value threshold count_max, the input circuit still does not detect the third rising edge, and returns to step 3;

[0053] If the count value count1 output by the counter does not reach the maximum count value threshold value count_max, the input circuit detects the third rising edge, the abnormality detection circuit receives the third detection enable signal sent by the input circuit, and the counter register temporarily stores the count value count1 corresponding to the third rising edge. The abnormality detection circuit uses the time corresponding to the count value count1 corresponding to the third rising edge as the discharge trigger pulse phase difference delta_DC_Trig_phase, and compares it with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the discharge trigger pulse flag Find_DC_Trig_Flag is set, and then step 4.6 is executed; otherwise, the process returns to step 3.

[0054] Step 4.6: The input circuit continues to detect the rising edge of the serial data signal SERDA, and the counter continues to count;

[0055] At the same time, the abnormality detection circuit judges the count value count1:

[0056] If the input circuit still does not detect the fourth rising edge when the count value count1 output by the counter reaches the maximum count value threshold value count_max, return to step 3;

[0057] If the count value countl output by the counter does not reach the maximum count value threshold value count_max, the input circuit detects the fourth rising edge, and the abnormality detection circuit receives the fourth detection enable signal sent by the input circuit, then the register of the counter temporarily stores the count value countl corresponding to the fourth rising edge, and the abnormality detection circuit uses the time corresponding to the count value countl corresponding to the fourth rising edge as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase and compares it with the magnetic pulser reference pulse count threshold interval MEG_REF_thr. If the magnetic pulser reference pulse phase difference delta_MEG_REF_phase is within the range of the magnetic pulser reference pulse count threshold interval MEG_REF_thr, the abnormality detection circuit sets the magnetic pulser reference pulse flag Find_MEG_REF_Flag and the integrity error flag SERDA_Integrity_Error in the status flag register and executes step 5; otherwise, returns to step 3.

[0058] The above step 5 specifically includes the following steps:

[0059] The output circuit outputs the data temporarily stored in the counter, sampling circuit and status flag register to the external monitoring control unit. The external monitoring control unit turns on the link switch so that the complete and abnormal serial data signal SERDA in the current input circuit detected by step 4 is input into the HCG half-cycle power generation unit of the corresponding Loran C transmitter, and then returns to step 2.

[0060] A set of the above-mentioned Loran C key signal detection device processes one serial data signal SERDA, and four serial data signals SERDA are input in parallel to the corresponding set of the above-mentioned Loran C key signal detection device.

[0061] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0062] The present invention effectively solves the problem of monitoring the SERDA signal in the Roland wave control system, and ensures the normal operation of the broadcast control system by detecting the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 Schematic diagram of a single serial data signal (SERDA signal) in the Roland broadcast control system.

[0064] Figure 2 This diagram shows the relative timing relationship of the four serial data signals (SERDA signals) in the Roland broadcast control system. ① represents the first SERDA signal, ② represents the second SERDA signal, ③ represents the third SERDA signal, and ④ represents the fourth SERDA signal.

[0065] Figure 3 The figure is a schematic diagram of the structure of a device for detecting Loran C key signals.

[0066] Among them, 1-input circuit; 2-counter; 3-clock source; 4-abnormal detection circuit; 5-status flag register; 6-sampling circuit; 7-reset control circuit; 8-output circuit; 9-external monitoring control unit; 10-link switch; 11-HCG half-cycle power generation unit. DETAILED DESCRIPTION

[0067] In order to facilitate those skilled in the art to understand and implement the present invention, the present invention is further described in detail below in conjunction with embodiments. It should be understood that the embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0068] Example 1

[0069] A device for detecting a Loran-C key signal, comprising an input circuit 1, a counter 2, a sampling circuit 6, a state flag register 5, an anomaly detection circuit 4 and an output circuit 8, wherein:

[0070] The input circuit 1 is used for capturing a serial data signal SERDA and detecting a rising edge in the serial data signal SERDA, and when the input circuit 1 detects a rising edge in the serial data signal SERDA, the input circuit 1 sends a counting enable signal to the counter 2 (in this embodiment, the input circuit 1 sends a counting enable signal to the counter 2 when the input circuit 1 detects the first rising edge in the serial data signal SERDA), and at the same time, the input circuit 1 sends a detection enable signal to the anomaly detection circuit 4 (in this embodiment, the input circuit 1 sends a detection enable signal to the anomaly detection circuit 4 every time the input circuit 1 detects a rising edge in the serial data signal SERDA); in this embodiment, the input circuit 1 adopts a three-stage shift register structure, and determines whether a rising edge occurs according to the state change of the serial data signal SERDA;

[0071] The counter 2 receives a clock signal of a clock source 3 and the counting enable signal output by the input circuit 1, and starts counting from an initial state when the counter 2 receives the counting enable signal, and sends the count value countl corresponding to each time point to the anomaly detection circuit 4 in sequence; since the counter 2 starts counting only after the input circuit 1 detects the first rising edge, the count value countl corresponding to the next rising edge as the current rising edge can represent the phase difference between the current rising edge and the first rising edge; in this embodiment, the clock source 3 provides a clock with a frequency of 100 MHz, and each increase of 1 in the count value countl represents a time of 10 ns;

[0072] The anomaly detection circuit 4 determines whether the serial data signal SERDA is complete (i.e., determines whether the serial data signal SERDA sequentially includes four single pulses of a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig and a magnetic pulse reference pulse MEG_REF, and the count values countl corresponding to the four single pulses are within the count value threshold intervals corresponding to the four single pulses, respectively) according to the received detection enable signal, the count value countl and the preset count threshold, and outputs the flag setting signals corresponding to the single pulses in the serial data signal SERDA and the integrity error flag SERDA_Integrity_Error to the state flag register 5 according to the determination result; wherein the preset count threshold includes a maximum count value threshold count_max and the count value threshold intervals corresponding to the single pulses in the serial data signal SERDA; the threshold interval corresponding to each single pulse includes:

[0073] The charge trigger pulse counting threshold interval Charge_thr represents the time limit of the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge;

[0074] The discharge trigger pulse counting threshold interval DC_Trig_thr represents the time limit of the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig;

[0075] The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF;

[0076] The flag bits corresponding to the single pulse include:

[0077] The start pulse flag Find_STP_Flag corresponds to the start pulse STP;

[0078] The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge;

[0079] The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig;

[0080] The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF;

[0081] The status flag register 5 sets the flag corresponding to each single pulse in the serial data signal SERDA and the integrity error flag SERDA_Integrity_Error according to the flag setting signal output by the abnormality detection circuit 4; wherein, the start pulse flag Find_STP_Flag is used to identify whether the corresponding start pulse STP is correctly detected, the charge trigger pulse flag Find_Charge_Flag is used to identify whether the corresponding charge trigger pulse Charge is correctly detected, the discharge trigger pulse flag Find_DC_Trig_Flag is used to identify whether the corresponding discharge trigger pulse DC_Trig is correctly detected, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is used to identify whether the corresponding magnetic pulser reference pulse MEG_REF is correctly detected, and the integrity error flag SERDA_Integrity_Error is used to identify whether the entire serial data signal SERDA is received;

[0082] The sampling circuit 6 receives the clock signal of the clock source 3, reads the corresponding flag bits (i.e. the start pulse flag bit Find_STP_Flag and the charge trigger pulse flag bit Find_Charge_Flag) of the start pulse STP and the charge trigger pulse Charge of the serial data signal SERDA in the state flag register 5, and selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A rate phase encoding φA data according to the preset sampling time point after detecting the start pulse STP and the charge trigger pulse Charge.

[0083] The reset control circuit 7 reads the value of the integrity error flag bit SERDA_Integrity_Error in the state flag register 5, selects whether to send a reset execution signal to the counter 2, the sampling circuit 6 and the state flag register 5, and thus resets and initializes the counter 2, the sampling circuit 6 and the state flag register 5.

[0084] In order to facilitate monitoring and checking the data temporarily stored in the counter 2, the sampling circuit 6 and the state flag register 5, the application further comprises an output circuit 8. The output circuit 8 reads the value of each single pulse corresponding flag bit and the integrity error flag bit SERDA_Integrity_Error in the state flag register 5, and selects whether to output the data temporarily stored in the counter 2, the sampling circuit 6 and the state flag register 5 to the external monitoring control unit 9. The output circuit 8 is used to output the data temporarily stored in the counter 2, the sampling circuit 6 and the state flag register 5 to the external monitoring control unit 9 when all the four single pulses are correctly detected.

[0085] The count value countl corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnet pulser reference pulse MEG_REF temporarily stored in the counter 2 (the count value countl corresponding to the charge trigger pulse Charge corresponds to the phase difference between the charge trigger pulse Charge and the start pulse STP, the count value countl corresponding to the discharge trigger pulse DC_Trig corresponds to the phase difference between the discharge trigger pulse DC_Trig and the start pulse STP, and the count value countl corresponding to the magnet pulser reference pulse MEG_REF corresponds to the phase difference between the magnet pulser reference pulse MEG_REF and the start pulse STP);

[0086] The eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A rate phase encoding φA temporarily stored in the sampling circuit 6.

[0087] The value of each single pulse corresponding flag bit and the integrity error flag bit SERDA_Integrity_Error temporarily stored in the state flag register 5.

[0088] The external monitoring control unit 9 controls the link switch 10 between the input circuit 1 and the HCG half-cycle power generating unit 11 according to the value of the integrity error flag bit SERDA_Integrity_Error in the received status flag register 5; in this embodiment, when the value of the integrity error flag bit SERDA_Integrity_Error is 1, the link switch 10 is closed, and when the value of the integrity error flag bit SERDA_Integrity_Error is 0, the link switch 10 is opened.

[0089] Embodiment 2

[0090] A method for detecting a Loran C key signal, which utilizes the device for detecting a Loran C key signal as described in Embodiment 1.

[0091] The timing pulse control unit in the Loran C control cabinet generates four parallel serial data signals SERDA, each of which, as shown in Figure 1 includes four single pulses (start pulse STP, charge trigger pulse Charge, discharge trigger pulse DC_Trig, and magnet pulse reference pulse MEG_REF) and eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, and one-bit A rate phase encoding φA. The four parallel serial data signals SERDA are input into the input circuit 1 of the device for detecting a Loran C key signal of the present application, and the timing of each signal in each serial data signal SERDA is in turn: start pulse STP, charge trigger pulse Charge, eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, one-bit A rate phase encoding φA, discharge trigger pulse DC_Trig, and magnet pulse reference pulse MEG_REF;

[0092] Among them, the rising edge moments of the start pulse STP in the four-way serial data signals SERDA are the same, the rising edge moments of the eight-bit digital amplitude reference DAR in the four-way serial data signals SERDA are the same, the rising edge moments of the seven-bit amplitude compensation delay ACD in the four-way serial data signals SERDA are the same, and the rising edge moments of the one-bit A-rate phase code φA in the four-way serial data signals SERDA are the same; within a 200μs time interval from the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase code φA to the start pulse STP signal, the charge trigger pulse Charge in the second serial data signal SERDA, the charge trigger pulse Charge in the third serial data signal SERDA, and the charge trigger pulse Charge in the fourth serial data signal SERDA are respectively relative to the charge trigger pulse Charge in the first serial data signal SERDA. Charge is delayed by 5μs, 10μs and 15μs; the discharge trigger pulse DC_Trig in the second serial data signal SERDA, the discharge trigger pulse DC_Trig in the third serial data signal SERDA and the discharge trigger pulse DC_Trig in the fourth serial data signal SERDA are delayed by 5μs, 10μs and 15μs respectively relative to the discharge trigger pulse DC_Trig in the first serial data signal SERDA; the magnetic pulser reference pulse MEG_REF in the second serial data signal SERDA, the magnetic pulser reference pulse MEG_REF in the third serial data signal SERDA and the magnetic pulser reference pulse MEG_REF in the fourth serial data signal SERDA are delayed by 5μs, 10μs and 15μs respectively relative to the magnetic pulser reference pulse MEG_REF in the first serial data signal SERDA; Figure 2 shown.

[0093] One set of the Loran C key signal detection device processes one serial data signal SERDA. Four serial data signals SERDA are input in parallel into the corresponding set of the Loran C key signal detection device. The detection of each serial data signal SERDA does not affect each other. Each serial data signal SERDA is independently detected according to the following steps:

[0094] Step 1: Set the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit 4, and set the preset sampling time point in the sampling circuit 6;

[0095] Count thresholds include:

[0096] The maximum count value threshold, count_max, indicates the maximum value that count value count1 in counter 2 can reach. When count value count1 exceeds the maximum count value threshold, count_max, a fault is considered to have occurred. The maximum count value threshold, count_max, is set to the maximum interval between two consecutive serial data signals SERDA on the same path. In this embodiment, the maximum interval between two consecutive serial data signals SERDA on the same path is 99ms. As long as the time corresponding to count value count1 exceeds 99ms, the integrity error flag, SERDA_Integrity_Error, is set to 1. If there is no signal or no rising edge input and the count value count1 exceeds 99ms, count value count1 is cleared and count restarts. This process is repeated in a continuous loop. In this embodiment, the system uses a 100MHz clock frequency, and each increase in count value count1 represents the passage of 10ns.

[0097] The charge trigger pulse count threshold interval Charge_thr represents the limited range corresponding to the phase difference between the rising edge of the charge trigger pulse and the rising edge of the start pulse; the lower limit Charge_thr_l of the charge trigger pulse count threshold interval Charge_thr is greater than 5μs, and the upper limit Charge_thr_h of the charge trigger pulse count threshold interval Charge_thr is less than 60μs; in this embodiment, the rising edges of the charge trigger pulse Charge in the preset four serial data signals SERDA are respectively 15μs, 20μs, 25μs, and 30μs away from the rising edge of the start pulse STP, and the charge trigger pulse count threshold interval Charge_thr corresponding to the four serial data signals SERDA is [13μs, 32μs].

[0098] The discharge trigger pulse counting threshold interval DC_Trig_thr represents the limited range corresponding to the phase difference between the rising edge of the discharge trigger pulse and the rising edge of the start pulse. The lower limit DC_Trig_thr_l of the discharge trigger pulse counting threshold interval DC_Trig_thr is greater than 200 μs, and the upper limit DC_Trig_thr_h of the discharge trigger pulse counting threshold interval DC_Trig_thr is less than 405 μs. In this embodiment, DC_Trig_thr = [373 μs, 397 μs];

[0099] The threshold interval of the reference pulse of the magnetic pulser MEG_REF_thr represents a defined range corresponding to the phase difference of the rising edge of the reference pulse of the magnetic pulser relative to the rising edge of the start pulse; the lower limit of the threshold interval of the reference pulse of the magnetic pulser MEG_REF_thr_l is greater than or equal to 405 μs, and the upper limit of the threshold interval of the reference pulse of the magnetic pulser MEG_REF_thr_h is less than 425 μs.

[0100] During the counting process of the counter 2, the abnormality detection circuit 4 checks in real time whether the time corresponding to the count value countl in the counter 2 is within the threshold interval of the four single pulses. When the rising edge is detected and at the same time the threshold interval corresponding to the corresponding single pulse is met, it is considered that the single pulse is correctly detected, and the count value countl at this time is recorded, and the flag bit corresponding to the single pulse (the start pulse flag bit Find_STP_Flag, the charge trigger pulse flag bit Find_Charge_Flag, the discharge trigger pulse flag bit Find_DC_Trig_Flag, and the reference pulse flag bit of the magnetic pulser Find_MEG_REF_Flag) is set.

[0101] The preset sampling time point determines the time point at which the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A rate phase encoding φA are sampled. In this embodiment, the sampling time points corresponding to the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A rate phase encoding φA are 60 μs, 160 μs, and 195 μs, respectively, relative to the start pulse STP interval.

[0102] Step 2, the link switch 10 is set to off;

[0103] Step 3, the count value countl in the counter 2, the registers of the sampling circuit 6, and all the flag bits in the state flag register 5 are reset and initialized by the reset control circuit 7;

[0104] In this embodiment, the initialization of the count value countl and all the single pulse corresponding flag bits is set to 0, and the integrity error flag bit SERDA_Integrity_Error is initialized to 1;

[0105] The single pulse corresponding flag bits include: the start pulse flag bit Find_STP_Flag, the charge trigger pulse flag bit Find_Charge_Flag, the discharge trigger pulse flag bit Find_DC_Trig_Flag, and the reference pulse flag bit of the magnetic pulser Find_MEG_REF_Flag.

[0106] Step 4: Perform integrity check and data sampling on the serial data signal SERDA:

[0107] Input circuit 1 captures serial data signal SERDA and detects rising edges in the serial data signal SERDA. Counter 2 starts counting. Abnormality detection circuit 4 detects the start pulse STP, charge trigger pulse Charge, discharge trigger pulse DC_Trig, and magnetic pulser reference pulse MEG_REF in the serial data signal SERDA using the count value count1 output by counter 2, and determines the integrity of the serial data signal SERDA. If the serial data signal SERDA is complete, that is, the serial data signal SERDA includes four single pulses, namely the start pulse STP, charge trigger pulse Charge, discharge trigger pulse DC_Trig, and magnetic pulser reference pulse MEG_REF, and the times corresponding to the count values ​​count1 of the four single pulses meet the preset counting threshold requirements, then step 5 is executed. If any of the start pulse STP, charge trigger pulse Charge, discharge trigger pulse DC_Trig, and magnetic pulser reference pulse MEG_REF is not detected, then the circuit returns to step 3 and re-detects the next rising edge. The specific steps are:

[0108] Step 4.1: Input circuit 1 captures the serial data signal SERDA. Input circuit 1 uses a shift register and edge detection to detect the rising edge of serial data signal SERDA. When input circuit 1 detects a rising edge, it is considered that input circuit 1 has detected the first single pulse, and step 4.2 is executed. In this embodiment, input circuit 1 uses a three-stage shift register to determine whether a rising edge has occurred based on the state changes of serial data signal SERDA.

[0109] Step 4.2. When the input circuit 1 detects the first rising edge, the count value count1 output by the counter 2 starts counting from 0, the abnormality detection circuit 4 receives the first detection enable signal sent by the input circuit 1, and the abnormality detection circuit 4 outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register 5, so that the start pulse flag Find_STP_Flag is set. In this embodiment, the start pulse flag Find_STP_Flag is set to 1; after the counter 2 starts counting, it continues to send the count value count1 corresponding to each moment to the abnormality detection circuit 4.

[0110] Since when the program is initially run (or an error in the serial data signal SERDA is detected and the program is reset), the count value count1 and the flag bits corresponding to all single pulses are 0, then any pulse detected is regarded as the start pulse STP, and the corresponding start pulse flag Find_STP_Flag is set to 1. If the next single pulse is input, the input circuit 1 regards the second pulse as the charge trigger pulse Charge.

[0111] Step 4.3: Input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0112] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0113] If the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max and the input circuit 1 still does not detect the second rising edge (that is, the abnormality detection circuit 4 does not receive the second detection enable signal), then return to step 3;

[0114] If the count value count1 output by the counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects a second rising edge, and the abnormality detection circuit 4 receives the second detection enable signal sent by the input circuit 1. At this time, the start pulse flag Find_STP_Flag is 1 and the charge trigger pulse flag Find_Charge_Flag is 0, and the second pulse is considered to be the charge trigger pulse Charge. At this time, the register of the counter 2 temporarily stores the phase difference between the rising edge of the second pulse and the rising edge of the start pulse STP (that is, the time corresponding to the count value count1 corresponding to the second rising edge); the abnormality detection circuit 4 uses the time corresponding to the count value count1 corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase And determine whether the charge trigger pulse phase difference delta_Charge_phase is within the set charge trigger pulse count threshold interval Charge_thr. If the charge trigger pulse phase difference delta_Charge_phase is within the charge trigger pulse count threshold interval Charge_thr, the abnormality detection circuit 4 sets the charge trigger pulse flag Find_Charge_Flag in the status flag register 5. In this embodiment, the charge trigger pulse flag Find_Charge_Flag is set to 1, and then executes step 4.4; otherwise, return to step 3 (that is, set the flag positions corresponding to all single pulses to 0, clear all caches, set the integrity error flag SERDA_Integrity_Error to 1, and keep the link switch 10 closed).

[0115] Step 4.4: Counter 2 continues counting. After sampling circuit 6 identifies the charge trigger pulse flag Find_Charge_Flag as 1, it sequentially samples the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase code φA at the preset sampling time point. The sampling results are stored in the register of sampling circuit 6 as buffered data (the buffered data is not output in step 4.4). Then, proceed to step 4.5.

[0116] In step 4.4, sampling only needs to be performed according to the preset sampling time point. Only when the four single pulses of the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF are detected will the sampled data (eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD, one-bit A-rate phase code φA) be output to the external monitoring control unit 9.

[0117] During the sampling process, the abnormality detection circuit 4 does not judge the count value count1.

[0118] Step 4.5: Input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0119] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0120] If the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max and the input circuit 1 still does not detect the third rising edge, return to step 3;

[0121] If the count value count1 output by the counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects the third rising edge, and the abnormality detection circuit 4 receives the third detection enable signal sent by the input circuit 1. At this time, the start pulse flag Find_STP_Flag and the charge trigger pulse flag Find_Charge_Flag are both 1, and the discharge trigger pulse flag Find_DC_Trig_Flag is 0. This single pulse is considered to be the discharge trigger pulse DC_Trig, and the register of the counter 2 temporarily stores the phase difference between the rising edge of the third pulse and the rising edge of the start pulse STP (that is, the time corresponding to the count value count1 corresponding to the third rising edge) as the discharge trigger pulse phase difference delta_DC_Trig_phase. The abnormality detection circuit 4 will discharge The trigger pulse phase difference delta_DC_Trig_phase is compared with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the abnormality detection circuit 4 sets the discharge trigger pulse flag Find_DC_Trig_Flag in the status flag register 5. In this embodiment, the discharge trigger pulse flag Find_DC_Trig_Flag is set to 1, and then the next step 4.6 is executed; otherwise, return to step 3 (that is, set the flag positions corresponding to all single pulses to 0, clear all caches, set the integrity error flag SERDA_Integrity_Error to 1, and the link switch 10 remains closed).

[0122] In step 4.5, when both the start pulse STP and the charge trigger pulse Charge are detected, when detecting the third single pulse, it may be interfered by the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase encoding φA signal, causing these data to be mistakenly judged as the discharge trigger pulse DC_Trig. Therefore, the third single pulse is judged by the discharge trigger pulse flag Find_DC_Trig_Flag to eliminate the serial data signal SERDA with data bit interference.

[0123] Step 4.6: Input circuit 1 continues to detect the rising edge of serial data signal SERDA, while counter 2 continues to count;

[0124] At the same time, the abnormality detection circuit 4 judges the count value count1:

[0125] If the count value count1 output by the counter 2 reaches the maximum count value threshold value count_max and the input circuit 1 still does not detect the fourth rising edge, the process returns to step 3;

[0126] If the count value count1 output by the counter 2 does not reach the maximum count value threshold value count_max, the input circuit 1 detects the fourth rising edge, and the abnormality detection circuit 4 receives the fourth detection enable signal sent by the input circuit 1. At this time, the fourth single pulse is input and the flags corresponding to the first three pulses of the serial data signal SERDA (i.e., the start pulse flag Find_STP_Flag, the charge trigger pulse flag Find_Charge_Flag, and the discharge trigger pulse flag Find_DC_Trig_Flag) are all 1, the register of the counter 2 temporarily stores the phase difference between the rising edge of the fourth pulse and the rising edge of the first pulse (i.e., the time corresponding to the count value count1 corresponding to the fourth rising edge), which is recorded as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase, and the abnormality detection circuit 4 compares the magnetic pulser reference pulse phase difference delta_MEG_REF_phase with the magnetic pulser reference pulse counting threshold value. The interval MEG_REF_thr is used for comparison. If the magnetic pulser reference pulse phase difference delta_MEG_REF_phase is within the range of the magnetic pulser reference pulse counting threshold interval MEG_REF_thr, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is set. In this embodiment, the magnetic pulser reference pulse flag Find_MEG_REF_Flag is set to 1, indicating that the four single pulses of the serial data signal SERDA are all detected, and the integrity error flag SERDA_Integrity_Error is set. In this embodiment, the integrity error flag SERDA_Integrity_Error is set to 0, and the process goes to step 5; otherwise, the process returns to step 3 (i.e., the flags corresponding to all single pulses are set to 0, all caches are cleared, the integrity error flag SERDA_Integrity_Error is set to 1, and the link switch 10 remains closed).

[0127] If any single pulse is not detected in step 4, the count value count1 is set to 0 and the integrity error flag SERDA_Integrity_Error is set to 1. At the same time, the program is reset and waits for the next single pulse to be detected.

[0128] Since the count value count1 is constantly counting, the moment of the first pulse input is recorded as time 0 and the count value is cleared. If there is no serial data signal SERDA input, counter 2 will continue counting, that is, regardless of whether there is a signal input, and will only be reset to 0 when the start pulse STP input is detected, the program is reset, or there is no signal input, causing the count value count1 to exceed the maximum count threshold. If the count value count1 exceeds the maximum count threshold count_max, the integrity error flag SERDA_Integrity_Error is set to 1, and the process returns to step 3 to restart counting. The maximum count threshold count_max is set to the maximum interval between the two consecutive serial data signals SERDA on the same channel. In this embodiment, the maximum interval between the two consecutive serial data signals SERDA on the same channel is 99 ms. If the time recorded by the count value count1 exceeds 99 ms, the integrity error flag SERDA_Integrity_Error is set to 1. If there is no signal input and the count value count1 has been counting for more than 99 ms, the count value count1 is cleared and counting restarts. This process continues continuously.

[0129] In steps 4.3-4.6, if no rising edge is detected, the program continues to detect rising edges after resetting. It is possible that the pulse detected after reset is not actually the start pulse STP. Due to the threshold range limit of each single pulse in the serial data signal SERDA, even if the program mistakenly detects other pulses as the start pulse STP, the program will still reset and recount because the next pulse is not within the preset charge trigger pulse counting threshold range Charge_thr.

[0130] Step 5. At this point, the integrity check of the entire serial data signal SERDA has been completed. The output circuit 8 outputs the data temporarily stored in the counter 2, the sampling circuit 6, and the status flag register 5 to the external monitoring control unit 9. The external monitoring control unit 9 opens the link switch 10 so that the complete and abnormal serial data signal SERDA in the current input circuit 1 detected in step 4 is input to the HCG half-cycle power generation unit 11 of the corresponding Loran C transmitter, and then returns to step 2.

[0131] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Persons skilled in the art may make various modifications, additions, or substitutions to the described specific embodiments without departing from the spirit of the present invention or exceeding the scope of the appended claims.

Claims

1. A device for detecting a Loran C key signal, comprising an input circuit (1), characterized in that: The input circuit (1) captures the serial data signal SERDA. When the input circuit (1) detects the first rising edge of the serial data signal SERDA, the input circuit (1) sends a count enable signal to the counter (2). Whenever the input circuit (1) detects a rising edge of the serial data signal SERDA, the input circuit (1) sends a detection enable signal to the abnormality detection circuit (4). The counter (2) receives a clock signal and a count enable signal from a clock source (3). When the counter (2) receives the count enable signal, it starts to count continuously and sends the count value count1 to the abnormality detection circuit (4) in sequence. The abnormality detection circuit (4) judges whether the serial data signal SERDA includes four single pulses, namely, a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig, and a magnetic pulser reference pulse MEG_REF, in sequence, and whether the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse. According to the judgment result, the abnormality detection circuit (4) outputs a flag setting signal corresponding to each single pulse and a flag setting signal corresponding to the integrity error flag SERDA_Integrity_Error to the status flag register (5), thereby setting the flag corresponding to the single pulse and the integrity error flag SERDA_Integrity_Error; the reset control circuit (7) selects whether to send a reset execution signal to the counter (2) and the status flag register (5) according to the value of the integrity error flag SERDA_Integrity_Error in the status flag register (5); The external monitoring control unit (9) controls the link switch (10) between the input circuit (1) and the HCG half-cycle power generation unit (11) according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register (5).

2. The device for detecting a Loran-C key signal according to claim 1, wherein: The counting value threshold intervals corresponding to each single pulse include: The charge trigger pulse counting threshold interval Charge_thr represents the time limit of the count value countl corresponding to the rising edge of the charge trigger pulse, corresponding to the charge trigger pulse Charge; The discharge trigger pulse counting threshold interval DC_Trig_thr represents the time limit of the count value count1 corresponding to the rising edge of the discharge trigger pulse, corresponding to the discharge trigger pulse DC_Trig; The magnetic pulser reference pulse counting threshold interval MEG_REF_thr represents the time limit corresponding to the count value count1 corresponding to the rising edge of the magnetic pulser reference pulse, corresponding to the magnetic pulser reference pulse MEG_REF; The flag bits corresponding to each single pulse in the serial data signal SERDA include: The start pulse flag Find_STP_Flag corresponds to the start pulse STP; The charge trigger pulse flag bit Find_Charge_Flag corresponds to the charge trigger pulse Charge; The discharge trigger pulse flag Find_DC_Trig_Flag corresponds to the discharge trigger pulse DC_Trig; The magnetic pulser reference pulse flag Find_MEG_REF_Flag corresponds to the magnetic pulser reference pulse MEG_REF.

3. The device for detecting a Loran C key signal according to claim 1 is characterized in that , the input circuit (1) adopts a three-stage shift register structure.

4. The device for detecting a Loran C key signal according to claim 2, characterized in that , further comprising a sampling circuit (6) and an output circuit (8), The sampling circuit (6) receives the clock signal of the clock source (3) and selects whether to sample and temporarily store the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD and the one-bit A-rate phase code φA according to the flag bits corresponding to the start pulse STP and the charge trigger pulse Charge; The output circuit (8) reads the flag bits corresponding to each single pulse of the status flag register (5) and the value of the integrity error flag bit SERDA_Integrity_Error, and selects whether to transmit the data temporarily stored in the counter (2), the sampling circuit (6) and the status flag register (5) to the external monitoring control unit (9); The data temporarily stored in the counter (2) are: the count value count1 corresponding to the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF; The data temporarily stored in the sampling circuit (6) are: eight-bit digital amplitude reference DAR, seven-bit amplitude compensation delay ACD and one-bit A-rate phase code φA; The data temporarily stored in the status flag register (5) are: the flag bits corresponding to each single pulse and the value of the integrity error flag bit SERDA_Integrity_Error; The reset control circuit (7) selects whether to send a reset execution signal to the sampling circuit (6) according to the value of the integrity error flag bit SERDA_Integrity_Error in the status flag register (5).

5. A method for detecting a Loran C key signal, using the device for detecting a Loran C key signal according to claim 4, characterized in that , including the following steps: Step 1: setting the count value threshold interval and the maximum count value threshold count_max corresponding to each single pulse in the abnormality detection circuit (4), and setting the preset sampling time point in the sampling circuit (6); Step 2: The link switch (10) is set to off; Step 3: Reset and initialize the count value count1 in the counter (2), the register of the sampling circuit (6), and all the flag bits in the status flag register (5) through the reset control circuit (7); Step 4: The input circuit (1) captures the serial data signal SERDA and detects the rising edge in the serial data signal SERDA, the counter (2) starts counting, and the abnormality detection circuit (4) detects the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF in the serial data signal SERDA through the count value count1 output by the counter (2), and determines whether the serial data signal SERDA is complete. If the serial data signal SERDA is complete, that is, the serial data signal SERDA includes four single pulses, namely the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF, in sequence, and the time corresponding to the count value count1 of the four single pulses is respectively within the count value threshold interval corresponding to each single pulse, then step 5 is executed; if any one of the start pulse STP, the charge trigger pulse Charge, the discharge trigger pulse DC_Trig and the magnetic pulser reference pulse MEG_REF is not detected, then the process returns to step 3; Step 5: The external monitoring control unit (9) turns on the link switch (10) so that the complete and normal serial data signal SERDA in the input circuit (1) is input into the HCG half-cycle power generation unit (11) of the corresponding Loran C transmitter, and then returns to step 2.

6. The method for detecting a Loran-C key signal according to claim 5, wherein In step 1, the maximum count value threshold count_max is set to the maximum interval time between the two serial data signals SERDA on the same path.

7. The method for detecting a Loran-C key signal according to claim 5, characterized in that , in the step 1, Set the lower limit of the charge trigger pulse count threshold interval Charge_thr_l in the charge trigger pulse count threshold interval Charge_thr to be greater than 5μs, and the upper limit of the charge trigger pulse count threshold interval Charge_thr_h to be less than 60μs; The discharge trigger pulse count threshold interval lower limit DC_Trig_thr_l in the discharge trigger pulse count threshold interval DC_Trig_thr is greater than 200 μs, and the discharge trigger pulse count threshold interval upper limit DC_Trig_thr_h is less than 405 μs; The magnetic pulser reference pulse count threshold interval lower limit MEG_REF_thr_l in the magnetic pulser reference pulse count threshold interval MEG_REF_thr is greater than or equal to 405 μs, and the magnetic pulser reference pulse count threshold interval upper limit MEG_REF_thr_h is less than 425 μs.

8. The method for detecting a Loran C key signal according to claim 5, characterized in that , the step 4 specifically includes the following steps: Step 4.1, the serial data signal SERDA is captured by the input circuit (1); Step 4.2: When the input circuit (1) detects the first rising edge, the count value count1 output by the counter (2) starts counting from 0, the abnormality detection circuit (4) receives the first detection enable signal sent by the input circuit (1), and the abnormality detection circuit (4) outputs a flag setting signal corresponding to the start pulse flag Find_STP_Flag to the status flag register (5), so that the start pulse flag Find_STP_Flag in the status flag register (5) is set; After the counter (2) starts counting, it continuously sends the count value count1 corresponding to each moment to the abnormality detection circuit (4); Step 4.3, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) judges the count value count1: If the input circuit (1) still does not detect the second rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, the process returns to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects a second rising edge, and the abnormality detection circuit (4) receives the second detection enable signal sent by the input circuit (1), then the register of the counter (2) temporarily stores the count value count1 corresponding to the second rising edge; the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the second rising edge as the charge trigger pulse phase difference delta_Charge_phase and determines whether the charge trigger pulse phase difference delta_Charge_phase is within the set charge trigger pulse count threshold interval Charge_thr; if the charge trigger pulse phase difference delta_Charge_phase is within the charge trigger pulse count threshold interval Charge_thr, the abnormality detection circuit (4) sets the charge trigger pulse flag Find_Charge_Flag in the status flag register (5) and then executes step 4.4; otherwise, returns to step 3; Step 4.4, the counter (2) continues counting, and after the sampling circuit (6) identifies that the charge trigger pulse flag Find_Charge_Flag is 1, the eight-bit digital amplitude reference DAR, the seven-bit amplitude compensation delay ACD, and the one-bit A-rate phase code φA are sequentially sampled according to the preset sampling time point, and the sampling results are temporarily stored in the register of the sampling circuit (6); During the sampling process, the abnormality detection circuit (4) does not judge the count value count1; Step 4.5, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) judges the count value count1: If the input circuit (1) still does not detect the third rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, the process returns to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects the third rising edge, the abnormality detection circuit (4) receives the third detection enable signal sent by the input circuit (1), the register of the counter (2) temporarily stores the count value count1 corresponding to the third rising edge, the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the third rising edge as the discharge trigger pulse phase difference delta_DC_Trig_phase, and compares it with the set discharge trigger pulse count threshold interval DC_Trig_thr. If the discharge trigger pulse phase difference delta_DC_Trig_phase is within the range of the discharge trigger pulse count threshold interval DC_Trig_thr, the discharge trigger pulse flag Find_DC_Trig_Flag is set, and then step 4.6 is executed; otherwise, return to step 3; Step 4.6, the input circuit (1) continues to detect the rising edge of the serial data signal SERDA, and the counter (2) continues to count; At the same time, the abnormality detection circuit (4) judges the count value count1: If the input circuit (1) still does not detect the fourth rising edge when the count value count1 output by the counter (2) reaches the maximum count value threshold value count_max, return to step 3; If the count value count1 output by the counter (2) does not reach the maximum count value threshold value count_max, the input circuit (1) detects the fourth rising edge, and the abnormality detection circuit (4) receives the fourth detection enable signal sent by the input circuit (1), then the register of the counter (2) temporarily stores the count value count1 corresponding to the fourth rising edge, and the abnormality detection circuit (4) uses the time corresponding to the count value count1 corresponding to the fourth rising edge as the magnetic pulser reference pulse phase difference delta_MEG_REF_phase and compares it with the magnetic pulser reference pulse count threshold interval MEG_REF_thr. If the magnetic pulser reference pulse phase difference delta_MEG_REF_phase is within the range of the magnetic pulser reference pulse count threshold interval MEG_REF_thr, the abnormality detection circuit (4) sets the magnetic pulser reference pulse flag Find_MEG_REF_Flag and the integrity error flag SERDA_Integrity_Error in the status flag register (5) and executes step 5; otherwise, returns to step 3.

9. A method for detecting a Loran C key signal according to claim 8, characterized in that , the step 5 specifically includes the following steps: The output circuit (8) outputs the data temporarily stored in the counter (2), the sampling circuit (6) and the status flag register (5) to the external monitoring control unit (9). The external monitoring control unit (9) opens the link switch (10) so that the complete and abnormal serial data signal SERDA detected in step 4 in the current input circuit (1) is input into the HCG half-cycle power generation unit (11) of the corresponding Loran C transmitter, and then returns to step 2.

10. A method for detecting a Loran C key signal according to claim 5, characterized in that A set of the aforementioned Roland C key signal detection device processes one serial data signal SERDA, and four serial data signals SERDA are input in parallel into the corresponding set of the aforementioned Roland C key signal detection device.

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