Zero-knowledge proof oriented CPU-GPU data processing and transmission optimization system and method

Abstract

The application discloses a CPU-GPU data processing and transmission optimization system for zero-knowledge proof, which is used for performing multi-scalar multiplication operation based on elliptic curve cryptography to realize generation of zero-knowledge proof, and comprises a CPU and a GPU, wherein a data transmission channel is arranged between the CPU and the GPU, the CPU is used for acquiring and storing a point set and a scalar set related to the multi-scalar multiplication operation, and performing communication with the GPU by using a set parallelization data transmission mechanism, the GPU performs calculation of multi-scalar multiplication based on the point set and the scalar set, and returns the calculation result to the CPU. Through the synergistic effect of multiple technical points, the speed and efficiency of the generation of zero-knowledge proof are significantly improved, and the resource use efficiency is optimized.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a CPU-GPU data processing and transmission optimization system and method for zero-knowledge proofs. Background Technology

[0002] Zero-Knowledge Proof (ZKP) is a cryptographic protocol based on the agreement of two or more parties. Its purpose is to enable the prover to convince the verifier of the truth of a statement without revealing any useful information. The key to this protocol is ensuring both the verifier's trust and the prover's privacy. The core value of zero-knowledge proof lies in its ability to prove the truth of a statement without disclosing any specific information. However, implementing this technology faces significant computational challenges, primarily due to the computationally intensive nature of its algorithms. Traditional central processing unit (CPU) architectures struggle to handle such high-concurrency, high-computational-density tasks, especially when dealing with large datasets and complex calculations. Limited by their single-threaded performance and memory access latency, CPUs often fail to achieve satisfactory efficiency.

[0003] To overcome this limitation, heterogeneous computing architectures, particularly Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and Graphics Processing Units (GPUs), have become key to achieving efficient computation of zero-knowledge proofs due to their unique parallel processing capabilities and customized computing advantages. FPGAs, through parallel processing and pipeline optimization, can significantly improve the speed of complex mathematical operations in ZKP, thereby shortening the time for proof generation and verification, which is particularly important for applications with high real-time requirements. Furthermore, the programmability and flexibility of FPGAs allow for customized designs for specific ZKP algorithms, enabling more efficient computational paths, reducing unnecessary data movement and storage, thus improving overall performance and making large-scale deployment possible. ASICs are integrated circuits specifically customized for a particular type of application. For zero-knowledge proofs, ASICs can be designed to specifically perform certain key mathematical operations, such as modular multiplication and elliptic curve point addition, thereby providing higher-performance customized computation, lower power consumption, smaller physical size, and long-term economic benefits. Especially in stable, large-scale applications, the fixed circuit design of ASICs ensures computational efficiency and data processing security. For example, PipeZK uses ASIC chips to implement a pipelined architecture, accelerating the computationally intensive stages of fast number theory transformations and multi-scalar multiplication through dedicated circuits, achieving efficient zero-knowledge proof generation. GPUs possess a large number of simple computational units specifically designed for parallel computing, capable of executing numerous similar computational tasks simultaneously. This is highly effective for matrix operations, vector operations, and parallelized large number operations common in zero-knowledge proofs. GPUs offer a robust programming environment, providing developers with user-friendly development tools and libraries, enabling them to program using high-level languages ​​similar to C++. This significantly lowers the learning curve for developing zero-knowledge proof algorithms, allowing developers from a wider range of backgrounds to participate. Furthermore, the GPU market is relatively mature, with abundant driver support and development tools.

[0004] However, existing heterogeneous computing architectures for generating zero-knowledge proofs have the following drawbacks:

[0005] 1) FPGA design and implementation typically require deep knowledge of hardware description languages ​​(such as Verilog or VHDL) and a thorough understanding of hardware logic design principles. This results in a high technical barrier and learning cost; for developers with a software background, mastering FPGA development skills often requires a significant amount of time and effort. Furthermore, circuit designs on FPGAs are usually highly customized, optimized for specific algorithms or applications. This exclusivity means that porting designs between different application scenarios can be difficult, requiring re-evaluation and adjustment of hardware configurations, increasing project development time and costs.

[0006] 2) While applying ASIC chips to the generation and verification of zero-knowledge proofs can significantly improve the efficiency of specific algorithms and reduce energy consumption, it also has some limitations. For example, poor flexibility: once the design of an ASIC chip is completed, its circuit layout and function are fixed, meaning it cannot easily adapt to new ZKP algorithms or parameter changes; high development costs: designing and manufacturing ASIC chips requires high upfront investment, including design fees, mask costs, and testing and production costs, which is uneconomical for small-scale applications or experimental ZKP schemes; long update cycles: the design and manufacturing cycle of ASICs is long, and if there are major breakthroughs or algorithm improvements in the ZKP field, ASICs cannot keep up in time, leading to obsolescence.

[0007] 3) Although GPUs possess high-bandwidth video memory, ZKP computations can involve significant data transfers, especially when data needs to be frequently exchanged between the CPU and GPU. This adds additional latency and overhead. Data transfer between the host (CPU) and the device (GPU) requires traversing the PCIe bus, which is a bottleneck. For ZKP computations, if the algorithm requires extensive data exchange, this communication latency can significantly impact performance. This problem is exacerbated by frequent data transfers, particularly when ZKP involves complex interactive protocols. Furthermore, latency exists not only in communication between the GPU and external systems but also in data sharing and synchronization between different threads within the GPU. Poorly designed ZKP algorithms leading to unnecessary memory access patterns or excessive synchronization operations can also increase computational latency.

[0008] In existing zero-knowledge proof generation libraries, such as the Bellman algorithm library, the architecture is often limited by the data transfer between the CPU and GPU, resulting in performance bottlenecks. Figure 1 As shown, multi-scalar multiplication typically involves the transfer of a large number of point sets and scalar sets between heterogeneous architectures. However, since the GPU must wait for the CPU to complete the data transfer before it can begin computation, the GPU remains idle during this period, thus impacting overall computational efficiency.

[0009] In summary, the widespread application of zero-knowledge proof technology still faces challenges such as high computational demands, lengthy generation cycles, and high operating costs. These factors significantly hinder its widespread adoption within architectures such as blockchain. Especially in environments like financial markets where immediate response is crucial, the latency in generating and verifying zero-knowledge proofs directly threatens the confidentiality and robustness of transactions, leading to a series of negative effects such as transaction delays, decreased trust, and potential economic losses. It is worth noting that frequent data exchange between the host computer and the graphics processing unit (GPU) often results in idle computing resources, creating a bottleneck for performance improvement. Therefore, optimizing the communication mechanism between the CPU and GPU and improving memory access strategies are key strategies for enhancing the performance of zero-knowledge proofs, aiming to significantly reduce proof construction time. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a CPU-GPU data processing and transmission optimization system and method oriented towards zero-knowledge proof.

[0011] According to a first aspect of the present invention, a CPU-GPU data processing and transmission optimization system for zero-knowledge proofs is provided, which is used to perform multi-scalar multiplication operations based on elliptic curve cryptography to generate zero-knowledge proofs. The system includes a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU. The CPU is used to acquire and store the point set and scalar set involved in the multi-scalar multiplication operation, and communicates with the GPU using a set parallel data transmission mechanism. The GPU performs multi-scalar multiplication calculations based on the point set and the scalar set, and sends the calculation results back to the CPU.

[0012] According to a second aspect of the present invention, a CPU-GPU data processing and transmission optimization method for zero-knowledge proofs is provided. The method includes the following steps:

[0013] The point set and scalar set involved in the multi-scalar multiplication operation are stored in the CPU. This multi-scalar multiplication operation is based on elliptic curve cryptography and is used to generate zero-knowledge proofs.

[0014] The system utilizes a set parallel data transfer mechanism to transfer data between the CPU and GPU, thereby controlling the GPU to perform multi-scalar multiplication calculations based on the point set and the scalar set, and then sending the calculation results back to the CPU.

[0015] Compared with existing technologies, the advantages of this invention lie in its innovative parallel data transmission mechanism for CPU-GPU heterogeneous architectures. The core of this parallel mechanism is a redesign of the data flow, allowing the GPU to immediately process the already transmitted partial data while the CPU prepares the data, without waiting for all data to be transmitted completely at once. This design improves the throughput of zero-knowledge proof generation, reduces GPU idle cycles, and shortens proof generation time through more efficient task scheduling. Thus, without increasing hardware overhead, it effectively improves system performance and reduces computational costs. This invention solves problems such as communication latency between the CPU and GPU, as well as data sharing and synchronization latency.

[0016] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0018] Figure 1 This is the existing Bellman execution diagram;

[0019] Figure 2 This is a schematic diagram of a CPU-GPU heterogeneous architecture for zero-knowledge proof according to an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram illustrating the update process of a shared pre-computation table according to an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram illustrating the calculation of an elliptic curve according to an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram comparing CPU-GPU transmission performance for zero-knowledge proof according to an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of zero-copy technology according to an embodiment of the present invention. Detailed Implementation

[0024] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0029] In the computation of zero-knowledge proofs, efficient data transfer between the CPU and GPU is crucial. Improving data transfer efficiency can significantly reduce the latency of data exchange between the CPU and GPU, reduce waiting time during transmission, thereby accelerating the generation and verification of zero-knowledge proofs. Furthermore, it can provide users with a smoother and more efficient service experience while ensuring high security and privacy, meeting the growing demands for big data processing and complex computations.

[0030] The CPU-GPU data processing and transmission optimization system for zero-knowledge proofs provided in this invention is a CPU-GPU heterogeneous architecture. See [link to related documentation]. Figure 2 As shown. The CPU (Central Processing Unit) is the main computing unit of a computer, including components such as the controller, ALU (Arithmetic Logic Unit), cache, and memory. The CPU is responsible for controlling and coordinating the operation of the system, including but not limited to running the operating system, managing memory, and I / O devices. In the context of ZKP, the CPU is typically responsible for handling non-parallel logical processes, such as initialization, data preparation, and result summarization, as well as performing necessary data preprocessing and post-processing before and after GPU (Graphics Processing Unit) computation. GPUs were originally designed for graphics rendering, but due to their powerful parallel computing capabilities, they are now widely used in scientific computing, machine learning, and cryptography. A GPU consists of multiple stream processors (SMs), each employing a single-instruction, multi-threaded parallel processing mode, supporting thousands of synchronous threads residing in GPU main memory. This gives GPUs high parallelism, making them particularly suitable for handling large-scale computational tasks without data dependencies, such as the operations required in zero-knowledge proofs. In zero-knowledge proof scenarios, GPUs are mainly used to perform a large number of parallel mathematical operations, such as matrix multiplication, modular arithmetic, and polynomial operations, which are the most time-consuming parts of the zero-knowledge proof generation and verification process.

[0031] Overall, the system architecture of this invention focuses on optimizing the communication and memory architectures, both of which are crucial for improving efficient data transfer between the CPU and GPU in zero-knowledge proofs (ZKP). Regarding the communication architecture, a high-speed data transfer channel, such as PCIe (Peripheral Component Interconnect Express), is required between the CPU and GPU. The optimized system utilizes more efficient transmission protocols and hardware to achieve intelligent scheduling and optimization of data flow, ensuring efficient data flow between the CPU and GPU, reducing unnecessary data copying and waiting time, and ensuring that data transfer does not become a bottleneck for overall system performance. Regarding the memory architecture, the system typically includes two types of memory: CPU memory and GPU memory. To improve efficiency, data needs to be intelligently managed and scheduled between these memory spaces to minimize data copying and transfer during computation.

[0032] To address the performance bottlenecks in the zero-knowledge proof generation process, this invention proposes an innovative high-performance computing framework focused on optimizing data transmission and preprocessing mechanisms. This framework aims to significantly improve the execution efficiency of zero-knowledge proof algorithms while ensuring the rational utilization of resources, thereby enhancing the overall performance and security of the system. The following sections will detail embodiments of the optimized preprocessing and data transmission mechanisms.

[0033] First, optimize the preprocessing mechanism.

[0034] 1. Shared pre-calculation table

[0035] A precomputation table is a data structure used to pre-compute and store the results of specific functions or operations that will be frequently used in subsequent computations. By creating such a table before computation begins or in the early stages of computationally intensive tasks, a portion of the computationally intensive workload can be offloaded to the preprocessing phase. This approach can significantly reduce the cost of online or real-time computation and improve computational efficiency.

[0036] In the context of multi-scalar multiplication (MSM) in Elliptic Curve Cryptography (ECC), shared precomputation tables are an optimization technique used to reduce computation time and storage requirements. Shared precomputation tables are an efficient method to accelerate subsequent MSM computations by pre-compiling and storing multiples of points on the elliptic curve. This approach is particularly useful when dealing with multiple related points, as it allows these points to share the same optimization table, thereby reducing redundant computation and storage burdens.

[0037] The basic idea of ​​a shared pre-calculation table is: assuming there is a set of points {P1, P2, ..., P...} n} and these points all lie in the same subgroup on the elliptic curve. This means that for any point P i and P j There exists some integer k such that P i =k·P j Or P j =k·P i If we can find a base point G that is the generator of all points, i.e., all points P... i =k i If G is the base point, then we can pre-calculate the multiples of G, and these multiples can be used to accelerate any point P. i Scalar multiplication.

[0038] In one embodiment, the steps of implementing multiscalar multiplication using a shared pre-computation table include:

[0039] S1, Selecting a base point: Find a suitable base point G that can generate a point containing all P. i Subgroups of.

[0040] Typically, G is a generator of a large prime order on an elliptic curve.

[0041] S2, Construct a pre-computation table: pre-compute the multiples sequence of G.

[0042] For example, the pre-computed multiples sequence of G is G, 2G, 3G, ..., lG, where l is the maximum length of the pre-computed table, usually 2. w , where w is the window size in the split window stage of the Pippenger (bucket) algorithm.

[0043] S3 optimizes scalar multiplication.

[0044] For example, for each point P i =k i ·G, scalar multiplication can be accelerated by looking up the appropriate value in the pre-computed table. Specifically, if k i In binary, it can be decomposed into k. i =b0+b1·2 w +b2·2 2w +..., where b j If it is a w-bit binary number, then point G in the pre-computed table can be used, 2. w G, 2 2w G..., and P is obtained through dot addition and doubling operations. i .

[0045] The core of the pre-computation table's storage lies in the carefully selected set of multiples of the base point G, and the scalar relationships between the points in each set and G. These multiples form the fundamental components for rapidly constructing arbitrary scalar multiplication results. By pre-compiling and storing a series of multiples of the base point G, subsequent large-scale scalar multiplication operations can be significantly accelerated, as many common multiplications can be decomposed into simple combinations of pre-computation points, reducing the need for real-time computation. Furthermore, to reduce the storage overhead of the pre-computation table, coordinate compression techniques can be employed, storing only the x-coordinates of the points, while the y-coordinates can be calculated when needed based on the elliptic curve equation, achieving efficient utilization of storage space.

[0046] To address different situations and performance requirements, in one embodiment, the pre-computation table will also be updated periodically, including but not limited to adding deeper pre-computation points to accommodate the Pippenger algorithm with a larger window size, or updating the algorithm to improve efficiency.

[0047] Figure 3 This is the process of updating the pre-computation table. At the start of computation, a certain amount of storage space is reserved in the pre-computation table to store pre-calculated point sets. These point sets are usually carefully selected based on the expected computational needs to cover most cases as much as possible in subsequent computations. When a point set that needs to be solved is encountered during computation, the system first tries to check if a corresponding calculated result exists in the pre-computation table. If it exists, the result can be retrieved directly from the table without performing complex calculations again, thus saving a significant amount of computation time and resources; if it does not exist, the point set is recalculated, and the result is returned to the GPU. As computation progresses, the contents of the pre-computation table also change. When a new calculation result is generated, it needs to be decided whether to add it to the pre-computation table. If the pre-computation table still has enough remaining space, the newly generated point set result will be directly inserted into the table for later querying. This design can further reduce future computational burden and improve computational efficiency. However, when the space in the pre-computation table is insufficient, an effective strategy is adopted to manage the contents of the table. Considering the significant temporal locality of computation in point sets—meaning that recently accessed point sets are likely to be accessed again within a certain timeframe—one embodiment employs a Least Recently Used (LRU) strategy to update the pre-computation table. The LRU algorithm is a replacement algorithm that prioritizes eliminating items that have not been used for the longest time, thus ensuring that the table contains only the most representative and frequently used point sets. In this way, the value of the pre-computation table can be maximized, keeping it in an optimal state to meet current computational needs.

[0048] Simultaneously, as the pre-computation table is updated, the point set relation database designed with the pre-computation table will also be checked and updated synchronously to ensure that all point sets that depend on the pre-computation table can be correctly mapped to the latest point set, thus maintaining the accuracy and efficiency of the computation. Finally, in terms of data structure selection, the pre-computation table is designed to efficiently manage the points and their scalar relationships in the pre-computation table. For example, a hash table is used to store the scalar values ​​of the base points, ensuring an average lookup time of O(1), that is, regardless of the size of the dataset, the time required to find the scalar value of a point is constant. Through this strategy, the pre-computation table can not only significantly improve the computational efficiency of multi-scalar multiplication in elliptic curve cryptography, but also effectively manage storage resources, ensuring the security and reliability of the system.

[0049] 2. Signed Window Method

[0050] Combination Figure 4 As shown, in elliptic curve cryptography, the negation of a point exhibits a significant computational efficiency advantage compared to point addition or doubling, primarily due to its simplified mathematical requirements. Specifically, in elliptic curve cryptography, the negative of a point P, -P, typically refers to the point on the elliptic curve that is symmetric to P about the x-axis. In most mathematical representations of elliptic curves, calculating the negative of a point is a very simple operation, as it only involves changing the sign of the y-coordinate, without requiring complex modular arithmetic, multiplicative inverse calculations, or square root calculations. Therefore, in one embodiment, the ease of sign taking in elliptic curve cryptography reduces the computational complexity of multi-scalar multiplication, improving the efficiency of zero-knowledge proof generation.

[0051] In contrast, dot addition or dot doubling not only involves polynomial calculations but also often requires solving for multiplicative inverses, which is a time-consuming task in finite fields. Therefore, this invention introduces this into multiscalar multiplication and dot product calculations. Given the efficient nature of the negation operation, it can significantly reduce computational resource consumption and improve overall computational speed, providing an important performance optimization approach for elliptic curve cryptography. In the traditional Pippenger unsigned window method, the window value range is [0, 2]. c-1 This could result in each window potentially needing to process up to 2 [units of data / processing]. c There are several different values. However, with the introduction of a signed window, the range of window values ​​becomes [-2]. c-1 ,2 c-1 -1]. This not only narrows the absolute range of window values, but also allows the use of negative representations of points, i.e., the inversion of points, to replace some dot product operations, thereby reducing the number of window values ​​that need to be processed separately.

[0052] In one embodiment, the step of converting a scalar k to a signed sliding window code includes:

[0053] Step S21, determine the window size

[0054] For example, choose a window size c. The window size determines how many bits are in each window.

[0055] Step S2: Represent the scalar k in binary form to obtain a binary string.

[0056] For example, if k = 23, its binary form is 10111.

[0057] Step S3: Divide the binary string into windows.

[0058] The binary string is divided into several windows of length c bits. For example, for c=3, 10111 will be divided into 010 and 111. It should be understood that in order to form a complete window, in some cases, it is necessary to pad with 0s before the most significant bit.

[0059] Step S4: Convert the window value to a decimal number.

[0060] For example, 010 is converted to 2, and 111 is converted to 7.

[0061] Step S5, signed conversion

[0062] For each window value v, if v > 2 c-1 -1, then subtract 2 from v. c This makes it a signed number. For example, if c = 3, the range of window values ​​should be [-4, 3]. If the window value is 5 or larger, it is converted to an equivalent negative number. For example, 5 will be converted to -3 because 5 - 8 = -3.

[0063] Step S6, adjust subsequent windows

[0064] If the current window value changes from positive to negative (i.e., subtracts 2) c If the value of the next window is 1, then the value of the next window needs to be incremented by 1 to maintain the equivalence of scalar multiplication.

[0065] In elliptic curve arithmetic, point addition and point doubling are the most fundamental and costly operations. The signed window method, by allowing the use of negative points to reduce the absolute size of the window value, enables more frequent use of the negated form of points in multi-scalar multiplication (MSM), thus improving computational efficiency. This efficiency significantly reduces the number of complex point operations, lowers computational resource consumption, improves computational efficiency, and ensures that computational efficiency and correctness are maintained even with smaller window sizes.

[0066] Second, optimize the data transmission mechanism.

[0067] 1. Asynchronous data transmission mechanism

[0068] The core value of asynchronous data transfer lies in its ability to break down the inherent boundaries between data transfer and computation tasks, enabling both to be performed in parallel. Specifically, while data is being copied from the CPU to the GPU, the GPU does not stall; instead, it continues to process existing datasets and perform computational tasks. This mechanism not only significantly shortens GPU idle time but also greatly improves hardware resource utilization efficiency through the overlap of data transfer and computation.

[0069] To achieve this optimization in the data transmission portion of zero-knowledge proof generation, one embodiment proposes a point-set-based batch transmission strategy. The key to this strategy lies in meticulous performance evaluation and data management. First, the large dataset is divided into several smaller batches, the size of each batch being evaluated based on GPU performance. This ensures the GPU has sufficient workload after receiving data while avoiding waiting time during data transmission. The aim of this strategy is to keep the GPU constantly active, fully utilizing its computing power and avoiding performance waste due to data transmission.

[0070] Furthermore, in the data processing flow, after each batch of data is processed, the GPU immediately sends the results back to the CPU, rather than waiting until all data is processed before summarizing. This instant feedback mechanism allows the CPU to promptly reduce and integrate subtasks, preparing for the next computation in advance, further accelerating the entire computation process. Moreover, to address the storage requirements of large-scale datasets while reducing storage costs, this strategy also emphasizes effective memory management. Once the dataset or some of its elements are no longer involved in computation, the occupied memory space is immediately released, ensuring efficient resource utilization.

[0071] In summary, by implementing an asynchronous data transfer strategy, combined with batch processing and real-time feedback mechanisms for point sets, and dynamic memory management strategies, the efficiency of CPU and GPU collaboration can be significantly improved. This overlapping computation and data transfer method not only reduces GPU latency but also optimizes memory usage, providing strong technical support for processing large-scale datasets, especially demonstrating significant potential and advantages in computationally intensive tasks such as the generation and verification of zero-knowledge proofs (ZKP). Compared to existing zero-knowledge generation systems, and... Figure 1 To make a comparison, Figure 5 The CPU improved by 4 time blocks, and the GPU improved by 2 time blocks. Moreover, as the amount of data increases, the efficiency improvement of the CPU and GPU proposed in this invention will become more and more obvious.

[0072] 2. Zero-copy technology

[0073] Zero-copy technology refers to a series of methods and strategies designed to minimize or completely eliminate data copying operations during data transfer between different software layers or hardware components. By reducing the number of data copies, zero-copy technology can significantly improve system performance, reduce latency, and decrease CPU and memory bandwidth consumption, thereby improving overall system efficiency. In zero-knowledge proofs involving multi-scalar multiplication, efficient data transfer between the CPU and GPU is a key factor in improving overall system performance. Traditionally, data transfer from CPU memory to GPU memory requires explicit copying operations, which not only increases the CPU load but also leads to significant latency and bandwidth consumption on large datasets. To address these issues, this invention introduces zero-copy technology while implementing a multi-batch asynchronous transfer mechanism.

[0074] Zero-copy technology is an asynchronous memory mapping method that directly maps fixed (non-pageable) host memory to GPU memory and implicitly transfers it to the GPU. This technology allows GPU threads to directly access host memory. When a GPU thread reads a variable mapped to the host, it submits a PCIe read transaction, and the host returns the data via the PCIe bus. The core principle of zero-copy technology is to reduce or eliminate the number of times data is copied between different memory regions, especially during data transfer between the CPU and GPU. In traditional data transfer, data typically needs to be copied from host memory to the kernel buffer and then from the kernel buffer to the GPU's device memory. This series of copying operations consumes a significant amount of CPU cycles and memory bandwidth. In contrast, zero-copy technology allows data to be transferred directly from host memory to GPU device memory without intermediate copying steps, thus significantly reducing CPU intervention and data transfer latency.

[0075] In traditional CUDA programming, data must be explicitly copied from host memory to the GPU's device memory using APIs such as cudaMemcpy. This process not only adds latency but also consumes CPU resources. In contrast, ... Figure 6As shown, this invention implements the CUDA Unified Virtual Addressing (UVA) feature in a CUDA environment to achieve a zero-copy effect. After implementing UVA, the CPU and GPU share a unified virtual address space. This means that both the CPU and GPU can use the same virtual address to access data without needing to know which physical memory region (CPU memory or GPU memory) the data is actually stored in. UVA allows the GPU to directly access host memory without explicitly copying data to GPU device memory. This simplifies data management and accelerates data transfer.

[0076] In summary, this invention significantly improves the speed and efficiency of ZKP generation through the synergistic effect of multiple technologies, while optimizing resource utilization, providing strong support for zero-knowledge proof technology in high-performance computing environments. Compared with existing technologies, the advantages of this invention are mainly reflected in the following aspects:

[0077] 1) This invention introduces an innovative preprocessing mechanism. By utilizing the CPU to pre-execute key computational tasks, this mechanism constructs an efficient computational framework, significantly shortening the ZKP generation time, especially when processing large-scale datasets. For example, the shared pre-computation table design enables efficient utilization of computing resources. By caching intermediate data for complex operations, redundant computations are avoided, reducing computation time and energy consumption when processing large-scale datasets or highly complex algorithms, particularly in multi-scalar multiplication. Furthermore, taking advantage of the low cost of elliptic curve inversion, a signed window technique is designed for multi-scalar multiplication. By expanding the sign of operands, the number of dot-matrix operations is reduced, lowering the complexity of large-number multiplication in elliptic curve cryptography. This signed sliding window technique, through sign expansion and optimized operand processing, reduces the number of dot-matrix operations required for large-number multiplication in elliptic curve cryptography, directly accelerating the zero-knowledge proof generation process.

[0078] 2) This invention provides an optimization scheme for the proof generation speed of zero-knowledge proof systems. It does not require refactoring the original proof generation logic but focuses on optimizing the communication efficiency between heterogeneous computing platforms. By refining the data transmission mechanism between the CPU and GPU, it effectively reduces generation latency and significantly improves system performance. For example, by improving the transmission method between systems and using zero-copy transmission technology, a faster and more resource-efficient data exchange process is achieved during data processing and transmission. This zero-copy transmission technology optimizes the data processing and transmission process, significantly reducing the CPU's processing burden and memory bandwidth consumption, and greatly shortening data transmission latency, thereby accelerating data processing and significantly improving overall system performance. Furthermore, by improving the data transmission method between heterogeneous architectures and implementing a batch transmission strategy, the incremental delivery of point sets and scalar sets to the GPU is achieved, avoiding GPU idle waiting periods and ensuring continuous utilization of GPU resources, thus significantly improving resource utilization and overall efficiency in the zero-knowledge proof generation process. This design not only significantly improves GPU utilization but also greatly optimizes overall computational efficiency. Especially when processing large-scale datasets, this incremental delivery mechanism drastically reduces waiting time, promotes continuous and maximized resource utilization, and thus achieves a leap in system performance. This phased, decoupled data transfer strategy enables the CPU and GPU to work collaboratively, rather than waiting alternately, thereby ensuring continuous utilization of GPU resources.

[0079] 3) This invention has undergone multiple simulation tests, and experiments have proven that it can meet the expected design specifications. For example, by utilizing the parallel computing capabilities of the CPU, a series of key computational tasks are pre-executed, and a pre-computation table is constructed. This allows the results of these pre-computational calculations to be directly referenced when generating zero-knowledge proofs, avoiding redundant calculations and greatly reducing the time required to generate proofs.

[0080] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0081] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0082] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0083] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, Python, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0084] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0085] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0086] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0088] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A CPU-GPU data processing and transmission optimization system for zero-knowledge proofs, used to perform multi-scalar multiplication operations based on elliptic curve cryptography to generate zero-knowledge proofs. The system includes a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU. The CPU is used to acquire and store the point set and scalar set involved in the multi-scalar multiplication operation, and communicates with the GPU using a set parallel data transmission mechanism. The GPU performs multi-scalar multiplication calculations based on the point set and the scalar set, and sends the calculation results back to the CPU.

2. The system according to claim 1, characterized in that, The GPU uses a shared pre-computation table to perform multi-scalar multiplication operations. This shared pre-computation table stores a series of multiples of a base point G and stores the scalar relationships between points in each point set and the base point G, where the base point G is the generator of all points in the point set.

3. The system according to claim 1, characterized in that, GPUs implement multi-scalar multiplication based on the bucket algorithm. In this bucket algorithm, the scalar k is converted into a signed sliding window in the following way: Determine the window size c, which limits the number of bits in each window; Represent the scalar k in binary form to form a binary string; The binary string is divided into multiple windows according to a length of c bits to obtain multiple window values; Convert each window value to a decimal number to obtain the decimal window value; For each decimal window value v, if v > 2 c-1 -1, then subtract 2 from v. c This makes it a signed number; If the value of the current window changes from positive to negative, the value of the next window is incremented by 1 to maintain the equivalence of scalar multiplication.

4. The system according to claim 2, characterized in that, The shared pre-calculation table is configured to be updated periodically according to the following steps: At the start of the calculation, a set amount of storage space is reserved in the shared pre-calculation table to store the pre-calculated point set; During the computation process, for the point set to be solved, the shared pre-computation table is checked to see if there is a corresponding calculated result. If it exists, the result is retrieved from the table. If it does not exist, the point set is recalculated and the calculation result is returned to the GPU. When a new point set result is generated, if the shared pre-computation table still has enough remaining space, the newly generated point set result is inserted into the table. When the space of the shared pre-computation table is insufficient, the stored content in the table is updated using the set update strategy.

5. The system according to claim 4, characterized in that, The update strategy adopts the least recently used strategy to prioritize the elimination of items that have not been used for the longest time.

6. The system according to claim 1, characterized in that, The parallel data transmission mechanism is based on a point-set batch transmission strategy, including: The point set stored in the CPU is divided into several batches according to the performance of the GPU and then transferred to the GPU in batches. After the GPU obtains the calculation results for each batch, it immediately sends the calculation results of that batch back to the CPU and releases the memory space occupied by elements that are no longer participating in the calculation.

7. The system according to claim 1, characterized in that, During multiscalar multiplication, the CPU and GPU share a unified virtual address space to enable data transfer between the CPU and GPU through zero-copy technology.

8. The system according to claim 1, characterized in that, In the shared pre-computation table, a hash table is used to store the scalar value of the base point G, and for points in the point set, only the x-coordinate of the point is stored.

9. A CPU-GPU data processing and transmission optimization method for zero-knowledge proofs, comprising the following steps: The point set and scalar set involved in the multi-scalar multiplication operation are stored in the CPU. This multi-scalar multiplication operation is based on elliptic curve cryptography and is used to generate zero-knowledge proofs. The system utilizes a set parallel data transfer mechanism to transfer data between the CPU and GPU, thereby controlling the GPU to perform multi-scalar multiplication calculations based on the point set and the scalar set, and then sending the calculation results back to the CPU.

10. A computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the steps of the method according to claim 9.

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