Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a first substrate; forming a compound semiconductor layer on the first substrate; forming an active layer on the compound semiconductor layer; bonding a second substrate on the surface of the active layer; an etching process is adopted to remove the compound semiconductor layer and the first substrate so as to expose the active layer, and the etching selection ratio of the active layer to the compound semiconductor layer is larger than that of the active layer to the first substrate; and forming a metal wiring layer on the surface of the active layer. According to the semiconductor structure preparation method, the stress damage to the wafer in the wafer thinning process can be reduced, so that the product yield can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower preparation cost, and higher capacity density, and has a wide range of applications. As the demand for storage continues to rise, the integration of its devices needs to be further improved.

[0003] Currently, WOW (Wafer on wafer) technology has been proposed to improve device integration. However, WOW technology usually requires a grinding process to thin the wafer. During the wafer grinding process, strong stress can easily cause the wafer to warp, resulting in a reduction in product yield. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a first substrate; forming a compound semiconductor layer on the first substrate; forming an active layer on the compound semiconductor layer; bonding a second substrate to the surface of the active layer; removing the compound semiconductor layer and the first substrate using an etching process to expose the active layer, wherein an etching selectivity ratio between the active layer and the compound semiconductor layer is greater than an etching selectivity ratio between the active layer and the first substrate; and forming a metal wiring layer on the surface of the active layer.

[0005] In some embodiments, an active layer is formed on the compound semiconductor layer, including: forming the active layer on the compound semiconductor layer using an epitaxial growth process; forming an isolation groove, wherein the isolation groove penetrates the compound semiconductor layer and the active layer and exposes the first substrate; and forming an isolation structure in the isolation groove, wherein the isolation structure isolates the active layer into multiple active pillars.

[0006] In some embodiments, an etching process is used to remove the compound semiconductor layer and the first substrate, including: flipping the first substrate; performing a planarization process to remove a portion of the first substrate and expose the isolation structure; and using an etching process to remove the first substrate and the compound semiconductor layer to expose the plurality of active pillars.

[0007] In some embodiments, forming a metal wiring layer on the active layer includes: forming a metal wiring layer on the surfaces of the plurality of active pillars, the metal wiring layer filling between the isolation structures, and the top surface of the metal wiring layer being flush with the top surface of the isolation structure.

[0008] In some embodiments, the active layer includes a storage area and a peripheral area, and the multiple active pillars are formed in the storage area; the first substrate and the compound semiconductor layer are removed by an etching process, including: forming a patterned mask layer, the patterned mask layer covers the first substrate above the peripheral area and exposes the first substrate above the storage area; removing the first substrate and the compound semiconductor layer above the storage area; removing the patterned mask layer.

[0009] In some embodiments, an etching process is used to remove the compound semiconductor layer and the first substrate, including: patterning the first substrate to form an etching opening, wherein the etching opening exposes the compound semiconductor layer; and using a wet etching process to remove the compound semiconductor layer along the etching opening to peel off the first substrate.

[0010] In some embodiments, forming a compound semiconductor layer on the first substrate includes: forming the compound semiconductor layer on the first substrate using an epitaxial growth process, wherein a material of the first substrate includes silicon, and a material of the compound semiconductor layer includes silicon germanium.

[0011] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a compound semiconductor layer; forming an active layer on the compound semiconductor layer using an epitaxial growth process; forming a device structure in the active layer; bonding a second substrate to the surface of the active layer; removing the compound semiconductor layer using an etching process, an etching selectivity ratio between the device structure and the compound semiconductor layer being greater than an etching selectivity ratio between the device structure and the second substrate; and forming a metal wiring layer on the active layer.

[0012] According to a third aspect of an embodiment of the present disclosure, a semiconductor structure is provided, comprising: an active layer, the active layer comprising a storage area and a peripheral area; a compound semiconductor layer, the compound semiconductor layer being located above the active layer in the peripheral area; a first substrate, the first substrate being located above the compound semiconductor layer, an etching selectivity ratio between the active layer and the compound semiconductor layer being greater than an etching selectivity ratio between the active layer and the first substrate; and a metal wiring layer, the metal wiring layer being located above the active layer in the storage area.

[0013] In some embodiments, the active layer includes a plurality of active pillars arranged in an array, and the semiconductor structure further includes: an isolation structure formed between the plurality of active pillars, and the top surface of the metal wiring layer is flush with the top surface of the isolation structure.

[0014] In the embodiments of the present disclosure, a compound semiconductor layer is formed on a first substrate, an active layer is formed on the compound semiconductor layer, and then a second substrate is bonded to the surface of the active layer. An etching process is used to remove the compound semiconductor layer and the first substrate to expose the active layer. The etching selectivity ratio of the active layer to the compound semiconductor layer is greater than the etching selectivity ratio of the active layer to the first substrate. This can reduce etching damage to the active layer and avoid using a grinding process to remove the first substrate, thereby reducing stress damage to the wafer during wafer thinning, thereby improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0016] Figure 2 is a flow chart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure;

[0017] Figures 3a to 3j is a schematic diagram of a preparation process of a semiconductor structure according to some embodiments of the present disclosure;

[0018] Figures 4a to 4f is a schematic diagram of a preparation process of another semiconductor structure according to some embodiments of the present disclosure;

[0019] Figure 5a to Figure 5c It is a schematic diagram of a preparation process of another semiconductor structure according to some embodiments of the present disclosure.

[0020] Description of reference numerals:

[0021] 10 / 20 / 30: semiconductor structure; 11: bit line; 12: active pillar; 13: word line; 14: capacitor; 110 / 210: first substrate; 120 / 220 / 320: compound semiconductor layer; 130 / 230 / 330: active layer; 140: isolation structure; 141: first isolation substructure; 142: second isolation substructure; 150 / 250 / 350: second substrate; 160: patterned mask layer; 170 / 270 / 370: metal wiring layer; 170': metal wiring pattern; 170a: metal connection portion; 170b metal protrusion; 171: metal silicide layer; 172 metal barrier layer; T1: isolation groove; T2: wiring groove; HL1; first hole; HL2: second hole; KS1: etching opening; KS2: etching gap; M: storage area; P: peripheral area; X: first direction; Y: second direction; Z: third direction. DETAILED DESCRIPTION

[0022] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0023] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0024] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0025] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0026] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0027] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0028] Figure 1 1 is a schematic diagram of a semiconductor structure 10 according to an exemplary embodiment, wherein the semiconductor structure 10 includes a plurality of active pillars 12 and capacitors 14 arranged in an array, a plurality of word lines 13, and a plurality of bit lines 11. One end of the active pillar 12 is connected to the bit line 11, and the other end is connected to the capacitor structure 14, for example, the bottom end of the active pillar 12 is connected to the bit line 11, and the top end of the active pillar 12 is connected to the capacitor structure 14. The word line 13 at least partially covers the side wall of the active pillar 12, and the part of the active pillar 12 serves as a channel. Each bit line 11 extends along a first direction X and is connected to a plurality of active pillars 12 arranged along the first direction X, and each word line 13 extends along a second direction Y and is connected to a plurality of active pillars 12 arranged along the second direction Y, and the active pillars 12 and the capacitors 14 correspond to each other one by one and are stacked along a third direction Z. It can be understood that in this example, the third direction Z is the extension direction of the active pillar 12, and the first direction X and the second direction Y can be perpendicular to the third direction Z, respectively. The transistor formed by the active pillar 12 and the word line 13 is a vertical channel transistor (VCT), and the word line 13 controls the turning on or off of the transistor.

[0029] A vertical channel transistor (VCT) refers to a transistor structure in which an active column extends from a substrate roughly in a direction perpendicular to the substrate plane. Taking a dynamic random access memory as an example, the use of a vertical channel transistor can improve the integration of the dynamic random access memory. In the preparation process of a semiconductor device containing a VCT, it is necessary to form a capacitor 14 and a bit line 11 at both ends of the active column 12. If a semiconductor device containing a VCT is prepared using WOW technology, the active column 12 and the capacitor 14 can be made on the front side of the wafer, and then the back side of the wafer is thinned to form a bit line 11 connecting the active column 12. If a grinding process is used to thin the back side of the wafer, it is difficult to control the grinding thickness. The existing grinding process is difficult to accurately thin the wafer to less than 10 microns, and during the wafer grinding process, strong application is prone to cause wafer warping, which will damage the device structures such as the active column 12 and the capacitor 14 formed on the front side of the wafer, thereby affecting the product yield.

[0030] Based on this, in order to solve the above problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure.

[0031] Figure 2 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present disclosure; Figures 3a to 3j is a schematic diagram of a preparation process of a semiconductor structure according to some embodiments of the present disclosure; Figures 4a to 4f is a schematic diagram of a preparation process of another semiconductor structure according to some embodiments of the present disclosure; Figure 5a to Figure 5c FIG. 1 is a schematic diagram of another semiconductor structure preparation process according to some embodiments of the present disclosure. Figure 2 , Figures 3a to 3j , Figures 4a to 4e and Figure 5a to Figure 5c The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0032] It should be noted that the first direction, the second direction, and the third direction used in the present disclosure are respectively represented as X, Y, and Z, the first direction X and the second direction Y are parallel to the plane where the first substrate 100 is located, and the third direction Z is perpendicular to the plane where the first substrate 100 is located. The first direction X and the second direction Y intersect, and the angle between the first direction X and the second direction Y includes an acute angle, a right angle, or an obtuse angle, which will not be repeated hereafter. In some embodiments, the angle between the first direction X and the second direction Y is a right angle, that is, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other.

[0033] Reference Figure 2 As shown, the method for preparing a semiconductor structure provided by the present disclosure comprises at least the following steps:

[0034] S21: providing a first substrate;

[0035] S22: forming a compound semiconductor layer on the first substrate;

[0036] S23: forming an active layer on the compound semiconductor layer;

[0037] S24: bonding a second substrate on the surface of the active layer;

[0038] S25: removing the compound semiconductor layer and the first substrate by an etching process to expose the active layer, wherein an etching selectivity ratio between the active layer and the compound semiconductor layer is greater than an etching selectivity ratio between the active layer and the first substrate;

[0039] S26: forming a metal wiring layer on the surface of the active layer.

[0040] It should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0041] In the embodiments of the present disclosure, a compound semiconductor layer is formed on a first substrate, an active layer is formed on the compound semiconductor layer, and then a second substrate is bonded to the surface of the active layer. An etching process is used to remove the compound semiconductor layer and the first substrate to expose the active layer. The etching selectivity ratio of the active layer to the compound semiconductor layer is greater than the etching selectivity ratio of the active layer to the first substrate. This can reduce etching damage to the active layer and avoid using a grinding process to remove the first substrate, thereby reducing stress damage to the wafer during wafer thinning, thereby improving product yield.

[0042] Reference Figures 3a to 3j As shown, some embodiments of the present disclosure provide a schematic diagram of a preparation process of a semiconductor structure 20. Figure 3aAs shown, a first substrate 110 is provided, and the material of the first substrate 110 includes a semiconductor material, for example, the first substrate 110 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, etc. A compound semiconductor layer 120 is formed on the first substrate 110, and the material of the compound semiconductor layer 120 may include a semiconductor material different from the first substrate 110, such as silicon germanium (SiGe). An active layer 130 is formed on the compound semiconductor layer 120, and the material of the active layer 130 may be a single semiconductor material (for example, single crystal silicon, polycrystalline silicon, etc.) or an oxide semiconductor material (for example, zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO") and one or more of other similar materials). The compound semiconductor layer 120 and the active layer 130 may be formed by an epitaxial growth process or a deposition process. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).

[0043] In some embodiments, an epitaxial growth process may be used to form an active layer 130 on the compound semiconductor layer 120. The thickness of the active layer 130 is less than the thickness of the first substrate 110 and greater than the thickness of the compound semiconductor layer 120. For example, the thickness of the first substrate 110 is 200 μm-700 μm, the thickness of the compound semiconductor layer 120 is 5 nm-50 nm, and the thickness of the active layer 130 ranges from 100 nm to 1000 nm, for example, 150 nm to 250 nm. Taking epitaxial growth of a silicon germanium layer on a silicon wafer as the compound semiconductor layer 120 as an example, the concentration of germanium doped in the silicon germanium layer may be 1%-99%, for example, 10%-30%. By forming the active layer 130 through an epitaxial growth process, the thickness of the active layer 130 may be precisely controlled, a thinner thickness of the active layer 130 may be achieved, and the integration of the semiconductor structure may be effectively improved.

[0044] In some embodiments, reference Figure 3b and 3cAs shown, an isolation groove T1 is formed in the stacked structure formed by the first substrate 110, the compound semiconductor layer 120 and the active layer 130, and an insulating material (for example, a low dielectric constant material such as silicon oxide, silicon nitride or silicon oxynitride) is filled in the isolation groove T1 to form an isolation structure 140. The isolation groove T1 penetrates the compound semiconductor layer 120 and the active layer 130 and exposes the first substrate 100. The depth of the isolation groove T1 is greater than the sum of the thicknesses of the compound semiconductor layer 120 and the active layer 130, the depth of the isolation groove T1 is less than the sum of the thicknesses of the compound semiconductor layer 120, the active layer 130 and the first substrate 110, and the bottom surface of the isolation groove T1 is located in the first substrate 110. The ratio of the thickness of the first substrate 110 below the isolation groove T1 to the original thickness of the first substrate 110 is 0.1-0.5. By setting the isolation groove T1 with a specific depth, the integrity of the first substrate 110 can be ensured, the first substrate 110 can be prevented from being broken, and the thickness of the first substrate 110 that needs to be removed later can be reduced.

[0045] In some embodiments, the material of the isolation structure 140 may be silicon oxide. The formation process of the insulating material includes a thin film deposition process, for example, at least one of a physical vapor deposition process, a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, and an atomic layer deposition process. The isolation structure 140 may include a plurality of first isolation substructures 141 extending along the first direction X and arranged in parallel along the second direction Y, and a plurality of second isolation substructures 142 extending along the second direction Y and arranged in parallel along the first direction X. The plurality of first isolation substructures 141 and the plurality of second isolation substructures 142 are parallel to the plane where the first substrate 110 is located, and intersect or are perpendicular to each other. The isolation structure 140 composed of the plurality of first isolation substructures 141 and the plurality of second isolation substructures 142 isolates the active layer 130 into a plurality of active pillars 131, and the plurality of active pillars 131 are arranged in an array along the first direction X and the second direction Y. The sizes of the first isolation substructure 141 and the second isolation substructure 142 along the third direction Z may be the same or different.

[0046] In some embodiments, after forming a plurality of active pillars 131, the active pillars 131 are further doped to form source and drain electrodes at both ends of the active pillars and a channel region in the middle of the active pillars. After forming a plurality of active pillars 131, word lines covering the sidewalls of the channel regions of the active pillars 131 are also formed. For example, the word lines may extend along the second direction Y and be arranged in parallel along the first direction X.

[0047] Reference Figure 3dAs shown, the second substrate 150 is bonded to the surface of the active layer 130, and the material of the second substrate 150 includes a semiconductor material, for example, a single semiconductor material (for example, silicon (Si) or germanium (Ge), etc.), a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art. The material of the second substrate 150 can be the same as that of the first substrate 110, for example, the materials of the first substrate 110 and the second substrate 150 are both single crystal silicon, and the first substrate 110 and the second substrate 150 are both silicon wafers. The surface of the active layer 130 can be bonded to the surface of the second substrate 150 by a wafer bonding process. For example, the surface of the active layer 130 may be bonded to the surface of the second substrate 150 by a fusion bonding process, and the bonding temperature range is 200° C. to 350° C., preferably 220° C. to 250° C., which can reduce the impact of high temperature on the active layer 130 .

[0048] In some embodiments, after forming a plurality of active pillars 131, a capacitor array layer is further formed above the active layer 130, and the capacitor array layer includes capacitors arranged one-to-one corresponding to the active pillars 131. A second substrate 150 may also be bonded to the surface of the capacitor array layer. It is understood that the second substrate 130 is a bearing structure for the active layer 130 and the capacitor array layer, and is used to bear and protect the active layer 130 and the capacitor array layer in subsequent processes.

[0049] In some embodiments, the first substrate 110 has a first surface and a second surface opposite to each other along the third direction Z. After the compound semiconductor layer 120 is formed on the first surface of the first substrate 110 and the active layer 130 is formed on the compound semiconductor layer 120, Figure 3e and Figure 3f As shown, the stacked structure formed by the first substrate 110, the compound semiconductor layer 120 and the active layer 130 is turned over to expose the second surface of the first substrate 110. A planarization process is performed on the second surface of the first substrate 110 to remove a portion of the first substrate 110. The planarization process may include a chemical mechanical polishing process, etc. It can be understood that the orientation of the second surface of the first substrate 110 in the figure is only for convenience of illustration. In the actual planarization process, the second surface of the first substrate 110 may face the polishing pad in the chemical mechanical polishing equipment.

[0050] In some embodiments, reference Figure 3f and Figure 3gAs shown, by performing a planarization process, a portion of the thickness of the first substrate 110 is removed to expose the isolation structure in the first substrate 110. After the planarization process is performed, the semiconductor structure 20 can also be flipped to face the second surface of the first substrate 110 upward along the third direction Z. At this time, the isolation structure 140 can separate the remaining first substrate 110 into a plurality of first graphics 111 arranged in an array, and the isolation structure 140 also separates at least part of the compound semiconductor layer 120 into a plurality of second graphics 121 arranged in an array. The ratio of the thickness of the removed portion of the first substrate 110 to the original thickness of the first substrate 110 is 0.1-0.5, and the ratio of the thickness of the first graphics 111 along the third direction Z to the original thickness of the first substrate 110 is 0.5-0.9. The first graphics 111 and the second graphics 121 correspond to each other and are stacked on each active column. Since only a portion of the thickness of the first substrate 110 needs to be removed by the planarization process, the grinding process time can be effectively reduced, and the stress effect and structural damage of the grinding process on the semiconductor structure 20 can be reduced.

[0051] Reference Figure 3g and 3h As shown, an etching process is used to remove at least a portion of the compound semiconductor layer 120 and at least a portion of the first substrate 110 to expose the active layer 130, and the etching selectivity ratio of the active layer 130 to the compound semiconductor layer 120 is greater than the etching selectivity ratio of the active layer 130 to the first substrate 110. A first hole HL1 is obtained by removing a portion of the first substrate 110 through a first etching process, and the exposed compound semiconductor layer 120 is removed along the first hole HL1 to obtain a second hole HL2, and the bottom of the second hole HL2 exposes the surface of a plurality of active pillars 131 of the active layer 130. The etching process includes a dry etching process or a wet etching process, and the dry etching includes at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP) or high concentration plasma etching (HDP). Since the isolation structure 140 and the first substrate 110 are made of different materials and have a relatively large etching selectivity, it is not necessary to form an additional etching protection structure above the isolation structure 140 when forming the first hole HL1; since the isolation structure 140 and the compound semiconductor layer 120 are made of different materials and have a relatively large etching selectivity, it is not necessary to form an additional etching protection structure above the isolation structure 140 when forming the second hole HL2. Therefore, by forming the isolation structure 140 in advance, the second hole HL2 exposing the active pillar 131 can be formed by self-alignment.

[0052] In some embodiments, reference Figure 3g and 3hAs shown, the active layer 130 includes a storage area M and a peripheral area P, an isolation structure 140 is formed in the storage area M, a plurality of active pillars 131 are formed in the storage area M, and an etching process is used to remove the first substrate 110 and the compound semiconductor layer 120, including: forming a patterned mask layer 160, the patterned mask layer 160 covers the first substrate 110 above the peripheral area P and exposes the first substrate 110 above the storage area M; removing the first substrate 100 and the compound semiconductor layer 120 above the storage area M by an etching process; and removing the patterned mask layer 160. By removing only the first pattern 111 and the second pattern 121 located above the storage area M, the first substrate 100 and the compound semiconductor layer 120 located in the peripheral area P are retained, so that the active layer 130 located in the peripheral area P can be protected in subsequent processes.

[0053] In some embodiments, a first hole HL1 is obtained by removing a plurality of first patterns 111 through a first etching process, and a second hole HL2 is obtained by removing a plurality of exposed second patterns 121 along the first hole HL1. The bottom of the second hole HL2 exposes the surface of a plurality of active pillars 131 of the active layer 130.

[0054] For example, taking the case where the materials of the first substrate 110 and the active layer 130 are silicon and the material of the compound semiconductor layer 120 is silicon germanium, the etching selectivity of silicon and silicon germanium can reach 150-300 by using an etching solution such as hydrofluoric acid or acetic acid to remove silicon germanium. Therefore, after removing the first substrate 110, the active layer 130 is protected by the compound semiconductor layer 120, and then the exposed compound semiconductor layer 120 is removed along the first hole HL1, which can effectively reduce the damage of the etching process to the active layer 130.

[0055] In some embodiments, a metal wiring layer 170 is formed on the active layer 130 , including: forming a metal wiring layer 170 on the surfaces of multiple active pillars 131 , the metal wiring layer 170 is filled between the isolation structures 140 , and the top surface of the metal wiring layer 170 is flush with the top surface of the isolation structure 140 .

[0056] In some embodiments, reference Figure 3j As shown, the metal wiring layer 170 may include a plurality of metal wiring patterns 170' extending along the first direction X and arranged in parallel along the second direction Y. Figure 3iAs shown, a wiring trench T2 extending along the first direction X can be formed by removing part of the second sub-isolation layer 142, that is, removing all or part of the second sub-isolation layer 142 between the second holes HL2 along the first direction X. It can be understood that when all the second sub-isolation layers 142 between the second holes HL2 along the first direction X are removed, the projection morphology of the formed wiring trench T2 along the second direction Y is rectangular; when part of the second sub-isolation layer 142 between the second holes HL2 along the first direction X is removed, the projection morphology of the formed wiring trench T2 along the second direction Y is comb-shaped. A conductive material is deposited in the wiring trench T2, and the conductive material can cover the top surface of the isolation structure 140. Then, a part of the conductive material is etched back to form a metal wiring layer 170, and the top surface of the metal wiring layer 170 is flush with the top surface of the isolation structure 140. The conductive material refers to one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co-based alloys, Ni-based alloys, Al-based alloys, Cu-based alloys, Ti-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon).

[0057] In some embodiments, reference Figure 3i As shown, when forming the isolation structure 140, the first isolation substructure 141 and the second isolation substructure 142 can be set to have different sizes along the third direction Z. For example, the size of the first isolation substructure 141 along the third direction Z is larger than the size of the second isolation substructure 142 along the third direction Z. Figure 3c As shown, the bottom surface of the first isolation substructure 141 is lower than the bottom surface of the second isolation substructure 142 . After the semiconductor structure 20 is turned over, the top surface of the first isolation substructure 141 is higher than the top surface of the second isolation substructure 142 .

[0058] In some embodiments, the height difference between the first spacer structure 141 and the second spacer structure 142 along the third direction Z is less than or equal to the sum of the thicknesses of the first substrate 110 and the compound semiconductor layer 120 along the third direction Z.

[0059] After removing the first substrate 110 and the compound semiconductor layer 120, the top surface of the isolation structure 140 between the active pillars 131 arranged along the first direction X is lower than the isolation structure 140 between the active pillars 131 arranged along the second direction Y. Therefore, before depositing the conductive material to form the metal wiring layer 170, it is not necessary to remove part of the second sub-isolation layer 142. By utilizing the height difference between the first isolation substructure 141 and the second isolation substructure 142, the space between the first isolation substructure 141 and the second isolation substructure 142 is used as the wiring groove T2 to form a metal wiring pattern 170' electrically connected to the plurality of active pillars 131 arranged along the first direction X. The metal wiring pattern 170' may include a plurality of metal protrusions 170b facing the active pillars 131, and a metal connection portion 170a connecting the plurality of metal protrusions 170b arranged along the first direction X. It can be understood that the thickness of the metal connection portion 170a along the third direction Z is the same as the height difference between the first isolation substructure 141 and the second isolation substructure 142. When the height difference between the first spacer structure 141 and the second spacer structure 142 along the third direction Z is equal to the sum of the thicknesses of the first substrate 110 and the compound semiconductor layer 120 along the third direction Z, the metal wiring pattern 170 ′ may include only the metal connection portion 170 a without the metal protrusion 170 b .

[0060] In the method for preparing the semiconductor structure provided by the present disclosure, by forming the isolation structure 140 deep into the first substrate 110 in advance, after the semiconductor structure 20 is turned over, the first substrate 110 and the compound semiconductor layer 120 are removed, the isolation structure 140 protrudes from the active pillar 131 of the active layer 130 along the third direction Z, so that the metal wiring layer 170 in contact with the active pillar 131 can be formed based on the wiring groove T2 defined by the isolation structure 140, and the multiple metal wiring patterns 170' included in the metal wiring layer 170 can be aligned with the active pillar 131 with zero deviation, and the multiple metal wiring patterns 170' can be self-aligned and isolated from each other. In addition, by setting the metal wiring layer 170 flush with the top surface of the isolation structure 140, the thickness and width of the metal wiring layer can be accurately controlled.

[0061] In other embodiments, the extension direction of the metal wiring pattern 170' in the metal wiring layer 170 may be set based on actual needs. For example, the metal wiring layer 170 may also include a plurality of metal wiring patterns 170' extending along the second direction Y and arranged in parallel along the first direction X. The extension direction of the metal wiring pattern 170' in the metal wiring layer 170 may intersect with the extension direction of the word line formed in the active layer.

[0062] In some embodiments, after forming the second hole HL2 or after forming the wiring trench T2, a metal silicide layer 171 and / or a metal barrier layer 172 may be formed on the exposed surfaces of the plurality of active pillars 131, and then a metal wiring layer 170 may be formed on the metal silicide layer 171 and / or the metal barrier layer 171. The metal silicide layer 171 may include cobalt silicide, nickel silicide, titanium silicide, etc. The metal barrier layer 172 may include titanium nitride, titanium, tantalum nitride, tantalum, etc. By forming the metal silicide layer 171, the contact resistance between the active pillar 131 and the metal wiring layer 170 may be reduced, and by forming the metal barrier layer 172, the situation where the metal elements in the metal wiring layer 170 diffuse and contaminate the active pillar 131 may be avoided.

[0063] Reference Figures 4a to 4f As shown, some embodiments of the present disclosure provide a schematic diagram of a preparation process of a semiconductor structure 30. Figure 4a As shown, a first substrate 210 is provided, the first substrate 210 has a first surface and a second surface opposite to each other along a third direction Z, a compound semiconductor layer 220 is formed on the first surface of the first substrate 210, and an active layer 230 is formed on the compound semiconductor layer 220. Figure 4b As shown, the second substrate 250 is bonded to the surface of the active layer 230. Figure 4c , the semiconductor structure 30 is turned over to face the second surface of the first substrate 210 upward along the third direction Z. Figure 4d and Figure 4e As shown, the compound semiconductor layer 220 and the first substrate 210 are removed by an etching process to expose the active layer 230, and the etching selectivity ratio of the active layer 230 to the compound semiconductor layer 220 is greater than the etching selectivity ratio of the active layer 230 to the first substrate 210. Figure 4f As shown, after peeling off the first substrate 210, the surface of the active layer 230 is exposed, so that a metal wiring layer 270 can be formed on the exposed surface of the active layer 230. Before forming the metal wiring layer 270, the exposed surface of the active layer 230 can also be cleaned, metallized, etc. to reduce the contact resistance between the active layer 230 and the metal wiring layer 270.

[0064] In some embodiments, reference Figure 4dAs shown, the compound semiconductor layer 220 and the first substrate 210 are removed by an etching process, including: patterning the first substrate 210 to form an etching opening KS1, the etching opening KS1 exposing the compound semiconductor layer 220; removing the compound semiconductor layer 220 along the etching opening KS1 by a wet etching process to form an etching gap KS2, so as to peel the first substrate 230 from the active layer 230. After the second surface of the first substrate 210 is oriented upward along the third direction Z, the first substrate 210 can be patterned along the second surface of the first substrate 210, for example, a dry etching process is used to remove a portion of the first substrate 210 to form the etching opening KS1.

[0065] In some embodiments, a plurality of etching openings KS1 arranged at intervals may be formed to increase the contact area between the etching solution and the compound semiconductor layer 220. The projection shape of the etching opening KS1 in the third direction Z may be rectangular, trapezoidal, circular, annular, or the like.

[0066] In some embodiments, the bottom surface of the etching opening KS1 is flush with the surface of the compound semiconductor layer 220. In other embodiments, the bottom surface of the etching opening KS1 is located between two opposite surfaces of the compound semiconductor layer 220 along the third direction Z, that is, the bottom sidewall of the etching opening KS1 also exposes the compound semiconductor layer 220, which can increase the contact area between the etching solution and the compound semiconductor layer 220 and improve the etching efficiency of the wet etching. In addition, when forming the etching opening KS1, since the compound semiconductor layer 220 covers the active layer 230, it is possible to avoid damaging the active layer in the process of forming the etching opening KS1.

[0067] Reference Figure 4e As shown, the etching opening KS1 penetrates the first substrate 210 and exposes the compound semiconductor layer 220, so that the wet etching solution can contact the compound semiconductor 220 along the etching opening KS1 to remove the compound semiconductor layer 220. Since the etching selectivity of the active layer 230 to the compound semiconductor layer 220 is greater than the etching selectivity of the active layer 230 to the first substrate 210, for example, taking the first substrate 210 and the active layer 230 as silicon, and the compound semiconductor layer 220 as silicon germanium, the etching selectivity of silicon to silicon germanium can reach 150-300 when using an etching solution such as hydrofluoric acid or acetic acid to remove silicon germanium. Therefore, when removing the compound semiconductor layer 220, the wet etching process with a high etching selectivity can effectively reduce the damage to the active layer 130.

[0068] In the preparation method of the semiconductor structure provided by the present invention, the first substrate 210 is peeled off by a dry etching process plus a wet etching process, thereby avoiding the grinding treatment of the first substrate 210, shortening the time for removing the first substrate 210, and efficiently transferring the active layer 230 from the first substrate 210 to the second substrate 250 and exposing the first surface of the first substrate 210, thereby avoiding the stress influence and structural damage of the grinding process on the semiconductor structure 30.

[0069] Reference Figure 5a to Figure 5c As shown, some embodiments of the present disclosure provide a schematic diagram of a preparation process of a semiconductor structure 40. The preparation method of the semiconductor structure 40 provided by the present disclosure includes at least the following steps: providing a compound semiconductor layer 320; forming an active layer 330 on the compound semiconductor layer 320 by using an epitaxial growth process; forming a device structure 340 in the active layer 330; bonding a second substrate 350 on the surface of the active layer 330; removing the compound semiconductor layer 320 by using an etching process, wherein the etching selectivity ratio of the active layer 330 to the compound semiconductor layer 320 is greater than the etching selectivity ratio of the active layer 330 to the second substrate 350; and forming a metal wiring layer 370 on the active layer 330.

[0070] The material of the compound semiconductor layer 320 includes a semiconductor material, for example, silicon germanium, a III-V compound semiconductor material (for example, gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), etc.), a II-VI compound semiconductor material (for example, zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), etc.), an organic semiconductor material or other semiconductor materials known in the art. The material of the active layer 330 can be a single semiconductor material (for example, single crystal silicon, polycrystalline silicon, etc.) or an oxide semiconductor material (for example, zinc tin oxide (ZnxSnyO, commonly known as "ZTO"), indium zinc oxide (InxZnyO, commonly known as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly known as "IGZO") and one or more of other similar materials). The material of the compound semiconductor 320 is different from that of the active layer 330, and the material of the compound semiconductor 320 and the material of the active layer 330 have an etching selectivity greater than 150. The material of the second substrate 350 can be the same as that of the active layer 330, for example, both are single crystal silicon.

[0071] In some embodiments, an epitaxial growth process may be used to form an active layer 330 on the compound semiconductor layer 320, and the thickness of the active layer 330 is less than the thickness of the compound semiconductor layer 320. For example, the compound semiconductor layer 320 is a silicon germanium wafer, the active layer 130 is a single crystal silicon layer, the thickness of the compound semiconductor layer 320 is 200 μm-700 μm, and the thickness of the active layer 130 is in the range of 150 nm-250 nm. Since the active layer 130 may have a relatively thin thickness, after the compound semiconductor layer 320 is removed by an etching process, it is not necessary to use a grinding process to thin the active layer 130.

[0072] In some embodiments, the active layer 130 includes a memory region M and a peripheral region P. The device structure 340 includes memory device structures in the memory region M, such as transistors and capacitors, and may also include peripheral device structures in the peripheral region P, such as sense amplifiers and word line drivers.

[0073] In some embodiments, the active layer 330 has a first surface and a second surface opposite to each other along a third direction Z, and the device structure 340 may be embedded in the active layer 330, that is, the device structure 340 is only formed on the first surface of the active layer 330 in the third direction Z. After removing the compound semiconductor layer 320 by an etching process to expose the second surface of the active layer 330, forming the metal wiring layer 370 on the active layer 330 includes: etching along the second surface of the active layer 330 to expose the device structure 340, and then forming the metal wiring layer 370 electrically connected to the device structure 340.

[0074] In some embodiments, the device structure 340 may also penetrate the active layer 330 . After the compound semiconductor layer 320 is removed by an etching process to expose the device structure 340 , a metal wiring layer 370 is formed on the device structure 340 .

[0075] In the preparation method of the semiconductor structure provided by the present disclosure, on the first hand, there is no need to provide a first substrate, but an active layer 330 is directly formed on the compound semiconductor layer 320, and then after the device structure 340 is formed on the active layer 330, the compound semiconductor layer 320 is directly removed by an etching process by utilizing the high etching selectivity ratio between the compound semiconductor layer 320 and the active layer 330, thereby avoiding the use of a grinding process, thereby reducing damage to the device structure 340 in the active layer 330, and effectively improving the product yield; on the second hand, the active layer 330 is formed on the compound semiconductor layer 320 by adopting an epitaxial growth process, so that the thickness of the active layer 330 can be accurately controlled, and a thinner thickness of the active layer 330 can be achieved, thereby reducing the size of the device structure 340 formed in the active layer 330, and effectively improving the integration of the semiconductor structure.

[0076] Based on the above-mentioned method for preparing the semiconductor structure, the embodiment of the present disclosure further provides a semiconductor structure 20. Figure 3j 3j is a schematic diagram of a semiconductor structure 20 according to an embodiment of the present disclosure. Referring to 3j, the semiconductor structure 20 includes: an active layer 130, the active layer 130 includes a storage area M and a peripheral area P; a compound semiconductor layer 120, the compound semiconductor layer 120 is located above the active layer 130 in the peripheral area P; a first substrate 110, the first substrate 110 is located above the compound semiconductor layer 120, and the etching selectivity ratio of the active layer 130 to the compound semiconductor layer 120 is greater than the etching selectivity ratio of the active layer to the first substrate 110; a metal wiring layer 170, the metal wiring layer 170 is located above the active layer 130 in the storage area M.

[0077] The storage region M is a region for forming a storage device structure, for example, a region for forming a vertical channel transistor, and is also used to form a bit line and a capacitor in the storage region M. The peripheral region P is a region for forming a peripheral device structure. The compound semiconductor layer 120 and the first substrate 110 located in the peripheral region P can protect the active layer 130 in the peripheral region P during the process of forming the storage device structure in the storage region M, and avoid etching damage to the active layer 130 by the etching process.

[0078] In the semiconductor structure provided by the present disclosure, the multiple metal wiring patterns 170' included in the metal wiring layer 170 are aligned with the active pillars 131 with zero deviation, which can increase the contact area between the metal wiring layer 170 and the active pillars 131 and avoid poor contact. In addition, the multiple metal wiring patterns 170' are self-aligned and isolated from each other through the isolation structure 140, which can reduce the coupling effect between adjacent metal wiring patterns 170'.

[0079] In some embodiments, the active layer 130 includes a plurality of active pillars 131 arranged in an array, and the semiconductor structure 20 further includes an isolation structure 140 formed between the plurality of active pillars 131 , and a top surface of the metal wiring layer 170 is flush with a top surface of the isolation structure 140 .

[0080] In some embodiments, reference Figure 3i As shown, the isolation structure 140 may include a plurality of first isolation substructures 141 extending along the first direction X and arranged in parallel along the second direction Y, and a plurality of second isolation substructures 142 extending along the second direction Y and arranged in parallel along the first direction X. The plurality of first isolation substructures 141 and the plurality of second isolation substructures 142 are parallel to the plane where the first substrate 110 is located, and intersect or are perpendicular to each other.

[0081] In some implementations, reference Figure 3jAs shown, the metal wiring layer 170 may include a plurality of metal wiring patterns 170 ′ extending along a first direction X and arranged in parallel along a second direction Y.

[0082] In some embodiments, the first isolation substructure 141 and the second isolation substructure 142 have different sizes along the third direction Z. For example, the size of the first isolation substructure 141 along the third direction Z is larger than the size of the second isolation substructure 142 along the third direction Z. The height difference between the first isolation substructure 141 and the second isolation substructure 142 along the third direction Z is less than or equal to the sum of the thicknesses of the first substrate 110 and the compound semiconductor layer 120 along the third direction Z.

[0083] In some embodiments, the metal wiring pattern 170 ′ may include a plurality of metal protrusions 170 b facing the active pillars 131 , and a metal connection portion 170 a connecting the plurality of metal protrusions 170 b arranged along the first direction X.

[0084] In some embodiments, in some embodiments, a metal silicide layer 171 and / or a metal barrier layer 172 are further included between the metal wiring pattern 170' and the active pillar 131, and the metal silicide layer 171 may include cobalt silicide, nickel silicide, titanium silicide, etc. The metal barrier layer 172 may include titanium nitride, titanium, tantalum nitride, tantalum, etc. By forming the metal silicide layer 171, the contact resistance between the active pillar 131 and the metal wiring layer 170 can be reduced, and by forming the metal barrier layer 172, the situation where the metal elements in the metal wiring layer 170 diffuse and contaminate the active pillar 131 can be avoided.

[0085] In some embodiments, the active layer 130 may be an epitaxial growth layer, and the formation process has been described above and will not be repeated here.

[0086] The various semiconductor structures shown in this specific embodiment can be used for electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by the following memories: dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), magnetic random access memory (MRAM) or resistive random access memory (RRAM).

[0087] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a first substrate; forming a compound semiconductor layer on the first substrate; forming an active layer on the compound semiconductor layer; Bonding a second substrate on the surface of the active layer; Using an etching process to remove the compound semiconductor layer and the first substrate to expose the active layer, wherein an etching selectivity ratio between the active layer and the compound semiconductor layer is greater than an etching selectivity ratio between the active layer and the first substrate; A metal wiring layer is formed on the surface of the active layer.

2. The method according to claim 1, characterized in that An active layer is formed on the compound semiconductor layer, comprising: forming the active layer on the compound semiconductor layer by using an epitaxial growth process; forming an isolation groove, wherein the isolation groove penetrates the compound semiconductor layer and the active layer and exposes the first substrate; An isolation structure is formed in the isolation groove, wherein the isolation structure isolates the active layer into a plurality of active pillars.

3. The method according to claim 2, characterized in that Removing the compound semiconductor layer and the first substrate by an etching process, comprising: Performing a planarization process to remove a portion of the first substrate and expose the isolation structure; The first substrate and the compound semiconductor layer are removed by an etching process to expose the plurality of active pillars.

4. The method according to claim 2, characterized in that: Forming a metal wiring layer on the active layer, comprising: A metal wiring layer is formed on the surfaces of the plurality of active pillars. The metal wiring layer is filled between the isolation structures, and the top surface of the metal wiring layer is flush with the top surface of the isolation structure.

5. The method according to claim 3, characterized in that: The active layer includes a storage area and a peripheral area, and the plurality of active pillars are formed in the storage area; Removing the first substrate and the compound semiconductor layer by an etching process includes: forming a patterned mask layer, wherein the patterned mask layer covers the first substrate above the peripheral area and exposes the first substrate above the storage area; Using an etching process to remove the first substrate and the compound semiconductor layer above the storage area; The patterned mask layer is removed.

6. The method according to claim 1 or 2, characterized in that: Removing the compound semiconductor layer and the first substrate by an etching process, comprising: Patterning the first substrate to form an etching opening, wherein the etching opening exposes the compound semiconductor layer; The compound semiconductor layer is removed along the etching opening by a wet etching process to peel off the first substrate.

7. The method according to claim 1, characterized in that Forming a compound semiconductor layer on the first substrate, comprising: The compound semiconductor layer is formed on the first substrate by using an epitaxial growth process, the material of the first substrate includes silicon, and the material of the compound semiconductor layer includes silicon germanium.

8. A method for preparing a semiconductor structure, characterized in that: include: providing a compound semiconductor layer; forming an active layer on the compound semiconductor layer by using an epitaxial growth process; forming a device structure in the active layer; Bonding a second substrate on the surface of the active layer; Removing the compound semiconductor layer by using an etching process, wherein an etching selectivity ratio between the active layer and the compound semiconductor layer is greater than an etching selectivity ratio between the active layer and the second substrate; A metal wiring layer is formed on the active layer.

9. A semiconductor structure, characterized in that: include: an active layer, the active layer comprising a storage region and a peripheral region; a compound semiconductor layer, the compound semiconductor layer being located above the active layer in the peripheral region; a first substrate, wherein the first substrate is located above the compound semiconductor layer, and an etching selectivity ratio between the active layer and the compound semiconductor layer is greater than an etching selectivity ratio between the active layer and the first substrate; A metal wiring layer is located above the active layer of the storage area.

10. The semiconductor structure according to claim 9, characterized in that: The active layer includes a plurality of active pillars arranged in an array, and the semiconductor structure further includes: An isolation structure is formed between the plurality of active pillars, and a top surface of the metal wiring layer is flush with a top surface of the isolation structure.

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