Memory device and forming method thereof

Abstract

A memory device includes a two-dimensional array of access transistors on a semiconductor substrate; a metal interconnect structure embedded in the dielectric material layer and electrically connected to an electrical node of the access transistor; and a two-dimensional array of resistive memory structures embedded in the dielectric material layer. The metal interconnection structure comprises two first source lines which are located on the first metal line level and transversely extend in the first horizontal direction. The second source electrode line is positioned on the second metal line level and transversely extends along the first horizontal direction; and a vertical connection structure including a plurality of interconnected via structures and at least one line level metal structure, and providing a vertical electrical connection between the two first source lines and the second source line. The embodiment of the invention also discloses a method for forming the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] Memory devices are susceptible to performance degradation due to high resistance in the source lines. Structures and methods for reducing source line resistance in a memory array are desired. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: an array of access transistors located on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer and electrically connected to an electrical node of each access transistor in the array of access transistors; and an array of resistive memory structures located in the dielectric material layer and electrically connected to a corresponding one of the access transistors, wherein the metal interconnect structure comprises: at least one first source line located at a first metal line level and extending laterally along a first horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing; a second source line located at a second metal line level and extending laterally along the first horizontal direction, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the first vertical spacing being different from the first vertical spacing; and a vertical connection structure comprising a plurality of interconnected via structures and at least one line-level metal structure, and providing a vertical electrical connection between at least one first source line and a second source line.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a column of access transistors, located on a semiconductor substrate and arranged along a first horizontal direction; a metal interconnect structure, embedded in a dielectric material layer and electrically connected to an electrical node of each access transistor in the column of access transistors; and a column of resistive memory structures, formed in the dielectric material layer, wherein the metal interconnect structure comprises: two first source lines, located at a first metal line level and extending laterally along a first horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing; a first source contact via structure, located on a bottom surface of one of the two first source lines; and a second source contact via structure, located on a bottom surface of the other of the two first source lines, wherein each source region in the column of access transistors is located on a corresponding one of the first source contact via structures and on a corresponding one of the second source contact via structures.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, the method comprising: forming a column of access transistors arranged along a first horizontal direction on a semiconductor substrate; forming a lower-level metal interconnect structure formed in a lower-level dielectric material layer above the column of access transistors, wherein the lower-level metal interconnect structure comprises two first source lines located at a first metal line level, the two first source lines extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing, wherein each source region in the column of access transistors is spaced apart from each other by a first vertical spacing. electrically connected to each of the two first source lines; forming a column of resistive memory structures, wherein each resistive memory structure within the column of resistive memory structures is electrically connected to a drain region of a corresponding access transistor within the column of access transistors; and forming an upper level metal interconnect structure formed within the upper level dielectric material layer, wherein the upper level metal interconnect structure includes a second source line at a second metal line level, the second source line extending laterally along a first horizontal direction and electrically connected to each of the two first source lines, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the second vertical spacing being different from the first vertical spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming an access transistor array, a contact level via structure, and a first line level metal interconnect structure according to an embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A A top view of a first configuration of an exemplary structure, the hinged vertical plane AA' is Figure 1A cross section.

[0009] Figure 1C is along Figure 1B A vertical cross-sectional view of a first configuration of an exemplary structure of a vertical plane CC'.

[0010] Figure 2A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming additional dielectric material layers and additional metal interconnect structures according to an embodiment of the present disclosure.

[0011] Figure 2B yes Figure 2AA top view of a first configuration of an exemplary structure of FIG. 1 , wherein the invisible structure below is shown in dashed lines. The vertical plane AA' of the hinge is Figure 2A cross section.

[0012] Figure 2C is along Figure 2B A vertical cross-sectional view of a first configuration of an exemplary structure of a vertical plane CC'.

[0013] Figure 2D yes Figure 2B A first revision of a top-down view of FIG. 1 , in which invisible structural elements below the word lines are not shown.

[0014] Figure 2E yes Figure 2B A second revised version of a top-down view of FIG. 1 , in which the invisible structural elements overlying the first line level metal interconnect structure are not shown.

[0015] Figure 3A is a vertical cross-sectional view of a second configuration of an exemplary structure according to an embodiment of the present disclosure.

[0016] Figure 3B yes Figure 3A A second configuration of the exemplary structure along Figure 3A The horizontal cross-section of the horizontal plane B-B'. The hinged vertical plane A-A' is Figure 3A cross section.

[0017] Figure 3C is along Figure 3B A vertical cross-sectional view of a second configuration of the exemplary structure of a vertical plane CC'.

[0018] Figure 3D is along Figure 3A and Figure 3C A horizontal cross-sectional view of a second configuration of an exemplary structure of a horizontal plane DD′.

[0019] Figure 3E is along Figure 3A and Figure 3C A horizontal cross-sectional view of a second configuration of the exemplary structure along a horizontal plane EE'.

[0020] Figure 4A is a vertical cross-sectional view of a third configuration of an exemplary structure according to an embodiment of the present disclosure.

[0021] Figure 4B is along Figure 4A The horizontal plane B-B' Figure 4A A third configuration horizontal cross-sectional view of an exemplary structure. The hinged vertical plane A-A' is Figure 4A cross section.

[0022] Figure 4C is along Figure 4A A horizontal cross-sectional view of a third configuration of the exemplary structure along a horizontal plane CC'.

[0023] Figure 4D is with Figure 4A A horizontal cross-sectional view of an alternative embodiment of a third configuration of the exemplary structure within a horizontal plane corresponding to horizontal plane BB'.

[0024] Figure 5A is a vertical cross-sectional view of a fourth configuration of an exemplary structure according to an embodiment of the present disclosure.

[0025] Figure 5B is along Figure 5A The horizontal plane B-B' Figure 5A A horizontal cross-sectional view of a fourth configuration of an exemplary structure. The hinged vertical plane AA' is Figure 5A cross section.

[0026] Figure 5C is along Figure 5A A horizontal cross-sectional view of a fourth configuration of the exemplary structure taken along a horizontal plane CC'.

[0027] Figure 6 is a flow chart showing steps for forming a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not meant to be limiting. The drawings are not drawn to scale. Elements with the same reference numerals represent the same elements and are assumed to have the same material composition and the same thickness range unless otherwise expressly indicated. Unless otherwise expressly stated, embodiments that repeat multiple instances of any of the described elements are expressly contemplated. Embodiments that omit non-essential elements are expressly contemplated, even if these embodiments are not expressly disclosed but are known in the art.

[0029] Ordinal numbers such as "first", "second", "third" and the like are usually not part of the noun of the element, but are merely adjectives. Therefore, in the present application, the same element can be represented in different orders. In addition, whenever there are multiple elements and / or similar elements, these multiple elements or similar elements can be numbered in any order. Therefore, for each case where there are multiple elements, the possibility of numbering the elements with different ordinal numbers is clearly considered. In addition, for ease of description, spatial relative terms such as "below ... ", "below ... " and "lower", "above ... " and "upper" etc. can be used herein to describe the relationship between an element or component and another element or component shown. In addition to the directions shown in the figures, spatial relative terms are intended to cover different directions of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can also be interpreted accordingly.

[0030] The performance of a resistive random access memory (RRAM) device can be improved by reducing the resistance of the metal interconnect structure that provides electrical wiring to the RRAM device. The voltage drop on the source side of the access transistor may also cause resistive heating of the access transistor and may cause device degradation and reliability issues during the operation of the RRAM device. Therefore, the low resistance of the source line can stabilize the threshold voltage of the access transistor by providing sufficient current to flow through the access transistor while minimizing the voltage drop on the source side during the operation of the RRAM device. The size and power consumption level of the RRAM array may also affect the resistance requirements of the metal wiring in the RRAM array. For example, a large RRAM array requires higher current handling capabilities. Therefore, it is desirable to reduce the resistance of the metal wiring in the RRAM device, especially for an RRAM array that includes a large number of RRAM cells. The source voltage drift in the RRAM device has a greater adverse effect on the device performance than the voltage drift in the word line or bit line, and therefore, the source resistance needs to be reduced to achieve reliable operation of the RRAM array.

[0031] The desire to reduce source resistance in RRAM arrays stems from the inherent operating characteristics of these memory devices and their sensitivity to performance degradation due to voltage drift. Typically, RRAM devices store data by applying a voltage to change the resistance of the dielectric material between two electrodes. This change in resistance represents a binary data state (0 and 1). The operation of RRAM involves several key voltages, including those applied to the word line (WL), bit line (BL), and source line. These voltages control the writing, reading, and erasing of data in the RRAM array.

[0032] Voltage drift refers to unwanted changes in applied voltage, which can be particularly problematic for the precise control required in RRAM operation.Drift in the source line (SL) voltage is more detrimental than drift in the WL voltage or the BL voltage for several reasons.

[0033] The first reason is the threshold switching accuracy required for RRAM devices to operate. RRAM devices operate by sensing the switching of the resistance state of the material when a certain threshold voltage is exceeded. In the event of supply voltage drift, the exact threshold point of switching can become unpredictable, resulting in unreliable data storage and retrieval. Lower source resistance helps to apply voltage more evenly across the array. High source resistance can cause voltage drops, meaning that all cells in the array do not receive the same voltage during operation. This can cause non-uniformity in switching behavior, adversely affecting device reliability and data integrity.

[0034] The second reason is energy efficiency. Higher source resistance requires higher voltage to achieve the same electric field across the RRAM material, resulting in increased power consumption. Lowering the source resistance can improve the energy efficiency of the device, which is beneficial for battery-powered and low-power applications.

[0035] The third reason is the reliability of the RRAM device. Voltage instability (partly due to high source resistance) can cause more frequent and unstable switching, stressing the material and potentially shortening the life of the device. Embodiments of the present disclosure can be used to reduce the source resistance within an RRAM array. Various aspects of the present disclosure are now described with reference to the accompanying drawings.

[0036] Reference Figure 1A-Figure 1C , showing a first configuration of an exemplary structure. The first configuration of the exemplary structure includes a semiconductor substrate 10 and an array of access transistors 310 formed on the semiconductor substrate 10 in a memory array region 300. The semiconductor substrate 10 may include a bulk semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor substrate 10 may be a commercially available single crystal silicon wafer.

[0037] The memory array region 300 is a region where a resistance memory array is subsequently formed. According to one aspect of the present disclosure, a vertical connection region 600 is disposed adjacent to an edge of the memory array region 300. A vertical connection structure providing a vertically extending conductive path is subsequently formed in the vertical connection region 600.

[0038] A shallow trench may be formed in an upper portion of the semiconductor substrate 10 and may be filled with a dielectric material to form a shallow trench isolation structure 12. In one embodiment, the shallow trench isolation structure 12 may have a grid pattern including a rectangular array of M x N openings therethrough. Each opening in the shallow trench isolation structure 12 defines an active region AR in which a source region 332, a drain region 338, and a channel region of a corresponding access transistor 310 are formed. The integer M may be in the range of 2 to 216, although larger numbers may also be used. The integer N may be in the range of 2 to 2 16but larger numbers can be used. In a plan view, for example Figure 1B From the top view, each active region AR can be completely located within the region of the repeating unit RU.

[0039] Generally, a two-dimensional array of resistance memory devices may be formed in the memory array region 300. Each resistance memory device may constitute a repeating unit RU of the two-dimensional array. Each resistance memory device may include an access transistor 310 formed on the top surface of the semiconductor substrate 10, a resistance memory structure formed subsequently, and a metal interconnect structure for electrically connecting the drain region of the access transistor 310 to the electrode of the resistance memory structure to electrically bias the access transistor 310 and various nodes of the resistance memory structure.

[0040] For example, a two-dimensional array of resistive memory devices may include an M x N rectangular array of resistive memory devices, including M rows and N columns. Each column of resistive memory devices may be arranged along a first horizontal direction hd1, and adjacent columns of resistive memory devices may be laterally spaced apart along a second horizontal direction hd2. Each row of resistive memory devices may be arranged along a second horizontal direction hd2, and resistive memory devices of adjacent rows may be laterally spaced apart along the first horizontal direction hd1. In one embodiment, each column of resistive memory devices may include M resistive memory devices arranged along the first horizontal direction hd1. In one embodiment, each row of resistive memory devices may include N resistive memory devices arranged along the second horizontal direction hd2.

[0041] Specifically, a two-dimensional array of access transistors 310 may be formed on a semiconductor substrate 10. Each access transistor 310 includes a source region 332, a drain region 338, a gate stack including a gate dielectric 352, a gate electrode 354, and a gate cap dielectric 358, and a gate spacer 356. The source region 332 may include a combination of a source extension region and a deep source region. The drain region 338 may include a combination of a drain extension region and a deep drain region. Each column of access transistors 310 may be arranged along a first horizontal direction hd1, and each row of access transistors 310 may also be arranged along a second horizontal direction hd2.

[0042] A dielectric material layer may be formed on the two-dimensional array of access transistors 310. The dielectric material layer is referred to herein as a lower level dielectric material layer 50. A lower level metal interconnect structure (62, 64) may be formed in the lower level dielectric material layer 50. The lower level metal interconnect structure (62, 64) may include a metal via structure 62 and a metal line structure 64. The level at which the metal via structure in contact with the source region 332 or the drain region 338 is formed is referred to herein as a contact level. The metal via structure 62 formed in this processing step may include a contact level metal via structure (62S, 62D, 62G), i.e., a metal via structure formed at the contact level. The contact level metal via structure (62S, 62D, 62G) includes a source contact via structure 62S, a drain contact via structure 62D, and a gate contact via structure 62G.

[0043] The metal line level formed in contact with the top surface of the contact level metal via structure (62S, 62D, 62G) is referred to herein as the first metal line level, i.e., the first level in which the metal lines are formed, counted in order of proximity to the semiconductor substrate 10. The metal line structure 64 formed in this processing step may include first line level metal lines (64S, 64D, 64G), i.e., a metal line structure formed at the first metal line level or M1 level, the M1 level being the line level closest to the semiconductor substrate 10. The first line level metal lines (64S, 64D, 64G) include a first source line 64S, a first line level drain connection metal line 64D, and a first line level gate connection metal line 64G. The top surfaces of the first line level metal lines (64S, 64D, 64G) may be formed in the same horizontal plane.

[0044] Each first source line 64S contacts a corresponding column of the M columns of source contact via structures 62S arranged along the first horizontal direction hd1, and is electrically connected to the M source regions 332 in the M columns of access transistors 310 arranged along the first horizontal position hd1. Each first line-level drain connection metal line 64D may have a configuration of a metal pad, may have an area smaller than an area of ​​a corresponding underlying drain region 338, and may be electrically connected to the drain region 338 of the corresponding underlying access transistor 310 through the corresponding drain contact via structure 62D. Each first line-level gate connection metal line 64G may have a configuration of a metal pad, may have an area smaller than an area of ​​a corresponding underlying gate electrode 354, and may be electrically connected to the gate electrode 354 of the corresponding underlying access transistor 310 through the corresponding gate contact via structure 62G.

[0045] The metal line structures 64 within the lower level metal interconnect structure ( 62 , 64 ) are generally formed within the memory array region 300 , except for a first source line 64S that extends laterally through the memory array region 300 and into the vertical connection region 600 .

[0046] In one embodiment, all metal lines in the first metal line level may extend laterally along a first horizontal direction hd1 and may have a uniform lateral dimension, i.e., a uniform width, along a second horizontal direction hd2. Adjacent metal line pairs in the first metal line level may be laterally spaced apart from each other at a uniform lateral spacing. The sum of the uniform width of each first line level metal line (64S, 64D, 64G) and the uniform lateral spacing at the first metal line level defines a line pattern pitch of the first line level metal lines along the second horizontal direction hd2.

[0047] The first source line 64S, the first line level drain connection metal line 64D, and the first line level gate connection metal line 64G may be located at a first metal line level. The first metal line level is vertically spaced apart from the top surface of the semiconductor substrate 10 by a first vertical spacing. The first source lines 64S extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2. Each source region 332 within a column of access transistors 310 is electrically connected to each of the two first source lines 64S overlying the column of access transistors.

[0048] According to one aspect of the present disclosure, each repeating unit RU has a plan view (e.g. Figure 1B The repeating unit RU may have a rectangular shape in a top view of the second horizontal direction hd2, and the width of the rectangular shape of each repeating unit in the plan view along the second horizontal direction hd2 may be equal to three times the line pattern pitch of the first line-level metal lines (64S, 64D, 64G) along the second horizontal direction hd2. In other words, three metal lines of the same width along the second horizontal direction hd2 may be embedded in the rectangular region of the repeating unit RU.

[0049] In one embodiment, two first source lines 64S, a column of M first line-level drain connection metal lines 64D, and a column of M first line-level gate connection metal lines 64G may be formed in each region of the columns of the M repeating units RU arranged along the first horizontal direction hd1. Each of the two first source lines 64S may extend continuously on each of the M access transistors 310 in the region of the columns of the M repeating units RU.

[0050] Two first source lines 64S and two columns of source contact via structures 62S may be arranged along a first horizontal direction hd1 in the region of the column of access transistors 310. Each source contact via structure 62S contacts a bottom surface of a corresponding one of the two first source lines 64S and contacts a top surface of a source region 332 of a corresponding access transistor 310 within the column of access transistors 310. Each source region 332 within the column of access transistors 310 contacts a corresponding first source contact via structure 62S contacting a bottom surface of one of the two first source lines 64S and contacts a corresponding second source contact via structure 62S contacting a bottom surface of the other of the two first source lines 64S.

[0051] The column of M first line-level drain connection metal lines 64D may be located between a pair of first source lines 64S overlying a column of an adjacent pair of access transistors 310. Each first line-level drain connection metal line 64D may have a configuration of a metal pad and may have a lateral extension along the first horizontal direction hd1 that is less than half, preferably less than one-third, of the length of the rectangular shape of the repeating unit RU along the first horizontal direction hd1. The column of M first line-level drain connection metal lines 64D may be electrically connected to the column of drain regions 338 through the column of drain contact via structures 62D.

[0052] The column of M first line-level gate connection metal lines 64G may be located between a pair of first source lines 64S overlying a column of an adjacent pair of access transistors 310. Each first line-level gate connection metal line 64G may have a configuration of a metal pad and may have a lateral extension along the first horizontal direction hd1 that is less than half, preferably less than one-third, of the length of the rectangular shape of the repeating unit RU along the first horizontal direction hd1. The column of M first line-level gate connection metal lines 64G may be electrically connected to the column of gate electrodes 354 through the column of gate contact via structures 62G.

[0053] Reference FIG. 2A to FIG. 2E , additional dielectric material layers and additional metal interconnect structures may be formed on the first line level metal lines (64S, 64D, 64G). The additional dielectric material layers are referred to herein as upper level dielectric materials 70. The additional metal interconnect structures are referred to herein as upper level metal interconnect structures (62, 64, 66, 68). A two-dimensional array of resistive memory structures 360 may be formed within the upper level dielectric material layer 70. In a plan view, the two-dimensional array of resistive memory structures 360 may be formed entirely within the memory array region 300.

[0054] The upper level metal interconnect structures (62, 64, 66, 68) include a metal via structure 62 formed at a metal via layer in the memory array region 300, a metal line structure 64 formed at a metal line level in the memory array region 300, a metal via structure 66 formed at a metal via level in the vertical connection region 600, and at least one line level metal structure 68 formed at a metal line level in the vertical connection region 600. The metal line structure 64 in the upper level metal interconnect structures (62, 64, 66, 68) is generally formed in the memory array region 300, except for a second source line 65S extending laterally through the memory array region 300 and into the vertical connection region 600. Generally, the metal interconnect structures (62, 64, 66, 68) are embedded in the dielectric material layer (50, 70) and are electrically connected to an electrical node of the access transistor 310.

[0055] The metal line structures 64 may include a second line level line structure 642 formed in a second metal line level, a third line level line structure 643 formed in a third metal line level, a fourth line level line structure 644 formed in a fourth metal line level, a fifth line level line structure 645 formed in a fifth metal line level, a sixth line level line structure 646 formed in a sixth metal line level, etc. Each nth metal line level or Mn level is the nth line level among all metal line levels in order of proximity to the semiconductor substrate 10. The integer n may range from 2 to 20, although a larger number may also be used for the value of the integer n.

[0056] In one embodiment, a first subset of the metal line structures 64 formed at the odd metal line levels may extend laterally along a horizontal direction (e.g., a first horizontal direction hd1), and a second subset of the metal line structures 64 formed at the even metal line levels may extend laterally along another horizontal direction (e.g., a second horizontal direction hd2 perpendicular to the first horizontal direction hd1). For example, the first source line 64S and the first line-level drain connection metal line 64D, the third line-level line structure 643, the fifth line-level line structure 645, the seventh line-level line structure 647, etc. may extend laterally along the first horizontal direction hd1, and the second line-level line structure 642, the fourth line-level line structure 644, the sixth line-level line structure 646, etc. may extend laterally along the second horizontal direction hd2.

[0057] The metal via structures 62 may include a first via level connecting via structure 621 formed in a first metal via level, a second via level connecting via structure 622 formed in a second metal via level, a third via level connecting via structure 623 formed in a third metal via level, a fourth via level connecting via structure 624 formed in a fourth metal via level, a sixth via level wiring via structure 626 formed in a sixth metal via level, etc. Each nth metal via level or Vn level is the nth via level in the order of proximity to the semiconductor substrate 10 among all metal via levels except the contact via level. The integer n may range from 2 to 19, although a larger number may also be used for the value of the integer n.

[0058] A subset of the metal line structures 64 within the upper level metal interconnect structures (62, 64, 66, 68) includes word lines 64W, which may be arranged in a plan view (eg, Figure 2B and Figure 2D 354 and the word line 64W are formed in a fourth metal line level. In a layout where the metal lines in the odd-numbered metal line levels extend laterally along the first horizontal direction hd1 and the metal lines in the even-numbered metal line levels extend laterally along the second horizontal direction hd2, the word line 64W can be formed in any even-numbered metal line level. A subset of the metal via structure 62 and the metal line structure 64 provide electrical connections to the gate electrode 354 and the word line 64W.

[0059] A subset of the metal line structures 64 within the upper level metal interconnect structures (62, 64, 66, 68) includes bit lines 64B, which may be located in a plan view (eg, Figure 2B and Figure 2E 3. The bit line 64B is formed at the seventh metal line level. In a layout where the metal lines of the odd-numbered metal line levels extend laterally along the first horizontal direction hd1 and the metal lines of the even-numbered metal line levels extend laterally along the second horizontal direction hd2, the bit line 64B may be formed at any odd-numbered metal line level except the first metal line level. The metal via structure 62 and a subset of the metal line structure 64 provide electrical connections to the second electrode 366 of the resistive memory structure 360 ​​and the bit line 64B.

[0060] A resistive memory device is formed within the volume of each repeating unit RU. Each resistive memory device may include an access transistor 310, a resistive memory structure 360, and a subset of metal interconnect structures (62, 64) located within the volume of the corresponding repeating unit RU. Each resistive memory structure 360 ​​includes a first electrode 364 (which may be a bottom electrode), a resistive memory element 365 (including a material that provides at least two different resistance states), and a second electrode 366 (which may be a top electrode). The first electrode 364 may include a first inert metal material, such as TiN, TaN, WN and / or MoN. The second electrode 366 may include a second inert metal material, such as TiN, TaN, WN and / or MoN. The metal via structure 62 may include a bottom electrode contact via structure 362 that contacts the bottom surface of the first electrode 364 (which is the bottom electrode) and a top electrode contact via structure 368 that contacts the top surface of the second electrode 366 (which is the top electrode). Generally, an array of resistive memory structures 360 may be formed at a metal via level (e.g., as Figure 3A and Figure 3C within the fifth metal via level shown.

[0061] The material of each resistive memory element 365 that provides at least two different resistance states is referred to herein as a resistive memory material. In general, the resistive memory material may be any type of resistive memory material known in the art. In one embodiment, the resistive memory material may include a metal oxide material (such as hafnium oxide, titanium oxide, niobium pentoxide, germanium telluride, silver sulfate, zinc oxide, vanadium oxide, tantalum oxide, zirconium oxide, etc.) that forms a filament, which provides higher conductivity when a conductive filament is formed therein. In one embodiment, the resistive memory material may include a phase change memory material containing a chalcogenide glass (such as an alloy of germanium, antimony and tellurium, and optional additional additives). In one embodiment, the resistive memory material may include a conductive bridge forming material, in which a conductive bridge may be formed or broken (such as silver, copper, silver sulfide, mixed ion electronic conductor material (such as yttria-stabilized zirconium oxide), etc.). In one embodiment, the resistive memory material may include an organic polymer material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a perovskite-based material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a two-dimensional material, such as molybdenum disulfide (MoS2), which can provide at least two different resistance states. In one embodiment, the resistance memory material may include an organic-inorganic hybrid resistance memory material, which may provide at least two different resistance states. In one embodiment, the resistance memory material may include a rare earth oxide resistance memory material, which may provide at least two different resistance states.

[0062] In an embodiment where the repeating unit RU is repeated in a pattern of an M x N rectangular array as described above, an array of M x N access transistors 310, an array of M x N resistive memory structures 360, and an array of M x N metal interconnect structures (62, 64) may be provided. Each component of the metal interconnect structures (62, 64) may be configured to provide electrical connections to a corresponding access transistor 310 and a corresponding resistive memory structure 360.

[0063] According to one aspect of the present disclosure, the second source line 69S may be formed at a metal line level overlying the first metal line layer. Typically, the metal line level of the second source line 69S is referred to herein as the second metal line level, which is different from the first metal line level at which the first source line 64S is formed. As described above, the first metal line level may be the first metal line level. Typically, the second metal line level may be any one of the odd-numbered metal line levels counted upward from the top surface of the semiconductor substrate 10. FIG. 2A to FIG. 2E In the example shown, the second metal line level may be a ninth level. The second metal line level is vertically spaced apart from the top surface of semiconductor substrate 10 by a second vertical spacing that is different from the first vertical spacing between the first metal line level and the top surface of semiconductor substrate 10 .

[0064] The second source line 69S extends laterally along the first horizontal direction hd1, and may have a uniform width along the second horizontal direction hd2. In one embodiment, the second source line 69S may be formed as a "coarse line level" whose line pitch along the second horizontal direction hd2 is greater than the line pitch at the first metal line level (i.e., M1 level). In one embodiment, the line pitch of the second source line 69S along the second horizontal direction hd2 may be the same as the width of the rectangular shape of the repeating unit RU in the plane view along the second vertical direction hd2. Therefore, the pattern of the second source line 69S may be repeated along the second horizontal direction hd2 with the same periodicity as the width of the rectangular shape of the repeating unit RU in the plane view along the second horizontal direction hd2. In one embodiment, the width of each second source line 69S along the second horizontal direction hd2 may be the same as the width of each first source line 64S, or may be approximately three times the width of each first source line 64S.

[0065] According to one aspect of the present disclosure, vertical connection structures 660 are formed in the upper level dielectric material layer 70 within the vertical connection region 600 located outside the memory array region 300. Each vertical connection structure 660 includes a stack of multiple interconnection via structures 66 and at least one line-level metal structure 68, and provides a vertical electrical connection between a corresponding set of two first source lines 64S and second source lines 69S. In one embodiment, each vertical connection structure 660 may include a vertical alternating sequence of multiple interconnection via structures 66 and multiple line-level metal structures 68.

[0066] The interconnection via structures 66 may include a first via level connection via structure 661 formed in a first metal via layer, a second via level connection via structure 662 formed in a second metal via level, a third via level connection via structure 663 formed in a third metal via level, a fourth via level connection via structure 664 formed in a fourth metal via level, a fifth via level wiring via structure 665 formed in a fifth metal via level, a sixth via level connection via structure 666 formed in a sixth metal via level, a seventh via level connection via structure 667 formed in a seventh metal via level, an eighth via level connection via structure 668 formed in an eighth metal via level, etc. Each nth metal via level or Vn level is the nth via level in the order of proximity to the semiconductor substrate 10 among all interconnection via levels except the contact via level. The integer n may range from 2 to 19, although larger values ​​of the integer n may also be used.

[0067] The line level metal structures 68 may include a second line level metal structure 682 formed in a second metal line level, a third line level metal structure 683 formed in a third metal line level, a fourth line level metal structure 684 formed in a fourth metal line level, a fifth line level metal structure 685 formed in a fifth metal line level, a sixth line level metal structure 686 formed in a sixth metal line level, a seventh line level metal structure 687 formed in a seventh metal line level, an eighth line level metal structure 688 formed in an eighth metal line level, etc. Each nth metal line level or Mn level is the nth line level among all metal line levels in order of proximity to the semiconductor substrate 10. The integer n may range from 2 to 20, although a larger number may also be used for the value of the integer n.

[0068] Typically, for each column of the resistance memory structures 360 electrically connected to the columns of the access transistors 310, each resistance memory structure within the column of the resistance memory structures 360 is electrically connected to the drain region of the corresponding access transistor within the column of the access transistors 310. For each combination of the columns of the resistance memory structures 360 and the columns of the access transistors 310, two source lines 64S are provided at a first metal line level, the first metal line level being vertically spaced apart from the top surface of the semiconductor substrate 10 by a first vertical spacing. For each combination of the columns of the resistance memory structures 360 and the columns of the access transistors 310, a second source line 69S at a second metal line level may be provided, the second metal line level being vertically spaced apart from the top surface of the semiconductor substrate 10 by a second vertical spacing different from the first vertical spacing, and the second source line 69S extending laterally along a first horizontal direction hd1 and being electrically connected to each of the two first source lines 64S.

[0069] In one embodiment, each column of access transistors 310 is formed in the memory array region 300, and each vertical connection structure 660 is formed in the vertical connection region 600, which is laterally offset from the memory array region 300 in a plan view. For each column of access transistors 310, two first source lines 64S, a column of first source contact via structures 62S, and a column of second source contact via structures 62S may be provided. One of the two first source lines 64S is formed on the column of the first source contact via structures 62S, and the other is formed on the column of the second source contact via structures 62S. Each source region 332 in the column of access transistors 310 is contacted with a corresponding one of the first source connection via structures 62S and the second source connection via structures 62S, respectively.

[0070] In one embodiment, each vertical connection structure 660 extends continuously from the top surface of a corresponding set of two first source lines 64S to the bottom surface of a corresponding second source line 69S. In one embodiment, the two first source lines 64S extend laterally over the columns of access transistors 310 within a two-dimensional array of access transistors 310 (which includes a set of N access transistors 310) and are electrically connected to each source region 332 within the set of N access transistors 310. N is an integer greater than 1.

[0071] In one embodiment, the plurality of interconnect via structures 66 within each vertical connection structure 660 include two first interconnect via structures (e.g., two first via level connection via structures 661), each of which contacts the top surface of a corresponding one of the two first source lines 64S and is laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, at least one line-level metal structure 68 within each vertical connection structure 660 includes a first metal pad (including a second line-level metal structure 682) contacting the top surfaces of the two first interconnect via structures (e.g., two first via level connection via structures 661). In one embodiment, the plurality of interconnect via structures 66 of each vertical connection structure 660 include a second interconnect via structure (e.g., a second via level connection via structure 662) contacting the top surface of the first metal pad (including the second line-level metal structure 682). In this embodiment, the second interconnect via structure (eg, second via-level connection via structure 662 ) may be the only metal structure contacted by the top surface of the first metal pad (including the second line-level metal structure 682 ).

[0072] In one embodiment, the plurality of interconnected via structures 66 within the vertical connection structure 660 include at least three additional interconnected via structures 66 that are vertically spaced apart from each other in a plan view and have an area overlap therebetween. For example, the plurality of interconnected via structures 66 within the vertical connection structure 660 may include a third through-hole level connection via structure 663, a fourth through-hole level connection via structure 664, a fifth through-hole level connection via structure 665, a sixth through-hole level connection via structure 666, a seventh through-hole level connection via structure 667, and / or an eighth through-hole level connection via structure 668. Each of the at least three additional interconnected via structures 66 overlies two first interconnected vias (e.g., two first through-hole level connection via structures 661).

[0073] For each column of resistive memory structures 360 electrically connected to the column of access transistors 310, a bit line 64B is provided that overlies a horizontal plane including the top surface of the column of resistive memory structures 360 and is electrically connected to the top electrodes of the resistive memory structure columns 360 within the two-dimensional array of resistive memory structures 360. In one embodiment, the second source line 69S overlies the bit line 64B and may have an area overlap with the bit line 64B in a top view. In one embodiment, the second source line 69S has an area overlap with each of the two first source lines 64S in a plan view.

[0074] In general, the columns of access transistors 310 may be located on the semiconductor substrate 10 and may be arranged along a first horizontal direction hd1. A metal interconnect structure (62, 64, 66, 68) may be provided, which is embedded in the dielectric material layer (50, 70) and electrically connected to the electrical nodes of the access transistors 310. The columns of the resistive memory structures 360 may be embedded in the dielectric material layer, such as the upper level dielectric material 70. For each combination of the columns of access transistors 310 and the columns of the resistive memory structures 360, the metal interconnect structure (62, 64, 66, 68) may include two first source lines 64S, which are located at a first metal line level vertically spaced from the top surface of the semiconductor substrate 10 by a first vertical spacing and extend laterally along the first horizontal direction hd1; a first source contact via structure 62S, which contacts the bottom surface of one of the two first source lines 64S; and a second source contact via structure 62S, which contacts the bottom surface of the other of the two first source lines 64S. Each source region 332 within a column of access transistors 310 is contacted with a corresponding one of the first source contact via structure 62S and the second source contact via structure 62S, respectively.

[0075] For each combination of columns of access transistors 310 and columns of resistive memory structures 360, the metal interconnect structure (62, 64, 66, 68) may include: a second source line 69S located at a second metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a second vertical spacing different from the first vertical spacing, and extending laterally along a first horizontal direction hd1; and a vertical connection structure 660, which includes a plurality of interconnected via structures 66 and at least one line level metal structure 68, and provides a vertical electrical connection between two first source lines 64S and a second source line 69S.

[0076] For each combination of a column of access transistors 310 and a column of resistive memory structures 360, a bit line 64B may be provided that overlies a horizontal plane including a top surface of the column of resistive memory structures 360 and is electrically connected to a top electrode within the column of resistive memory structures 360. A second source line 69S may overlie the bit line 64B.

[0077] Reference FIG. 3A to FIG. 3E , showing a second configuration of the exemplary structure according to an embodiment of the present disclosure. The second configuration of the exemplary structure can be derived from the first configuration in the exemplary structure by forming an additional source line 65S at the third metal line level. In this embodiment, the metal line pattern of the third metal line level (such as Figure 3E ) can be connected to the metal line pattern of the first metal line level (such as Figure 3D shown).

[0078] The second source line 69S may be formed above the bit line 64B, and the additional source line 65S formed at the third metal line level may be referred to as the third source line. Alternatively, the additional source line 65S formed at the third metal line level may be referred to as the second source line. As described above, the serial number is not part of the component name, and the various source lines (64S, 69S, 65S) may be represented by different serial numbers.

[0079] For each combination of a column of access transistors 310 and a column of resistive memory structures 360, the metal interconnect structure (62, 64, 66, 68) may include: two first source lines 64S located at a first metal line level spaced vertically from the top surface of the semiconductor substrate 10 by a first vertical spacing and extending laterally along a first horizontal direction hd1; a first source contact via structure 62S contacting a bottom surface of one of the two first source lines 64S; and a second source contact via structure 62S contacting a bottom surface of the other of the two first source lines 64S. Each source region 332 within the column of access transistors 310 is contacted with a corresponding one of the first source contact via structure 62S and the second source contact via structure 62S, respectively.

[0080] For each combination of a column of access transistors 310 and a column of resistive memory structures 360, the metal interconnect structures (62, 64, 66, 68) may include: a second source line 69S located at a second metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a second vertical spacing different from the first vertical spacing and extending laterally along a first horizontal direction hd1; and a vertical connection structure 660 including a plurality of interconnecting via structures 66 and at least one line level metal structure 68 and providing a vertical electrical connection between two first source lines 64S and a second source line 69S. The second source line 69S may overlie a bit line 64B connected to a second electrode 366 of the resistive memory structure 360.

[0081] For each combination of a column of access transistors 310 and a column of resistive memory structures 360, the metal interconnect structure (62, 64, 66, 68) includes two additional source lines 65S (which may be referred to as two second source lines or two third source lines) that are located at an additional metal line level (which may be referred to as a second metal line level or a third metal line level) that is vertically spaced from the top surface of the semiconductor substrate 10 at a vertical spacing different from the first vertical spacing and extends laterally along the first horizontal direction hd1. The two additional source lines 65S may be formed at the third metal line level. The first vertical connection structure 660 may provide a first electrical connection between one of the two first source lines 64S and one of the two additional source lines 65S, and the second vertical interconnect structure may provide a second electrical connection between the other of the two first source lines 64S and the other of the two additional source lines 65S. In this configuration, the source lines (64S, 69S, 65S) may be formed at three different metal line levels and may be interconnected to each other by the vertical connection structure 660.

[0082] Reference Figure 4A-4C , by forming an additional source line 67S, the exemplary structure third configuration can be derived from the second configuration of the exemplary structure. In this configuration, the interconnect via structure 66 can also include a ninth via level connecting via structure 669 formed in the ninth metal via level and a tenth via level connecting via structure 66X formed in the tenth metal via level. The line level metal structure 68 can include a ninth line level metal structure 689 formed in the ninth metal line level. Another additional source line 67S can be formed as a subset of the tenth line level metal structure. In the present disclosure, another additional source line 67S can be referred to as a fourth source line, a third source line, a second source line, or a first source line.

[0083] A third configuration of the exemplary structure may include reference Figure 3A-3EEach component within the second configuration of the exemplary structure described. For each combination of a column of access transistors 310 and a column of a resistive memory structure 360, the metal interconnect structure (62, 64, 66, 68) may include: a further additional source line 67S located at a corresponding metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a vertical spacing different from the first vertical spacing and extending laterally along a first horizontal direction hd1; and a vertical connection structure 660 including a plurality of interconnecting via structures 66 and at least one line level metal structure 68, and providing a vertical electrical connection between the two first source lines 64S and the further additional source line 67S. The further additional source line 67S may overlie the bit line 64B connected to the second electrode 366 of the resistive memory structure 360.

[0084] refer to Figure 4D By modifying the layout of the second source lines 69S, the line-level metal structures 68, and the upper-level connecting via structures (such as the fourth via-level connecting via structure 664 and the overlying connecting via structure), an alternative embodiment of the third configuration of the exemplary structure can be derived from the third configuration of the exemplary structure. In this embodiment, the width of each second source line 69S along the second horizontal direction hd2 can be greater than six times the width of each first source line 64S. A first subset of the first source lines 64S has a complete area overlap with the corresponding overlying second source lines 69S, while a second subset of the first source lines 64S has no area overlap with any overlying second source line 69S, or has only a partial overlap with the overlying second source line 69S. Each first source line 64S within the first subset is electrically shorted to the corresponding overlying second source line 69S, which reduces the effective source resistance of the first source lines 64S. Each first source line 64S in the second subset is not only electrically short-circuited with the adjacent first source line 64S, but also electrically short-circuited with a pair of second source lines 69S through two sets of vertical electrical connection structures. The pair of second source lines 69S can significantly reduce the source resistance of each source line 64S in the second subset.

[0085] Reference FIG. 5A to FIG. 5C, by forming further additional source lines (67S', 67S"), the exemplary structure fourth configuration can be derived from the third configuration of the exemplary structure. In this configuration, the interconnect via structure 66 can also include an eleventh via level connecting via structure 66P formed in the eleventh metal via level, a twelfth via level connecting via structure 66Q formed in the twelfth metal via level, a thirteenth via level connecting via structure 66R formed in the thirteenth metal via level, and a fourteenth via level connecting via structure 66S formed in the fourteenth metal via level. The line-level metal structure 68 can include an eleventh line-level metal structure 68P formed in the eleventh metal line level and a thirteenth line-level metal structure 68R formed in the thirteenth metal line level. The further additional source lines (67S', 67S") can be formed as a subset of the twelfth line-level metal structure and the fourteenth line-level metal line structure. In the present disclosure, the other additional source lines ( 67S′, 67S″) may be referred to as a sixth source line, a fifth source line, a fourth source line, a third source line, a second source line, or a first source line.

[0086] A fourth configuration of the exemplary structure may include reference Figure 4A-4C Each component within the second configuration of the exemplary structure described. For each combination of a column of access transistors 310 and a column of a resistive memory structure 360, the metal interconnect structure (62, 64, 66, 68) may include: at least one additional source line (67S', 67S") located at a corresponding metal line level that is vertically spaced from the top surface of the semiconductor substrate 10 by a vertical spacing different from the first vertical spacing and extending laterally along the first horizontal direction hd1; and a vertical connection structure 660, which includes a plurality of interconnecting via structures 66 and at least one line level metal structure 68, and provides a vertical electrical connection between the two first source lines 64S and at least one additional additional source line (67S', 67S"). Each additional source line 67S may overlie a bit line 64B connected to the second electrode 366 of the resistive memory structure 360.

[0087] Common Reference Figures 1A to 5CAccording to various embodiments of the present disclosure, a memory device is provided, which includes: a two-dimensional array of access transistors 310 located on a semiconductor substrate 10; a metal interconnect structure (62, 64, 66, 68) formed in a dielectric material layer 70 and electrically connected to an electrical node of each access transistor in the two-dimensional array of access transistors 310; and a two-dimensional array of resistive memory structures 360 formed in the dielectric material layer 70. The metal interconnect structure (62, 64, 66, 68) includes: two first source lines 64S, which are located at a first metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a first vertical spacing, and extend laterally along the first horizontal direction hd1; second source lines (69S, 65S, 67S, 67S', 67S"), which are located at a second metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a second vertical spacing different from the first vertical spacing, and extend laterally along the first horizontal direction hd1; and a vertical connection structure 660, which includes a plurality of interconnection through-hole structures 66 and at least one line-level metal structure 68, and provides a vertical electrical connection between the two first source lines 64S and the second source lines (69S, 65S, 67S, 67S', 67S")

[0088] In one embodiment, the vertical connection structure 660 extends continuously from the top surfaces of the two first source lines 64S to the bottom surfaces of the second source lines (69S, 65S, 67S, 67S', 67S") In one embodiment, the two-dimensional array of the resistive memory structures 360 is located in a memory array region in a plan view; and the vertical connection structure 660 is located in a vertical connection region that is laterally offset from the memory array region in a plan view.

[0089] In one embodiment, two first source lines 64S extend laterally over a column of access transistors 310 including a group of N access transistors 310 in a two-dimensional array of access transistors 310 and are electrically connected to each source region 332 in the group of N access transistors 310, where N is an integer greater than 1. In one embodiment, the memory device includes two columns of source contact via structures 62S arranged along a first horizontal direction hd1, wherein each source contact via structure 62S contacts a bottom surface of a corresponding one of the two first source lines 64S and contacts a top surface of a source region 332 of a corresponding access transistor 310 in the column of access transistors 310. In one embodiment, each source region 332 in the column of access transistors 310 contacts a corresponding first source contact via structure 62S contacting a bottom surface of one of the two first source lines 64S and contacts a corresponding second source contact via structure 62S contacting a bottom surface of the other of the two first source lines 64S.

[0090] In one embodiment, the multiple interconnecting through-hole structures 66 of the vertical connection structure 660 include two first interconnecting through-hole structures (e.g., two first through-hole level connection through-hole structures 661), each of which contacts the top surface of a corresponding one of the two first source lines 64S and is laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0091] In one embodiment, at least one line-level metal structure 68 includes a first metal pad (including a second line-level metal structure 682), which contacts the top surfaces of two first interconnected via structures (for example, two first via-level connecting via structures 661); the multiple interconnected via structures 66 of the vertical connection structure 660 include a second interconnected via structure (for example, a second via-level connecting via structure 662) that contacts the top surface of the first metal pad (including the second line-level metal structure 682), and the second interconnected via structure (for example, the second line-level connecting via structure 662) is the only metal structure that contacts the top surface of the first metal pad (including the second line-level metal structure 682).

[0092] In one embodiment, the plurality of interconnecting via structures 66 of the vertical connection structure 660 includes at least three additional interconnecting via structures 66 that are vertically spaced apart from each other and have an area overlap therebetween in plan view. Each of the at least three additional interconnecting via structures 66 overlies two first interconnecting vias (e.g., two first via level connection via structures 661).

[0093] In one embodiment, the memory device includes a bit line 64B that overlies a horizontal plane including a top surface of the resistive memory structure 360 ​​and is electrically connected to a top electrode of a column of the resistive memory structure 360 ​​within the two-dimensional array of resistive memory structures 360. A second source line (69S, 65S, 67S, 67S', 67S") overlies the bit line 64B. In one embodiment, the second source line (69S, 65S, 67S, 67S', 67S") has an area overlapping each of the two first source lines 64S in a plan view.

[0094] According to another aspect of the present invention, a memory device is provided, which includes: a column of access transistors 310 located on a semiconductor substrate 10 and arranged along a first horizontal direction hd1; a metal interconnect structure (62, 64, 66, 68) formed in a dielectric material layer 70 and electrically connected to an electrical node of each access transistor in the column of access transistors 310; and a column of resistive memory structures 360 formed in the dielectric material layer 70. The metal interconnect structure (62, 64, 66, 68) includes: two first source lines 64S, which are located at a first metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a first vertical spacing and extend laterally along a first horizontal direction hd1; a first source contact via structure 62S, which contacts the bottom surface of one of the two first source lines 64S; and a second source contact via structure 62S, which contacts the bottom surface of the other of the two first source lines 64S, wherein each source region 332 within a column of the access transistor 310 is respectively contacted with a corresponding one of the first source contact via structure 62S and the second source contact via structure 62S.

[0095] In one embodiment, the metal interconnect structure (62, 64, 66, 68) includes: a second source line (69S, 65S, 67S, 67S', 67S"), which is located at a second metal line level with a second vertical spacing from the top surface of the semiconductor substrate 10 that is different from the first vertical spacing, and extends laterally along the first horizontal direction hd1; and a vertical connection structure 660, which includes a plurality of interconnected via structures 66 and at least one line-level metal structure 68, and provides a vertical electrical connection between two first source lines 64S and the second source lines (69S, 65S, 67S, 67S', 67S").

[0096] In one embodiment, the memory device includes a bit line 64B that overlies a horizontal plane including a top surface of a column of resistive memory structures 360 and is electrically connected to a top electrode within the column of resistive memory structures 360, wherein a second source line (69S, 65S, 67S, 67S', 67S") overlies the bit line 64B.

[0097] In one embodiment, the metal interconnect structure (62, 64, 66, 68) includes: two second source lines (69S, 65S, 67S, 67S', 67S"), which are located at a second metal line level vertically spaced from the top surface of the semiconductor substrate 10 at a second vertical spacing different from the first vertical spacing, and extend laterally along a first horizontal direction hd1; a first vertical connection structure 660, which provides a first electrical connection between one of the two first source lines 64S and one of the two second source lines (69S, 65S, 67S, 67S', 67S"); and a second vertical connection structure 660, which provides a second electrical connection between the other of the two first source lines 64S and the other of the two second source lines (69S, 65S, 67S, 67S', 67S")

[0098] According to one embodiment of the present disclosure, each of the first source line 64S and at least one second source line (69S, 65S, 67S, 67S', 67S") may extend laterally along the same horizontal direction (e.g., the first horizontal direction hd1) and may be formed at corresponding odd-numbered line levels. For example, the first source line 64S may be formed at a first line level, and each of the at least one second source line (69S, 65S, 67S, 67S', 67S") may be formed at a corresponding odd-numbered line level, such as a third line level, a fifth line level, a seventh line level, a ninth line level, etc. There may be at least one odd-numbered level that does not include any source lines.

[0099] According to one embodiment of the present disclosure, the source lines (64S, 69S, 65S, 67S, 67S', 67S") and the bit lines 64B may extend laterally along the same horizontal direction (e.g., the first horizontal direction hd1). Each of the source lines (64S, 69S, 65S, 67S, 67S', 67S") and the bit lines 64B may be formed at a corresponding odd-numbered line level. The word line 64W extends laterally along a horizontal direction (e.g., a second horizontal direction h2) that is different from the lateral extension direction of the source lines (64S, 69S, 65S, 67S, 67S', 67S") and the bit lines 64B. In one embodiment, the word line 64W may be located at an even line level, which may be a second line level, a fourth line level, a sixth line level, etc. In one embodiment, the lateral extension direction (e.g., the second horizontal direction hd2) of the word line 64W may be perpendicular to the lateral extension direction (e.g., the first horizontal direction hd1) of the source lines (64S, 69S, 65S, 67S, 67S', 67S") and the bit lines 64B.

[0100] Figure 6 is a flow chart illustrating steps for forming a memory device according to an embodiment of the present disclosure.

[0101] Referring to steps 610 and Figure 1A-Figure 1C , columns of access transistors 310 may be formed, which may be arranged on the semiconductor substrate 10 along a first horizontal direction hd1.

[0102] Reference steps 620 and Figure 1A-Figure 1C A lower level metal interconnect structure (62, 64) embedded in the lower level dielectric material layer 50 may be formed on the column of access transistors 310. The lower level metal interconnect structure (62, 64) includes two first source lines 64S, which are located at a first metal line level vertically spaced apart from the top surface of the semiconductor substrate 10 by a first vertical spacing, and extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2. Each source region 332 within the column of access transistors 310 is electrically connected to each of the two first source lines 64S.

[0103] Referring to steps 630 and Figure 2A-Figure 5C , a column of resistive memory structures 360 may be formed. Each resistive memory structure 360 ​​within a column of resistive memory structures 360 is electrically connected to a drain region of a corresponding access transistor 310 within the column.

[0104] Refer to step 640 and Figure 2A-Figure 5C , an upper level metal interconnect structure (62, 64, 66, 68) formed in the upper level dielectric material layer 70 can be formed. The upper level metal interconnect structure (62, 64, 66, 68) includes a second source line (69S, 65S, 67S, 67S', 67S"), which is located at a second metal line level vertically spaced from the top surface of the semiconductor substrate 10 by a second vertical spacing different from the first vertical spacing, and extends laterally along the first horizontal direction hd1, and is electrically connected to each of the two first source lines 64S.

[0105] Various embodiments of the present disclosure may be used to provide a memory array including source lines (64S, 69S, 65S, 67S, 67S', 67S") disposed at two or more metal line levels. Replication or multiple levels of source lines (64S, 69S, 65S, 67S, 67S', 67S") may provide a low resistance source side conduction path, reduce source line resistance and provide a stable threshold voltage for access transistor 310, thereby enhancing device stability of the memory array.

[0106] As described above, the present disclosure provides a reduction in source resistance in an RRAM array. By reducing the source resistance, various embodiments disclosed herein can provide an RRAM array having more stable and predictable operating characteristics, enhanced reliability, improved energy efficiency, and superior overall performance. Such enhancements in RRAM arrays allow for memory storage solutions with higher speed and reliability, which continue to grow in demand driven by advances in computing technology and growing data storage needs for a variety of applications.

[0107] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: an array of access transistors located on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer and electrically connected to an electrical node of each access transistor in the array of access transistors; and an array of resistive memory structures located in the dielectric material layer and electrically connected to a corresponding one of the access transistors, wherein the metal interconnect structure comprises: at least one first source line located at a first metal line level and extending laterally along a first horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing; a second source line located at a second metal line level and extending laterally along the first horizontal direction, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the first vertical spacing being different from the first vertical spacing; and a vertical connection structure comprising a plurality of interconnected via structures and at least one line-level metal structure, and providing a vertical electrical connection between at least one first source line and a second source line.

[0108] In some embodiments, the at least one first source line includes two first source lines; and the vertical connection structure continuously extends from top surfaces of the two first source lines to a bottom surface of the second source line.

[0109] In some embodiments, the array of resistive memory structures is located in a memory array region in plan view; and the vertical connection structure is located in a vertical connection region that is laterally offset from the memory array region in plan view.

[0110] In some embodiments, two first source lines extend laterally across a column of access transistors within an access transistor array including a group of N access transistors and are electrically connected to each source region within the group of N access transistors, N being an integer greater than 1.

[0111] In some embodiments, the memory device further comprises two columns of source contact via structures arranged along a first horizontal direction, wherein each source contact via structure contacts a bottom surface of a corresponding one of the two first source lines and contacts a top surface of a source region of a corresponding access transistor within a column of access transistors.

[0112] In some embodiments, each source region within a column of access transistors contacts a corresponding first source contact via structure at a bottom surface of one of the two first source lines and contacts a corresponding second source contact via structure at a bottom surface of the other of the two first source lines.

[0113] In some embodiments, the plurality of interconnect via structures of the vertical connection structure include two first interconnect via structures, each of which contacts a top surface of a corresponding one of the two first source lines and is laterally spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction.

[0114] In some embodiments, at least one line-level metal structure includes a first metal pad contacting the top surfaces of two first interconnect via structures; and a plurality of interconnect via structures of the vertical connection structure include a second interconnect via structure contacting the top surfaces of the first metal pad, the second interconnect via structure being the only metal structure contacting the top surfaces of the first metal pads.

[0115] In some embodiments, the plurality of interconnecting through-hole structures of the vertical connection structure include at least three additional interconnecting through-holes, the at least three additional interconnecting through-holes being vertically spaced apart from each other and having an area overlap between the at least three additional interconnecting through-holes in a plan view, wherein each of the at least three additional interconnecting through-holes covers two first interconnecting through-holes.

[0116] In some embodiments, the memory device also includes a bit line that overlies a horizontal plane that includes a top surface of each of the array of resistive memory structures and is electrically connected to a top electrode of a column of resistive memory structures within the array of resistive memory structures, wherein the second source line overlies the bit line.

[0117] In some embodiments, in a plan view, the second source line has an area overlap with each of the two first source lines.

[0118] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a column of access transistors, located on a semiconductor substrate and arranged along a first horizontal direction; a metal interconnect structure, embedded in a dielectric material layer and electrically connected to an electrical node of each access transistor in the column of access transistors; and a column of resistive memory structures, formed in the dielectric material layer, wherein the metal interconnect structure comprises: two first source lines, located at a first metal line level and extending laterally along a first horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing; a first source contact via structure, located on a bottom surface of one of the two first source lines; and a second source contact via structure, located on a bottom surface of the other of the two first source lines, wherein each source region in the column of access transistors is located on a corresponding one of the first source contact via structures and on a corresponding one of the second source contact via structures.

[0119] In some embodiments, the metal interconnect structure includes: a second source line located at a second metal line level and extending laterally along a first horizontal direction, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the second vertical spacing being different from the first vertical spacing; and a vertical connection structure including a plurality of interconnected via structures and at least one line level metal structure, and providing a vertical electrical connection between two first source lines and a second source line.

[0120] In some embodiments, the memory device further includes a bit line overlying a horizontal plane including a top surface of the column of resistive memory structures and electrically connected to a top electrode within the column of resistive memory structures, wherein the second source line overlies the bit line.

[0121] In some embodiments, the metal interconnect structure includes: two second source lines located at a second metal line level and extending laterally along a first horizontal direction, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the second vertical spacing being different from the first vertical spacing; a first vertical connection structure providing a first electrical connection between one of the two first source lines and one of the two second source lines; and a second vertical connection structure providing a second electrical connection between another one of the two first source lines and another one of the two second source lines.

[0122] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, the method comprising: forming a column of access transistors arranged along a first horizontal direction on a semiconductor substrate; forming a lower-level metal interconnect structure formed in a lower-level dielectric material layer above the column of access transistors, wherein the lower-level metal interconnect structure comprises two first source lines located at a first metal line level, the two first source lines extending laterally along a first horizontal direction and laterally spaced apart from each other along a second horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing, wherein each source region in the column of access transistors is spaced apart from each other by a first vertical spacing. electrically connected to each of the two first source lines; forming a column of resistive memory structures, wherein each resistive memory structure within the column of resistive memory structures is electrically connected to a drain region of a corresponding access transistor within the column of access transistors; and forming an upper level metal interconnect structure formed within the upper level dielectric material layer, wherein the upper level metal interconnect structure includes a second source line at a second metal line level, the second source line extending laterally along a first horizontal direction and electrically connected to each of the two first source lines, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the second vertical spacing being different from the first vertical spacing.

[0123] In some embodiments, the method further includes forming a vertical connection structure vertically connecting the two first source lines and the second source line, wherein the vertical connection structure includes a plurality of interconnected via structures and at least one line-level metal structure.

[0124] In some embodiments, the columns of access transistors are formed in a memory array region; and the vertical connection structures are formed in a vertical connection region that is laterally offset from the memory array region in plan view.

[0125] In some embodiments, the lower level metal interconnect structure includes a column of first source contact via structures and a column of second source contact via structures; one of the two first source lines is formed on the column of the first source contact via structures; the other of the two first source lines is formed on the column of the second source contact via structures; and each source region within the column of the access transistor is respectively in contact with a corresponding one of the first source contact via structures and a corresponding one of the second source contact via structures.

[0126] In some embodiments, the upper level metal interconnect structure includes a bit line overlying a horizontal plane including a top surface of a column of resistive memory structures and electrically connected to a top electrode of the column of resistive memory structures; and a second source line formed over the bit line.

[0127] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Unless otherwise clearly disclosed herein, each embodiment described using the term "including" inherently discloses that in some embodiments, the term "including" can be replaced by "substantially consisting of..." or by the term "consisting of...". In some embodiments, whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, the Markush group (Markush group) of the list including two or more elements can also be implicitly disclosed. Whenever the auxiliary verb "may" is used in this disclosure to explain the formation of elements or the implementation of processing steps, it is also clearly expected that there are embodiments in which such elements or such processing steps are not implemented, provided that the resulting equipment or device can provide equivalent results. In this way, whenever the formation of elements or processing steps are omitted and the same or equivalent results can be provided, the auxiliary verb "may" applied to form such elements or implement such processing steps should also be interpreted as "may" or "may or may not", and equivalent results include slightly better results and slightly worse results. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A memory device, comprising: an array of access transistors located on a semiconductor substrate; a metal interconnect structure formed within the dielectric material layer and electrically connected to an electrical node of each access transistor in the array of access transistors; as well as an array of resistive memory structures located within the dielectric material layer and electrically connected to a corresponding one of the access transistors, Wherein, the metal interconnect structure comprises: at least one first source line located at a first metal line level and extending laterally in a first horizontal direction, the first metal line level being vertically spaced a first vertical spacing from a top surface of the semiconductor substrate; a second source line located at a second metal line level and extending laterally along the first horizontal direction, the second metal line level being vertically spaced apart from the top surface of the semiconductor substrate by a second vertical spacing, the first vertical spacing being different from the first vertical spacing; and A vertical connection structure includes a plurality of interconnecting via structures and at least one line-level metal structure and provides a vertical electrical connection between at least one first source line and a second source line.

2. The memory device according to claim 1, wherein: The at least one first source line includes two first source lines; and The vertical connection structure continuously extends from the top surfaces of the two first source lines to the bottom surface of the second source line.

3. The memory device according to claim 2, wherein: In plan view, the array of resistive memory structures is located within a memory array region; and The vertical connection structure is located in a vertical connection region that is laterally offset from the memory array region in plan view.

4. The memory device according to claim 1, wherein: The two first source lines extend laterally over a column of access transistors in an access transistor array including a group of N access transistors and are electrically connected to each source region in the group of N access transistors, N being an integer greater than 1.

5. The memory device according to claim 4, further comprising two columns of source contact via structures arranged along the first horizontal direction, wherein: Each source contact via structure contacts a bottom surface of a corresponding one of the two first source lines and contacts a top surface of a source region of a corresponding access transistor within the column of access transistors.

6. The memory device according to claim 4, wherein: Each source region within the column of access transistors contacts a corresponding first source contact via structure at a bottom surface of one of the two first source lines and contacts a corresponding second source contact via structure at a bottom surface of the other of the two first source lines.

7. The memory device of claim 1 , further comprising a bit line overlying a horizontal plane including a top surface of each of the array of resistive memory structures and electrically connected to a top electrode of a column of resistive memory structures within the array of resistive memory structures, wherein The second source line overlies the bit line.

8. A memory device comprising: A column of access transistors located on the semiconductor substrate and arranged along a first horizontal direction; a metal interconnect structure embedded in the dielectric material layer and electrically connected to an electrical node of each access transistor in the column of access transistors; as well as a column of resistive memory structures formed within the dielectric material layer, Wherein, the metal interconnect structure comprises: two first source lines located at a first metal line level and extending laterally in a first horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing; A first source contact via structure located on a bottom surface of one of the two first source lines; and A second source contact via structure is located on a bottom surface of the other of the two first source lines, wherein each source region within the column of access transistors is located on a corresponding one of the first source contact via structures and on a corresponding one of the second source contact via structures.

9. A method of forming a memory device, the method comprising: forming columns of access transistors arranged along a first horizontal direction on a semiconductor substrate; forming a lower level metal interconnect structure formed in a lower level dielectric material layer over the column of access transistors, wherein the lower level metal interconnect structure includes two first source lines at a first metal line level, the two first source lines extending laterally along the first horizontal direction and laterally spaced apart from each other along a second horizontal direction, the first metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a first vertical spacing, wherein each source region within the column of access transistors is electrically connected to each of the two first source lines; forming a column of resistive memory structures, wherein each resistive memory structure within the column of resistive memory structures is electrically connected to a drain region of a corresponding access transistor within the column of access transistors; and An upper level metal interconnect structure is formed within the upper level dielectric material layer, wherein the upper level metal interconnect structure includes a second source line at a second metal line level, the second source line extending laterally along the first horizontal direction and electrically connected to each of the two first source lines, the second metal line level being vertically spaced apart from a top surface of the semiconductor substrate by a second vertical spacing, the second vertical spacing being different from the first vertical spacing.

10. The method according to claim 9, wherein: The lower level metal interconnect structure includes a column of first source contact via structures and a column of second source contact via structures; One of the two first source lines is formed on a column of the first source contact via structures; The other of the two first source lines is formed on a column of the second source contact via structures; and Each source region within the column of the access transistors is respectively in contact with a corresponding one of the first source contact via structures and a corresponding one of the second source contact via structures.

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