A trench gate power MOSFET and its manufacturing method

Abstract

The present application provides a trench gate power MOSFET and a manufacturing method thereof, wherein a contact hole with a width larger than the width of the trench structure is formed, and even as the cell size is reduced, the width of the metal-semiconductor contact hole (second contact hole) in the cell is ensured to be wide, so that when platinum metal is deposited, the platinum can be smoothly deposited to the surface of the semiconductor in the contact hole, platinum diffusion is realized to reduce the number of non-equilibrium carriers in the drift region, thereby reducing the reverse recovery loss. The wider contact hole in the present application does not require additional manufacturing processes, and can also reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. In addition, the present application can control the contact hole etching process to make the wider contact hole contact with the body region and the body contact region at the same time to form two kinds of body diodes, thereby reducing the reverse recovery loss and ensuring the surge capacity of the body diode. In addition, the present application can realize better device optimization through the adjustment of the MOS channel.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices and relates to a trench gate power MOSFET and a manufacturing method thereof. Background Art

[0002] Trench-gate power MOSFETs with buried source electrodes have extremely low on-resistance. This is due to the charge compensation effect within the electrode, which significantly increases the doping concentration in the drift region without affecting its breakdown voltage. Furthermore, due to the shielding effect of the buried source electrode from the gate electrode to the drain electrode, trench-gate power MOSFETs with buried source electrodes have extremely low Miller capacitance, making them more advantageous in high-speed switching applications.

[0003] With the continuous improvement of process technology, the cell size of trench gate power MOSFETs with buried source electrodes continues to shrink, which helps to enhance the charge compensation effect within the body, thereby further reducing its on-resistance. For high-speed switching applications, not only do devices need to have extremely low on-resistance and extremely small Miller capacitance, but also low reverse recovery losses in their body diodes.

[0004] For trench-gate power MOSFETs with buried source electrodes, during the conduction period of their body diodes, a large number of unbalanced carriers are injected from the P-type region into the N-type drift region. These unbalanced carriers will cause large reverse recovery losses. By integrating MOS trench diodes, the total amount of unbalanced carriers injected from the P-type region into the N-type region can be effectively reduced, thereby reducing reverse recovery losses. Another effective method is to reduce the number of unbalanced carriers in the drift region through carrier lifetime control technology. Carrier lifetime control technologies include electron irradiation, proton implantation, platinum doping, etc. Among them, platinum doping is widely used due to its extremely low leakage and simple process.

[0005] Integrated MOS trench diodes require a turn-on voltage lower than the PN junction's 0.7V turn-on voltage. This requires a thinner oxide layer or a lower concentration of the P-type base region. A thinner oxide layer requires additional processing and can lead to corresponding reliability issues. A lower concentration of the P-type base region also requires additional processing. Furthermore, due to the lower concentration of the P-type base region, the device may experience punch-through when the drain-source voltage is high. Proton implantation is generally not used alone for carrier lifetime control. Electron irradiation introduces shallower energy levels, while platinum doping introduces deeper energy levels. Therefore, to achieve the same level of carrier lifetime control, the increase in leakage current caused by platinum doping is much lower than that caused by electron irradiation. Typically, platinum doping is performed by depositing or ion implanting platinum onto the semiconductor surface after etching the metal-semiconductor contact hole. However, for trench-gate power MOSFETs with buried source electrodes, whose cell dimensions are constantly decreasing, the metal-semiconductor contact hole depth often exceeds 1 micron, while the hole width is only about 0.4 micron. In actual processes, platinum cannot be deposited in such metal-semiconductor contact holes.

[0006] In view of this, how to provide a trench gate power MOSFET with a buried source electrode that has low manufacturing cost, high reliability, and is suitable for platinum diffusion has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0007] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0008] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a trench gate power MOSFET and a method for manufacturing the same, so as to solve the problem that platinum metal cannot be deposited through contact holes to the semiconductor surface and diffuse under small cell sizes.

[0009] To achieve the above-mentioned and other related objectives, the present invention provides a method for manufacturing a trench gate power MOSFET, comprising the following steps:

[0010] forming a drift layer on a substrate layer, and forming a first trench structure and a second trench structure alternately and spaced apart in a horizontal direction in the drift layer, wherein the first trench structure and the second trench structure both start from a top surface of the drift layer and extend downward, wherein the first trench structure has a gate electrode and a first buried source electrode, and the second trench structure has a second buried source electrode;

[0011] forming a body region on an upper surface layer of the drift layer, and forming a source contact region on an upper surface layer of the body region;

[0012] forming an interlayer dielectric layer above the drift layer, wherein the interlayer dielectric layer covers the first trench structure, the second trench structure, and the source contact region;

[0013] forming first contact holes and second contact holes alternately and spaced apart in a horizontal direction, wherein the width of the first contact holes is smaller than the width of the first trench structure, the first contact holes vertically penetrate the interlayer dielectric layer and extend downward into the first buried source electrode, and the width of the second contact holes is larger than the width of the second trench structure, the second contact holes vertically penetrate the interlayer dielectric layer and extend downward into the second trench structure and the body regions on both sides of the second trench structure;

[0014] forming a body contact region in the body region through the second contact hole, wherein the body contact region is adjacent to the source contact region;

[0015] doping platinum in the drift layer through the second contact hole;

[0016] forming a first contact portion in the first contact hole and forming a second contact portion in the second contact hole;

[0017] A source metal layer is formed on the interlayer dielectric layer, wherein the source metal layer is connected to the first contact portion and the second contact portion.

[0018] Optionally, doping platinum in the drift layer through the second contact hole comprises the following steps:

[0019] forming a platinum metal layer on the inner wall of the second contact hole to obtain a platinum silicide layer;

[0020] removing the platinum metal layer using aqua regia;

[0021] performing annealing to diffuse platinum in the platinum silicide layer into the drift layer;

[0022] The platinum silicide layer is removed.

[0023] Optionally, forming first trench structures and second trench structures alternately and spaced apart in a horizontal direction in the drift layer includes the following steps:

[0024] forming first trenches and second trenches alternately and spaced apart in a horizontal direction in the drift layer, wherein both the first trenches and the second trenches open from the top surface of the drift layer and extend downward;

[0025] forming a field oxide layer on an inner wall of the first trench and an inner wall of the second trench;

[0026] forming a first polysilicon layer in the first trench and in the second trench, wherein the first polysilicon layer in the first trench serves as the first buried source electrode, and the first polysilicon layer in the second trench serves as the second buried source electrode;

[0027] etching back the field oxide layer to form a gate trench in the first trench and a dummy gate trench in the second trench, the gate trench being located on both sides of the first buried source electrode, and the dummy gate trench being located on both sides of the second buried source electrode;

[0028] forming a gate oxide layer on the inner wall of the gate trench and on the inner wall of the dummy gate trench;

[0029] forming a second polysilicon layer in the gate trench and in the dummy gate trench, the second polysilicon layer in the gate trench serving as the gate electrode, and the second polysilicon layer in the dummy gate trench serving as a third buried source electrode.

[0030] Optionally, the body contact region contacts the sidewall of the second trench structure at one end of the second trench structure, all the bottom surfaces of the second contact hole are higher than the bottom surface of the body contact region, or the bottom surface of the portion of the second contact hole between the sidewall of the second trench structure and the outer sidewall of the third buried source electrode is lower than the bottom surface of the body contact region so that the second contact portion is adjacent to the body region.

[0031] Optionally, forming the first trench structure and the second trench structure alternately and spacedly arranged in the horizontal direction in the drift layer comprises the following steps:

[0032] forming the first trench and the second trench alternately and spacedly arranged in the horizontal direction in the drift layer, the first trench and the second trench both being open from the top surface of the drift layer and extending downward;

[0033] forming a field oxide layer on the inner wall of the first trench and on the inner wall of the second trench;

[0034] forming a first polysilicon layer in the first trench and in the second trench, wherein the first polysilicon layer in the first trench serves as the first buried source electrode, and the first polysilicon layer in the second trench serves as the second buried source electrode;

[0035] selectively etching back the field oxide layer in the first trench to form a gate trench in the first trench, the gate trench being located on both sides of the first buried source electrode;

[0036] forming a gate oxide layer on the inner wall of the gate trench;

[0037] A second polysilicon layer is formed in the gate trench to obtain the gate electrode.

[0038] Optionally, one end of the body contact region facing the second trench structure contacts a sidewall of the second trench structure, or one end of the body contact region facing the second trench structure is spaced a preset distance from the sidewall of the second trench structure.

[0039] The present invention also provides a trench gate power MOSFET, comprising:

[0040] substrate layer;

[0041] a drift layer disposed on the substrate layer and doped with platinum;

[0042] a first trench structure and a second trench structure alternately and spaced apart in a horizontal direction, located in the drift layer, wherein both the first trench structure and the second trench structure start from the top surface of the drift layer and extend downward, wherein the first trench structure has a gate electrode and a first buried source electrode, and the second trench structure has a second buried source electrode;

[0043] a body region located on an upper surface of the drift layer;

[0044] a source contact region, located on the upper surface of the body region;

[0045] a body contact region located in the body region and adjacent to the source contact region;

[0046] an interlayer dielectric layer, located above the drift layer and covering the first trench structure, the second trench structure and the source contact region;

[0047] first contact portions and second contact portions alternately and spaced apart in a horizontal direction, wherein the width of the first contact portion is smaller than the width of the first trench structure, the first contact portion vertically penetrates the interlayer dielectric layer and extends downward into the first buried source electrode, and the width of the second contact portion is larger than the width of the second trench structure, the second contact portion vertically penetrates the interlayer dielectric layer and extends downward to contact the second buried source electrode, the source contact region, and the body contact region;

[0048] The source metal layer is located on the interlayer dielectric layer and connected to the first contact portion and the second contact portion.

[0049] Optionally, one end of the body contact region facing the second trench structure contacts a sidewall of the second trench structure, or one end of the body contact region facing the second trench structure is spaced a preset distance from the sidewall of the second trench structure.

[0050] Optionally, the second trench structure further has a third buried source electrode, the third buried source electrode is located on both sides of the second buried source electrode, and the bottom surface of the third buried source electrode is higher than the bottom surface of the second buried source electrode.

[0051] Optionally, one end of the body contact region towards the second trench structure is in contact with the sidewall of the second trench structure, all the bottom surfaces of the second contact part are higher than the bottom surface of the body contact region, or the bottom surface of the part of the second contact part between the sidewall of the second trench structure and the outer sidewall of the third buried source electrode is lower than the bottom surface of the body contact region so that the part of the second contact part between the sidewall of the second trench structure and the outer sidewall of the third buried source electrode is adjacent to the body region.

[0052] As described above, in the manufacturing method of the trench gate power MOSFET of the present application, the first contact hole and the second contact hole are formed in the horizontal direction, which are arranged alternately and spaced apart, corresponding to the first trench structure and the second trench structure arranged alternately and spaced apart in the horizontal direction, wherein the width of the second contact hole is greater than the width of the second trench structure, so that the width of the metal-semiconductor contact hole (the second contact hole) in the cell can be ensured to be wide, and when platinum metal is deposited, the surface of the semiconductor in the contact hole can be smoothly deposited, platinum diffusion is realized to reduce the number of non-equilibrium carriers in the drift region, thereby reducing the reverse recovery loss. In the present application, the wider metal-semiconductor contact hole (the second contact hole) does not require additional manufacturing processes, and the larger contact hole can reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. In addition, in the present application, the contact hole etching process can be controlled so that the second contact hole is in contact with the body region and the body contact region at the same time, thereby forming two kinds of body diodes at the same time, one with high injection efficiency and the other with low injection efficiency. The body diode with low injection efficiency can ensure lower non-equilibrium carrier injection, thereby reducing the reverse recovery loss, and the body diode with high injection efficiency can ensure the surge capacity of the body diode. In addition, the first trench structure has a gate electrode and the second trench structure does not have a gate electrode, and through the adjustment of the MOS channel, better device performance can be achieved, thereby being more advantageous in high-frequency applications. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 A structure schematic diagram of a trench gate power MOSFET with a buried source electrode is shown.

[0054] Figure 2 A process flow chart of the manufacturing method of the trench gate power MOSFET of the present application is shown.

[0055] Figure 3Schematic diagram showing the structure obtained after forming the first trench and the second trench in the drift layer in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0056] Figure 4 It is a schematic diagram showing the structure obtained after forming the field oxide layer in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0057] Figure 5 It is a schematic diagram showing the structure obtained after forming the first buried source electrode and the second buried source electrode in the manufacturing method of the trench gate power MOSFET of the present invention in the first embodiment.

[0058] Figure 6 It is a schematic diagram showing the structure obtained after forming the gate trench and the dummy gate trench in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0059] Figure 7 It is a schematic diagram showing the structure obtained after forming the gate oxide layer in the manufacturing method of the trench gate power MOSFET in Example 1 of the present invention.

[0060] Figure 8 It is a schematic diagram showing the structure obtained after forming the gate electrode and the third buried source electrode in the manufacturing method of the trench gate power MOSFET of the present invention in the first embodiment.

[0061] Figure 9 It is a schematic diagram showing the structure obtained after forming the body region and the source contact region in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0062] Figure 10 It is a schematic diagram showing the structure obtained after forming the interlayer dielectric layer in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0063] Figure 11 It is a schematic diagram showing the structure obtained after forming the first contact hole and the second contact hole in the manufacturing method of the trench gate power MOSFET in the first embodiment of the present invention.

[0064] Figure 12 It is a schematic diagram showing the structure obtained after forming the body contact region in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0065] Figure 13 It is a schematic diagram showing the structure obtained after forming the first contact portion and the second contact portion in the manufacturing method of the trench gate power MOSFET of the present invention in the first embodiment.

[0066] Figure 14It is a schematic diagram showing the structure obtained after forming the source metal layer in the first embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0067] Figure 15 It shows an exemplary structural diagram of a trench gate power MOSFET manufactured by the manufacturing method of the trench gate power MOSFET in Example 2 of the present invention.

[0068] Figure 16 It is a schematic diagram showing the structure obtained after forming the gate trench in the second embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0069] Figure 17 It is a schematic diagram showing the structure obtained after forming the gate oxide layer in the second embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0070] Figure 18 It is a schematic diagram showing the structure obtained after forming the gate electrode in the second embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0071] Figure 19 It is a schematic diagram showing the structure obtained after forming the body region, source contact region and interlayer dielectric layer in the second embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0072] Figure 20 Schematic diagram showing the structure obtained after forming the first contact hole, the second contact hole, the body contact region, the first contact portion, the second contact portion and the source metal layer in the second embodiment of the manufacturing method of the trench gate power MOSFET of the present invention.

[0073] Figure 21 Shown is an exemplary structural schematic diagram of a trench gate power MOSFET manufactured by the manufacturing method of the trench gate power MOSFET in Example 4 of the present invention.

[0074] Component number description

[0075] 101 drain metal layer

[0076] 102 N-type substrate layer

[0077] 103 N-type drift layer

[0078] 104 interlayer dielectric layer

[0079] 105 source metal layer

[0080] 106 groove structure

[0081] 1061 Polysilicon buried source electrode

[0082] 1062 polysilicon gate electrode

[0083] 107 first contact hole

[0084] 108 body region

[0085] 109 source contact region

[0086] 110 body contact region

[0087] 111 second contact hole

[0088] 201 substrate layer

[0089] 202 drift layer

[0090] 203 first trench structure

[0091] 203' second trench structure

[0092] 2031 first buried source electrode

[0093] 2032 gate electrode

[0094] 2033 gate trench

[0095] 204 second trench structure

[0096] 204' second trench

[0097] 2041 second buried source electrode

[0098] 2042 third buried source electrode

[0099] 2043 dummy gate trench

[0100] 205 field oxide layer

[0101] 206 gate oxide layer

[0102] 207 body region

[0103] 208 source contact region

[0104] 209 interlayer dielectric layer

[0105] 210 first contact hole

[0106] 211 second contact hole

[0107] 212 body contact region

[0108] 213 first contact portion

[0109] 214 second contact portion

[0110] 215 source metal layer

[0111] 216 drain metal layer DETAILED DESCRIPTION

[0112] See also Figure 1 , showing a schematic diagram of the structure of a trench gate power MOSFET with a buried source electrode, which includes a drain metal layer 101, an N-type substrate layer 102, an N-type drift layer 103, an interlayer dielectric layer 104 and a source metal layer 105 stacked in sequence from bottom to top, wherein the N-type drift layer 103 is provided with a plurality of spaced trench structures 106, each of which is provided with a polysilicon buried source electrode 1061 and a polysilicon gate electrode 1062, the polysilicon buried source electrode 106 1 is connected to the source metal layer 105 through a first contact hole 107, the polysilicon gate electrode 1062 is connected to the gate metal layer (located in another area) (not shown) through a contact hole (located in another area) (not shown), and a body region 108, a source contact region 109, and a body contact region 110 are provided in the N-type drift layer 103 between two adjacent trench structures. The source contact region 109 and the body contact region 110 are connected to the source metal layer 105 through a second contact hole 111.

[0113] Generally speaking, the width of the second contact hole 111 is relatively narrow, for example, about 0.4 microns, and it is difficult to achieve platinum doping through it. The inventors of this application have improved the structure of the trench gate power MOSFET with a buried source electrode and its manufacturing method through extensive research. As the cell size decreases, it is still possible to ensure that the width of the metal semiconductor contact hole in the cell is relatively wide, so that when platinum metal is deposited, it can be smoothly deposited on the surface of the semiconductor in the contact hole, achieving platinum diffusion to reduce the number of unbalanced carriers in the drift region, thereby reducing reverse recovery loss. At the same time, Figure 1 Compared with the structure shown in FIG, the new structure of the present invention can achieve a better device figure of merit, and thus has more advantages in high-frequency applications.

[0114] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0115] See also Figures 2 to 21It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0116] Example 1

[0117] The present invention provides a method for manufacturing a trench gate power MOSFET. Figure 2 , including the following steps:

[0118] S1: forming a drift layer on a substrate layer, and forming a first trench structure and a second trench structure alternately and spaced apart in a horizontal direction in the drift layer, wherein the first trench structure and the second trench structure both start from a top surface of the drift layer and extend downward, wherein the first trench structure has a gate electrode and a first buried source electrode, and the second trench structure has a second buried source electrode;

[0119] S2: forming a body region on an upper surface layer of the drift layer, and forming a source contact region on an upper surface layer of the body region;

[0120] S3: forming an interlayer dielectric layer above the drift layer, wherein the interlayer dielectric layer covers the first trench structure, the second trench structure, and the source contact region;

[0121] S4: forming first contact holes and second contact holes alternately and spaced apart in a horizontal direction, wherein the width of the first contact holes is smaller than the width of the first trench structure, the first contact holes vertically penetrate the interlayer dielectric layer and extend downward into the first buried source electrode, and the width of the second contact holes is larger than the width of the second trench structure, the second contact holes vertically penetrate the interlayer dielectric layer and extend downward into the second trench structure and the body regions on both sides of the second trench structure;

[0122] S5: forming a body contact region in the body region through the second contact hole, wherein the body contact region is adjacent to the source contact region;

[0123] S6: doping platinum into the drift layer through the second contact hole;

[0124] S7: forming a first contact portion in the first contact hole, and forming a second contact portion in the second contact hole;

[0125] S8: forming a source metal layer on the interlayer dielectric layer, wherein the source metal layer is connected to the first contact portion and the second contact portion.

[0126] First see Figures 3 to 8, perform step S1: forming a drift layer 202 on the substrate layer 201, and forming a first trench structure 203 and a second trench structure 204 alternately and spaced apart in the horizontal direction in the drift layer 202, wherein the first trench structure 203 and the second trench structure 204 both start from the top surface of the drift layer 202 and extend downward, the first trench structure 203 has a gate electrode 2032 and a first buried source electrode 2031, and the second trench structure 204 has a second buried source electrode 2041. In this embodiment, the second trench structure 204 also has a third buried source electrode 2042, and the third buried source electrode 2042 is located on both sides of the second buried source electrode 2041, and the bottom surface of the third buried source electrode 2042 is higher than the bottom surface of the second buried source electrode 2041.

[0127] As an example, the substrate layer 201 may be an N-type semiconductor substrate, including but not limited to an N-type silicon substrate, and the drift layer 202 may be an N-type semiconductor layer epitaxially grown on the substrate layer 201 , including but not limited to an N-type silicon layer.

[0128] As an example, the drift layer 202 may be uniformly doped or graded doped as required.

[0129] As an example, forming the first trench structures 203 and the second trench structures 204 alternately and spaced apart in the horizontal direction in the drift layer 202 includes the following steps:

[0130] like Figure 3 As shown, semiconductor processes such as photolithography and etching are used to form first trenches 203 ′ and second trenches 204 ′ alternately and spaced apart in the horizontal direction in the drift layer 202 . Both the first trenches 203 ′ and the second trenches 204 ′ open from the top surface of the drift layer 202 and extend downward.

[0131] like Figure 4 As shown, an oxide layer is grown using an oxidation method or other suitable method, and the oxide layer outside the trench is removed by etching back, leaving the oxide layer located on the inner wall of the first trench 203' and the inner wall of the second trench 204' as the field oxide layer 205. In this embodiment, the field oxide layer 205 is formed using a dry oxidation method, a wet oxidation method, and a dry oxidation method in sequence, which can achieve both high film quality and a fast growth rate.

[0132] like Figure 5As shown, a first polysilicon layer is formed in the first trench 203' and the second trench 204' by chemical vapor deposition or other suitable methods, and the first polysilicon layer is etched back to remove the polysilicon outside the trench, wherein the first polysilicon layer in the first trench 203' serves as the first buried source electrode 2031, and the first polysilicon layer in the second trench 204' serves as the second buried source electrode 2041.

[0133] like Figure 6 As shown, the field oxide layer 205 is etched back to form a gate trench 2033 in the first trench 203 ′ and a dummy gate trench 2043 in the second trench 204 ′. The gate trench 2033 is located on both sides of the first buried source electrode 2031 , and the dummy gate trench 2043 is located on both sides of the second buried source electrode 2041 .

[0134] like Figure 7 As shown, an oxidation method such as a dry oxygen method is used to form a gate oxide layer 206 on the inner wall of the gate trench 2033 and the inner wall of the dummy gate trench 2043.

[0135] like Figure 8 As shown, a second polysilicon layer is formed in the gate trench 2033 and the dummy gate trench 2043 by chemical vapor deposition or other suitable methods, and the second polysilicon layer is etched back to remove the polysilicon outside the trench, wherein the second polysilicon layer in the gate trench 2033 serves as the gate electrode 2032, and the second polysilicon layer in the dummy gate trench 2043 serves as the third buried source electrode 2042.

[0136] At this point, the first trench structure 203 and the second trench structure 204 are manufactured.

[0137] See also Figure 9 , perform step S2: use ion implantation or other suitable methods to form a body region 207 on the upper surface of the drift layer 202, and use ion implantation or other suitable methods to form a source contact region 208 on the upper surface of the body region 207.

[0138] In this embodiment, an annealing activation step is further included after the ion implantation, wherein the annealing activation process of the body region 207 and the source contact region 208 can be performed at the same time.

[0139] See also Figure 10 , perform step S3: use chemical vapor deposition, physical vapor deposition or other suitable methods to form an interlayer dielectric layer 209 above the drift layer 202, and the interlayer dielectric layer 209 covers the first trench structure 203, the second trench structure 204 and the source contact area 208.

[0140] As an example, the interlayer dielectric layer 209 may include a silicon oxide layer, a silicon nitride layer or other suitable insulating layers.

[0141] See also Figure 11 , perform step S4: use dry etching or other suitable methods to form first contact holes 210 and second contact holes 211 that are alternately and spaced apart in the horizontal direction, the width of the first contact hole 210 is smaller than the width of the first trench structure 203, the first contact hole 210 vertically penetrates the interlayer dielectric layer 209 and extends downward into the first buried source electrode 2031, the width of the second contact hole 211 is larger than the width of the second trench structure 204, the second contact hole 211 vertically penetrates the interlayer dielectric layer 209 and extends downward into the second trench structure 204 and the body region 207 on both sides of the second trench structure 204.

[0142] In this embodiment, by controlling the etching selectivity, the bottom surface of the portion of the second contact hole 211 between the sidewall of the second trench structure 204 and the outer sidewall of the third buried source electrode 2042 is lower than the bottom surface of the remaining portion.

[0143] See also Figure 12 , performing step S5: forming a body contact region 212 in the body region 207 through the second contact hole 211 , wherein the body contact region 212 is adjacent to the source contact region 208 .

[0144] In this embodiment, the direction and depth of ion implantation are controlled so that the body contact region 212 contacts the side wall of the second trench structure 204 toward one end of the second trench structure 204. At the same time, the bottom surface of the second contact hole 211 located between the side wall of the second trench structure 204 and the outer wall of the third buried source electrode 2042 is lower than the bottom surface of the body contact region 212, so that the second contact portion 214 formed subsequently located between the side wall of the second trench structure 204 and the outer wall of the third buried source electrode 2042 can be adjacent to the body region 207.

[0145] Furthermore, the step S6 is performed: platinum is doped into the drift layer 202 through the second contact hole 211 .

[0146] As an example, doping platinum into the drift layer 202 via the second contact hole 211 includes the following steps:

[0147] (1) Depositing a platinum metal layer by sputtering or other suitable methods. In this case, platinum will smoothly enter the second contact hole 211 of larger size and react with silicon at a high temperature (e.g., 300° C.-450° C.) to obtain a platinum silicide layer located on the inner wall of the second contact hole 211.

[0148] (2) removing the platinum metal layer using aqua regia;

[0149] (3) performing annealing to diffuse the platinum in the platinum silicide layer into the drift layer 202;

[0150] (4) Remove the platinum silicide layer by dry etching or other suitable methods.

[0151] See also Figure 13 , performing step S7: forming a first contact portion 213 in the first contact hole 210 , and forming a second contact portion 214 in the second contact hole 211 .

[0152] As an example, the first contact portion 213 and the second contact portion 214 may be tungsten plugs or other suitable conductive plugs, and may be formed by chemical vapor deposition or other suitable methods.

[0153] Specifically, in this embodiment, since the bottom surface of the portion of the second contact hole 211 located between the sidewall of the second trench structure 204 and the outer sidewall of the third buried source electrode 2042 is lower than the bottom surface of the body contact region 212, the portion of the second contact portion 214 formed in this step located between the sidewall of the second trench structure 204 and the outer sidewall of the third buried source electrode 2042 is adjacent to the body region 207, so that the second contact portion 214 is not only in direct contact with the body contact region 212, but also in direct contact with the body. The body contact region 212 is in direct contact with the body region 207, thereby forming two body diodes. One is a first body diode composed of the body contact region 212 (heavily P-type doped), the body region 207 (P-type doped), the drift layer 202 (N-type doped) and the substrate layer 201 (N-type doped). The other is a second body diode composed of the body region 207 (P-type doped), the drift layer 202 (N-type doped) and the substrate layer 201 (N-type doped). Due to the doping concentration of the body contact region 212 (usually 1e19cm -3 ) is much higher than the doping concentration of the body region 207 (the concentration is usually 1e17cm -3 ), during reverse conduction, the turn-on voltage and injection efficiency of the second body diode are lower than those of the first body diode. That is, in this embodiment, the introduction of the second contact hole 211 significantly reduces the injection efficiency of the body diode of the trench gate power MOSFET, thereby achieving less unbalanced carrier injection and thus lower reverse recovery loss.

[0154] See also Figure 14 , performing step S8: forming a source metal layer 215 on the interlayer dielectric layer 209 by chemical vapor deposition, physical vapor deposition, or other suitable methods, wherein the source metal layer 215 connects the first contact portion 213 and the second contact portion 214. The source metal layer 215 may include an aluminum layer or other suitable conductive metal layer.

[0155] In this embodiment, a drain metal layer 216 is further formed on the back surface of the substrate layer 201 .

[0156] Thus, a trench-gate power MOSFET has been fabricated, featuring a second contact hole with a relatively wide width (greater than the width of the second trench structure). Even as the cell size decreases, platinum can still be smoothly deposited onto the semiconductor surface within the contact hole during platinum metal deposition, enabling platinum diffusion to reduce the number of unbalanced carriers in the drift region, thereby reducing reverse recovery losses. The wider second contact hole does not require additional manufacturing processes, and its larger size reduces the thermal resistance of the chip surface, improving the chip's heat dissipation capabilities.

[0157] In addition, by controlling parameters such as the etching selectivity, this embodiment can produce a trench gate power MOSFET having two body diodes, one body diode with high injection efficiency and the other body diode with low injection efficiency. The body diode with low injection efficiency can ensure lower unbalanced carrier injection, thereby reducing reverse recovery loss, and the body diode with high injection efficiency can ensure the surge capability of the body diode.

[0158] In addition, in the trench gate power MOSFET manufactured in this embodiment, the second contact hole 211 on the second trench structure 204 is directly connected to the second polysilicon layer in the second trench structure 204, and Figure 1 In the trench gate power MOSFET with a buried source electrode shown in FIG, the second polysilicon layer in each trench structure is connected to the gate metal layer. That is, in the trench gate power MOSFET manufactured in this embodiment, the first trench structure 203 has a gate electrode, while the second trench structure 204 does not have a gate electrode. Figure 1 The MOS trench density of the trench gate power MOSFET with buried source electrode shown in FIG is doubled. The coupling from gate electrode to drain in the structure made in this embodiment is only Figure 1 That is, the Miller capacitance of the trench gate power MOSFET manufactured in this embodiment is only 1 / 2 of the structure shown in FIG. Figure 11 / 2 of the structure shown. For high voltage power devices, such as but not limited to 150V voltage level trench gate power MOSFET devices with buried source electrodes, reducing the MOS channel density by 1 / 2 will result in an increase of about 10% in on-resistance. Usually, the figure of merit of a power MOSFET device is defined by the product of on-resistance and Miller capacitance. The smaller the product, the better the performance of the device. Through simple calculation, it can be concluded that the figure of merit of the trench gate power MOSFET produced in this embodiment is only Figure 1 That is to say, the present invention can achieve a better device figure of merit through the adjustment of the MOS channel, thus having more advantages in high-frequency applications.

[0159] Example 2

[0160] This embodiment employs substantially the same technical solution as the first embodiment, differing in that, in the method for fabricating a trench-gate power MOSFET provided in the first embodiment, by controlling the etching selectivity and ion implantation conditions, the bottom surface of the portion of the second contact hole 211 located between the sidewall of the second trench structure 204 and the outer sidewall of the third buried source electrode 2042 is lower than the bottom surface of the remaining portion, and the second contact portion 214 is in direct contact not only with the body contact region 212 but also with the body region 207, thereby forming two body diodes with different implantation efficiencies. In contrast, in this embodiment, by controlling the etching selectivity and ion implantation conditions, the bottom surfaces of all portions of the second contact hole 211 are higher than the bottom surface of the body contact region 212, and the portion of the second contact portion 214 located between the sidewall of the second trench structure 204 and the outer sidewall of the third buried source electrode 2042 does not abut the body region 207.

[0161] See also Figure 15 , which shows an exemplary structure of a trench gate power MOSFET fabricated in this embodiment. In this structure, the second contact portion 214 is in direct contact with the body contact region 212 but not with the body region 207. There is only one body diode, formed by the body contact region 212 (heavily P-type doped), the body region 207 (P-type doped), the drift layer 202 (N-type doped), and the substrate layer 201 (N-type doped).

[0162] The trench gate power MOSFET manufactured in this embodiment can also ensure that platinum can be smoothly deposited on the semiconductor surface during platinum metal deposition. The wider metal semiconductor contact hole does not require additional manufacturing processes. At the same time, the larger metal semiconductor contact hole can reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. Through the adjustment of the MOS channel, a better device figure of merit can be achieved, which is more advantageous in high-frequency applications.

[0163] Example 3

[0164] This embodiment and the first embodiment adopt basically the same technical solution, except that, in the method for manufacturing the trench gate power MOSFET provided in the first embodiment, when manufacturing the first trench structure 203 and the second trench structure 204, the second polysilicon layer is simultaneously formed in the two trench structures, while in the method for manufacturing the trench gate power MOSFET provided in this embodiment, when manufacturing the first trench structure 203 and the second trench structure 204, the second polysilicon layer is only formed in the first trench structure 203.

[0165] As an example, the manufacturing method of the trench gate power MOSFET provided in this embodiment first performs the same steps as in the first embodiment. Figures 3 to 5 Basically the same steps are shown.

[0166] Specifically, such as Figure 3 As shown, a drift layer 202 is formed on a substrate layer 201, and semiconductor processes such as photolithography and etching are used to form first trenches 203' and second trenches 204' that are alternately and spaced apart in a horizontal direction in the drift layer 202. The first trenches 203' and the second trenches 204' are both opened from the drift layer 202 and extend downward.

[0167] like Figure 4 As shown, an oxide layer is grown using an oxidation method or other suitable method, and the oxide layer outside the trench is removed by etching back, leaving the oxide layer located on the inner wall of the first trench 203' and the inner wall of the second trench 204' as the field oxide layer 205. In this embodiment, the field oxide layer 205 is formed using a dry oxidation method, a wet oxidation method, and a dry oxidation method in sequence, which can achieve both high film quality and a fast growth rate.

[0168] like Figure 5 As shown, a first polysilicon layer is formed in the first trench 203' and the second trench 204' by chemical vapor deposition or other suitable methods, and the first polysilicon layer is etched back to remove the polysilicon outside the trench, wherein the first polysilicon layer in the first trench 203' serves as the first buried source electrode 2031, and the first polysilicon layer in the second trench 204' serves as the second buried source electrode 2041.

[0169] For details, please refer to Figure 16Next, different from the first embodiment, in this embodiment, the area where the second trench 204' is located is masked, and the field oxide layer 205 in the first trench 203' is selectively etched back to form gate trenches 2033 in the first trench 203'. The gate trenches 2033 are located on both sides of the first buried source electrode 2031. The field oxide layer 205 on the inner wall of the second trench 204' remains at its original height.

[0170] As an example, selective wet etching is performed to etch away the field oxide layer 205 to a certain depth on the surface of the unshielded area. In this step, the wet etching only etches the field oxide layer 205 without etching the silicon drift layer 202, and only a portion of the field oxide layer 205 is etched.

[0171] See also Figure 17 An oxidation method such as a dry oxidation method is used to form a gate oxide layer 206 on the inner wall of the gate trench 2033.

[0172] See also Figure 18 , a second polysilicon layer is formed in the gate trench 2033 using chemical vapor deposition or other suitable methods, and the second polysilicon layer is etched back to remove the polysilicon outside the trench, wherein the second polysilicon layer in the gate trench 2033 serves as the gate electrode 2032.

[0173] At this point, the first trench structure 203 and the second trench structure 204 are fabricated. Unlike the first embodiment, in which the second trench structure 204 includes both the second buried source electrode 2041 and the third buried source electrode 2042, the second trench structure 204 in this embodiment only includes the second buried source electrode 2041 without the third buried source electrodes 2042 located on both sides of the second buried source electrode 2041.

[0174] See also Figure 19 , performing steps basically the same as those in Example 1, forming a body region 207 on the upper surface of the drift layer 202 by ion implantation or other suitable methods, and forming a source contact region 208 on the upper surface of the body region 207 by ion implantation or other suitable methods, and forming an interlayer dielectric layer 209 above the drift layer 202 by chemical vapor deposition, physical vapor deposition or other suitable methods, and the interlayer dielectric layer 209 covering the first trench structure 203, the second trench structure 204 and the source contact region 208.

[0175] See also Figure 20, performing steps substantially similar to those in the first embodiment, dry etching or other suitable methods are used to form first contact holes 210 and second contact holes 211 that are alternately and spaced apart in a horizontal direction. The width of the first contact holes 210 is smaller than the width of the first trench structure 203. The first contact holes 210 vertically penetrate the interlayer dielectric layer 209 and extend downward into the first buried source electrode 2031. The width of the second contact holes 211 is larger than the width of the second trench structure 204. The second contact holes 211 vertically penetrate the interlayer dielectric layer 209 and extend downward into the second trench structure 204 and into the body regions 207 on both sides of the second trench structure 204. Body contact regions 212 are then formed in the body regions 207 through the second contact holes 211. The body contact regions 212 are adjacent to the source contact regions 208. In this embodiment, the direction and depth of ion implantation are controlled so that the body contact regions 212 contact the sidewalls of the second trench structure 204 at one end facing the second trench structure 204. Then, platinum is doped into the drift layer 202 through the second contact hole 211, and then a first contact portion 213 is formed in the first contact hole 210, a second contact portion 214 is formed in the second contact hole 211, and a source metal layer 215 is formed on the interlayer dielectric layer 209. The source metal layer 215 connects the first contact portion 213 and the second contact portion 214.

[0176] In this embodiment, the second trench structure 204 only has the second buried source electrode 2041 but does not have the third buried source electrode 2042 located on both sides of the second buried source electrode 2041. The second contact portion 214 is in direct contact with the body contact region 212 but not in direct contact with the body region 207. There is only one body diode, which is composed of the body contact region 212 (heavily P-type doped), the body region 207 (P-type doped), the drift layer 202 (N-type doped) and the substrate layer 201 (N-type doped).

[0177] The trench gate power MOSFET manufactured in this embodiment can also ensure that platinum can be smoothly deposited on the semiconductor surface during platinum metal deposition. The wider metal semiconductor contact hole does not require additional manufacturing processes. At the same time, the larger metal semiconductor contact hole can reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. Through the adjustment of the MOS channel, a better device figure of merit can be achieved, which is more advantageous in high-frequency applications.

[0178] Example 4

[0179] This embodiment and the third embodiment adopt basically the same technical solution, except that, in the method for manufacturing the trench gate power MOSFET provided in the third embodiment, the body contact region 212 is in contact with the side wall of the second trench structure 204 by controlling the direction and depth of ion implantation, while in this embodiment, the body contact region 212 is in contact with the side wall of the second trench structure 204 by controlling the direction and depth of ion implantation. As a result, the second contact portion 214 is in direct contact not only with the body contact region 212 but also with the body region 207, thereby forming two body diodes with different injection efficiencies.

[0180] See also Figure 21 , which shows an example structural diagram of a trench gate power MOSFET manufactured in this embodiment. This trench gate power MOSFET can ensure that platinum can be smoothly deposited on the semiconductor surface when platinum metal is deposited when the cell size is reduced. The wider metal semiconductor contact hole does not require additional manufacturing processes. At the same time, the larger metal semiconductor contact hole can reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. Of the two body diodes, the body diode with low injection efficiency can ensure lower unbalanced carrier injection, thereby reducing reverse recovery loss, and the body diode with high injection efficiency can ensure the surge capability of the body diode. By adjusting the MOS channel, a better device figure of merit can be achieved, which is more advantageous in high-frequency applications.

[0181] Example 5

[0182] This embodiment provides a trench gate power MOSFET. Figure 14 , which is a schematic diagram of an example structure of the trench gate power MOSFET, which can be manufactured using the manufacturing method described in Example 1 or other suitable methods.

[0183] Specifically, such as Figure 14As shown, the trench gate power MOSFET includes a substrate layer 201, a drift layer 202, a first trench structure 203, a second trench structure 204, a body region 207, a source contact region 208, a body contact region 212, an interlayer dielectric layer 209, a first contact portion 210, a second contact portion 211 and a source metal layer 215, wherein the drift layer 202 is located on the substrate layer 201 and is doped with platinum; the first trench structure 203 and the second trench structure 204 are located on the drift layer 20 2 and are arranged alternately and spaced apart in the horizontal direction, the first trench structure 203 and the second trench structure 204 both start from the top surface of the drift layer 202 and extend downward, the first trench structure 203 has a gate electrode 2032 and a first buried source electrode 2031, and the second trench structure 204 has a second buried source electrode 2041; the body region 207 is located on the upper surface of the drift layer 202; the source contact region 208 is located on the upper surface of the body region 207; the body contact Region 212 is located in the body region 207 and is adjacent to the source contact region 208; the interlayer dielectric layer 209 is located above the drift layer 202 and covers the first trench structure 203, the second trench structure 204 and the source contact region 208; the first contact portions 210 and the second contact portions 211 are alternately and spaced apart in the horizontal direction, the width of the first contact portion 210 is smaller than the width of the first trench structure 203, the first contact portion 210 vertically penetrates the interlayer dielectric layer 209 and extends downward into the first buried source electrode 2031, the width of the second contact portion 211 is larger than the width of the second trench structure 204, the second contact portion 211 vertically penetrates the interlayer dielectric layer 209 and extends downward to contact the second buried source electrode 2041, the source contact region 208 and the body contact region 212; the source metal layer 215 is located on the interlayer dielectric layer 209 and connects the first contact portion 210 and the second contact portion 211.

[0184] As an example, the second trench structure 204 further includes a third buried source electrode 2042 . The third buried source electrode 2042 is located on both sides of the second buried source electrode 2041 . The bottom surface of the third buried source electrode 2042 is higher than the bottom surface of the second buried source electrode 2041 .

[0185] As an example, the body contact region 212 contacts the side wall of the second trench structure 204 toward one end of the second trench structure 204, and the bottom surface of the second contact portion 214 located between the side wall of the second trench structure 204 and the outer wall of the third buried source electrode 2042 is lower than the bottom surface of the body contact region 212 so that the second contact portion 214 located between the side wall of the second trench structure 204 and the outer wall of the third buried source electrode 2042 is adjacent to the body region 207, so that the second contact portion 214 is not only in direct contact with the body contact region 212, but also in direct contact with the body region 207, thereby forming two body diodes with different injection efficiencies, one is a first body diode formed by the body contact region 212, the body region 207, the drift layer 202 and the substrate layer 201, and the other is a second body diode formed by the body region 207, the drift layer 202 and the substrate layer 201.

[0186] Example 6

[0187] This embodiment provides a trench gate power MOSFET. Figure 15 , which is a schematic diagram of an example structure of the trench gate power MOSFET, which can be manufactured using the manufacturing method described in Example 2 or other suitable methods.

[0188] Specifically, such as Figure 15As shown, the trench gate power MOSFET includes a substrate layer 201, a drift layer 202, a first trench structure 203, a second trench structure 204, a body region 207, a source contact region 208, a body contact region 212, an interlayer dielectric layer 209, a first contact portion 210, a second contact portion 211 and a source metal layer 215, wherein the drift layer 202 is located on the substrate layer 201 and is doped with platinum; the first trench structure 203 and the second trench structure 204 are located on the drift layer 20 2 and are arranged alternately and spaced apart in the horizontal direction, the first trench structure 203 and the second trench structure 204 both start from the top surface of the drift layer 202 and extend downward, the first trench structure 203 has a gate electrode 2032 and a first buried source electrode 2031, and the second trench structure 204 has a second buried source electrode 2041; the body region 207 is located on the upper surface of the drift layer 202; the source contact region 208 is located on the upper surface of the body region 207; the body contact Region 212 is located in the body region 207 and is adjacent to the source contact region 208; the interlayer dielectric layer 209 is located above the drift layer 202 and covers the first trench structure 203, the second trench structure 204 and the source contact region 208; the first contact portions 210 and the second contact portions 211 are alternately and spaced apart in the horizontal direction, the width of the first contact portion 210 is smaller than the width of the first trench structure 203, the first contact portion 210 vertically penetrates the interlayer dielectric layer 209 and extends downward into the first buried source electrode 2031, the width of the second contact portion 211 is larger than the width of the second trench structure 204, the second contact portion 211 vertically penetrates the interlayer dielectric layer 209 and extends downward to contact the second buried source electrode 2041, the source contact region 208 and the body contact region 212; the source metal layer 215 is located on the interlayer dielectric layer 209 and connects the first contact portion 210 and the second contact portion 211.

[0189] As an example, the second trench structure 204 further includes a third buried source electrode 2042 . The third buried source electrode 2042 is located on both sides of the second buried source electrode 2041 . The bottom surface of the third buried source electrode 2042 is higher than the bottom surface of the second buried source electrode 2041 .

[0190] As an example, one end of the body contact region 212 facing the second trench structure 204 contacts a sidewall of the second trench structure 204 .

[0191] Compared with the trench gate power MOSFET in Example 5, in the trench gate power MOSFET in this embodiment, all bottom surfaces of the second contact portion 214 are higher than the bottom surface of the body contact region 212, so that the second contact portion 214 is in direct contact with the body contact region 212 but not in direct contact with the body region 207, forming only a body diode.

[0192] Example 7

[0193] This embodiment provides a trench gate power MOSFET. Figure 20 , which is a schematic diagram of an example structure of the trench gate power MOSFET, which can be manufactured using the manufacturing method described in Example 3 or other suitable methods.

[0194] Specifically, such as Figure 20 As shown, the trench gate power MOSFET includes a substrate layer 201, a drift layer 202, a first trench structure 203, a second trench structure 204, a body region 207, a source contact region 208, a body contact region 212, an interlayer dielectric layer 209, a first contact portion 210, a second contact portion 211 and a source metal layer 215, wherein the drift layer 202 is located on the substrate layer 201 and is doped with platinum; the first trench structure 203 and the second trench structure 204 are located on the drift layer 20 2 and are arranged alternately and spaced apart in the horizontal direction, the first trench structure 203 and the second trench structure 204 both start from the top surface of the drift layer 202 and extend downward, the first trench structure 203 has a gate electrode 2032 and a first buried source electrode 2031, and the second trench structure 204 has a second buried source electrode 2041; the body region 207 is located on the upper surface of the drift layer 202; the source contact region 208 is located on the upper surface of the body region 207; the body contact Region 212 is located in the body region 207 and is adjacent to the source contact region 208; the interlayer dielectric layer 209 is located above the drift layer 202 and covers the first trench structure 203, the second trench structure 204 and the source contact region 208; the first contact portions 210 and the second contact portions 211 are alternately and spaced apart in the horizontal direction, the width of the first contact portion 210 is smaller than the width of the first trench structure 203, the first contact portion 210 vertically penetrates the interlayer dielectric layer 209 and extends downward into the first buried source electrode 2031, the width of the second contact portion 211 is larger than the width of the second trench structure 204, the second contact portion 211 vertically penetrates the interlayer dielectric layer 209 and extends downward to contact the second buried source electrode 2041, the source contact region 208 and the body contact region 212; the source metal layer 215 is located on the interlayer dielectric layer 209 and connects the first contact portion 210 and the second contact portion 211.

[0195] As an example, the body contact region 212 is in contact with the sidewall of the second trench structure 204 at one end of the second trench structure 204.

[0196] Compared with the trench gate power MOSFET in Embodiment Five, the trench gate power MOSFET in this embodiment has only the second buried source electrode 2041 in the second trench structure 204 without the third buried source electrode 2042 on both sides of the second buried source electrode 2041, and the second contact portion 214 is in direct contact with the body contact region 212 but not in direct contact with the body region 207, only forming a body diode.

[0197] Embodiment Eight

[0198] In this embodiment, a trench gate power MOSFET is provided, please refer to Figure 21 , which shows a schematic diagram of an example structure of the trench gate power MOSFET, which can be made by the manufacturing method described in Embodiment Four or other suitable methods.

[0199] Specifically, as Figure 21As shown, the trench gate power MOSFET includes a substrate layer 201, a drift layer 202, a first trench structure 203, a second trench structure 204, a body region 207, a source contact region 208, a body contact region 212, an interlayer dielectric layer 209, a first contact portion 210, a second contact portion 211 and a source metal layer 215, wherein the drift layer 202 is located on the substrate layer 201 and is doped with platinum; the first trench structure 203 and the second trench structure 204 are located on the drift layer 20 2 and are arranged alternately and spaced apart in the horizontal direction, the first trench structure 203 and the second trench structure 204 both start from the top surface of the drift layer 202 and extend downward, the first trench structure 203 has a gate electrode 2032 and a first buried source electrode 2031, and the second trench structure 204 has a second buried source electrode 2041; the body region 207 is located on the upper surface of the drift layer 202; the source contact region 208 is located on the upper surface of the body region 207; the body contact Region 212 is located in the body region 207 and is adjacent to the source contact region 208; the interlayer dielectric layer 209 is located above the drift layer 202 and covers the first trench structure 203, the second trench structure 204 and the source contact region 208; the first contact portions 210 and the second contact portions 211 are alternately and spaced apart in the horizontal direction, the width of the first contact portion 210 is smaller than the width of the first trench structure 203, the first contact portion 210 vertically penetrates the interlayer dielectric layer 209 and extends downward into the first buried source electrode 2031, the width of the second contact portion 211 is larger than the width of the second trench structure 204, the second contact portion 211 vertically penetrates the interlayer dielectric layer 209 and extends downward to contact the second buried source electrode 2041, the source contact region 208 and the body contact region 212; the source metal layer 215 is located on the interlayer dielectric layer 209 and connects the first contact portion 210 and the second contact portion 211.

[0200] As an example, one end of the body contact region 212 facing the second trench structure 204 is spaced apart from a sidewall of the second trench structure 204 by a preset distance.

[0201] Compared to the trench-gate power MOSFET in the fifth embodiment, the second trench structure 204 of the trench-gate power MOSFET in this embodiment only has the second buried source electrode 2041 and does not have the third buried source electrodes 2042 located on both sides of the second buried source electrode 2041. Compared to the trench-gate power MOSFET in the seventh embodiment, in the trench-gate power MOSFET in this embodiment, the second contact portion 214 is in direct contact not only with the body contact region 212 but also with the body region 207, thereby forming two body diodes with different injection efficiencies.

[0202] It should be noted that the present invention can also partially use the structure of the above embodiment in one device, that is, another part can use Figure 1 The conventional structure shown in FIG. 1 is used to individually adjust the product of the device's on-capacitance and Miller capacitance.

[0203] In summary, in the method for manufacturing a trench-gate power MOSFET of the present invention, corresponding to the first trench structure and the second trench structure that are alternately and spaced apart in the horizontal direction, first contact holes and second contact holes that are alternately and spaced apart in the horizontal direction are formed, wherein the width of the second contact hole is greater than the width of the second trench structure. Even as the cell size decreases, the width of the metal-semiconductor contact hole (second contact hole) in the cell can still be ensured to be relatively wide, thereby ensuring that when platinum metal is deposited, it can be smoothly deposited on the surface of the semiconductor in the contact hole, achieving platinum diffusion to reduce the number of unbalanced carriers in the drift region, thereby reducing reverse recovery loss. In the present invention, the wider metal-semiconductor contact hole (second contact hole) does not require additional manufacturing processes. At the same time, the larger contact hole can reduce the thermal resistance of the chip surface and improve the heat dissipation capacity of the chip. In addition, the present invention can control the contact hole etching process so that the second contact hole contacts the body region and the body contact region at the same time, thereby forming two body diodes at the same time, one with high injection efficiency and one with low injection efficiency. The body diode with low injection efficiency can ensure lower unbalanced carrier injection, thereby reducing reverse recovery loss, and the body diode with high injection efficiency can ensure the surge capability of the body diode. In addition, the first trench structure of the present invention has a gate electrode and the second trench structure does not have a gate electrode. Through this adjustment of the MOS channel, a better device figure of merit can be achieved, which is more advantageous in high-frequency applications. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0204] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for manufacturing a trench gate power MOSFET, characterized in that: The following steps are involved: forming a drift layer on a substrate layer, and forming a first trench structure and a second trench structure alternately and spaced apart in a horizontal direction in the drift layer, wherein the first trench structure and the second trench structure both start from a top surface of the drift layer and extend downward, wherein the first trench structure has a gate electrode and a first buried source electrode, and the second trench structure has a second buried source electrode; forming a body region on an upper surface layer of the drift layer, and forming a source contact region on an upper surface layer of the body region; forming an interlayer dielectric layer above the drift layer, wherein the interlayer dielectric layer covers the first trench structure, the second trench structure, and the source contact region; forming first contact holes and second contact holes alternately and spaced apart in a horizontal direction, wherein the width of the first contact holes is smaller than the width of the first trench structure, the first contact holes vertically penetrate the interlayer dielectric layer and extend downward into the first buried source electrode, and the width of the second contact holes is larger than the width of the second trench structure, the second contact holes vertically penetrate the interlayer dielectric layer and extend downward into the second trench structure and the body regions on both sides of the second trench structure; forming a body contact region in the body region through the second contact hole, wherein the body contact region is adjacent to the source contact region; doping platinum in the drift layer through the second contact hole; forming a first contact portion in the first contact hole and forming a second contact portion in the second contact hole; A source metal layer is formed on the interlayer dielectric layer, wherein the source metal layer is connected to the first contact portion and the second contact portion.

2. The method for manufacturing a trench gate power MOSFET according to claim 1, wherein: Doping platinum in the drift layer through the second contact hole comprises the following steps: forming a platinum metal layer on the inner wall of the second contact hole to obtain a platinum silicide layer; removing the platinum metal layer using aqua regia; performing annealing to diffuse platinum in the platinum silicide layer into the drift layer; The platinum silicide layer is removed.

3. The method for manufacturing a trench gate power MOSFET according to claim 1, wherein: Forming first trench structures and second trench structures alternately and spaced apart in a horizontal direction in the drift layer includes the following steps: forming first trenches and second trenches alternately and spaced apart in a horizontal direction in the drift layer, wherein both the first trenches and the second trenches open from the top surface of the drift layer and extend downward; forming a field oxide layer on an inner wall of the first trench and an inner wall of the second trench; forming a first polysilicon layer in the first trench and the second trench, wherein the first polysilicon layer in the first trench serves as the first buried source electrode, and the first polysilicon layer in the second trench serves as the second buried source electrode; etching back the field oxide layer to form a gate trench in the first trench and a dummy gate trench in the second trench, wherein the gate trench is located on both sides of the first buried source electrode and the dummy gate trench is located on both sides of the second buried source electrode; forming a gate oxide layer on the inner wall of the gate trench and the inner wall of the dummy gate trench; A second polysilicon layer is formed in the gate trench and the dummy gate trench, the second polysilicon layer in the gate trench serves as the gate electrode, and the second polysilicon layer in the dummy gate trench serves as a third buried source electrode.

4. The method for manufacturing a trench gate power MOSFET according to claim 3, wherein: The body contact region contacts the side wall of the second trench structure toward one end of the second trench structure, and all bottom surfaces of the second contact holes are higher than the bottom surface of the body contact region, or the bottom surface of a portion of the second contact hole located between the side wall of the second trench structure and the outer side wall of the third buried source electrode is lower than the bottom surface of the body contact region so that a portion of the second contact portion located between the side wall of the second trench structure and the outer side wall of the third buried source electrode is adjacent to the body region.

5. The method for manufacturing a trench gate power MOSFET according to claim 1, wherein: Forming first trench structures and second trench structures alternately and spaced apart in a horizontal direction in the drift layer includes the following steps: forming first trenches and second trenches alternately and spaced apart in a horizontal direction in the drift layer, wherein both the first trenches and the second trenches open from the top surface of the drift layer and extend downward; forming a field oxide layer on an inner wall of the first trench and an inner wall of the second trench; forming a first polysilicon layer in the first trench and the second trench, wherein the first polysilicon layer in the first trench serves as the first buried source electrode, and the first polysilicon layer in the second trench serves as the second buried source electrode; Selectively etching back the field oxide layer in the first trench to form a gate trench in the first trench, wherein the gate trench is located on both sides of the first buried source electrode; forming a gate oxide layer on an inner wall of the gate trench; A second polysilicon layer is formed in the gate trench to obtain the gate electrode.

6. The method for manufacturing a trench gate power MOSFET according to claim 5, wherein: One end of the body contact region facing the second trench structure contacts the sidewall of the second trench structure, or one end of the body contact region facing the second trench structure is spaced a preset distance from the sidewall of the second trench structure.

7. A trench gate power MOSFET, characterized in that: include: substrate layer; a drift layer disposed on the substrate layer and doped with platinum; a first trench structure and a second trench structure alternately and spaced apart in a horizontal direction, located in the drift layer, wherein both the first trench structure and the second trench structure start from the top surface of the drift layer and extend downward, wherein the first trench structure has a gate electrode and a first buried source electrode, and the second trench structure has a second buried source electrode; a body region located on an upper surface of the drift layer; a source contact region, located on the upper surface of the body region; a body contact region located in the body region and adjacent to the source contact region; an interlayer dielectric layer, located above the drift layer and covering the first trench structure, the second trench structure and the source contact region; first contact portions and second contact portions alternately and spaced apart in a horizontal direction, wherein the width of the first contact portion is smaller than the width of the first trench structure, the first contact portion vertically penetrates the interlayer dielectric layer and extends downward into the first buried source electrode, and the width of the second contact portion is larger than the width of the second trench structure, the second contact portion vertically penetrates the interlayer dielectric layer and extends downward to contact the second buried source electrode, the source contact region, and the body contact region; The source metal layer is located on the interlayer dielectric layer and connected to the first contact portion and the second contact portion.

8. The trench gate power MOSFET according to claim 7, wherein: One end of the body contact region facing the second trench structure contacts the sidewall of the second trench structure, or one end of the body contact region facing the second trench structure is spaced a preset distance from the sidewall of the second trench structure.

9. The trench gate power MOSFET according to claim 7, wherein: The second trench structure further includes a third buried source electrode. The third buried source electrode is located on both sides of the second buried source electrode. The bottom surface of the third buried source electrode is higher than the bottom surface of the second buried source electrode.

10. The trench gate power MOSFET according to claim 9, wherein: The body contact region contacts the side wall of the second trench structure toward one end of the second trench structure, and all bottom surfaces of the second contact portions are higher than the bottom surface of the body contact region, or the bottom surface of a portion of the second contact portion located between the side wall of the second trench structure and the outer side wall of the third buried source electrode is lower than the bottom surface of the body contact region so that the portion of the second contact portion located between the side wall of the second trench structure and the outer side wall of the third buried source electrode is adjacent to the body region.

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