A novel method for preparing a power device and a power device

Abstract

The present application discloses a method for preparing a novel power device and a power device, which relates to the technical field of power semiconductor devices and can solve the problem of power devices burning out due to thermal instability in hot-swap circuits. The method is used to prepare a power device, which includes a plurality of units with different threshold voltages. When the power device is turned on, it is turned on in the order of threshold voltage from low to high, including: etching a plurality of grooves on the first surface of the substrate, each groove including a corresponding gate region, the gate polysilicon is located in the gate region, a first channel is formed between the first side of the gate polysilicon and the source, a second channel is formed between the second side of the gate polysilicon and the source, and the source is formed in the substrate under the gate oxide layer between two adjacent gate regions; according to the length of the first channel and the length of the second channel, a plurality of gates are formed, and the plurality of gates and the source form a plurality of different threshold voltages; a drain is formed on the second surface of the substrate.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a preparation method of a novel power device and a power device. Background Art

[0002] For high-availability network equipment, it is necessary to have a near-zero downtime rate throughout its entire life cycle. If a single board of a network device fails or needs to be upgraded, it needs to be replaced without interrupting other single boards of the network device, that is, the single board that fails or needs to be upgraded is removed from the network device, and a new single board is inserted into the network device. This process is called hot swapping, the single board is called a hot-swappable single board, and the circuit used on the single board is called a hot-swappable circuit.

[0003] With the widespread use of hot-swap circuits, hot-swap circuits may be used in high-power application scenarios.

[0004] Current power devices are usually single-threshold voltage devices, which have the problem of burning out due to thermal instability in hot-swap circuits. Summary of the invention

[0005] The present application provides a novel method for preparing a power device and a power device, which can solve the problem of power devices in hot-swap circuits being burned out due to thermal instability.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] A method for preparing a novel power device provided in an embodiment of the present application is used to prepare a power device, wherein the power device includes a plurality of units with different threshold voltages, and when the power device is turned on, it is turned on in the order of threshold voltages from low to high. The method includes:

[0008] A plurality of grooves are formed by etching on a first surface of the substrate, each of the grooves includes a corresponding gate region, the gate polysilicon is located in the gate region, a first channel is formed between a first side of the gate polysilicon and a source, a second channel is formed between a second side of the gate polysilicon and the source, and the source is formed in the substrate under the gate oxide layer between two adjacent gate regions;

[0009] According to the length of the first channel and the length of the second channel, a plurality of gates are formed, wherein the plurality of gates and the source form a plurality of different threshold voltages;

[0010] A drain is formed on the second surface of the substrate.

[0011] As a possible implementation manner, the gate includes a first gate and a second gate, a first channel of the first gate and a second channel of the first gate have the same length, a first channel of the second gate and a second channel of the second gate have the same length, and a length of the first channel of the first gate is less than a length of the first channel of the second gate;

[0012] The forming of a plurality of gates according to the length of the first channel and the length of the second channel comprises:

[0013] Filling gate polysilicon in the gate region in the first trench to obtain a first gate;

[0014] After etching the two side walls of the corresponding second trench in the gate region into a step shape, gate polysilicon is filled to obtain a second gate.

[0015] As a possible implementation manner, the length of the first channel of the gate is greater than the length of the second channel of the gate; and the forming of a plurality of gates according to the length of the first channel and the length of the second channel includes:

[0016] The first side wall of the corresponding trench in each gate region is etched into a first step, and the second side wall is etched into a second step, and then gate polysilicon is filled, wherein the side wall length of the trench corresponding to the first step is greater than the side wall length of the trench corresponding to the second step.

[0017] As a possible implementation manner, the length of the first channel of the gate is greater than the length of the second channel of the gate; and the forming of a plurality of gates according to the length of the first channel and the length of the second channel includes:

[0018] After a side wall of a corresponding trench in each gate region is etched into a step shape, gate polysilicon is filled in the gate region in the trench.

[0019] As a possible implementation manner, after etching a plurality of grooves on the first surface of the substrate, the method further includes:

[0020] Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with a first polysilicon;

[0021] Etching the first polysilicon to expose the gate region to obtain shielding gate polysilicon;

[0022] A dielectric layer is formed on the shielding gate polysilicon, and the gate region is located on the dielectric layer.

[0023] As a possible implementation manner, etching two sidewalls of the corresponding second trench in the gate region into a step shape includes:

[0024] After the oxide layer on the surface of the trench opening is polished, the two side walls of the trench corresponding to the gate region are etched into a step shape using photoresist.

[0025] As a possible implementation manner, after forming the plurality of gates, the method further includes:

[0026] A first conductive type body region is first formed in the substrate under the gate oxide layer between two adjacent gate regions by ion implantation, and a second conductive type doped region is formed on the first conductive type body region to obtain the source electrode.

[0027] As a possible implementation manner, after obtaining the source electrode, the method further includes:

[0028] forming a passivation layer on the gate oxide layer;

[0029] After forming an etched hole in the passivation layer, a hole-etched surface is obtained, and the etched hole is etched into the source electrode.

[0030] As a possible implementation manner, after the etching hole is formed in the passivation layer to obtain the hole etching surface, the method further includes:

[0031] A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source electrode through the etching hole.

[0032] In a second aspect of an embodiment of the present application, a power device is provided, the power device comprising:

[0033] A substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves, each of the grooves comprising a corresponding gate region, the gate polysilicon being located in the gate region, a first channel being formed between a first side surface of the gate polysilicon and a source electrode, and a second channel being formed between a second side surface of the gate polysilicon and the source electrode;

[0034] A plurality of gates, each gate being formed according to a length of a corresponding first trench and a length of the second trench;

[0035] A source electrode is formed in the substrate below the gate oxide layer between two adjacent gate regions;

[0036] A drain is formed on the second surface of the substrate.

[0037] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0038] The preparation method of the novel power device provided in the embodiment of the present application is to form a plurality of grooves by etching on the first surface of the substrate, each of the grooves includes a corresponding gate region, the gate polysilicon is located in the gate region, a first channel is formed between the first side of the gate polysilicon and the source, a second channel is formed between the second side of the gate polysilicon and the source, and the source is formed in the substrate under the gate oxide layer between two adjacent gate regions; a plurality of gates are formed according to the length of the first channel and the length of the second channel; a drain is formed on the second surface of the substrate. The power device prepared by the preparation method of the novel power device provided in the present application can form a plurality of different threshold voltage units in one device, and the safe operating area SOA of the device can be expanded, so that when the device is turned on, the low threshold voltage unit is turned on first, and the high threshold voltage unit is not turned on, and this part generates almost no current, generates no heat and participates in heat dissipation, which greatly reduces the possibility of the device burning out due to thermal instability. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A flow chart of a method for preparing a novel power device provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application Figure 1 ;

[0041] Figure 3 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application Figure 2 ;

[0042] Figure 4 A schematic diagram of a longitudinal section of a power device provided in an embodiment of the present application Figure 3 .

[0043] Reference numerals:

[0044] 1- oxide layer, 2- shielding gate polysilicon, 3- gate polysilicon, 4- source, 5- passivation layer, 6- gate oxide layer, 7- metal electrode, 8- drain, 9- dielectric layer. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0047] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0048] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] The present application provides a method for preparing a power device, such as Figure 1 As shown, the method is used to prepare a power device, wherein the power device includes a plurality of units with different threshold voltages. When the power device is turned on, it is turned on in the order of threshold voltages from low to high. The method includes the following steps:

[0050] Step 101, etching a plurality of grooves on a first surface of a substrate, each of the grooves including a corresponding gate region, a gate polysilicon located in the gate region, a first channel formed between a first side of the gate polysilicon and a source, a second channel formed between a second side of the gate polysilicon and the source, and the source formed in the substrate under the gate oxide layer between two adjacent gate regions;

[0051] Step 102: forming a plurality of gates according to the length of the first channel and the length of the second channel, wherein the plurality of gates and the source electrode form a plurality of different threshold voltages;

[0052] Step 103: forming a drain on the second surface of the substrate.

[0053] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.

[0054] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The gate region and source of the power device are formed on the first surface. The drain of the power device is formed on the second surface of the substrate.

[0055] Optionally, the gate includes a first gate and a second gate, the first channel of the first gate and the second channel of the first gate have the same length, the first channel of the second gate and the second channel of the second gate have the same length, and the length of the first channel of the first gate is less than the length of the first channel of the second gate;

[0056] The forming of a plurality of gates according to the length of the first channel and the length of the second channel comprises:

[0057] Filling gate polysilicon in the gate region in the first trench to obtain a first gate;

[0058] After etching the two side walls of the corresponding second trench in the gate region into a step shape, gate polysilicon is filled to obtain a second gate.

[0059] Specifically, etching the two sidewalls of the corresponding second trench in the gate region into a step shape includes:

[0060] After the oxide layer on the surface of the trench opening is polished, the two side walls of the trench corresponding to the gate region are etched into a step shape using photoresist.

[0061] The power device prepared in the above embodiment can be referred to Figure 2 , the multiple gates can be divided into a first gate and a second gate, and the two sidewalls of the corresponding second trench in the gate region of the second gate are etched into steps, while the sidewalls of the first gate are vertical trench sidewalls, so that the channel length formed by the second gate and the source is greater than the channel length formed by the first gate and the source. The device unit corresponding to the second gate is a high threshold voltage unit, and the device unit corresponding to the first gate is a low threshold voltage unit. In this way, when the device is turned on, the low threshold voltage unit is turned on first, and the high threshold voltage unit part is not turned on. This part almost does not generate current, does not generate heat and participates in heat dissipation, which greatly reduces the possibility of the device burning out due to thermal instability.

[0062] Optionally, the length of the first channel of the gate is greater than the length of the second channel of the gate; and the forming of a plurality of gates according to the length of the first channel and the length of the second channel comprises:

[0063] The first side wall of the corresponding trench in each gate region is etched into a first step, and the second side wall is etched into a second step, and then gate polysilicon is filled, wherein the side wall length of the trench corresponding to the first step is greater than the side wall length of the trench corresponding to the second step.

[0064] It can be understood that by etching the first sidewall of the corresponding trench in each gate region into a first step with a longer length, and etching the second sidewall of the corresponding trench in each gate region into a second step with a shorter length, different threshold voltages can be formed in the device, and the low threshold portion is turned on first, and the high threshold portion is not turned on during the switching process. This portion generates almost no current, generates no heat and participates in heat dissipation, which greatly reduces the possibility of the device burning out due to thermal instability. For details, please refer to Figure 3 .

[0065] Optionally, the length of the first channel of the gate is greater than the length of the second channel of the gate; and the forming of a plurality of gates according to the length of the first channel and the length of the second channel comprises:

[0066] After a side wall of a corresponding trench in each gate region is etched into a step shape, gate polysilicon is filled in the gate region in the trench.

[0067] It can be understood that by etching one side wall of the corresponding trench in each gate region into a long step shape, the second side wall of the trench corresponding to each gate region is a vertical trench side wall, so that different threshold voltages can be formed in the device, the low threshold part is turned on first, and the high threshold part is not turned on during the switching process. This part almost generates no current, no heat and participates in heat dissipation, which greatly reduces the possibility of the device burning out due to thermal instability. For details, please refer to Figure 4 .

[0068] Optionally, after etching the first surface of the substrate to form a plurality of grooves, the method further comprises:

[0069] Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with a first polysilicon;

[0070] Etching the first polysilicon to expose the gate region to obtain shielding gate polysilicon;

[0071] A dielectric layer is formed on the shielding gate polysilicon, and the gate region is located on the dielectric layer.

[0072] Optionally, after forming the plurality of gates, the method further includes:

[0073] A first conductive type body region is first formed in the substrate under the gate oxide layer between two adjacent gate regions by ion implantation, and a second conductive type doped region is formed on the first conductive type body region to obtain the source electrode.

[0074] Optionally, after obtaining the source electrode, the method further includes:

[0075] forming a passivation layer on the gate oxide layer;

[0076] After forming an etched hole in the passivation layer, a hole-etched surface is obtained, and the etched hole is etched into the source electrode.

[0077] Optionally, after the etching hole is formed in the passivation layer to obtain the hole etching surface, the method further comprises:

[0078] A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source electrode through the etching hole.

[0079] The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0080] The preparation method of the novel power device provided in the embodiment of the present application is to form a plurality of grooves by etching on the first surface of the substrate, each of the grooves includes a corresponding gate region, the gate polysilicon is located in the gate region, a first channel is formed between the first side of the gate polysilicon and the source, a second channel is formed between the second side of the gate polysilicon and the source, and the source is formed in the substrate under the gate oxide layer between two adjacent gate regions; a plurality of gates are formed according to the length of the first channel and the length of the second channel; a drain is formed on the second surface of the substrate. The power device prepared by the preparation method of the novel power device provided in the present application can form a plurality of different threshold voltage units in one device, and the safe operating area SOA of the device can be expanded, so that when the device is turned on, the low threshold voltage unit is turned on first, and the high threshold voltage unit is not turned on, and this part generates almost no current, generates no heat and participates in heat dissipation, which greatly reduces the possibility of the device burning out due to thermal instability.

[0081] The present application also provides a power device, such as Figure 1 As shown, the power device includes a plurality of units with different threshold voltages. When the power device is turned on, it is turned on in the order of threshold voltages from low to high. The power device includes:

[0082] A substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves, each of the grooves comprising a corresponding gate region, a gate polysilicon 3 being located in the gate region, a first channel being formed between a first side surface of the gate polysilicon 3 and a source 4, and a second channel being formed between a second side surface of the gate polysilicon 3 and the source 4;

[0083] A plurality of gates, each gate being formed according to a length of a corresponding first channel and a length of the second channel, and the plurality of gates and the source forming a plurality of different threshold voltages;

[0084] A source electrode 4 is formed in the substrate below the gate oxide layer 6 between two adjacent gate regions;

[0085] The drain electrode 8 is formed on the second surface of the substrate.

[0086] Please refer to Figure 2 , the gate includes a first gate and a second gate, the first channel of the first gate and the second channel of the first gate have the same length, the first channel of the second gate and the second channel of the second gate have the same length, and the length of the first channel of the first gate is less than the length of the first channel of the second gate;

[0087] The first gate is obtained by filling the gate polysilicon 3 in the gate region in the first trench;

[0088] The second gate is obtained by etching the two side walls of the corresponding second trench in the gate region into a step shape and then filling the gate polysilicon 3 .

[0089] Please refer to Figure 3 , a length of the first channel of the gate is greater than a length of the second channel of the gate;

[0090] The gate is obtained by etching the first side wall of the corresponding trench in each gate area into a first step, etching the second side wall into a second step, and filling the gate polysilicon 3, wherein the side wall length of the trench corresponding to the first step is greater than the side wall length of the trench corresponding to the second step.

[0091] Please refer to Figure 4 , a length of the first channel of the gate is greater than a length of the second channel of the gate;

[0092] The gate is obtained by etching a side wall of a corresponding trench in each gate region into a step shape and then filling the gate region in the trench with gate polysilicon 3 .

[0093] Optionally, the power device further includes:

[0094] An oxide layer 1, wherein the oxide layer 1 is obtained by oxidizing the bottom of the trench, the sidewalls of the trench, and the surface of the trench opening;

[0095] A first polysilicon is located in the trench;

[0096] Shielding gate polysilicon 2, obtained by etching the first polysilicon to expose the gate region;

[0097] A dielectric layer 9 is formed on the first surface of the shielding gate polysilicon 2 , and the gate region is located on the dielectric layer 9 .

[0098] Optionally, the source 4 includes:

[0099] A first conductivity type body region, which is first formed by ion implantation in the substrate below the gate oxide layer 6 between two adjacent gate regions;

[0100] The second conductive type doped region is formed on the first conductive type body region.

[0101] Optionally, the power device further includes:

[0102] A passivation layer 5 formed on the gate oxide layer 6;

[0103] The hole-etched surface is a surface obtained after forming an etched hole in the passivation layer 5, wherein the etched hole is etched into the source electrode 4;

[0104] A metal electrode 7 is formed on the surface of the hole etching, and the metal electrode 7 is connected to the source electrode 4 through the etching hole.

[0105] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0106] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the power device in the embodiments of the present application, and no further details will be given here.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0108] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a novel power device, characterized in that: Used to prepare a power device, the power device includes a plurality of units with different threshold voltages, and the power device is turned on in the order of threshold voltages from low to high when turned on, the method comprising: A plurality of grooves are formed by etching on a first surface of the substrate, each of the grooves includes a corresponding gate region, the gate polysilicon is located in the gate region, a first channel is formed between a first side of the gate polysilicon and a source, a second channel is formed between a second side of the gate polysilicon and the source, and the source is formed in the substrate under the gate oxide layer between two adjacent gate regions; According to the length of the first channel and the length of the second channel, a plurality of gates are formed, wherein the plurality of gates and the source form a plurality of different threshold voltages; forming a drain electrode on the second surface of the substrate; The gate includes a first gate and a second gate, the first channel of the first gate and the second channel of the first gate have the same length, the first channel of the second gate and the second channel of the second gate have the same length, and the length of the first channel of the first gate is less than the length of the first channel of the second gate; the forming of multiple gates according to the length of the first channel and the length of the second channel includes: filling gate polysilicon in the gate region in the first trench to obtain the first gate; etching the two side walls of the corresponding second trench in the gate region into a step shape, and then filling the gate polysilicon to obtain the second gate; Alternatively, the length of the first channel of the gate is greater than the length of the second channel of the gate; the forming of multiple gates according to the length of the first channel and the length of the second channel comprises: etching the first side wall of the corresponding trench in each gate region into a first step, etching the second side wall into a second step, and then filling the gate polysilicon, wherein the side wall length of the trench corresponding to the first step is greater than the side wall length of the trench corresponding to the second step; Alternatively, the length of the first channel of the gate is greater than the length of the second channel of the gate; and multiple gates are formed based on the length of the first channel and the length of the second channel, including: etching a side wall of the corresponding trench in each gate area into a step shape, and then filling the gate area in the trench with gate polysilicon.

2. The method according to claim 1, characterized in that After etching a plurality of grooves on the first surface of the substrate, the method further comprises: Oxidizing the bottom of the trench, the sidewalls of the trench and the surface of the trench opening to obtain a corresponding oxide layer, and then filling the trench with a first polysilicon; Etching the first polysilicon to expose the gate region to obtain shielding gate polysilicon; A dielectric layer is formed on the shielding gate polysilicon, and the gate region is located on the dielectric layer.

3. The method according to claim 1, characterized in that The etching of two sidewalls of the corresponding second trench in the gate region into a step shape comprises: After the oxide layer on the surface of the trench opening is polished, the two side walls of the trench corresponding to the gate region are etched into a step shape using photoresist.

4. The method according to claim 1, characterized in that: After forming the plurality of gates, the method further comprises: A first conductive type body region is first formed in the substrate under the gate oxide layer between two adjacent gate regions by ion implantation, and a second conductive type doped region is formed on the first conductive type body region to obtain the source electrode.

5. The method according to claim 4, characterized in that After obtaining the source electrode, the method further includes: forming a passivation layer on the gate oxide layer; After forming an etched hole in the passivation layer, a hole-etched surface is obtained, and the etched hole is etched into the source electrode.

6. The method according to claim 5, characterized in that After the etching holes are formed in the passivation layer to obtain the hole etching surface, the method further comprises: A metal electrode is formed on the surface of the hole etching, and the metal electrode is connected to the source electrode through the etching hole.

7. A power device, characterized in that: The power device includes a plurality of units with different threshold voltages. When the power device is turned on, it is turned on in the order of threshold voltages from low to high. The power device is prepared by the method for preparing a novel power device according to any one of claims 1 to 6. The power device includes: A substrate, the substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a plurality of grooves, each of the grooves comprising a corresponding gate region, the gate polysilicon being located in the gate region, a first channel being formed between a first side surface of the gate polysilicon and a source electrode, and a second channel being formed between a second side surface of the gate polysilicon and the source electrode; A plurality of gates, each gate being formed according to a length of a corresponding first trench and a length of the second trench, and the plurality of gates and the source forming a plurality of different threshold voltages; A source electrode is formed in the substrate below the gate oxide layer between two adjacent gate regions; A drain is formed on the second surface of the substrate.

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