A highly durable fefet based on ferroelectric semiconductor channel and anti-ferroelectric gate dielectric and a method of making the same

Abstract

The application discloses a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferromagnetic gate dielectric and a preparation method thereof. A back gate electrode layer, an antiferromagnetic gate dielectric layer, a ferroelectric semiconductor channel layer, a top gate high-k gate dielectric layer and a top gate electrode layer are sequentially stacked in the FeFET structure. The antiferromagnetic gate dielectric layer serves as a back gate dielectric layer, and the top gate high-k gate dielectric layer serves as a top gate dielectric layer. The thickness of the back gate dielectric layer is greater than that of the top gate dielectric layer, and an asymmetric double-gate structure is formed. In the application, a hafnium oxide-based antiferromagnetic film is used to replace a ferroelectric film as a gate dielectric of the FeFET, so that the operating voltage is effectively reduced. There is no interface layer between the ferroelectric semiconductor channel and the antiferromagnetic gate dielectric, and the durability failure caused by the charge trapping and defect generation associated with the interface layer of the traditional FeFET is inhibited. The out-of-plane spontaneous polarization of the ferroelectric semiconductor channel is continuously and accurately adjustable, and the FeFET has a gate storage mode and a channel storage mode which are switched with each other based on the asymmetric double-gate structure of the FeFET, so that the FeFET is expected to exhibit higher durability.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a high-durability ferroelectric transistor (FeFET) based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric, and its fabrication method. Background Technology

[0002] The emergence of new technologies such as smart chips, the Internet of Things, autonomous driving, and cloud computing heralds the arrival of the data age for human society. The massive volume of data has triggered a revolution in data computing and storage. In terms of data computing, the traditional von Neumann architecture separates data computation and storage, requiring data to be moved back and forth between the central processing unit (CPU) and various levels of storage, limiting computing power and increasing power consumption. Regarding data storage, caches, represented by static random access memory (SRAM) at higher storage levels, offer fast data access speeds, but suffer from low integration density and data volatility. External storage, represented by flash memory at lower storage levels, offers high integration density and non-volatile data, but suffers from slow data access speeds and low durability. Therefore, traditional memory struggles to simultaneously achieve high speed, high durability, and non-volatility. To address the challenges posed by massive data volumes to computing and storage, developing new types of memory and in-memory computing architectures based on these new memory types is particularly important and urgent. Hafnium oxide-based ferroelectric transistor (FeFET) memory has attracted widespread attention from academia and industry due to its advantages such as non-volatility of data, fast erase and write speed, low power consumption, and great potential for three-dimensional integration.

[0003] Despite its numerous advantages, hafnium oxide-based FeFETs also face the critical issue of low durability. On one hand, a layer exists between the ferroelectric layer and the channel in conventional silicon channel FeFETs. Due to the low dielectric constant of this layer, it often experiences a high electric field during erase / write operations on hafnium oxide-based FeFETs. This exacerbates charge trapping and defect formation near the interface, leading to a gradual decrease in the FeFET's memory window (MW) and ultimately, failure. On the other hand, the high coercivity of hafnium oxide-based ferroelectric films results in persistently high operating voltages for the FeFETs, further aggravating the "weakest link" effect of the interface layer and hindering further improvements in the durability of hafnium oxide-based FeFETs. Improving durability has become a bottleneck restricting the application and development of hafnium oxide-based FeFETs. Summary of the Invention

[0004] The purpose of this invention is to propose a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric, and its fabrication method.

[0005] Specifically, the technical solution of the present invention is as follows:

[0006] A high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric mainly includes: an insulating substrate, a back gate electrode layer on the insulating substrate, an antiferroelectric gate dielectric layer on the back gate electrode layer, a ferroelectric semiconductor channel layer on the antiferroelectric gate dielectric layer, source and drain metal electrodes on both sides of the ferroelectric semiconductor channel layer, the source and drain metal electrodes being located on the antiferroelectric gate dielectric layer, a top gate high-k gate dielectric layer on the ferroelectric semiconductor channel layer, and a top gate electrode layer on the top gate high-k gate dielectric layer. The antiferroelectric gate dielectric layer serves as the back gate dielectric layer, the top gate high-k gate dielectric layer serves as the top gate dielectric layer, and the thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, forming an asymmetric dual-gate structure.

[0007] The aforementioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric can use any substrate with insulating properties, such as mica, sapphire, diamond, strontium titanate (STO), or silicon oxide (SiO2).

[0008] The aforementioned high-durability FeFETs based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics can use common metals such as TiN, Al, Au, Pt, TaN, and W as back gate electrode materials, as well as heavily doped Si or Ge and conductive oxides, including but not limited to LSMO, Nb-STO, and RuO2. Any material with excellent conductivity can be used as a candidate material for the back gate electrode.

[0009] The aforementioned high-durability FeFETs based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics require antiferroelectric gate dielectrics with large band gaps, low leakage currents, and significant double hysteresis characteristics. Hafnium oxide-based antiferroelectric materials can be selected, such as Zr-doped HfO2, HfO2 with a certain concentration of Al doping, HfO2 or ZrO2 with a certain concentration of Si doping.

[0010] The aforementioned high-durability FeFET based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics requires ferroelectric semiconductor channel materials with a bandgap of less than 3.5V and excellent and stable out-of-plane spontaneous polarization. The built-in field introduced by the spontaneous polarization intensity can effectively shift the double hysteresis curve of the antiferroelectric gate dielectric. Furthermore, the coercive field of the ferroelectric semiconductor channel must be more than twice as large as the equivalent coercive field of the antiferroelectric gate dielectric to avoid affecting the polarization state of the ferroelectric semiconductor channel during data erasure and writing on the antiferroelectric gate dielectric. Suitable materials include, but are not limited to, α-In₂Se₃, 1T-MoTe₂, WTe₂, ReS₂, and InSe.

[0011] For the aforementioned high-durability FeFET based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics, the source and drain metal electrodes should form good ohmic contacts with the ferroelectric semiconductor channel to reduce contact resistance. Suitable metals include, but are not limited to, Al, Ti, Au, Ag, Pt, and Pd.

[0012] The aforementioned high-durability FeFET based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics requires a large bandgap, low leakage current, high dielectric constant, and strong breakdown resistance in the top-gate high-k dielectric. Materials such as Al2O3, HfO2, and ZrO2 can be selected for the top-gate high-k dielectric. Furthermore, the thickness of the top-gate high-k dielectric should be thinner than that of the back-gate antiferroelectric gate dielectric to increase the control of the polarization state of the ferroelectric channel by the top-gate electrode.

[0013] The aforementioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric requires the top gate electrode material to have excellent conductivity and thermal stability. The materials that can be selected include, but are not limited to, Pt, TiN, Al, Au, Ag, Pd, TaN, W, etc.

[0014] For the aforementioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric, the total thickness of the insulating substrate should be greater than 100 μm, and the effective insulating layer thickness should be greater than 20 nm. The back gate electrode material thickness is 30–50 nm. The antiferroelectric gate dielectric material thickness is 10–20 nm. The ferroelectric semiconductor channel material thickness is 0.7–40 nm, and its lateral dimension should be greater than 10 μm. The source and drain metal electrode thicknesses on both sides of the ferroelectric semiconductor channel material are between 20–80 nm. The top gate high-k dielectric material thickness is 5–10 nm. The top gate electrode thickness is 30–50 nm.

[0015] This invention also provides a method for fabricating the above-mentioned high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric, comprising the following steps:

[0016] (1) First, the size and dimensions of the back gate electrode are defined on the insulating substrate using photolithography. Then, a back gate electrode material with a thickness of 30-50 nm is deposited through physical vapor deposition / electron beam evaporation / atomic layer deposition and patterned through etching / lifting processes.

[0017] (2) An antiferroelectric gate dielectric with a thickness of 10-20 nm is grown on the sample obtained in step (1) using atomic layer deposition (ALD) process;

[0018] (3) A stress layer with a thickness of 5 to 30 nm is grown on the sample obtained in step (2) using atomic layer deposition (ALD) process / physical vapor deposition (PVD) process, and the antiferroelectricity of the antiferroelectric gate dielectric is activated by rapid thermal annealing (RTA) in N2 atmosphere.

[0019] (4) Remove the stress layer by immersion in an etchant / chemical etching method;

[0020] (5) Using physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) processes, ferroelectric semiconductor channel materials with a thickness of 0.7 nm to 40 nm are grown on the sample obtained in step (4) or transferred by micromechanical peeling.

[0021] (6) Define the source and drain metal positions using electron beam lithography (EBL) process, and deposit source and drain metal materials with a thickness of 20-80 nm on the sample obtained in step (5) using physical vapor deposition (PVD) / electron beam evaporation (EBE) process, and strip them to pattern them.

[0022] (7) Photolithography defines the position of the top gate high k gate dielectric and physical vapor deposition (PVD) process is used to deposit a top gate high k gate dielectric material with a thickness of 5-10 nm on the sample obtained in step (6), and then stripping it to pattern it.

[0023] (8) Define the position of the top gate electrode using electron beam lithography (EBL) process, and deposit a top gate electrode material with a thickness of 30-50 nm on the sample obtained in step (7) using physical vapor deposition (PVD) / electron beam evaporation (EBE) process, and strip it to pattern it.

[0024] In the above preparation process, the stress layer selected in step (3) should have a small coefficient of thermal expansion and be able to apply sufficient in-plane tensile stress to the antiferroelectric thin film, thereby activating antiferroelectricity in subsequent annealing. Suitable stress layer materials include, but are not limited to, TiN, TaN, W, Ti, and Ru. The temperature range of the rapid thermal annealing (RTA) process is 400℃ to 700℃, and the annealing time ranges from 30s to 150s, which need to be appropriately adjusted according to the selected antiferroelectric gate dielectric material.

[0025] The technical effects of this invention are as follows:

[0026] 1. Replace ferroelectric thin films with hafnium oxide-based antiferroelectric thin films as the gate dielectric (back gate dielectric and top gate dielectric) of FeFETs to reduce device operating voltage and improve FeFET durability.

[0027] In hafnium oxide-based antiferroelectric thin films, dipoles in adjacent unit cells are arranged antiparallel, and the material exhibits a double hysteresis loop characteristic under an external electric field. One branch of the double hysteresis loop is very similar to the hysteresis loop of conventional ferroelectric thin films, but its equivalent coercive field is lower, and the voltage required for polarization reversal is lower. Therefore, using antiferroelectric thin films to replace ferroelectric thin films as the gate dielectric can reduce the operating voltage of the device, effectively suppress charge trapping and defect generation, and improve the durability of FeFETs.

[0028] Second, ferroelectric semiconductor channels have out-of-plane spontaneous polarization, which can apply a continuous, precise and controllable electric field to the antiferroelectric gate dielectric to achieve non-volatile data storage, and is expected to achieve electrical co-optimization of FeFET durability.

[0029] The antiparallel arrangement of dipoles in adjacent cells of hafnium oxide-based antiferroelectric thin films results in zero remanent polarization when an external electric field is removed, which is detrimental to non-volatile data storage. Ferroelectric semiconductor channels possess stable out-of-plane spontaneous polarization. An incompletely shielded depolarization field will cause a shift in the double hysteresis loop of the antiferroelectric gate dielectric, resulting in two stable remanent polarization states even without an applied electric field. Therefore, non-volatile data storage can be achieved simply by utilizing the hysteresis characteristic of a single branch of the antiferroelectric gate dielectric. Furthermore, the shift of the double hysteresis loop of the antiferroelectric gate dielectric can be controlled by the strength of the remanent polarization of the ferroelectric semiconductor channel, enabling electrical co-optimization of FeFET durability. For example, by using the electrical correlation model of charge trapping and defect generation, the electrical bias range corresponding to the weakest charge trapping and defect generation effects while maintaining the subhysteresis polarization reversal of the antiferroelectric gate dielectric can be obtained. The write and erase electrical bias of the FeFET can be controlled within the optimal range by adjusting the residual polarization of the ferroelectric channel, thereby improving the durability of the FeFET. After a certain number of write and erase cycles, when the durability of a subhysteresis of the antiferroelectric gate dielectric fails due to fatigue, the residual polarization of the ferroelectric channel can also be adjusted to make the double hysteresis loop of the antiferroelectric gate dielectric further shift, thereby using the other subhysteresis to realize data storage and reading / writing, achieving "double" durability characteristics.

[0030] Third, most ferroelectric semiconductor channels have no interface layer between them and the antiferroelectric gate dielectric, thus avoiding the durability degradation problems caused by charge trapping and defect generation associated with the interface layer in conventional FeFETs.

[0031] Most ferroelectric semiconductor channel materials are two-dimensional. As channel materials, they possess advantages such as no dangling bonds, excellent gate control, and atomically sharp interfaces. Therefore, there is no low-k interface layer between the two-dimensional ferroelectric semiconductor channel and the antiferroelectric gate dielectric, and the charge trapping and defect generation effects associated with the interface layer in conventional Si-channel FeFETs do not exist. The devices are expected to have superior durability characteristics.

[0032] Fourth, high-durability FeFETs based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics can achieve mode switching, which is expected to achieve superior durability.

[0033] High-durability FeFETs based on ferroelectric semiconductor channels and antiferroelectric gate dielectrics have an asymmetric dual-gate structure and two operating modes. Mode 1 is the gate storage mode, where the sub-hysteresis loops used for data storage can be switched. In gate storage mode, the thicker antiferroelectric gate (back gate), with a lower equivalent coercive field, handles data storage and erasure / writing, while the thinner top gate (high-k gate) is used to control the coercive field and residual polarization of the ferroelectric semiconductor channel. When operating in this mode, the polarization state of the ferroelectric semiconductor channel must first be set to "positive" or "negative" polarization using the top gate (high-k gate). Under the influence of the depolarization field caused by the residual polarization of the ferroelectric semiconductor channel, the dual hysteresis loops of the antiferroelectric gate dielectric will shift, and the two polarization states of the sub-hysteresis loops can be used for non-volatile data storage. Because the thickness of the antiferroelectric gate dielectric is greater than that of the top gate (high-k gate) dielectric, and its equivalent coercive field is lower than that of the ferroelectric semiconductor channel, erasing / writing the device in this mode does not affect the polarization state of the ferroelectric channel. In this mode, the continuous tunability of the ferroelectric semiconductor channel polarization allows for the switching of antiferroelectric gate dielectric sub-hysteresis, meaning the sub-hysteresis used for data storage can be any branch of the double hysteresis curve. Simultaneously, when storing data using different branches of the sub-hysteresis, the combined electric field direction of the antiferroelectric thin film is opposite. Therefore, when storing data using sub-hysteresis 2, the charge trapped in the antiferroelectric gate during sub-hysteresis 1 storage can be unpacked, thus achieving durability recovery. Repeated switching between sub-hysteresis effectively improves the durability of the FeFET. Mode two is the channel storage mode. In this mode, a ferroelectric semiconductor channel with a larger coercive field is used for data storage, while a high-k gate at the top is used for data erasure and writing. Switching between gate storage mode and channel storage mode, as well as switching between sub-hysteresis in gate storage mode, allows the FeFET to exhibit even higher durability. Attached Figure Description

[0034] Figure 1 This is a cross-sectional schematic diagram of a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric prepared according to an example of the present invention.

[0035] Figure 2 This is a schematic diagram illustrating the steps involved in fabricating a high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric according to an embodiment of the present invention, wherein:

[0036] (a) is a cross-sectional view of the back gate electrode material deposited on an insulating substrate using physical vapor deposition (PVD) / electron beam evaporation (EBE) / atomic layer deposition (ALD) processes, after photolithography and etching / lifting patterning.

[0037] (b) is a cross-sectional view of an antiferroelectric gate dielectric material with a thickness of 10-20 nm deposited on the whole wafer using atomic layer deposition (ALD) based on (a);

[0038] (c) is a cross-sectional view of a stress layer material with a thickness of 5 to 30 nm grown using atomic layer deposition (ALD) / physical vapor deposition (PVD) processes, based on (b), followed by a rapid thermal annealing (RTA) process to activate the antiferroelectricity of the antiferroelectric gate dielectric.

[0039] (d) is a cross-sectional view after removing the stress layer by immersion in etchant / chemical etching, based on (c);

[0040] (e) is a cross-sectional view of ferroelectric semiconductor channel material with a thickness of 0.7 nm to 40 nm grown using physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) processes or transferred using micromechanical lift-off processes, based on (d).

[0041] (f) is a cross-sectional view of the source and drain metal electrode positions defined by electron beam lithography (EBL) based on (e), and then source and drain metal electrode materials with a thickness of 20-80 nm are deposited by physical vapor deposition (PVD) / electron beam evaporation (EBE) process, and then stripped to pattern them.

[0042] (g) is a cross-sectional view of the top gate high-k gate dielectric material after (f) is patterned by using photolithography to define the position of the top gate high-k gate dielectric material and using physical vapor deposition (PVD) to deposit a top gate high-k gate dielectric material with a thickness of 5-10 nm.

[0043] (h) is based on (g), using electron beam lithography (EBL) to define the position of the top gate electrode, and using physical vapor deposition (PVD) / electron beam evaporation (EBE) to deposit a top gate electrode material with a thickness of 30-50 nm, and then stripping it to pattern it.

[0044] In the picture:

[0045] 1—Insulating substrate; 2—Back gate electrode layer

[0046] 3—Antiferroelectric gate dielectric layer; 4—Ferroelectric semiconductor channel layer

[0047] 5—Source and drain metal electrodes; 6—Top gate high-k gate dielectric layer

[0048] 7—Top gate electrode layer a—Stress layer Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0050] like Figure 1As shown, the fabricated high-durability FeFET based on a ferroelectric semiconductor channel and an antiferroelectric gate dielectric includes an insulating substrate 1, a back gate electrode layer 2, an antiferroelectric gate dielectric layer 3, a ferroelectric semiconductor channel layer 4, source and drain metal electrodes 5, a top gate high-k gate dielectric layer 6, and a top gate electrode layer 7. The patterned back gate electrode layer 2 is located above the insulating substrate 1, and the antiferroelectric gate dielectric layer 3 is located above the back gate electrode layer 2. The ferroelectric semiconductor channel layer 4 is located on the antiferroelectric gate dielectric layer 3, with source and drain metal electrodes 5 on both sides of the ferroelectric semiconductor channel layer 4. The top gate high-k gate dielectric layer 6 is located on the ferroelectric semiconductor channel layer 4, and the top gate electrode layer 7 is located on the top gate high-k gate dielectric layer 6. The entire device exhibits a dual-gate structure, where the antiferroelectric gate dielectric layer serves as the back gate dielectric layer, and the top gate high-k gate dielectric layer serves as the top gate dielectric layer. The thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, forming an asymmetric dual-gate structure.

[0051] The preparation method includes the following steps: Figure 2 As shown, it specifically includes:

[0052] (1) The size and dimensions of the back gate electrode are first defined on the insulating substrate 1 using photolithography. A back gate electrode material with a thickness of 30–50 nm is deposited using physical vapor deposition (PVD) / electron beam evaporation (EBE) / atomic layer deposition (ALD) processes. The material is then patterned using acetone ultrasonic lift-off. Figure 2 As shown in (a), the back gate electrode material can be common metals such as TiN, Al, Au, Pt, TaN, and W, as well as heavily doped Si or Ge and conductive oxides, including but not limited to LSMO, Nb-STO, and RuO2. Any material with excellent conductivity can be used as a candidate material for the back gate electrode.

[0053] (2) An antiferroelectric gate dielectric material with a thickness of 10–20 nm is grown on the whole wafer using atomic layer deposition (ALD) technology. The antiferroelectric gate dielectric material can be selected from Zr-doped HfO2, HfO2 with a certain concentration of Al doping, HfO2 with a certain concentration of Si doping, or ZrO2. 2， like Figure 2 As shown in (b);

[0054] (3) A stress layer a with a thickness between 5 and 30 nm was grown on the entire wafer using atomic layer deposition (ALD) / physical vapor deposition (PVD) processes. The sample was then subjected to rapid thermal annealing (RTA) in an N2 atmosphere to activate the antiferroelectricity of the antiferroelectric gate dielectric. Figure 2 (c) shows the annealing temperature range of 400℃ to 700℃ and the annealing time range of 30s to 150s. The annealing conditions should be adjusted appropriately depending on the type of antiferroelectric grid dielectric.

[0055] (4) Remove stress layer a using immersion in etchant / chemical etching, such as Figure 2As shown in (d). When removing the stress layer, a process with excellent etching selectivity should be selected to avoid damaging the antiferroelectric layer while removing the stress layer. For example, if the stress layer is TiN, a mixture of H2O2 and NH3·H2O (H2O2:NH3·H2O:H2O=1:1:5) can be used to remove TiN;

[0056] (5) Ferroelectric semiconductor channel materials with a thickness of 0.7 nm to 40 nm are grown using physical vapor transport (PVT) / physical vapor deposition (PVD) / chemical vapor deposition (CVD) processes or transferred using micromechanical lift-off processes, such as... Figure 2 As shown in (e). Ferroelectric semiconductor channel materials must possess suitable spontaneous polarization intensity, requiring a bandgap of less than 3.5V, excellent and stable out-of-plane spontaneous polarization, ensuring that the introduced built-in field effectively shifts the double hysteresis curve of the antiferroelectric gate dielectric. Simultaneously, its coercive field should be at least twice greater than the equivalent coercive field of the antiferroelectric gate dielectric. Suitable materials include, but are not limited to, α-In₂Se₃, 1T-MoTe₂, WTe₂, ReS₂, InSe, etc.

[0057] (6) The positions of the source and drain metal electrodes are defined using electron beam lithography (EBL), and then source and drain metal electrode materials with a thickness of 20–80 nm are deposited using physical vapor deposition (PVD) / electron beam evaporation (EBE). The electrodes are then patterned by acetone stripping. Figure 2 As shown in (f), the source and drain metal electrodes should form good ohmic contact with the ferroelectric semiconductor channel to reduce contact resistance. Metal materials such as Al, Ti, Au, Ag, Pt, and Pd can be used. Low-temperature annealing (100℃~200℃) can improve contact resistance.

[0058] (7) The position of the top-gate high-k gate dielectric is defined using photolithography, and then a top-gate high-k gate dielectric material with a thickness of 5-10 nm is deposited using physical vapor deposition (PVD). Acetone is used for stripping to pattern the material, as shown below. Figure 2 As shown in (g). The high-k gate dielectric of the top gate requires a large bandgap, low leakage current, high dielectric constant, and strong breakdown resistance. Materials such as Al2O3, HfO2, and ZrO2 can be selected.

[0059] (8) The position of the top gate electrode is defined using electron beam lithography (EBL), and a top gate electrode material with a thickness of 30-50 nm is deposited using physical vapor deposition (PVD) / electron beam evaporation (EBE). The material is then stripped to create a pattern, such as... Figure 2 As shown in (h). The top gate electrode material is required to have excellent electrical conductivity and thermal stability. The materials that can be selected include, but are not limited to, Pt, TiN, Al, Au, Ag, Pd, TaN, W, etc.

[0060] At this point, the high-durability FeFET based on ferroelectric semiconductor channel and antiferroelectric gate dielectric can be fabricated.

[0061] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A highly durable FeFET device based on ferroelectric semiconductor channel and anti-ferroelectric gate dielectric, comprising an insulating substrate, characterized in that, The back gate electrode layer is on the insulating substrate, the antiferromagnetic gate dielectric layer is on the back gate electrode layer, the ferroelectric semiconductor channel layer is on the antiferromagnetic gate dielectric layer, the source and drain metal electrodes are on both sides of the ferroelectric semiconductor channel layer and on the antiferromagnetic gate dielectric layer, the top gate high-k gate dielectric layer is on the ferroelectric semiconductor channel layer, and the top gate electrode layer is on the top gate high-k gate dielectric layer, wherein the antiferromagnetic gate dielectric layer serves as the back gate dielectric layer, the top gate high-k gate dielectric layer serves as the top gate dielectric layer, the thickness of the back gate dielectric layer is greater than the thickness of the top gate dielectric layer, and the two form an asymmetric double-gate structure. The thickness of the top gate high-k gate dielectric material is 5-10 nm, and the thickness of the antiferromagnetic gate dielectric material is 10-20 nm. The ferroelectric semiconductor channel material has a band gap less than 3.5 V and a stable out-of-plane spontaneous polarization, and the built-in field introduced by the spontaneous polarization is sufficient to shift the double-hysteresis curve of the antiferromagnetic gate dielectric, and the coercive field of the ferroelectric semiconductor channel is more than 2 times the equivalent coercive field of the antiferromagnetic gate dielectric. The FeFET device has two working modes. Mode one is a gate storage mode, which is used for switching between sub-hysteresis for data storage. In the gate storage mode, the antiferromagnetic gate with a larger thickness and a lower equivalent coercive field realizes data storage and erasing, and the top gate high-k gate with a smaller thickness is used to control the remanent polarization of the ferroelectric semiconductor channel. In this mode, the switching between sub-hysteresis of the antiferromagnetic gate dielectric is realized by using the continuous adjustability of the ferroelectric semiconductor channel polarization. Mode two is a channel storage mode, in which the ferroelectric semiconductor channel with a larger coercive field realizes data storage, and the top gate high-k gate realizes data erasing. The gate storage mode and the channel storage mode are switched.

2. The FeFET device of claim 1, wherein, The insulating substrate material is mica, sapphire, diamond, strontium titanate STO, or silicon oxide SiO2. The total thickness of the insulating substrate is greater than 100 μm, and the effective insulating layer thickness is greater than 20 nm.

3. The FeFET device of claim 1, wherein, The back gate electrode material is TiN, Al, Au, Pt, TaN, W, or heavily doped Si or Ge, and a conductive oxide: LSMO, Nb-STO, or RuO2. The thickness of the back gate electrode material is 30-50 nm.

4. The FeFET device of claim 1, wherein, The antiferromagnetic gate dielectric material is hafnium oxide-based antiferromagnetic material: Zr-rich doped HfO2, Al-doped HfO2 with a certain concentration, Si-doped HfO2 with a certain concentration, or ZrO2.

5. The FeFET device of claim 1, wherein, The ferroelectric semiconductor channel material is α-In2Se3, 1T-MoTe2, WTe2, ReS2, or InSe. The thickness of the ferroelectric semiconductor channel material is 0.7-40 nm, and the lateral size is greater than 10 μm.

6. The FeFET device of claim 1, wherein, The source and drain metal electrode material is Al, Ti, Au, Ag, Pt, or Pd. The thickness of the source and drain metal electrode is 20-80 nm.

7. The FeFET device of claim 1, wherein, The top gate high-k gate dielectric material is Al2O3, HfO2, or ZrO2.

8. The FeFET device of claim 1, wherein, The top gate electrode material is Pt, TiN, Al, Au, Ag, Pd, TaN, or W, and the thickness of the top gate electrode is 30-50 nm.

9. A method of fabricating a FeFET device as claimed in claim 1, wherein, The method comprises the following steps: (1) Defining the size and size of the back gate electrode on the insulating substrate by photolithography, depositing a back gate electrode material with a thickness of 30-50 nm by physical vapor deposition / electron beam evaporation / atomic layer deposition process and patterning by etching / peeling process; (2) Growing a thickness of 10-20 nm of antiferromagnetic gate dielectric on the sample obtained in step (1) by atomic layer deposition process; (3) Growing a thickness of 5-30 nm of stress layer on the sample obtained in step (2) by atomic layer deposition process / physical vapor deposition process, and performing rapid thermal annealing on the sample in N2 atmosphere to activate the antiferromagnetic property of the antiferromagnetic gate dielectric; (4) Removing the stress layer by soaking in etching solution / chemical etching method; (5) Growing a thickness of 0.7 nm-40 nm of ferroelectric semiconductor channel material on the sample obtained in step (4) by physical vapor transport / physical vapor deposition / chemical vapor deposition process, or transferring by micro-mechanical peeling; (6) Defining the source and drain metal electrode position by electron beam lithography process, and depositing a thickness of 20-80 nm of source and drain metal electrode material on the sample obtained in step (5) by physical vapor deposition / electron beam evaporation process, and peeling to pattern; (7) Defining the position of the top gate high-k gate dielectric by photolithography, and depositing a thickness of 5-10 nm of top gate high-k gate dielectric material on the sample obtained in step (6) by physical vapor deposition process, and peeling to pattern; (8) Defining the position of the top gate electrode by electron beam lithography process, and depositing a thickness of 30-50 nm of top gate electrode material on the sample obtained in step (7) by physical vapor deposition / electron beam evaporation process, and peeling to pattern.

10. The method of claim 9, wherein the FeFET device is prepared by a process comprising: The material of the stress layer is TiN, TaN, W, Ti or Ru, and the temperature range of the rapid thermal annealing RTA process is 400-700℃, and the annealing time range is 30-150s.

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