Tunneling field effect transistor and manufacturing method thereof

Abstract

Asymmetry may be used to adjust electrical characteristics of tunneling field effect transistors (TFETs). An exemplary TFET includes a gate stack disposed over a semiconductor layer, a source and a drain disposed in the semiconductor layer. The gate stack includes a gate electrode disposed on a gate dielectric. The gate stack is disposed between the source and the drain. The source has a first conductivity type, and the drain has a second conductivity type different from the first conductivity type. The gate stack is asymmetric. For example, a gate stack has an asymmetric gate dielectric, an asymmetric gate electrode, an asymmetric gate foot, an asymmetric sidewall, or a combination thereof. In some embodiments, the source and drain have asymmetric profiles. In some embodiments, the semiconductor layer is a semiconductor fin, and the gate stack wraps the semiconductor fin. The embodiment of the invention also discloses a tunneling field effect transistor and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to a tunneling field effect transistor and a method for manufacturing the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. To date, these goals have been achieved in large part by reducing IC size (e.g., minimum IC component size), thereby increasing production efficiency and reducing associated costs. For example, reducing the size of transistors in an IC (and thus reducing their size) can reduce the supply voltage and / or threshold voltage required to operate the transistors.

[0003] However, it is difficult to obtain lower threshold voltages for metal oxide semiconductor field effect transistors (MOSFETs) because the leakage current increases (sometimes exponentially) as the threshold voltage is reduced, and the subthreshold swing (SS) of MOSFETs is limited to about 60 mV / dec. Therefore, tunneling field effect transistors using band-to-band tunneling (BTBT) are being explored as an alternative to MOSFETs. Although existing TFETs and methods of making such TFETs are generally adequate for their intended purposes, they are not completely satisfactory in all respects. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a tunneling field effect transistor is provided, comprising: a gate stack arranged above a semiconductor layer, wherein the gate stack includes a gate electrode arranged above a gate dielectric; a source and a drain arranged in the semiconductor layer, wherein the gate stack is arranged between the source and the drain, the source has a first conductivity type, and the drain has a second conductivity type different from the first conductivity type; and wherein the gate stack is asymmetric.

[0005] According to another aspect of an embodiment of the present application, a tunneling field effect transistor is provided, comprising: a channel region, arranged between a source and a drain; and a gate stack, arranged above the channel region, wherein the gate stack comprises a source-side gate dielectric, a drain-side gate dielectric and a gate electrode arranged above the source-side gate dielectric and the drain-side gate dielectric, wherein the source-side gate dielectric has a first dielectric constant and the drain-side gate dielectric has a second dielectric constant; and a source-side gate spacer and a drain-side gate spacer, arranged adjacent to the source-side gate dielectric and the drain-side gate dielectric, respectively.

[0006] According to another aspect of an embodiment of the present application, a method for manufacturing a tunneling field effect transistor is provided, comprising: forming a dummy gate; oxidizing the dummy gate to form a first oxide sidewall and a second oxide sidewall; forming a gate spacer adjacent to the first oxide sidewall and the second oxide sidewall; forming a gate opening by removing a remaining portion of the dummy gate; masking the first oxide sidewall; after removing the second oxide sidewall, forming a gate dielectric layer; and after unmasking the first oxide sidewall, forming a gate electrode in the gate opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a partial or full perspective view of a tunneling field effect transistor (TFET) according to various aspects of the present disclosure.

[0009] Figure 2A and Figure 2B The invention is based on various aspects of the present disclosure and is covered with an electric field and without an electric field. Figure 1 Top view of a portion of a TFET.

[0010] Figure 3 According to various aspects of the present disclosure Figure 1 A cross-sectional view of part or all of a TFET along line AA.

[0011] Figure 4 According to various aspects of the present disclosure Figure 1 A cross-sectional view of part or all of a TFET along line BB.

[0012] Figure 5 According to various aspects of the present disclosure Figure 1 A cross-sectional view of part or all of a TFET along line CC.

[0013] Figure 6 According to various aspects of the present disclosure Figure 1 A cross-sectional view of part or all of a TFET along line DD.

[0014] Figure 7 According to various aspects of the present disclosure Figure 1 Partial or full top view of a TFET, taken through line EE and line FF, respectively.

[0015] Figure 8 According to various aspects of the present disclosure Figure 1A partial or full cross-sectional view along line AA of another configuration of a TFET.

[0016] Fig. 9 According to various aspects of the present disclosure Figure 1 A cross-sectional view of part or all of a TFET along line AA, depicting the tunneling path.

[0017] Fig.10 According to various aspects of the present disclosure Figure 1 A top view of part or all of another configuration of a TFET.

[0018] Fig.11 According to various aspects of the present disclosure Figure 1 A partial or full cross-sectional view along line AA of another configuration of a TFET.

[0019] Fig.12 is a flow chart of a method for partially or fully fabricating a TFET according to various aspects of the present disclosure.

[0020] Figures 13A to 23A According to various aspects of the present disclosure Fig.12 A partial or complete top view of a TFET at various stages of fabrication of the method.

[0021] FIG. 13B to FIG. 23B and FIG. 13C to FIG. 23C According to various aspects of the present disclosure FIG. 13A to FIG. 23A Cross-sectional view of a TFET.

[0022] Fig.24 Depicted are various transistors (eg, Figure 1 TFET) device, part or all of the device. DETAILED DESCRIPTION

[0023] The present disclosure generally relates to tunneling field effect transistors (TFETs) with improved tunneling and methods of making the same.

[0024] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not meant to be limiting. For example, in the following description, forming a first component on or above a second component may include an embodiment in which the first and second components are directly contacted and formed, and may also include an embodiment in which additional features can be formed between the first and second components. In addition, in order to facilitate the disclosure of the relationship between one feature and another feature of the present invention, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "below", "lower", "upper", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used. Spatially relative terms are intended to cover different directions of devices including features. The present disclosure may also repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself determine the relationship between the various embodiments and / or configurations discussed.

[0025] In addition, when "about," "approximately," or the like is used to describe a value or a series of values, the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, the number or range includes a reasonable range that includes the described number, such as within + / -10% of the described number, based on known manufacturing tolerances associated with manufacturing features having the number associated with it. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.5 nm to 5.5 nm, and manufacturing tolerances associated with deposited material layers are known to those of ordinary skill in the art to be + / -10%. In addition, taking into account the differences inherent in any manufacturing process, when a device feature is described as having a "substantially" characteristic and / or feature, the term is intended to capture the characteristic and / or feature within the tolerance of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" feature is intended to capture a feature that is approximately vertical and horizontal within a given tolerance of the manufacturing process used to manufacture such feature, but is not mathematically or completely vertical and horizontal.

[0026] The details of an improved tunneling field effect transistor (TFET) and a method for manufacturing the same are described herein. As described herein, gate stack asymmetry (e.g., gate dielectric asymmetry, gate electrode asymmetry, gate footing asymmetry, gate sidewall asymmetry, etc.) and / or source / drain asymmetry are used to adjust and optimize the electrical performance of the TFET. The TFET disclosed herein can improve gate control adjacent to the source, reduce gate-induced drain leakage, reduce bipolar leakage, increase the electric field in the source region / region, reduce the electric field in the drain region / region, increase / expand the probability of inter-band tunneling, provide a gate dielectric with variable sensitivity to gate voltage (e.g., higher sensitivity in the source region / region, lower sensitivity in the drain region / region), reduce gate length, increase saturation current, increase threshold voltage, provide other advantages, or a combination thereof. In some embodiments, the TFET described herein can operate at a power supply voltage of less than about 0.5V. Different embodiments may have different advantages, and no embodiment requires a particular advantage.

[0027] Figure 1 is a perspective view of part or all of a tunneling field effect transistor (TFET) 100 according to various aspects of the present disclosure. Figure 2A and Figure 2B According to various aspects of the present disclosure Figure 1 Top view of a portion of a TFET with and without an electric field superimposed thereon. Figure 3 is a TFET 100 according to various aspects of the present disclosure along Figure 1 A partial or full cross-sectional view of line AA. Figure 4 is a TFET 100 according to various aspects of the present disclosure along Figure 1 A partial or full cross-sectional view of line BB. Figure 5 is a TFET 100 according to various aspects of the present disclosure along Figure 1 Partial or complete cross-sectional view of line CC.

[0028] Figure 6 is a TFET 100 according to various aspects of the present disclosure along Figure 1 A partial or full cross-sectional view of line DD. Figure 7 According to various aspects of the present disclosure, Figure 1 A partial or full top view of TFET 100 taken along line EE and line FF. Figure 8 is a cross-sectional view of part or all of another configuration of a TFET 100 according to various aspects of the present disclosure. Fig. 9 is a portion or all of a TFET 100 according to various aspects of the present disclosure along Figure 1 Cross-section through line AA with the tunneling path superimposed on it. Fig.10 and Fig.11According to various aspects of the present disclosure Figure 1 A partial or complete top view and a cross-sectional view along line AA of another configuration of a TFET. For ease of description and understanding, this article also discusses Figure 1 , Figure 2A , Figure 2B and Figure 3-Figure 11 For the sake of clarity, Figure 1 , Figure 2A , Figure 2B and Figure 3-Figure 11 It has been simplified to provide a better understanding of the inventive concepts of the present disclosure. Additional features may be added to the TFET 100 , and some of the features described below may be replaced, modified, or eliminated in other embodiments of the TFET 100 .

[0029] The TFET 100 may be formed on and / or include a substrate 102. In the depicted embodiment, the substrate 102 is a silicon substrate. The substrate 102 may include: an elemental semiconductor such as silicon and / or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In some embodiments, the substrate 102 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 102 may include various doped regions, such as a p-type doped region (e.g., a p-well), an n-type doped region (e.g., an n-well), or a combination thereof. The N-type doped region includes an N-type dopant, such as phosphorus, arsenic, other N-type dopants, or a combination thereof. The p-type doped region includes a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the doped region includes a p-type dopant and an n-type dopant. The doped region can be formed directly on and / or in the substrate 102, for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, other suitable structures, or a combination thereof.

[0030] The TFET 100 has a channel 110C, a source 120S, and a drain 120D. In the depicted embodiment, the source 120S and the drain 120D are disposed in a fin 110 extending from the substrate 102, and the channel 110C is formed in a portion of the fin 110 disposed between the source 120S and the drain 1207. The fin 110 extends along the x-direction, has a length along the x-direction, a width along the y-direction, and a height along the z-direction. In some embodiments, the fin 110 is a semiconductor fin that includes silicon, germanium, silicon germanium, other suitable semiconductor materials, or a combination thereof. In some embodiments, the fin 110 is formed by a portion of the substrate 102. For example, the substrate 102 may be a silicon substrate, and the fin 110 may be a patterned portion and / or extension (i.e., a silicon fin) of the substrate 102. In some embodiments, the fin 110 is formed by depositing and patterning one or more semiconductor layers on the substrate 102. For example, substrate 102 may be a silicon substrate, and fin 110 may be formed of a silicon germanium layer (i.e., silicon germanium fin) deposited and patterned on substrate 102. In some embodiments, the composition and / or material of fin 110 is selected based on the type of TFET to which fin 110 belongs and / or the desired channel material.

[0031] The TFET 100 has an asymmetric source / drain. For example, the source 120S and the drain 120D are doped with opposite types of dopants (i.e., the source 1207 and the drain 1207 have opposite conductivities). In the depicted embodiment, the source 120S is doped with a p-type dopant (e.g., boron, gallium, indium, other p-type dopants, or a combination thereof), and the drain 120D is doped with an n-type dopant (e.g., phosphorus, arsenic, other n-type dopants, or a combination thereof). In some embodiments, the source 120S is a heavily doped p-type (p+) region, and the drain 120D is a heavily doped n-type (n+) region. For example, the source 120S may have a dopant density of about 1 x 10 19 Atom / cm 3 (cm -3 ) to about 1x10 21 cm -3 The p-type dopant concentration of the drain 120D may be about 1 x 10 19 cm -3 About 1x 10 21 cm 3 In some embodiments, the channel 110C is an intrinsic (I) region, such as an undoped / unintentionally doped (UID) region or a lightly doped region of the fin 110. For example, the channel 110C may be formed of an intrinsic semiconductor material (e.g., single crystal silicon), which is an undoped and / or unintentionally doped (UID) semiconductor material (i.e., having no or negligible p-type dopants and / or n-type dopants). In another example, the channel 110C may be formed of a semiconductor material having a dopant concentration (e.g., a p-type dopant concentration and / or an n-type dopant density) less than about 1×1015 cm -3 of semiconductor materials.

[0032] In addition to different electrical conductivities, the source 120S and the drain 120D may also include different materials, such as different bandgap materials. For example, the source 120S may include a first material having a first bandgap (a "small bandgap" material), and the drain 120D may include a second material having a second bandgap larger than the first bandgap (a "large bandgap" material). In some embodiments, the small bandgap material and the large bandgap material have an energy bandgap of less than about 1.2 electron volts (eV). The source 120S and / or the drain 120D include silicon (Si), germanium (Ge), gallium (Ga), antimony (Sb), indium (In), arsenic (As), phosphorus (P), aluminum (Al), tin (Sn), other suitable components, or combinations thereof. For example, the source 120S includes GaSb, InAs, InGaAs, SiGe, SiP, GeSn, InSb, GaAsSb, other semiconductor-containing materials, or a combination thereof, and the drain 120D includes GaSb, InAs, InGaAs, SiGe, SiP, GeSn, InSb, GaAsSb, other semiconductor-containing materials, or a combination thereof. In some embodiments, the source 120S and / or the drain 120D include a two-dimensional material, such as graphene. In some embodiments, the source 120S and / or the drain 120D include a metal compound and / or a metal alloy. In some embodiments, the source 120S and / or the drain 120D include more than one semiconductor layer, wherein the semiconductor layers include the same or different materials and / or the same or different concentrations of dopants. In some embodiments, the source 120S and / or the drain 120D are formed using an epitaxial growth process (eg, selective epitaxial growth (SEG)), and the source 120S and the drain 120D are referred to as an epitaxial source and an epitaxial drain, respectively.

[0033] The channel 110C includes silicon (Si), germanium (Ge), gallium (Ga), antimony (Sb), indium (In), arsenic (As), carbon (C), molybdenum (Mo), sulfur (S), tungsten (W), selenium (Se), other suitable components or combinations thereof. For example, the channel 110C can be formed and / or made of SiGe, InGaAs, InAs, GaAsSb, other semiconductor-containing materials or combinations thereof. In some embodiments, the channel 110C is formed and / or made of a two-dimensional material, such as molybdenum disulfide (MoS 2 ), tungsten selenide (WSe 2), carbon nanotubes (CNTs), or a combination thereof. In some embodiments, the channel 110C is formed and / or made of a metal compound and / or a metal alloy. In some embodiments, the channel 110C is formed and / or made of a third material having a third band gap (a "large band gap" material), the third band gap is greater than the first band gap of the first material of the source 120S, and the third band gap may be different from the second band gap of the second material of the drain 120D. In some embodiments, the third band gap is less than about 1.2 eV.

[0034] In the depicted embodiment, the TFET 100 is configured as an n-type TFET (N-TFET) having a P+ source and an n+ drain. In some embodiments, the source 120S is a P+SiGe source, the channel 110C is a Si channel, and the drain 120D is an N+SiP drain. In some embodiments, the source 120S is a P+InAs source, the channel 110C is an InAs channel, and the drain 120D is an N+GaSb drain. In some embodiments, the source 120S is a P+Ge source, the channel 110C is a Si channel, and the drain 120D is an N+SiP drain. In some embodiments, the channel 110C is a Si channel, and the source 120S is a P+Si source, a P+SiGe source, a P+Ge source, or a P+GeSn source, or a combination thereof. Figure 1 As shown, the TFET 100 is not limited to the example material configurations of the source 120S, the channel 110C, and the drain 120D. The present disclosure contemplates N-TFETs having other material configurations of the source 120S, the channel 110C, and the drain 120D.

[0035] In some embodiments, the TFET 100 is configured as a p-type TFET (p-TFET) having an N+ source and a p+ drain, such as Figure 8 As shown. In some embodiments, the source 120S is an N+Si source, the channel 110C is a Si channel, and the drain 120D is a P+SiGe drain. In some embodiments, the source 120S is an N+GaSb source, the channel 110C is an InGaAs channel, and the drain 120D is a P+InGaAs drain. In some embodiments, the channel 110C is an InAs channel, and the source 120S is an N+GaSb source. In some embodiments, the channel 110C is an InGaAs channel, and the source 120S is an N+InGaAs source, an N+InP source, or a combination thereof. Figure 8 As shown, TFET 100 is not limited to the example material configurations of source 120S, channel 110C, and drain 120D. The present invention contemplates a P-TFET having other material configurations of source 120S, channel 110C, and drain 120D.

[0036] The TFET 100 also includes a substrate isolation structure 125 that electrically isolates an active region (e.g., fin 110) from an adjacent active region. For example, the substrate isolation structure 125 can separate and electrically isolate the fin 110 from another fin of the TFET 100 or from a fin and / or active region of another device (e.g., another transistor). The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including, for example, silicon, oxygen, nitrogen, carbon, other suitable isolation components, etc.), or a combination thereof. The substrate isolation structure 125 may have a multilayer structure. For example, the substrate isolation structure 125 may include a bulk dielectric (e.g., an oxide layer) on a dielectric liner (including, for example, silicon nitride, silicon oxide, silicon oxynitride, carbon oxynitride, or a combination thereof). In another example, the substrate isolation structure 125 may include a dielectric layer on a doped liner (e.g., a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The dimensions and / or properties of substrate isolation structure 125 are configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof. In the depicted embodiment, substrate isolation structure 125 may be STI.

[0037] The TFET 100 also includes a gate structure having a gate stack 130 and a gate spacer 145. The gate structure is disposed on the channel 110C ( Figure 1 , Figure 2A , Figure 3 and Figure 5-Figure 7 ), the gate structure is disposed between the source 120S and the drain 120D ( Figure 1 , Figure 2A , Figure 3 and Figure 7 ), and the gate structure is disposed on the substrate isolation structure 125 ( Figure 1 and Figure 4 ). The gate structure extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 110. For example, the gate structure (e.g., its gate stack 130) extends longitudinally along the y direction, has a length along the y direction, a width along the x direction, and a height along the z direction. In a cross-sectional view along the length direction of the fin 110 ( Figure 3 ), the gate structure is disposed on the top of the channel 110C of the fin 110. In the top view along the longitudinal direction of the fin 110 ( Figure 2A and Figure 6 ), the gate structure is arranged along the sidewall of the channel 110C of the fin 110. In the cross-sectional view along the width direction of the fin 110 ( Figure 5 and Figure 6 ), the gate structure is disposed on the top and sidewalls of the channel 110C of the fin 110, and the gate structure wraps the channel 110C.

[0038] The gate stack 130 has an asymmetric gate dielectric 132, which can improve the performance of the TFET 100, such as band-to-band tunneling. For example, the gate dielectric 132 includes a source-side gate dielectric layer 134 and a drain-side gate dielectric layer 136. The source-side gate dielectric layer 134 and the drain-side gate dielectric layer 136 form the source-facing / adjacent sidewall and the drain-facing / adjacent sidewall of the gate stack 130, respectively (i.e., the gate stack 130 has an asymmetric sidewall). In a cross-sectional view along the length direction of the fin 110 ( Figure 3 ), the source-side gate dielectric layer 134 is disposed on the top of the source-side portion of the channel 110C, and the drain-side gate dielectric layer 136 is disposed on the top of the drain-side portion of the channel 110C. In a top view along the length direction of the fin 110 ( Figure 2A and Figure 7 ), the source side gate dielectric layer 134 and the drain side gate dielectric layer 136 extend along the sidewalls of the source side portion and the drain side portion of the channel 110C, respectively. In the cross-sectional view along the width direction of the fin 110 ( Figure 5 and Figure 6 ), the source-side gate dielectric layer 134 wraps the source-side portion of the channel 110C ( Figure 5 ), the drain side gate dielectric layer 136 wraps the drain side portion of the channel 110.

[0039] The dielectric constant of the source side gate dielectric layer 134 is greater than the dielectric constant of the drain side gate dielectric layer 136. Therefore, the source side gate dielectric layer 134 and the drain side gate dielectric layer 136 can be referred to as a high-k dielectric layer / portion and a low-k dielectric layer / portion of the gate dielectric 132, respectively. In some embodiments, the dielectric constant of the source side gate dielectric layer 134 is greater than about 10 (k≥10), and the dielectric constant of the drain side gate dielectric layer 136 is less than about 10 (k≤10). In the depicted embodiment, the source side gate dielectric layer 134 and the drain side gate dielectric layer 136 are a metal-and-oxygen-containing dielectric layer and a silicon-and-oxygen-containing dielectric layer, respectively. The metal of the metal-and-oxygen-containing dielectric layer is hafnium, zirconium, aluminum, lanthanum, zinc, titanium, tantalum, yttrium, strontium, barium, strontium, other suitable metals, or combinations thereof. The dielectric layer containing metal and oxygen may also include silicon and / or nitrogen, and the dielectric layer containing silicon and oxygen may also include nitrogen and / or carbon. In some embodiments, the source side gate dielectric layer 134 includes HfO 2 、HfSiO、HfSiO 4 , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlOx, ZrO, ZrSiO 2 、AlO、AlSiO、Al 2 O 3 、TiO、TiO2 、LaO、LaSiO、LaO 3 ,La 2 O 3 、 2 O 3 、 2 O 5 , Y 2 O 3 、SrTiO 3 、BaZrO、BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), HfO 2 -Al 2 O 3 , other dielectric materials containing metal and oxygen, or a combination thereof. In some embodiments, the source side gate dielectric layer 134 is a hafnium-based oxide (e.g., HfO 2 ) layer, zirconium-based oxide (such as ZrO 2 ) layer or lanthanum-based oxide (such as La 2 O 3 ) layer. In some embodiments, the drain side gate dielectric layer 136 is SiO x N 1-x layer (where x is the number of oxygen atoms in the silicon oxynitride molecule), SiC x O y N 1-x-y layer (where x is the number of carbon atoms and y is the number of oxygen atoms in the silicon oxycarbonitride molecule) or SiO 2 In some embodiments, the source side gate dielectric layer 134 and the drain side gate dielectric layer 136 each include a single layer, as shown. In some embodiments, the source side gate dielectric layer 134 has a multi-layer structure. In some embodiments, the drain side gate dielectric layer 136 has a multi-layer structure.

[0040] The gate dielectric 132 may also include an interfacial layer 138. In the depicted embodiment, the interfacial layer 138 is disposed between the source side gate dielectric layer 134 and the channel 110C. In some embodiments, the interfacial layer 138 is also disposed between the drain side gate dielectric layer 136 and the channel 110C. The interfacial layer 138 includes a dielectric material such as SiO 2 、SiGeO x , HfSiO, SiON, other dielectric materials or combinations thereof. The interface layer 138 may be in the active region (e.g., fin 110) of the TFET 100 but not in the isolation region (e.g., substrate isolation structure 125) of the TFET 200. For example, in the active region, the interface layer 138 may cover the top of the channel 110C of the fin 110 ( Figure 3), and the interface layer 138 may wrap the channel 110C ( Figure 6 ). In some embodiments, the interface layer 138 has a substantially uniform thickness, such as in the depicted embodiment.

[0041] The gate stack 130 also has a gate electrode 140 disposed on the gate dielectric 132. The gate electrode 140 is disposed on the source side gate dielectric layer 134 and the drain side gate dielectric layer 136. In a top view along the length direction of the fin 110 ( Figure 2A and Figure 7 ), the gate electrode 140 extends along the sidewalls of the source side portion and the drain side portion of the channel 110C respectively. In the cross-sectional view along the width direction of the fin 110 ( Figure 6 and Figure 7 ), the gate electrode 140 is provided at the source side portion of the channel 110C ( Figure 6 ) and the top and sidewalls of the drain side portion of the channel 110C ( Figure 7 ) (i.e., the gate electrode 40 wraps around the channel 110C of the fin 110). As further described herein, the gate electrode 140 can be asymmetric or symmetric in the gate stack 130, depending on its location (e.g., the portion of the gate stack 130 in the active area can be symmetric, while the portion of the gate stack 130 in the isolation area can be asymmetric), the size of the source-side gate dielectric layer 134, the size of the drain-side gate dielectric layer 136, other factors, or a combination thereof.

[0042] The gate electrode 140 includes at least one conductive gate layer. The conductive gate layer includes a conductive material, such as Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials or combinations thereof. In some embodiments, the gate electrode 140 includes a work function layer. The work function layer is a conductive layer tuned to have a desired work function, such as an n-type work function or a p-type work function. The work function layer includes a work function metal and / or its alloy, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2, TaAl, TaAlC, TaSiAlC, TiAlN or a combination thereof. In some embodiments, the gate electrode 140 includes a bulk layer located above the gate dielectric 132 and / or the work function layer. The bulk layer includes a suitable conductive material, such as Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or alloys thereof, or a combination thereof. In some embodiments, the gate electrode 140 includes a barrier layer on the work function layer and / or the gate dielectric 132. The barrier layer includes a material that can prevent or eliminate diffusion and / or reaction of components between adjacent layers and / or can promote adhesion between adjacent layers (e.g., between the work function layer and the bulk layer). In some embodiments, the barrier layer includes a metal and nitrogen, such as TiN, TaN, W 2 N, TiSiN, TaSiN, other suitable metal nitrides or combinations thereof.

[0043] The gate spacers 145 (collectively referred to as source side gate spacers 145S and drain side gate spacers 145D) are adjacent to and along the sidewalls of the gate stack 130. The source side gate spacers 145S and the drain side gate spacers 145D are separated from the gate electrode 140 by the source side gate dielectric layer 134 and the drain side gate dielectric layer 136, respectively. The gate spacers 145 may include sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, other suitable spacers, or combinations thereof. The gate spacers 145 may each be a single layer or have a multi-layer structure. The gate spacers 145 include a dielectric material, which may include silicon, oxygen, carbon, nitrogen, other suitable components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, carbon oxynitride, etc.). In the depicted embodiment, the composition of the gate spacer 145 is different from the composition of the drain side gate dielectric layer 136. For example, the gate spacer 145 includes silicon and nitrogen and / or carbon, and the gate spacer 145 may also include oxygen and / or hydrogen. For example, the gate spacer 145 includes a SiN layer, a SiC layer, or a SiCN layer, which may be directly adjacent to the sidewall of the gate stack 130.

[0044] The dielectric layer 150 is disposed on the substrate 102, the source 120S, the drain 120D, the substrate isolation structure 125, and the gate structure (e.g., the gate stack 130 and the gate spacer 145). The dielectric layer 150 may have a multi-layer structure, such as a contact etch stop layer (CESL) 152 and an interlayer dielectric (ILD) layer 154. The ILD layer 154 is disposed over the CESL 152. The ILD layer 154 includes a dielectric material, including, for example, silicon oxide, carbon-doped silicon oxide, silicon nitride, silicon oxynitride, an oxide formed of tetraethyl orthosilicate (TEOS), BSG, PSG, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, polyparaxylene, benzocyclobutene-based (BCB) dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 154 includes a dielectric material having a dielectric constant less than that of silicon dioxide (e.g., k<3.9). In some embodiments, the ILD layer 154 includes a dielectric material having a dielectric constant less than about 2.5, such as porous silicon oxide, silicon carbide, carbon-doped oxide (e.g., SiCOH-based materials), or a combination thereof. The CESL 152 includes a dielectric material different from the dielectric material of the ILD layer 154. For example, in the case where the ILD layer 154 includes silicon and oxygen (e.g., porous silicon oxide), the CESL 152 may include silicon and nitrogen, and the CESL 154 may be a silicon nitride layer, a silicon carbonitride layer, or a silicon carbon nitride oxide layer.

[0045] In the TFET 100, the profiles and compositions of the gate structure (e.g., the gate stack 130, the source side gate dielectric 134, the drain side gate dielectric 136, the gate electrode 140, or a combination thereof), the source 120S, and the drain 120D are tuned and / or configured to provide an asymmetric electric field along the channel 110C, which can increase gate control on the source side and reduce gate induced drain leakage (GIDL), thereby maximizing BTBT source channel tunneling while minimizing BTBT drain channel tunneling. For example, referring to Figure 2B, the profile and composition of the gate structure, source 120S, and drain 120D provide the TFET 100 with a gradient electric field along the channel 110C that decreases from the source 120S to the drain 120D. The gradient electric field may have a maximum strength near and / or adjacent to the source 120S and a minimum strength near and / or adjacent to the drain 120D, which increases the sensitivity of the source-channel junction to a voltage applied to the gate structure (e.g., gate electrode 140), reduces the sensitivity of the drain-channel junction to an applied gate voltage, reduces and / or minimizes the off-leakage current at the drain-channel junction, or a combination thereof. Increasing the sensitivity of the source-channel junction to an applied gate voltage may allow the TFET 100 to operate at a lower threshold voltage, thereby facilitating low power operation required for scaled devices. As further described, the profile of the gate structure and the profile of the source 120S can be configured to provide a gate-source overlap to increase the source-side electric field along the channel 110C, and the profile of the gate structure and the drain 120D can be configured to provide a gate-drain overlap to reduce the drain-side electric field along the channel 110C. The composition and / or thickness of the source-side gate dielectric 134 and the drain-side gate dielectric 136 can be configured to increase the source region-side electric field along the channel 110C and reduce the drain region-side electric field along the channel 110C, thereby improving the performance of the TFET 100.

[0046] Reference Figure 1 , Figure 2A , Figure 3 , Figure 4 and Figure 7 , the gate stack 130 has a gate width (also referred to as a gate critical dimension (CD)) along the length direction of the fin 110 (e.g., along the x-direction). Due to process limitations, such as the limited ability of the etching process to provide a high aspect ratio gate pattern with substantially vertical sidewalls, the lower, bottom portion of the gate stack 130 intersecting the fin 110 may be wider than the upper, top portion of the gate stack 130. For example, the top gate portion GT of the gate stack 130 has a width W T The bottom gate portion GB of the gate stack 30 has a width greater than W T Width W B In the depicted embodiment, the top gate portion MT has substantially vertical sidewalls such that the width W T The gate stack 130 has substantially the same height (ie, width W T The top gate portion GT is uniform from the top to the bottom), and the bottom gate portion GB has a tapered sidewall so that the width W B The gate stack 30 increases in height (ie, thickness W BIncreases from the top to the bottom of the bottom gate portion GB). Therefore, the gate stack 130 can have different gate widths (i.e., gate CD) when measured along its height at different locations of the gate stack 130. In the depicted embodiment, the top gate portion GT is located between the top of the gate stack 130 and the top of the fin 110 (or slightly below the bottom of the fin 110), which is designated as the fin top FT, and the bottom gate portion GB is located between the fin top FT and the substrate isolation structure 125 (or slightly below the fin top FT). In some embodiments, the top gate portion GT can be between the top of the gate stack 130 to the distance below the fin top FT, and the bottom gate portion GB can be between the distance below the fin top FT to the substrate isolation structure 125. In other words, the gate stack 130 can have a width W from its top to the distance below the fin top FT. T , and the gate stack 130 may have a width W from below the fin top FT to the substrate isolation structure 125 B .

[0047] The portion of the bottom gate portion GB that provides the widening of the gate stack 130 is called the gate footing. In MOS transistors, gate footing is generally considered to be detrimental to transistor performance because a larger gate CD results in a larger saturation current (Isat) and threshold voltage (Vt), so gate manufacturing and gate profiles are generally designed to limit the gate footing and / or reduce any overlap of the gate footing with the source / drain. In contrast, the present disclosure recognizes that in a TFET, the gate footing can be used to provide gate-source overlap to expand and / or improve source-side gate control and / or gate-drain overlap, thereby reducing drain-side bipolar leakage. The TFET 100 can therefore utilize the gate footing to provide gate-source overlap and / or gate-drain overlap to optimize its performance. For example, the fabrication of the gate structure (e.g., its dummy gate, which is subsequently replaced by the gate dielectric 132 and the gate electrode 140, as described below) is tuned and / or configured to provide the gate stack 130 with a source-side gate footing GFS and a drain-side gate footing GFD, which can increase the gate-source overlap and the gate-drain overlap, respectively, which can increase tunneling at the source-channel junction while reducing tunneling at the drain-channel junction.

[0048] refer to Figure 2A , Figure 4 and Figure 7 , the source-side gate footing GFS provides gate-source overlap in the x-direction and the y-direction, which increases the electric field along the channel 110C adjacent to and / or close to the source 120S, thereby increasing the tunneling probability at the source-channel junction and, therefore, increasing the tunneling current of the TFET 100. For example, referring to Fig. 9, the TFET 100 may have three source channel tunneling paths, such as a top vertical tunneling path along and / or in the top of the fin 110, a lateral tunneling path along and / or in the middle of the fin 110, and a bottom vertical tunneling path along and / or in the bottom of the fin 110. Using a source-side gate footing GFS to increase the overlap between the gate stack 130 and the source 120S may increase the vertical tunneling of the TFET 100. Referring to Figure 2A and Figure 4 The source side gate dielectric 134 and the gate electrode 140 both form a source side gate footing GFS, so that the source side gate dielectric 134 and the gate electrode 140 overlap the source 120S along the y direction. The source side gate footing GFS has a width G along the length direction of the fin 110 (eg, along the x direction). FX , and the width G FX The width G corresponds to the portion of the gate stack 130 that overlaps the source 120S in the isolation region of the TFET 100 (eg, along the y direction). In some embodiments, the width G FX Smaller than width W T About 30% (ie 0.3W T ≥G FX ≥0). Reference Figure 2A , Figure 4 and Figure 7 , gate-source overlap (L S-overlap ) is provided by the source side gate foot GFS. S-overlap corresponds to the length of the gate electrode 140 along the x direction that overlaps the source 120S along the y direction. In some embodiments, due to the width G of the source side gate footing GFS FX Can be increased from top to bottom, L S-overlap The source side gate footing GFS and / or the bottom gate portion GB may increase from the top to the bottom. In some embodiments, since the profile of the source 120S may vary, L S-overlap The width G of the gate stack 130 at a given position may be determined based on the profile of the source 120S and the width G of the gate stack 130 at a given position. FX And changes.

[0049] The profile of the source 120S can also be adjusted to provide the desired gate-source overlap. For example, the source 120S has curved sidewalls ( Figure 3 and Figure 4 ), which increases the width of the source 120S along the length direction of the fin 110, so that the source 120S extends laterally under the source side gate spacer 145S. The source 120S extends (e.g., along the x-direction) beyond the source side gate spacer 145S by a distance S push, so that the source 120S extends below the gate stack 130. In the depicted embodiment, the distance S push The distance S is greater than the thickness t1 of the source side gate dielectric 134, and the source 120S extends laterally beyond the source side gate dielectric 134. In other words, in the active area, the source 120S extends under the source side gate spacer 145S, the source side gate dielectric layer 134, and the gate electrode 140. push Corresponding to the gate-source overlap in the active region of TFET 100, the distance S push Located between the inner sidewall of the source-side gate spacer 145S (adjacent to the source-side gate dielectric layer 134) and the gate-side tip / edge T of the source 120S (corresponding to the farthest channel-facing / extension portion of the source 120S). In the depicted embodiment, the gate-side tip / edge T corresponds to the widest / longest portion of the source 120S along the longitudinal direction of the fin 110 (i.e., the portion of the source 120S having the largest width / length), which may be the middle portion of the source region 120S, such as in the case where the source region 120S is provided with a curved sidewall, as shown. In some embodiments, the source-side gate spacer 145S has a spacer thickness S along the longitudinal direction of the fin 110 (e.g., along the x-direction), and the distance S is push greater than about zero and less than about 60% of the spacer thickness S (i.e., 0.6S ≥ S push ≥0).

[0050] In some embodiments, at the fin top FT, the source 120S extends laterally below the source side gate spacer 145S, as shown. In such embodiments, the distance between the source 120S at the fin top FT and the inner sidewall of the source side gate spacer 145S is S min . Distance S min greater than zero and less than about 90% of the spacer thickness S (i.e. 0.9S ≥ S min >0). In other words, at the fin top FT, the source 120S does not extend under and / or contact the inner sidewalls of the source side gate spacer 145S, but the source 120S may extend under and be in physical contact with the source side gate spacer 145S by less than about 10% of the spacer thickness S.

[0051] The source-side gate footing GFS is used to increase the gate-source overlap (e.g., along the y-direction and the x-direction), and the profile of the source 120S is enlarged to increase the gate-source overlap (e.g., by pushing the source 120S closer to the gate region (e.g., its gate electrode 140) along the z-direction and the x-direction), thereby increasing the electric field strength adjacent to the source 120S. Therefore, the TFET 100 has a gate-source overlap along the channel 110C (e.g., see Figure 2B) is provided with a strong source-side electric field, which increases the sensitivity of the source-channel junction to the voltage applied to the gate structure (e.g., gate electrode 140), thereby increasing the source gate control and thereby maximizing the source-channel BTBT tunneling of TFET100.

[0052] refer to Figure 2A , Figure 4 and Figure 7 The drain-side gate footing GFD provides a gate-drain underlap in the x-direction and the y-direction, which reduces the electric field along the channel 110C adjacent to and / or close to the drain 120D, thereby reducing the bipolar effect and / or bipolar conduction at the drain-channel junction, thereby reducing GIDL. Figure 2A and Figure 4 , compared to the source-side gate footing GFS formed by the gate electrode 140 and the source-side gate dielectric layer 134, the drain-side gate footing GFD is formed by the drain-side gate dielectric layer 136 instead of the gate electrode 140. Because the drain-side gate footing GFD does not include the gate electrode 140, the gate electrode 140 does not overlap the drain 120D along the y-direction even if the width of the gate stack 130 increases along its height. Instead, the drain-side gate dielectric layer 136 and / or the drain-side gate spacer 145D overlap the drain 120D along the y-direction. The drain-side gate dielectric layer 136 has a thickness t2 in the top gate portion GT and a thickness t3 in the bottom gate portion GB. In the depicted embodiment, because the drain-side gate dielectric layer 136 fills the drain-side gate footing GFD, the thickness t3 may be a thickness t2 and a width G FX The thickness t3 corresponds to the portion of the gate stack 130 (here, the portion of the drain-side gate dielectric layer 136) in the isolation region of the TFET 100, which can separate the gate electrode 140 (e.g., its sidewalls) from the drain 120S (e.g., along the x-direction) and / or provide an underlap therebetween. In some embodiments, the thickness t3 is less than the width W T About 60% (ie 0.6W T ≥t3≥0). In some embodiments, in the top view ( Figure 2A ), the distance D is between the gate electrode 140 (e.g., its drain-side sidewall) and the drain 120D (e.g., its tip / edge), and the distance D is greater than or equal to the thickness t3 (e.g., D ≥ t3). Increasing the distance D and / or the thickness t3 (thereby increasing the thickness of the drain-side gate dielectric layer 136) may reduce the electric field near the drain 120D and / or increase the bandgap of the channel to the drain material (thereby reducing the tunneling probability), which may reduce the bipolar effect.

[0053] Reference Figure 2A , Figure 4 and Figure 7, gate-drain underlap (L D-underlap ) is provided by the drain side gate dielectric layer 136 and / or the drain side gate footing GFS. D-underlap corresponds to the distance along the x direction that the gate electrode 140 overlaps the drain electrode 120D along the y direction. In other words, L D-underlap is the distance between the gate electrode 140 (eg, its drain-side sidewall) and the drain 120D (eg, its tip / edge). In some embodiments, due to the width G of the drain-side gate footing GFD, FX It can increase from top to bottom, and the profile of the drain 120D can vary along its depth, so L D-underlap The width G of the gate stack 130 at a given position may be determined based on the profile of the drain 120D and the width G of the gate stack 130 at a given position. FX Even if the width of the bottom gate portion GB increases from top to bottom, the drain-side gate footing GFD formed by the drain-side gate dielectric layer 136 can maintain the gate-drain overlap. In some embodiments, as shown, the gate-drain overlap can be maintained along the entire height of the gate stack 130.

[0054] The profile of the drain 120D may also be adjusted to provide the desired gate-drain overlap. For example, the sidewalls of the drain 120D may be tapered (e.g., Figure 3 and Figure 4 ), its width gradually decreases from top to bottom along the length direction of the fin 110, and the drain 120D extends laterally or away from the gate stack 130 and / or the drain side gate spacer 145D. The distance d u Corresponding to the gate-drain overlap in the active region of TFET 100, the distance d u Between the drain-side sidewall of the gate electrode 140 adjacent to the drain-side gate dielectric layer 136 and the gate-side sidewall of the drain 120D. In the depicted embodiment, because the drain 120D has a tapered sidewall, the distance d u The depth along the drain 120E increases, for example, from the fin top FT to the depth of the drain 120D in the fin 110. To ensure sufficient gate-drain overlap, the distance d u The thickness may be at least t2 (ie, d u ≥ t2). In the depicted embodiment, the drain side spacer 145D also has a spacer thickness S, and at the fin top FT, the distance d u Greater than thickness t2 and less than the sum of thickness t2 and spacer thickness S (ie, (S+t2)>d u >t2). As the depth of the drain 120D increases, the distance d u Increase, and the distance d u can be greater than or equal to the sum of the thickness t2 and the spacer thickness S (ie, d u≥(S+t2)).

[0055] The drain-side gate footing GFD is used to increase the gate-drain overlap (e.g., in the y-direction and the x-direction), and the profile of the drain 120D is reduced to increase the gate-drain overlap. Figure 2B ) provides a weak drain-side electric field, which reduces the sensitivity of the drain-channel junction to the voltage applied to the gate structure (e.g., gate electrode 140) and the drain region gate control, thereby minimizing the drain channel BTBT tunneling of the TFET 100.

[0056] The asymmetric gate dielectric 132 further contributes to the asymmetric electric field along the channel 110C. For example, since increasing the dielectric constant of the gate dielectric 132 increases the electric field along the channel 110C, configuring the gate dielectric 132 to have a source-side gate dielectric layer 134 having a dielectric constant greater than the dielectric constant of the drain-side gate dielectric layer 136 increases the strength of the source-side electric field relative to the drain-side electric field, thereby increasing the sensitivity of the source-channel junction to a voltage applied to the gate structure (e.g., gate electrode 140) relative to the sensitivity of the drain-channel junction to an applied voltage. In the depicted embodiment, the source-side gate dielectric layer 134 and the drain-side gate dielectric layer 136 have substantially the same thickness (e.g., t1≈t2). In such an embodiment, the gate electrode 140 can be symmetrical along the center line M in the top gate portion GT (e.g., the source side portion of the gate electrode 40 can have a width w1 that is substantially equal to the width w2 of the drain side portion of the gate electrode 140 (i.e., w1≈w2)), but the gate electrode 140 can be asymmetrical along the center line M in the bottom gate portion GB (e.g., the width w1 of the source side portion of the gate 140 increases from the top to the bottom of the bottom gate portion GB, while the width w2 of the drain side portion of the gate 140 is substantially the same from the top to the bottom of the bottom gate portion GB). In addition, in the depicted embodiment, the length l1 of the source side gate dielectric 134 along the channel 110C is greater than the distance l2 of the drain side gate dielectric 134 along the channel 110C (i.e., l1>l2). In some embodiments, the length l1 is substantially the same as the length l2 (i.e., l1≈l2). In some embodiments, the length l1 is less than the length l2 (i.e., l1<l2), which can further reduce the sensitivity of the drain-side electric field and / or the drain-channel junction to the voltage applied to the gate structure (e.g., its gate electrode 140). In some embodiments, the thickness t1 is at least 0.8 nm (i.e., t1≥0.8 nm). In some embodiments, the thickness t2 of the drain-side gate dielectric layer 136 can be increased to further reduce the drain-side electric field, such as Fig.10 and Fig.11As shown. Increasing the thickness t2 increases the distance between the gate electrode 140 and the drain 120D. In such embodiments, the thickness t2 is greater than the thickness t1, and the gate electrode 140 can be asymmetric along the center line M in the top gate portion GT (e.g., the width w1 of the source side portion of the gate electrode 140 is greater than the width w2 of the drain side portion of the gate 140 (i.e., w1>w2). In addition, in these embodiments, the width of the gate electrode 140 is reduced.

[0057] Fig.12 is a flow chart of a method 200 for partially or fully fabricating a tunneling field effect transistor (TFET) according to various aspects of the present disclosure. FIG. 13A to FIG. 23A According to various aspects of the present disclosure, Fig.12 A partial or full top view of a device 300 at various stages of the method 200. According to various aspects of the present disclosure, FIG. 13B to FIG. 23B Along FIG. 13A to FIG. 23A A cross-sectional view of the device 300 along line AA, FIG. 13C to FIG. 23C Along the FIG. 13A to FIG. 23A The method 200 can produce a TFET of a device 300, which can be similar to the TFET 100. For ease of description and understanding, the method 200 is discussed at the same time. Fig.12 , FIG. 13A to FIG. 23A , FIG. 13B to FIG. 23B and FIG. 13C to FIG. 23C For the sake of clarity, Fig.12 , FIG. 13A to FIG. 23A , FIG. 13B to FIG. 23B and FIG. 13C to FIG. 23C The method 200 has been simplified to better understand the inventive concepts of the present disclosure. Additional steps may be provided before, during, and after the method 200, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of the method 200. Additional features may be added to the device 300, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the device 300.

[0058] refer to Fig.12 and Figure 13A-13C , the method 200 includes receiving a device precursor for fabricating a TFET at block 205. In the depicted embodiment, the device precursor includes a substrate 302, a fin 305 extending from the substrate 302, and a substrate isolation structure 310 disposed on the substrate 302. The substrate 302 may be similar to the substrate 102 described above, the fin 305 may be similar to the fin 110 described above, and the substrate isolation structure 310 may be similar to the substrate isolation structure 125 described above.

[0059] refer to Fig.12 and Figure 13A-13C , the method 200 includes, at block 210, forming a dummy gate over a channel region of the fin. FIG. 13A to FIG. 13C In the device 300, a dummy gate 305 is formed above the channel region of the fin 305. The dummy gate 315 extends longitudinally in a direction different from (e.g., orthogonal to) the longitudinal direction of the fin 305. For example, the fin 305 extends longitudinally along the x-direction, and the dummy gate 315 extends longitudinally along the y-direction. The corresponding dummy gate 315 is disposed above the channel region (C) of the fin 305 and between the source region (S) and the drain region (D). In the active area of ​​the device 300, the dummy gate 315 may be disposed on the top and sidewalls of the fin 305, and the dummy gate 315 may wrap the channel region of the fin 305. In the isolation region of the device 300, the dummy gate 315 may be disposed above the top of the substrate isolation structure 310. In Fig. 13C In the fin 305 (eg, active region), the corresponding dummy gate 315 is disposed over the top of the channel region of the corresponding fin 305 , and is also disposed between the source region and the drain region of the corresponding fin 305 .

[0060] The dummy gate 315 includes a dummy material that can be oxidized during subsequent processing to form an oxide layer, the composition of which reduces the sensitivity of the channel region of the fin 305 to gate control. In the depicted embodiment, the dummy material is a silicon-containing material, such as polysilicon, and the dummy gate 315 can be referred to as a polysilicon gate. Each dummy gate 315 can include a single layer (e.g., a polysilicon layer) or multiple layers, such as a dummy gate dielectric (e.g., a silicon oxide layer), a dummy gate electrode (e.g., a polysilicon layer), a hard mask, other suitable layers, or a combination thereof.

[0061] The pseudo gate 315 is formed by a deposition process, a photolithography process, an etching process, other suitable processes or combinations thereof. For example, forming the pseudo gate 315 may include depositing a polysilicon layer on the device 300, forming an etching mask on the polysilicon layer (e.g., performing a photolithography process to form a patterned hard mask and / or a patterned photoresist thereon), and etching the polysilicon layer using the etching mask. The remaining portion of the polysilicon layer forms a pseudo gate 315 on the fin 305, as shown. The polysilicon layer can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other deposition processes or combinations thereof.

[0062] The dummy gate 315 is fabricated by a process that takes into account and based on the target gate CD (eg, width W T and / or width W B), target gate source overlap, target gate drain under-stack, other target parameters (e.g., target gate source relationship parameters, target gate drain relationship parameters, target gate parameters, etc.), or combinations thereof. In the depicted embodiment, the dummy gate 315 is intentionally fabricated to have a gate footing GF that increases gate source overlap and / or increases gate drain under-stack, which can improve TFET performance, as described herein. The parameters of the dummy gate fabrication process (e.g., etching parameters such as etchant, etching time, etching direction, etching type, etc.) can be adjusted to provide a dummy gate 315 having a sidewall profile that provides a target gate CD (e.g., a substantially vertical sidewall above the fin top FT and a tapered sidewall below the fin top FT) and / or to provide a dummy gate 315 having a target gate bottom width (e.g., width W GFX ) and / or a target sidewall tapered gate footing GF. In some embodiments, the parameters of the dummy gate fabrication process are adjusted to provide a gate footing GF at a target position relative to the fin top FT of the fin 305 (e.g., from about the fin top FT to the substrate isolation structure 310, as shown, or in some embodiments, from below the fin top FT to the substrate isolation structure 310). The target gate footing width, target sidewall tapering, target position, or a combination thereof may take into account the source profile and the drain profile to maximize the gate-source overlap and the gate-drain underlap, respectively.

[0063] refer to Fig.12 and Figure 13A-13C , the method 200 includes, at block 215, partially oxidizing the dummy gate to form a source-side oxide sidewall and a drain-side oxide sidewall, wherein a remaining portion of the dummy gate is located between the source-side oxide sidewall and the drain-side oxide sidewall. FIG. 13A to FIG. 13C In the process, an oxidation process is performed to partially oxidize the dummy gate 315, thereby forming a source side oxide sidewall 320S adjacent to the source region of the fin 305 and a drain side oxide sidewall 320D adjacent to the drain region of the fin 305. In other words, a portion of the dummy gate 315 (e.g., a polysilicon gate) is converted into an oxide portion / layer (e.g., a polysilicon oxide portion / film). After the oxidation process, the remaining portion of each dummy gate 315 is disposed between the corresponding source side oxide sidewall 320S and the corresponding drain side oxide sidewall 320D. The source side oxide sidewall 320S and the drain side oxide sidewall 320D may include silicon and oxygen, and the dummy gate 315 may include polysilicon. The source side oxide sidewall 320S and the drain side oxide sidewall 320D may also include nitrogen, and in some embodiments, may also include carbon. For example, the source side oxide sidewall 320S and the drain side oxide sidewall 320D may be SiO x N layers.

[0064] The oxidation process takes into account and is adjusted based on the target gate-drain overlap and / or other target gate-drain relationship parameters (e.g., thickness t2, thickness t3, target distance between gate electrode and drain facing tip / edge of gate stack, etc.). For example, the oxidation process is adjusted to completely oxidize the portion of dummy gate 315 forming gate footing GF, so that after the oxidation process, gate footing GF is formed of oxide instead of dummy gate 315 (i.e., the thickness of source-side oxide sidewall 320S and drain-side oxide sidewall 320D at the bottom of the gate structure (e.g., below fin top FT) is at least W. GFX ). In addition, the oxidation process may continue until the drain side oxide sidewall 320D has a desired thickness at the top of the gate structure (ie, above the fin top FT), which may be a target thickness for the drain side gate dielectric of the TFET of the device 300 .

[0065] In some embodiments, the oxidation process is a thermal oxidation process. In such an embodiment, the source side oxide sidewall 320S and the drain side oxide sidewall 320D can be formed by thermal oxidation of polysilicon. In some embodiments, the thermal oxidation process is performed in an oxygen environment. In some embodiments, the thermal oxidation process is performed in a nitrogen environment and / or a carbon environment. In some embodiments, the parameters of the oxidation process can be adjusted to oxidize the outside of the dummy gate 315, but not the inside of the dummy gate 314, thereby forming an external oxide layer. Each outer oxide layer can form a corresponding source side oxide sidewall 320S and a corresponding drain side oxide sidewall 320D. In some embodiments, each outer oxide layer can also include a bottom extending from the corresponding source side oxide sidewall 320S to the corresponding drain side oxide sidewall 320D. In such an embodiment, the outer oxide layer can wrap the inside of the dummy gate 315 (i.e., the remaining unoxidized portion of the dummy gate 315), as shown. In some embodiments, the bottom of the dummy gate 315 is not oxidized by the oxidation process, and an oxide layer is not between the bottom of the dummy gate 315 and the fin top FT of the fin 305 and / or between the dummy gate 315 and the bottom of the substrate isolation structure 310. Parameters of the oxidation process that can be adjusted to achieve the desired oxidation include time, temperature, environment, pressure, other parameters, or combinations thereof.

[0066] Reference Fig.12 and Figure 15A-Figure 15C At block 220 , method 200 includes forming gate spacers along sidewalls of the dummy gate. FIG. 15A to FIG. 15C, the gate spacer 330 is formed along the sidewall of the dummy gate 315 to form a gate structure. In the depicted embodiment, since the dummy gate 315 is partially oxidized before forming the gate spacer 330, the gate spacer 330 is arranged along the source side oxide sidewall 320S and the drain side oxide sidewall 320D, so that the source side oxide sidewall 320S is located between the dummy gate 315 and the gate spacer 330, and the drain side oxide sidewall 320D is located between the dummy gate 315 and the gate spacer 330. The gate structure can be collectively referred to as the corresponding dummy gate 315 and the gate spacer 330 arranged along the sidewall thereof, and in the illustrated embodiment, it can also refer to the corresponding source side oxide sidewall 320S and the corresponding drain side oxide sidewall 320D. The gate spacer 330 can be similar to the above-mentioned gate spacer 145. For example, the gate spacer 330 includes a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbon, silicon oxynitride, or combinations thereof). In some embodiments, forming the gate spacer 330 includes depositing a spacer layer including silicon and nitrogen and / or carbon (e.g., a SiN layer, a SiC layer, or a SiCN layer) on the device 300, and etching the spacer layer. In some embodiments, the source side oxide sidewall 320S and the drain side oxide sidewall 320D may be referred to as a first gate spacer, and the gate spacer 330 may be referred to as a second gate spacer. In other words, the first gate spacer may be formed along the sidewall of the dummy gate 315 by partially oxidizing the dummy gate 315, and the second gate spacer may be formed along the sidewall of the dummy gate 315 and adjacent to the first gate spacer by a deposition process and an etching process.

[0067] Reference Fig.12 and Figure 16A-16C At block 225 , method 200 includes forming a source and a drain in the source region and the drain region of the fin, respectively. Figure 16A-16C , a source 335S is formed in a source region of the fin 305, and a drain 335D is formed in a drain region of the fin 305. The source 335S and the drain 335D can be similar to the source 120S and the drain region 120D described above, respectively. For example, the source 335S has a first conductivity type, the drain 335D has a second conductivity type opposite to the first conductivity type, the source 335S has a source profile that optimizes gate-source overlap, and the drain 335D has a drain profile that optimizes gate-drain overlap, as described herein.

[0068] Forming the source 335S and the drain 335D may include forming a source recess (e.g., with curved sidewalls) in the source region of the fin 305, forming a drain recess in the drain region in the fin 305, forming a first semiconductor material having a first conductivity type filling the source region, and forming a second semiconductor material having a second conductivity type filling the drain region. In some embodiments, the first semiconductor material and the second semiconductor material have the same composition but different conductivity. In some embodiments, the first semiconductor material and the second semiconductor material have different compositions and different conductivity. In some embodiments, the source 335S and the drain 335D are formed in separate process sequences. For example, the source region is masked when the drain 335D is formed, and the drain region is masked when the source 335S is formed. In some embodiments, the source 335S and the drain 335D are at least partially formed simultaneously. For example, the same epitaxial growth process may be used to form the semiconductor materials of the source 335S and the drain 335D.

[0069] In some embodiments, the first semiconductor material and / or the second semiconductor material are formed by an epitaxial process, which may use a chemical vapor deposition (CVD) deposition technique (e.g., remote plasma CVD (RPCVD), low pressure CVD (LPCVD), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD) or a combination thereof), molecular beam epitaxy (MBE), other suitable epitaxial growth processes or a combination thereof. In such embodiments, the source 335S and the drain 335D may be referred to as an epitaxial source and an epitaxial drain, respectively. The epitaxial process may use a gaseous precursor and / or a liquid precursor that interacts with the composition of the fin 305. In some embodiments, the first semiconductor material and / or the second semiconductor material are doped during the deposition process by adding impurities to the source material of the epitaxial process (i.e., in situ). In some embodiments, after the epitaxial process and / or other deposition processes, the first semiconductor material and / or the second semiconductor material are doped by an ion implantation process or other doping process. In some embodiments, an annealing process (eg, rapid thermal annealing and / or laser annealing) is performed to activate dopants in the first semiconductor material and / or the second semiconductor material.

[0070] In some embodiments, after forming a source (such as source 335S) and a drain (such as drain 335D), a dielectric layer 340 is formed on the device 300. The dielectric layer 340 can be similar to the dielectric layer 150 described above. For example, the dielectric layer 340 can include a CESL, such as CESL 152, and an ILD layer, such as ILD layer 154. In some embodiments, forming the dielectric layer 340 includes depositing the CESL on the device 300, depositing the ILD layer on the CESL, and performing a planarization process. The planarization process can remove any of the CESL and / or ILD layer on top of the dummy gate 315. In some embodiments, the planarization process stops when reaching the dummy gate 315.

[0071] refer to Fig.12 and Figure 17A-Figure 17C , the method 200 includes removing the remaining portion of the dummy gate to form a gate opening at block 230. Figure 17A-Figure 17C , removing the remaining portion of the dummy gate 315 to form a gate opening 345. In some embodiments, the etching process selectively removes the dummy gate 315 relative to the oxide sidewalls (e.g., the source side oxide sidewall 320S and the drain side oxide sidewall 320D). For example, the etching process etches the dummy gate 315 without etching (or ignoring) the source side oxide sidewall 320S and the drain side oxide sidewall 320D. The etchant of the etching process can etch polysilicon (i.e., the dummy gate 315) at a higher rate than the oxide (i.e., the source side oxide sidewall 320S and the drain side oxide sidewall 320D). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof. In some embodiments, the patterned mask layer covers the dielectric layer 340 and / or the gate spacer 330, and exposes the dummy gate 315 in the etching process. In some embodiments, the etching process can also selectively remove the dummy gate 315 relative to the gate spacer 330, the dielectric layer 340, or a combination thereof. For example, the etching process may etch the dummy gate 315 without etching (or negligibly) the oxide sidewalls, the gate spacers 330, and the dielectric layer 340. In such an example, the etchant of the etching process may etch the polysilicon (ie, the dummy gate 315) at a higher rate than the dielectric material.

[0072] refer to Fig.12 , Figures 18A-18C and Figure 19A-Figure 19C , method 200 includes removing the source side oxide sidewalls, such as source side oxide sidewalls 320S, at block 235. The drain side oxide sidewalls, such as drain side oxide sidewalls 320D, remain to provide a drain side gate dielectric for the gate stack, as described herein. Figures 18A-18CIn the embodiment of the present invention, such processing may include forming a mask 348 on the device 300. The mask 348 is a patterned hard mask and / or a patterned photoresist that covers the drain side oxide sidewall 320D and exposes the source side oxide sidewall 320S. The mask 348 may also cover the drain region of the device 300 adjacent to the drain side oxide sidewall 320D and expose the source region of the device 300 adjacent to the source side oxide sidewall 320S. In the depicted embodiment, the mask 348 has an opening therein that exposes the source side oxide sidewall 320S and the source region of the device 300 adjacent thereto. The mask 348 is further formed in the gate opening 345 and partially covers / fills the gate opening 345, so that the gate opening 345 has a width W after the mask 348 is formed. The width W may be adjusted / tuned (eg, wider or narrower) to adjust / tune the length of the source-side gate dielectric and the length of the drain-side gate dielectric along the channel region of the fin 305 .

[0073] In some embodiments, the mask 348 is formed by forming a photoresist layer on the device 300 (e.g., by spin coating) and performing a photolithography process on the photoresist to form a patterned photoresist that covers the drain side oxide sidewall 320D and the drain region adjacent thereto, but exposes the source side oxide sidewall 320S and the source region adjacent thereto. In some embodiments, the mask 348 is formed by depositing a hard mask material on the device 300 and performing a patterning process to remove a portion of the hard mask covering the source side oxide sidewall 320S and the source region adjacent thereto. The patterning process may include performing a photolithography process to form a patterned photoresist layer, the patterned photoresist layer covering the drain side oxide sidewall 320D and the hard mask material over the drain region adjacent thereto, and exposing the hard mask material over the source side oxide sidewall 320S and the source region adjacent thereto, and performing an etching process to selectively remove the exposed hard mask material. The composition and / or thickness of the mask 348 is configured to be resistant to the etching process used to remove the source side oxide sidewalls 320S.

[0074] exist Figure 19A-Figure 19CIn the embodiment of the present invention, the etching process selectively removes the source side oxide sidewall 320S relative to the gate spacer 330. For example, the etching process etches the source side oxide sidewall 320S without etching (or negligibly etching) the gate spacer 330 and the dielectric layer 340 on the source region of the fin 305. In some embodiments, the etchant of the etching process etches the source side oxide sidewall 320S (e.g., a dielectric material having a first composition) at a higher rate than the gate spacer 330 and the dielectric layer 340 (e.g., dielectric materials having a second composition and a third composition, respectively, that are different from the first composition). The mask 348 resists the etching process (e.g., the mask 348 is an etching mask) and protects the drain side oxide sidewall 330 (and the dielectric layer 340 on the drain region of the fin 305, as shown) from the etching process. The etching process can also selectively remove the source side oxide sidewall 320S relative to the fin 305 and / or the substrate isolation structure 310. For example, the etching process can selectively remove the exposed portion of the source side oxide sidewall 320S extending over the source side portion of the channel region of the fin 305 and / or the source side portion of the isolation region of the device 300. After the etching process, the drain side oxide sidewall 320D and the portion of the drain side oxide sidewall 320D extending over the drain side portion of the channel region of the fin 305 and / or the drain region portion of the isolation region of the device 300 can be referred to as the drain side gate dielectric layer 350. The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0075] refer to Fig.12 and Figure 20A-20C , the method 200 includes, at block 240, forming a source-side gate dielectric in the gate opening. Figure 20A-20C , a source side gate dielectric layer 352 is formed in the gate opening 345 and partially fills the gate opening 345. In the depicted embodiment, the source side gate dielectric layer 352 is formed before removing the mask 348 so that the source side gate dielectric layer 352 is confined to the source side of the gate opening 345. In some embodiments, the source side gate dielectric layer 352 is formed after removing the mask 348 by a selective growth / deposition process (e.g., a high-k material may be selectively formed / grown on the fin 305 and / or gate spacer 330, but not on the drain side oxide sidewall 320S). The source side gate dielectric layer 352 may be similar to the source side gate dielectric layer 136 described above. For example, the source side dielectric layer 352 includes a dielectric material having a dielectric constant that is higher than the dielectric constant of the drain side dielectric layer 350 (e.g., a dielectric constant of a dielectric material including silicon, oxygen, and nitrogen). In some embodiments, the dielectric material is HfO 2 、HfSiO、HfSiO 4, HfSiNO, HfLaO, HfTaO, HfSTiO, HfZrO, HfAlO x 、ZrO、ZrO 2 、ZrSiO 2 、AlO、AlSiO、Al 2 O 3 、TiO、TiO 2 、LaO、LaSiO、Ta 2 O 3 、 2 O 5 , Y 2 O 3 、SrTiO 3 、BaZrO、BaTiO 3 (BTO), (Ba,Sr)TiO 3 (BST), Si 3 N 4 、HfO2-alumina (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectric materials, or combinations thereof. The source side gate dielectric layer 352 is formed by ALD, CVD, PVD, an oxidation-based deposition process, other suitable processes, or combinations thereof. For example, the ALD process conformally deposits the source side gate dielectric layer 352 so that the thickness of the source side gate dielectric layer 352 is substantially uniform (conformal) on various surfaces. In some embodiments, the source side gate dielectric layer 352 has a thickness t1.

[0076] Reference FIG. 21A to FIG. 21C , the mask 348 is removed by an appropriate process. For example, in the case where the mask 348 is a patterned photoresist, the mask 348 can be removed by a photoresist stripping process and / or other suitable processes. In another example, when the mask 348 is a patterned hard mask, the mask 348 can be removed by an appropriate etching process (such as a reactive ion etching (RIE) process). The mask 348 is selectively removed relative to the source side gate dielectric layer 352, the drain side gate dielectric layer 350, and the dielectric layer 340, and the portion of the source side gate dielectric layer 352 disposed on the mask 348 is also removed. Therefore, the device 300 is provided with a gate dielectric 358 that partially fills the gate opening 345, and each gate dielectric 358 includes a corresponding source side gate dielectric layer 352 and a corresponding drain side gate dielectric layer 350, which can improve TFET performance as described herein.

[0077] refer to Fig.12 and Figure 22A-22C, method 200 includes, at block 245, forming a gate electrode on the source side gate dielectric and the drain side gate dielectric. The gate electrode fills the remaining portion of the gate opening. Figure 22A-22C , a gate electrode 360 ​​is formed in the gate opening 345 above the source side gate dielectric layer 352 and the drain side gate dielectric layer 350, and the gate electrode 360 ​​fills the remaining portion of the gate opening 345. In some embodiments, as shown, each gate electrode 360 ​​includes a corresponding work function layer 362, a corresponding cap 364, and a corresponding bulk (filling) layer 366.

[0078] In some embodiments, the gate electrode 360 ​​is formed by depositing a work function material on the device 300 that partially fills the gate opening 345, depositing a cap material on the work function material that partially fills the gate opening 345, depositing a bulk / filling material on the work function material that fills the remaining portion of the gate opening 345, and performing a planarization process to remove excess gate material (e.g., gate material disposed on the dielectric layer 340). For example, a CMP process removes the bulk / filling material (e.g., bulk layer 366), the cap material (e.g., cap 364), the work function material (e.g., work function layer 362), and the gate dielectric material (e.g., source side gate dielectric layer 352) disposed on the dielectric layer 340. The CMP process may be performed until the top surface of the dielectric layer 340 is reached and / or exposed. Thus, the device 300 is provided with gate stacks 370, each of which has a corresponding gate dielectric 358 (e.g., a corresponding source side gate dielectric layer 352 and a corresponding drain side gate dielectric layer 350) and a corresponding gate electrode 360 ​​(e.g., a corresponding work function layer 362, a corresponding cap 364, and a corresponding bulk layer 366). Because the drain side oxide sidewall 320D remains but the source side oxide sidewall 320S is removed, the gate stack 370 has an asymmetric gate footing, such as a source side gate footing GFS formed by the gate dielectric 358 (e.g., its source side gate dielectric layer 352) and the gate electrode 360 ​​(e.g., its work function layer 362), and a drain side gate footing GFD formed by the gate dielectric 358 (e.g., its drain side gate dielectric layer 350). In some embodiments, the CMP process may continue to reduce the thickness of the dielectric layer 340 and correspondingly reduce the height of the gate structure (e.g., the height of the gate stack 370 and its gate spacers 330). In the depicted embodiment, after the planarization process, the top of the gate structure (e.g., the top of the gate stack 370) is substantially planar with the top of the dielectric layer 340, and the remaining portion of the gate material filling the gate opening 345 forms the gate stack 370. The work function material, cap material, and bulk / fill material may be deposited by ALD, CVD, PVD, other suitable processes, or combinations thereof.

[0079] The work function layer 362 is a conductive layer tuned to have a desired work function. The work function layer 362 may be an n-type work function metal (N-WFM) layer, a p-type work function material (P-WFM), or a combination thereof. The N-WFM layer (also referred to as an n-metal layer) includes an n-type work function material, which generally refers to a conductive material tuned to have an n-type work function, while the P-WFM layer (also referred to as a p-metal layer) includes a p-type work function material, which generally refers to a conductive material tuned to have a p-type work function. The n-type work function material may include a metal having a sufficiently low effective work function, such as aluminum, titanium, tantalum, zirconium, other n-type metals, alloys thereof, or combinations thereof. In some embodiments, the N-WFM layer is a titanium aluminum layer, a titanium aluminum carbide layer, a tantalum carbide layer, a tantalum carbonitride layer, or a tantalum silicon nitride. The p-type work function material may include a metal having a sufficiently high effective work function, such as titanium, tantalum, ruthenium, molybdenum, tungsten, platinum, other p-type metals, alloys thereof, or combinations thereof. In some embodiments, the P-WFM layer is a titanium nitride layer, a titanium carbide layer, a titanium silicon nitride layer, a tantalum nitride layer, a tungsten carbonitride layer, or a molybdenum layer. In some embodiments, the work function layer has a multi-layer structure, such as more than one N-WFM layer, more than one P-WFM layer, or an N-WFM layer and a P-WFM layer.

[0080] The bulk / filling layer 366 includes a conductive material, such as Al, W, Cu, Ti, Ta, polysilicon, other suitable metals and / or alloys thereof, or combinations thereof. In some embodiments, the bulk layer 366 is a tungsten layer formed by PVD or CVD. In some embodiments, the bulk layer 366 is a fluorine-free tungsten (FFW) layer. In some embodiments, the bulk layer 366 has a multilayer structure, such as a glue layer and a metal filling layer, such as a tungsten layer. The glue layer may include a material that promotes adhesion between adjacent layers, such as adhesion between the work function layer 362 / cap 264 and a subsequently formed metal filling layer, and / or a material that prevents or eliminates diffusion and / or reaction of components between adjacent layers. For example, the glue layer may include a metal and nitrogen, such as TiN, TaN, W 2 N, TiSiN, TaSiN, other suitable metal nitride materials or combinations thereof.

[0081] refer to FIG. 23A to FIG. 23CIn some embodiments, processing may further include forming interconnects, such as gate interconnects, source interconnects, drain interconnects, or combinations thereof. For example, processing may include forming a source contact 380 to the source 335S, a drain contact 382 to the drain 335D, a source via 384 to the source contact 380, a drain via 386 to the drain contact 382, ​​and a gate contact / via 390 to the gate stack 370 (e.g., to its gate electrode 360). In some embodiments, forming the source / drain contact includes forming a source / source contact opening in the dielectric layer 340 that exposes the source 335S or the drain 335D, and forming at least one conductive layer (e.g., metal) in the source / drain contact opening. In some embodiments, the source / drain contact opening is formed by forming a patterned mask layer (e.g., an etch mask) on the dielectric layer 340 and etching the exposed portion of the dielectric layer 340. In some embodiments, forming at least one conductive layer in the source / drain contact opening includes forming a metal silicide layer on the source or drain, depositing a barrier / liner layer that partially fills the source / drain contact opening, depositing a metal layer on the barrier / liner layer that fills the remaining portion of the source / drain contact opening, and performing a planarization process to remove portions of the barrier / liner layer and / or the metal layer disposed on top of the dielectric layer 340.

[0082] Fig.24 4 is a schematic diagram of a device 400 according to various aspects of the present disclosure, which includes various transistors, such as TFETs herein. Device 400 may include transistor 405, transistor 410, and transistor 415. Transistor 405 may be a metal oxide semiconductor (MOS) FET, and transistor 410 may be a TFET, such as Figure 3 As shown in TFET 100, transistor 415 may be a TFET such as Figure 8 TFE 100 is shown. Transistor 405 has a symmetric source / drain (e.g., the source and drain have the same conductivity type), while transistor 410 and transistor 415 have asymmetric source / drain, e.g., the source and drain have different conductivity types. In some embodiments, the asymmetric source / drain may include different materials, different conductivity, different profiles, different sizes, or a combination thereof, while the symmetric source / drain may include the same material, the same conductivity, the same profile, the same size, or a combination thereof. In some embodiments, transistor 405 has a symmetric gate stack (e.g., a high-k dielectric layer and a gate electrode (G)), while transistor 410 and transistor 415 have an asymmetric gate stack. The asymmetric gate stack may have an asymmetric gate dielectric, an asymmetric gate electrode, an asymmetric sidewall, or a combination thereof. For clarity, Fig.24It is simplified to better understand the inventive concepts of the present disclosure. Additional features may be added in the device 400, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the device 400.

[0083] The present disclosure provides many different embodiments. An exemplary tunneling field effect transistor includes a gate stack disposed on a semiconductor layer, a source disposed in the semiconductor layer, and a drain disposed in the semiconductor layer. The gate stack includes a gate electrode disposed on a gate dielectric. The gate stack is disposed between the source and the drain. The source has a first conductivity type, and the drain has a second conductivity type different from the first conductivity type. The gate stack is asymmetric. In some embodiments, the semiconductor layer is a semiconductor fin, the source and the drain are disposed in the semiconductor fin, and the gate stack wraps the semiconductor fin.

[0084] In some embodiments, the source extends below the gate stack and the drain does not extend below the gate stack. In some embodiments, the gate stack has a source-side gate footing and a drain-side gate footing, wherein the source-side gate footing includes a gate electrode and a gate dielectric, and the drain-side gate footing includes a gate dielectric and no gate electrode.

[0085] In some embodiments, the gate dielectric of the gate stack has a source side gate dielectric and a drain side gate dielectric, and the source side gate dielectric is different from the drain side gate dielectric. In some embodiments, the source side gate dielectric has a first dielectric constant, the drain side gate dielectric has a second dielectric constant, and the second dielectric constant is different from the first dielectric constant. In some embodiments, the source side gate dielectric has a first thickness, the drain side gate dielectric has a second thickness, and the second thickness is different from the first thickness. In some embodiments, the source side gate dielectric forms a source side sidewall of the gate stack, and the drain side gate dielectric forms a drain side sidewall of the gate stack. In some embodiments, the source side gate dielectric includes metal and oxygen; and the drain side gate dielectric includes silicon, oxygen, and nitrogen.

[0086] Another exemplary tunneling field effect transistor includes a channel region, a source, and a drain. The channel region is disposed between the source and the drain. A gate stack is disposed above the channel region. The gate stack includes a source-side gate dielectric, a drain-side gate dielectric, and a gate electrode disposed above the source-side gate dielectric and the drain-side gate dielectric. The source-side gate dielectric has a first dielectric constant, and the drain-side gate dielectric has a second dielectric constant. The tunneling field effect transistor also includes a source-side gate spacer and a drain-side gate spacer, which are disposed adjacent to the source-side gate dielectric and the drain-side gate dielectric, respectively.

[0087] In some embodiments, the channel region, the source and the drain are disposed in a semiconductor fin, and the gate stack wraps the semiconductor fin. In some embodiments, the channel region is disposed in a semiconductor layer extending the source and the drain, and the gate stack at least partially surrounds the semiconductor layer.

[0088] In some embodiments, a first length of the source side gate dielectric along the top of the channel region is different from a second length of the drain side gate dielectric along the top of the channel region. In some embodiments, the source side gate dielectric has a first thickness, the drain side gate dielectric has a second thickness, and the second thickness is greater than the first thickness. In some embodiments, the contour of the source and the contour of the gate stack provide gate-source overlap; the contour of the drain and the contour of the gate stack provide gate-drain overlap. In some embodiments, the source has a curved sidewall and the drain has a tapered sidewall. In some embodiments, the gate stack has a source side gate footer and a drain side gate footer, the source side gate footer includes a gate electrode and a source side gate dielectric, and the drain side gate footer includes a drain side gate dielectric.

[0089] In some embodiments, the cross-sectional profile of the source is different from the cross-sectional profile of the drain. In some embodiments, the top profile of the source is different from the top profile of the drain. In some embodiments, the length of the longest part of the source is greater than the length of the shortest part of the drain.

[0090] One exemplary method includes forming a dummy gate, forming a gate spacer adjacent to the dummy gate, oxidizing the dummy gate to form a first oxide sidewall and a second oxide sidewall, forming a gate opening by removing a remaining portion of the dummy gate, masking the first oxide sidewall, forming a gate dielectric layer after removing the second oxide sidewall, and forming a gate electrode in the gate opening after not masking the first oxide sidewall. Another exemplary method includes forming a dummy gate, oxidizing the dummy gate to form a first oxide sidewall and a second oxide sidewall, forming a gate spacer adjacent to the first oxide sidewall and the second oxide sidewall, forming a gate opening by removing a remaining portion of the dummy gate, masking the first oxide sidewall, forming a gate dielectric layer after removing the second oxide sidewall, and forming a gate electrode in the gate opening after not masking the first oxide sidewall. In some embodiments, the method further includes forming a source and a drain after oxidizing the dummy gate and before removing the remaining portion of the dummy gate. In some embodiments, masking the first oxide sidewall includes masking the drain side oxide sidewall; and removing the second oxide sidewall includes removing the source side oxide sidewall. In some embodiments, the gate dielectric layer is formed before unmasking the first oxide sidewalls. In some embodiments, the method further comprises forming a dummy gate to have a source side gate footing and a drain side gate footing, wherein oxidation of the dummy gate is performed until the drain side gate footing is formed by the first oxide sidewalls.

[0091] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A tunneling field effect transistor, comprising: a gate stack disposed over the semiconductor layer, wherein the gate stack comprises a gate electrode disposed over a gate dielectric; a source and a drain disposed in the semiconductor layer, wherein the gate stack is disposed between the source and the drain, the source has a first conductivity type, and the drain has a second conductivity type different from the first conductivity type; and Wherein, the gate stack is asymmetric.

2. The tunneling field effect transistor according to claim 1, wherein: The gate dielectric of the gate stack has a source side gate dielectric and a drain side gate dielectric, and the source side gate dielectric is different from the drain side gate dielectric.

3. The tunneling field effect transistor according to claim 2, wherein: The source side gate dielectric has a first dielectric constant, the drain side gate dielectric has a second dielectric constant, and the second dielectric constant is different from the first dielectric constant.

4. The tunneling field effect transistor according to claim 2, wherein: The source side gate dielectric has a first thickness, the drain side gate dielectric has a second thickness, and the second thickness is different from the first thickness.

5. The tunneling field effect transistor according to claim 2, wherein: The source-side gate dielectric forms a source-side sidewall of the gate stack, and the drain-side gate dielectric forms a drain-side sidewall of the gate stack.

6. The tunneling field effect transistor according to claim 1, wherein: The gate stack has a source side gate footing and a drain side gate footing, wherein the source side gate footing includes the gate electrode and the gate dielectric, and the drain side gate footing includes the gate dielectric and is devoid of the gate electrode.

7. A tunneling field effect transistor, comprising: a channel region disposed between the source and the drain; as well as a gate stack disposed over the channel region, wherein the gate stack comprises a source-side gate dielectric, a drain-side gate dielectric, and a gate electrode disposed over the source-side gate dielectric and the drain-side gate dielectric, wherein the source-side gate dielectric has a first dielectric constant and the drain-side gate dielectric has a second dielectric constant; and A source-side gate spacer and a drain-side gate spacer are disposed adjacent to the source-side gate dielectric and the drain-side gate dielectric, respectively.

8. The tunneling field effect transistor according to claim 7, wherein: A profile of the source and a profile of the gate stack provide a gate-source overlap; as well as A profile of the drain and a profile of the gate stack provide a gate-drain overlap.

9. The tunneling field effect transistor according to claim 7, wherein: The source has a curved sidewall, and the drain has a tapered sidewall.

10. A method for manufacturing a tunneling field effect transistor, comprising: forming a dummy gate; Oxidizing the dummy gate to form a first oxide sidewall and a second oxide sidewall; forming a gate spacer adjacent to the first oxide sidewall and the second oxide sidewall; forming a gate opening by removing a remaining portion of the dummy gate; masking the first oxide sidewalls; After removing the second oxide sidewall, forming a gate dielectric layer; as well as A gate electrode is formed in the gate opening after unmasking the first oxide sidewalls.

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