Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the structure comprising: a substrate; a gate structure on the substrate; a channel column on the substrate and longitudinally penetrating the gate structure; a sidewall structure extending longitudinally between a sidewall of the channel column and the gate structure; and a compensation layer filled in a gap between the channel column and the gate structure at a bottom position of the sidewall structure. The present application is advantageous to improve the working performance of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Semiconductor devices are integrated on a package to realize integrated circuit (IC) chips to meet the use conditions of various electronic products. In recent years, the demand for integrated systems for special processing applications is increasing in complex scenarios such as the Internet of Things, edge computing, etc. The function-integrated system requires the integration of the underlying material. However, the traditional semiconductor memory device can be a two-dimensional or planar semiconductor memory device, and the integration degree is an important factor in determining the price of the product.

[0003] In addition, the integration degree mainly depends on the area occupied by the unit storage unit, and is therefore greatly affected by the level of fine pattern forming technology. However, the integration degree of the two-dimensional semiconductor memory device is increasing, but is still limited because the miniaturization of the pattern requires super expensive equipment. Therefore, it is necessary to improve the integration degree of the semiconductor memory device to meet the superior performance and low cost required by consumers. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to improve the working performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a channel column located on the substrate and longitudinally penetrating the gate structure; a side wall structure extending longitudinally between the side wall of the channel column and the gate structure; a compensation layer filled in the gap between the channel column and the gate structure at the bottom position of the side wall structure.

[0006] Optionally, the semiconductor structure further comprises: a spacer layer located between the side wall structure and the side wall of the channel column; and the compensation layer is further filled in the gap between the channel column and the gate structure at the bottom position of the spacer layer.

[0007] Optionally, the spacer layer is a protective layer covering the side wall of the side wall structure; or the spacer layer is an air gap.

[0008] Optionally, the spacer layer is a protective layer, and the material of the protective layer comprises amorphous silicon, polysilicon, a combination of polysilicon and silicon oxide, and a combination of polysilicon and titanium nitride.

[0009] Optionally, the compensation layer is further filled in the gap surrounded by the top of the side wall structure and the spacer layer.

[0010] Optionally, the side wall structure comprises a first side wall covering the sidewall of the gate structure, and a second side wall covering the sidewall of the first side wall; at the bottom of the side wall structure, the gap filled by the compensation layer is surrounded by the bottom of the second side wall, the bottom of the spacer layer, the first side wall, and the sidewall of the channel column; at the top of the side wall structure, the gap filled by the compensation layer is surrounded by the top of the second side wall, the sidewall of the spacer layer, and the sidewall of the first side wall.

[0011] Optionally, the material of the first side wall comprises silicon nitride; and the material of the second side wall comprises silicon oxide.

[0012] Optionally, the material of the compensation layer comprises silicon nitride.

[0013] Optionally, the semiconductor structure further comprises: a top dielectric layer covering the top of the gate structure; a bottom dielectric layer between the gate structure and the substrate; the channel column further extends through the top dielectric layer and the bottom dielectric layer; the side wall structure further extends between the sidewall of the channel column and the top dielectric layer; and the compensation layer further fills the gap between the channel column and the bottom dielectric layer.

[0014] Optionally, the semiconductor structure further comprises: a source-drain doped layer in the substrate, and the top surface of the substrate exposes the source-drain doped layer; and the channel column is on the source-drain doped layer and in contact with the source-drain doped layer.

[0015] Optionally, a groove in the channel column at a partial height is formed on one side of the top of the channel column, and the semiconductor structure further comprises: an insulating layer filled in the groove.

[0016] Correspondingly, the embodiment of the present application further provides a forming method of a semiconductor structure, comprising: providing a substrate, and a gate structure formed on the substrate; forming an opening through the gate structure; forming a side wall structure covering the sidewall of the opening; performing a gap compensation treatment at the bottom corner of the opening to form a compensation layer filling the gap at the bottom of the side wall structure; and forming a channel column on the substrate and through the gate structure in the opening.

[0017] Optionally, before the gap compensation treatment at the bottom corner of the opening, the method further comprises: forming a protective layer covering the sidewall of the side wall structure; in the step of performing the gap compensation treatment at the bottom corner of the opening, the compensation layer further fills the gap at the bottom of the protective layer at the bottom corner of the opening; and in the step of forming the channel column on the substrate and through the gate structure in the opening, the channel column is in contact with the protective layer.

[0018] Optionally, after the step of forming the channel column on the substrate and through the gate structure in the opening, the method further comprises: removing the protective layer to form an air gap between the side wall structure and the sidewall of the channel column.

[0019] Optionally, in the step of performing the gap compensation treatment at the bottom corner of the opening, the compensation layer further fills the gap surrounded by the top of the side wall structure and the protective layer.

[0020] Optionally, the step of forming the sidewall structure covering the sidewall of the opening comprises: forming a sidewall structure material layer covering the sidewall of the opening and the bottom, and the top of the gate structure; removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, and retaining the sidewall structure material layer covering the sidewall of the opening as the sidewall structure.

[0021] Optionally, in the step of providing the substrate, the top of the gate structure is further formed with a top dielectric layer, and the gate structure is further formed with a bottom dielectric layer between the gate structure and the substrate; in the step of forming the opening penetrating the gate structure, the opening further penetrates the top dielectric layer, and the opening further extends in the bottom dielectric layer by a partial thickness; in the step of removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, the step further comprises: removing the bottom dielectric layer by the remaining partial thickness to expose the top surface of the substrate; in the step of performing the gap compensation treatment at the corner of the bottom of the opening, the compensation layer further fills the gap surrounded by the bottom dielectric layer and the substrate at the corner of the bottom of the opening.

[0022] Optionally, the step of forming the sidewall structure material layer covering the sidewall of the opening and the bottom, and the top of the gate structure comprises: forming a first sidewall material layer covering the sidewall of the opening and the bottom, and the top of the gate structure; forming a second sidewall material layer covering the first sidewall material layer; in the step of removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, the first sidewall material layer and the second sidewall material layer on the bottom of the opening and the top of the gate structure are removed, the first sidewall material layer covering the sidewall of the opening is retained as the first sidewall, and the second sidewall material layer covering the sidewall of the opening is retained as the second sidewall; in the step of performing the gap compensation treatment at the corner of the bottom of the opening, the compensation layer fills the gap surrounded by the bottom surface of the second sidewall, the bottom surface of the protection layer, and the first sidewall, and the compensation layer further fills the gap surrounded by the top surface of the second sidewall, the sidewall of the protection layer, and the sidewall of the first sidewall.

[0023] Optionally, before the step of removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, the step further comprises: forming a protection material layer covering the sidewall structure material layer; in the step of removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, the step further comprises: removing the protection material layer on the bottom of the opening and the top of the gate structure, and retaining the protection material layer covering the sidewall of the sidewall structure as the protection layer.

[0024] Optionally, the sidewall structure material layer on the bottom of the opening and the top of the gate structure is removed by using a dry etching process; before the step of performing the gap compensation treatment at the corner of the bottom of the opening after the step of removing the sidewall structure material layer on the bottom of the opening and the top of the gate structure, the step further comprises: performing a cleaning treatment on the sidewall structure.

[0025] Optionally, the step of forming the compensation layer filling the gap at the bottom of the side wall structure includes: forming a compensation material layer covering the bottom of the opening, the side wall of the side wall structure, and the top of the gate structure; removing the compensation material layer covering the bottom of the opening, the side wall of the side wall structure, and the top of the gate structure, and leaving the compensation material layer filling the gap at the bottom of the side wall structure as the compensation layer.

[0026] Optionally, the compensation material layer covering the bottom of the opening, the side wall of the side wall structure, and the top of the gate structure is formed by an atomic layer deposition process or a low pressure chemical vapor deposition process.

[0027] Optionally, the compensation material layer covering the bottom of the opening, the side wall of the side wall structure, and the top of the gate structure is removed by a wet etching process.

[0028] Optionally, the etching solution of the wet etching process includes a phosphoric acid solution, the mass percentage of the phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%, and the process temperature of the wet etching process is 100℃ to 160℃.

[0029] Optionally, in the step of providing the substrate, an active source-drain doped layer is also formed in the substrate, and the top surface of the substrate exposes the source-drain doped layer; in the step of forming the opening penetrating the gate structure, the opening is formed above the source-drain doped layer; in the step of forming the channel column on the substrate and penetrating the gate structure in the opening, the channel column is formed on the source-drain doped layer and in contact with the source-drain doped layer.

[0030] Optionally, in the step of forming the channel column on the substrate and penetrating the gate structure in the opening, the channel column fills the opening; or, in the step of forming the channel column on the substrate and penetrating the gate structure in the opening, a groove in the channel column is formed on one side of the top of the channel column to a partial height; and an insulating layer filling the groove is formed.

[0031] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0032] The semiconductor structure provided by the embodiment of the present application is characterized in that the channel column is located on the substrate and longitudinally penetrates the gate structure, the sidewall structure longitudinally extends between the sidewall of the channel column and the gate structure, and the compensation layer is filled in the gap between the channel column and the gate structure at the bottom position of the sidewall structure. In the embodiment of the present application, the compensation layer is filled in the gap between the channel column and the gate structure at the bottom position of the sidewall structure, so that the compensation layer can compensate for the insulation performance of the bottom of the sidewall structure to the gate structure and the channel column, which is beneficial to guarantee the insulation effect between the gate structure and the channel column, thereby being beneficial to reduce the probability of the leakage current between the gate structure and the channel column, guarantee the threshold voltage of the semiconductor structure to meet the process requirement, reduce the probability of the decrease of the drain induced barrier lowering of the semiconductor structure, and further guarantee the working performance of the semiconductor structure.

[0033] The forming method provided by the embodiment of the present application is characterized in that the opening penetrating the gate structure is formed, the sidewall structure covering the sidewall of the opening is formed, the gap compensation treatment is performed at the bottom corner of the opening, the compensation layer filling the gap at the bottom of the sidewall structure is formed, and the channel column located on the substrate and penetrating the gate structure is formed in the opening. In the embodiment of the present application, the gap compensation treatment is performed at the bottom corner of the opening, so that the compensation layer can compensate for the insulation performance of the bottom of the sidewall structure to the gate structure and the channel column, which is beneficial to guarantee the insulation effect between the gate structure and the channel column, thereby being beneficial to reduce the probability of the leakage current between the gate structure and the channel column, guarantee the threshold voltage of the semiconductor structure to meet the process requirement, reduce the probability of the decrease of the drain induced barrier lowering of the semiconductor structure, and further guarantee the working performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structure diagram corresponding to a semiconductor structure;

[0035] Figure 2 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application;

[0036] Figure 3 is a structure diagram corresponding to another embodiment of the semiconductor structure of the present application;

[0037] Figure 4 is a structure diagram corresponding to still another embodiment of the semiconductor structure of the present application;

[0038] Figures 5 to 12 is a structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application;

[0039] Figures 13 to 15 is a structure diagram corresponding to each step in another embodiment of the forming method of the semiconductor structure of the present application;

[0040] Figure 16This is a schematic diagram of the structure corresponding to each step in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0041] As the background technology shows, it is currently difficult to guarantee the working performance of semiconductor structures. This paper analyzes, using an example semiconductor structure, why the working performance of semiconductor structures still needs improvement.

[0042] Figure 1 A schematic diagram of a semiconductor structure is shown.

[0043] refer to Figure 1 The semiconductor structure includes: a substrate 10, in which an active drain doped layer 11 is formed; a gate structure 20 located on the substrate 10; a channel pillar 61 located on the active drain doped layer 11 in the substrate 10 and extending longitudinally through the gate structure 20; and a sidewall 46 extending longitudinally between the sidewall of the channel pillar 61 and the gate structure 20.

[0044] In semiconductor manufacturing, the process of forming the sidewall 46 can easily cause damage to the bottom of the sidewall 46, resulting in the absence of the sidewall 46 at the bottom of the channel pillar 61 (e.g. Figure 1 As shown by the dashed coil in the middle, the isolation performance between the channel pillar 61 and the gate structure 20 is poor at the bottom of the sidewall 46, which easily leads to leakage current (Off-state Leakage Current, Ig) between the gate structure 20 and the channel pillar 61. off The threshold voltage (V) that affects the semiconductor structure t This leads to a decrease in the drain-induced barrier low (DIBL) of the semiconductor structure, thereby affecting the working performance of the semiconductor structure.

[0045] To address the technical problem, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; a channel pillar located on the substrate and extending longitudinally through the gate structure; a sidewall structure extending longitudinally between the sidewall of the channel pillar and the gate structure; and a compensation layer filling the gap between the channel pillar and the gate structure at the bottom of the sidewall structure.

[0046] In the embodiment of the present application, the compensation layer is filled in the gap between the channel column and the gate structure at the bottom position of the side wall structure, so that the compensation layer can compensate for the isolation performance of the bottom of the side wall structure to the gate structure and the channel column, which is beneficial to guarantee the insulation effect between the gate structure and the channel column, thereby being beneficial to reduce the probability of leakage current between the gate structure and the channel column, being beneficial to guarantee that the threshold voltage of the semiconductor structure meets the process requirement, being beneficial to reduce the probability of the decrease of the drain-induced barrier lowering of the semiconductor structure, and further being beneficial to guarantee the working performance of the semiconductor structure.

[0047] In order to make the above-mentioned purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0048] Figure 2 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application.

[0049] Reference Figure 2 The semiconductor structure comprises: a substrate 100; a gate structure 200 located on the substrate 100; a channel column 610 located on the substrate 100 and longitudinally penetrating the gate structure 200; a side wall structure 460 extending longitudinally between the sidewall of the channel column 610 and the gate structure 200; and a compensation layer 510 filled in the gap between the channel column 610 and the gate structure 200 at the bottom position of the side wall structure 460.

[0050] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0051] In the embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in the embodiment, the material of the substrate 100 is silicon oxide.

[0052] The gate structure 200 is used to control the opening and closing of the channel of the transistor.

[0053] In the embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. As an example, in the embodiment, the material of the gate structure 200 is W.

[0054] The channel column 610 is used as the channel of the transistor.

[0055] Specifically, in the embodiment, the channel pillar 610 extends through the gate structure 200 in the longitudinal direction, forming a vertical channel transistor (VCT). Through the vertical channel design, the integration of the transistor is improved, so that more transistors can be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0056] In the embodiment, the material of the channel pillar 610 includes silicon, germanium, silicon germanium, or group III-V semiconductor material. As an example, in the embodiment, the material of the channel pillar 610 is silicon. In other embodiments, the material of the channel pillar is determined according to the type and performance of the transistor.

[0057] The side wall structure 460 is used to isolate the gate structure 200 and the channel pillar 610.

[0058] In the embodiment, the side wall structure 460 includes a first side wall 440 covering the sidewall of the gate structure 200, and a second side wall 450 covering the sidewall of the first side wall 440.

[0059] The use of the first side wall 440 and the second side wall 450 to form the side wall structure 460 is advantageous to ensure the isolation effect of the side wall structure 460, and also allows the dielectric constant of the side wall structure 460 to be adjusted through the first side wall 440 and the second side wall 450.

[0060] Specifically, in the embodiment, the material of the first side wall 440 includes silicon nitride, and the material of the second side wall 450 includes silicon oxide.

[0061] In the embodiment, the thickness of the first side wall 440 is 1-8 nm, which is advantageous to make the first side wall 440 have sufficient thickness to ensure the isolation performance of the side wall structure 460, and the first side wall 440 will not occupy too much space to meet the integration of the semiconductor structure.

[0062] In the embodiment, the thickness of the second side wall 450 is 1-8 nm, which is advantageous to make the second side wall 450 have sufficient thickness to ensure the isolation performance of the side wall structure 460, and the second side wall 450 will not occupy too much space to meet the integration of the semiconductor structure.

[0063] The compensation layer 510 is filled in the gap between the gate structure 200 and the channel pillar 610 at the bottom position of the side wall structure 460 (as shown by the dashed line circle), which is used to compensate for the isolation effect between the gate structure 200 and the channel pillar 610 at the bottom of the side wall structure 460. Figure 2

[0064] ​In the embodiment, the compensation layer 510 is filled in the gap between the channel column 610 and the gate structure 200 at the bottom of the side wall structure 460, so that the compensation layer 510 can compensate for the isolation performance of the bottom of the side wall structure 460 to the gate structure 200 and the channel column 610, so as to help to guarantee the insulation effect between the gate structure 200 and the channel column 610, thereby helping to reduce the probability of leakage current between the gate structure 200 and the channel column 610, helping to guarantee that the threshold voltage of the semiconductor structure meets the process requirement, helping to reduce the probability of the decrease of the drain induced barrier lowering of the semiconductor structure, and further helping to guarantee the working performance of the semiconductor structure.

[0065] It should be noted that in the semiconductor process, the bottom of the side wall structure 460 is prone to form a gap due to process damage, and therefore, the compensation layer 510 is filled in the gap between the channel column 610 and the gate structure 200 at the bottom of the side wall structure 460.

[0066] In the embodiment, the material of the compensation layer 510 includes silicon nitride.

[0067] The use of silicon nitride to form the compensation layer 510 can achieve good isolation effect, and the silicon nitride has large hardness and small damage in the semiconductor process, so as to guarantee the isolation effect of the compensation layer 510.

[0068] In the embodiment, the semiconductor structure further includes a spacer layer 480 located between the side wall structure 460 and the side wall of the channel column 610.

[0069] The spacer layer 480 is located between the side wall structure 460 and the side wall of the channel column 610, and the region of the spacer layer 480 is used to protect the side wall structure 460 in the process of forming the channel column 610.

[0070] In the embodiment, the compensation layer 510 is also filled in the gap between the channel column 610 and the gate structure 200 at the bottom of the spacer layer 480.

[0071] Specifically, in the semiconductor process, the region of the spacer layer 480 covers the side wall of the side wall structure 460, so that in the forming process of the side wall structure 460, the bottom of the region of the spacer layer 480 will cause damage to the side wall structure 460, and accordingly, the compensation layer 510 is also filled in the gap between the channel column 610 and the gate structure 200 at the bottom of the spacer layer 480.

[0072] In the embodiment, the thickness of the spacer layer 480 is 3nm to 12nm.

[0073] The thickness of the spacer layer 480 is 3nm to 12nm, which is helpful to reduce the difficulty of forming the spacer layer 480 and also helps to provide sufficient protection to the side wall structure 460.

[0074] In the embodiment, the compensation layer 510 also fills the gap between the top of the side wall structure 460 and the spacer layer 480.

[0075] It should be noted that in the semiconductor process, the top of the side wall structure 460 is also exposed by the spacer layer 480, and the top of the side wall structure 460 is also likely to form a gap due to process damage, and therefore, the compensation layer 510 also fills the gap between the top of the side wall structure 460 and the spacer layer 480.

[0076] Specifically, in the embodiment, at the bottom of the side wall structure 460, the gap filled by the compensation layer 510 is surrounded by the bottom surface of the second side wall 450, the bottom surface of the spacer layer 480, the first side wall 440, and the sidewall of the channel column 610; at the top of the side wall structure 460, the gap filled by the compensation layer 510 is surrounded by the top surface of the second side wall 450, the sidewall of the spacer layer 480, and the sidewall of the first side wall 440.

[0077] It should be noted that in the semiconductor process, the side wall structure 460 covering the sidewall of the gate structure 200 is formed first, and then the channel column 610 is formed between the side wall structure 460, and in the process of the side wall structure 460, the second side wall 450 is closer to the area of the process operation than the first side wall 440, so that the second side wall 450 is more likely to be damaged, and the material of the first side wall 440 includes silicon nitride, and the material of the second side wall 450 includes silicon oxide, and silicon oxide is more likely to be damaged than silicon nitride, that is, the top and bottom of the second side wall 450 are easily removed by process damage, and therefore, at the bottom of the side wall structure 460, the gap filled by the compensation layer 510 is surrounded by the bottom of the second side wall 450, the bottom of the spacer layer 480, the first side wall 440, and the sidewall of the channel column 610; at the top of the side wall structure 460, the gap filled by the compensation layer 510 is surrounded by the top of the second side wall 450, the sidewall of the spacer layer 480, and the sidewall of the first side wall 440.

[0078] In the embodiment, the spacer layer 480 is a protection layer 470, and the protection layer 470 covers the sidewall of the side wall structure 460.

[0079] The protection layer 470 is used to protect the side wall structure 460 in the process of the side wall structure 460 to reduce damage to the side wall structure 460.

[0080] In the embodiment, the material of the protection layer 470 includes amorphous silicon, polysilicon, a combination of polysilicon and silicon oxide and tungsten, or a combination of polysilicon and silicon oxide and titanium nitride.

[0081] The protective layer 470 is formed by using amorphous silicon, polysilicon, a combination of polysilicon and silicon oxide, or a combination of polysilicon and titanium nitride, which can play a good protective role, and the protective layer 470 reserved on both sides of the channel column 610 will not introduce other elements that are easy to contaminate, which is beneficial to protect the basic working performance of the transistor.

[0082] In this embodiment, the semiconductor structure further includes a top dielectric layer 320 covering the top surface of the gate structure 200.

[0083] The top dielectric layer 320 is used to isolate the gate structure 200 and other device structures above it.

[0084] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0085] Correspondingly, in this embodiment, the side wall structure 460 also extends between the sidewall of the channel column 610 and the top dielectric layer 320.

[0086] In this embodiment, the semiconductor structure further includes a bottom dielectric layer 310 between the gate structure 200 and the substrate 100.

[0087] The bottom dielectric layer 310 is used to isolate the gate structure 200 and other device structures below it.

[0088] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0089] Correspondingly, in this embodiment, the channel column 610 also extends through the top dielectric layer 320 and the bottom dielectric layer 310.

[0090] In this embodiment, the compensation layer 510 also fills the gap between the channel column 610 and the bottom dielectric layer 310.

[0091] In the semiconductor process, the protective layer 470 covering the side wall structure 460 is formed first, and then the area for forming the channel column 610 is formed through the bottom dielectric layer 310. During the process operation, the sidewall of the bottom dielectric layer 310 is also exposed, so that the bottom dielectric layer 310 is also damaged by the process operation. Therefore, in the process of forming the compensation layer 510, the compensation layer 510 also fills the gap between the channel column 610 and the bottom dielectric layer 310.

[0092] In this embodiment, the semiconductor structure further includes a source-drain doped layer 110 in the substrate 100, and the top surface of the substrate 100 exposes the source-drain doped layer 110.

[0093] The source-drain doped layer 110 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0094] In the embodiment, the source-drain doped layer 110 is exposed on the top surface of the substrate 100, so that the channel pillar 610 on the substrate 100 is in contact with the source-drain doped layer 110.

[0095] Correspondingly, in the embodiment, the channel pillar 610 is on the source-drain doped layer 110 and in contact with the source-drain doped layer 110.

[0096] Figure 3 is a structural schematic diagram of another embodiment of the semiconductor structure of the present application.

[0097] The same as the foregoing embodiments, details are not described herein. The difference between the embodiment and the foregoing embodiments is that the structure of the channel pillar is different.

[0098] Referring to Figure 3 , the channel pillar 611 has a recess 620 formed on one side of the top of the channel pillar 611 at a partial height, and the semiconductor structure further comprises: an insulating layer 640 filled in the recess 620.

[0099] The channel pillar 611 does not fill the area between the sidewall structures 461 completely, and the insulating layer 640 is filled in the recess 620, which is beneficial to obtain a top surface of the channel pillar 611 with better surface flatness.

[0100] In the embodiment, the material of the insulating layer 640 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0101] Figure 4 is a structural schematic diagram of another embodiment of the semiconductor structure of the present application.

[0102] The same as the foregoing embodiments, details are not described herein. The difference between the embodiment and the foregoing embodiments is that the structure of the spacer layer is different.

[0103] Referring to Figure 4 , the spacer layer 482 is an air gap 650.

[0104] The air gap 650 is used to isolate the gate structure 202 and the channel pillar 612 together with the sidewall structure 462.

[0105] Specifically, in the embodiment, the protective layer occupies the position in advance, and after the channel pillar 612 is formed, the protective layer is removed to form the air gap 650.

[0106] In this embodiment, the air gap 650 together with the sidewall structure 462 isolates the gate structure 202 and the channel pillar 612, and the dielectric constant of air is low, so that the air gap 650 together with the sidewall structure 462 isolates the gate structure 202 and the channel pillar 612, which is beneficial to reduce the overall dielectric constant of the isolation between the gate structure 202 and the channel pillar 612, thereby reducing the parasitic capacitance and improving the working performance of the semiconductor structure.

[0107] Figures 5 to 12 is a structure diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure.

[0108] Reference Figure 5 A substrate 100 is provided, and the substrate 100 has a gate structure 200 formed thereon.

[0109] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0110] In this embodiment, the substrate 100 is a dielectric material, and specifically, the material of the substrate 100 includes silicon oxide or silicon nitride. As an example, in this embodiment, the material of the substrate 100 is silicon oxide.

[0111] The gate structure 200 is used to control the opening and closing of the channel of the transistor.

[0112] In this embodiment, the gate structure 200 is a metal gate structure, and specifically, the material of the gate structure 200 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. As an example, in this embodiment, the material of the gate structure 200 is W.

[0113] In this embodiment, in the step of providing the substrate 100, a top dielectric layer 320 is also formed on the top of the gate structure 200, and a bottom dielectric layer 310 is also formed between the gate structure 200 and the substrate 100.

[0114] The top dielectric layer 320 is used to isolate the gate structure 200 and other device structures above it.

[0115] In this embodiment, the material of the top dielectric layer 320 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0116] The bottom dielectric layer 310 is used to isolate the gate structure 200 and other device structures below it.

[0117] In this embodiment, the material of the bottom dielectric layer 310 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0118] In the step of providing the substrate 100, the source-drain doped layer 110 is also formed in the substrate 100, and the top surface of the substrate 100 exposes the source-drain doped layer 110.

[0119] The source-drain doped layer 110 is used as a source region or a drain region of a transistor. Specifically, the doping type of the source-drain doped layer 110 is the same as the channel conductivity type of the corresponding transistor.

[0120] In the embodiment, the top surface of the substrate 100 exposes the source-drain doped layer 110, so that the channel pillar formed subsequently on the substrate 100 can contact the source-drain doped layer 110.

[0121] With reference to Figure 5 , an opening 210 is formed through the gate structure 200.

[0122] The opening 210 is used to provide a spatial position for forming a sidewall structure and a channel pillar subsequently.

[0123] Correspondingly, in the step of forming the opening 210 through the gate structure 200, the opening 210 also penetrates the top dielectric layer 320, and the opening 210 extends in the bottom dielectric layer 310 by a partial thickness.

[0124] The opening 210 extends in the bottom dielectric layer 310 by a partial thickness, and the remaining thickness of the bottom dielectric layer 310 covers the top surface of the source-drain doped layer 110, so as to protect the source-drain doped layer 110 in the step of forming a sidewall structure subsequently.

[0125] In the step of forming the opening 210 through the gate structure 200, the opening 210 is formed above the source-drain doped layer 110.

[0126] The opening 210 is formed above the source-drain doped layer 110, so that the channel pillar formed subsequently can contact the source-drain doped layer 110.

[0127] With reference to Figure 6 and Figure 7 , a sidewall structure 460 is formed covering the sidewall of the opening 210.

[0128] The sidewall structure 460 is used to isolate the gate structure 200 from the channel pillar formed subsequently.

[0129] With reference to Figure 6 , the step of forming the sidewall structure 460 covering the sidewall of the opening 210 includes forming a sidewall structure material layer 400 covering the sidewall and bottom of the opening 210, and the top of the gate structure 200.

[0130] The sidewall structure material layer 400 is used to form the sidewall structure 460.

[0131] Specifically, in the embodiment, the step of forming the side wall structure material layer 400 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200 includes: forming a first side wall material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200.

[0132] The first side wall material layer 410 is used to form a first side wall.

[0133] In the embodiment, the material of the first side wall material layer 410 includes silicon nitride.

[0134] In the embodiment, in the step of forming the first side wall material layer 410 covering the sidewalls and bottom of the opening 210 and the top of the gate structure 200, the thickness of the first side wall material layer 410 is 1 nm to 8 nm, which is beneficial to make the subsequently formed first side wall have sufficient thickness to guarantee the isolation performance of the side wall structure 460, and the first side wall does not occupy too much space to meet the integration of the semiconductor structure.

[0135] In the embodiment, a second side wall material layer 420 covering the first side wall material layer 410 is formed.

[0136] Specifically, the second side wall material layer 420 conformally covers the first side wall material layer 410, and the second side wall material layer 420 is used to form a second side wall.

[0137] In the embodiment, the material of the second side wall material layer 420 includes silicon oxide.

[0138] In the embodiment, in the step of forming the second side wall material layer 420 covering the first side wall material layer 410, the thickness of the second side wall material layer 420 is 1 nm to 8 nm, which is beneficial to make the subsequently formed second side wall have sufficient thickness to guarantee the isolation performance of the side wall structure 460, and the second side wall does not occupy too much space to meet the integration of the semiconductor structure.

[0139] Reference Figure 7 The side wall structure material layer 400 covering the bottom of the opening 210 and the top of the gate structure 200 is removed, and the side wall structure material layer 400 covering the sidewalls of the opening is retained as the side wall structure 460.

[0140] In the embodiment, the dry etching process is used to remove the side wall structure material layer 400 covering the bottom of the opening 210 and the top of the gate structure 200.

[0141] The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, it is beneficial to reduce the damage to the substrate 100 at the bottom of the opening 210, and the dry etching is more directional in etching, which is beneficial to improve the appearance quality and size precision of the side wall structure 460.

[0142] Specifically, in the embodiment, in the step of removing the first sidewall material layer 410 and the second sidewall material layer 420 at the bottom of the opening 210 and the top of the gate structure 200, the first sidewall material layer 410 covering the sidewall of the opening 210 is reserved as the first sidewall 440, and the second sidewall material layer 420 covering the sidewall of the opening 210 is reserved as the second sidewall 450.

[0143] The first sidewall 440 and the second sidewall 450 are used to form the sidewall structure 460, which is conducive to guaranteeing the isolation of the sidewall structure 460 and adjusting the dielectric constant of the sidewall structure 460 through the first sidewall 440 and the second sidewall 450.

[0144] Specifically, in the embodiment, the material of the first sidewall 440 includes silicon nitride, and the material of the second sidewall 450 includes silicon oxide.

[0145] In the embodiment, before the gap compensation treatment is performed at the corner of the bottom of the opening 210, the method further includes: forming a protection layer 470 covering the sidewall of the sidewall structure 460.

[0146] The protection layer 470 is used to protect the sidewall structure 460 in the process of the sidewall structure 460, so as to reduce the damage to the sidewall structure 460.

[0147] In the embodiment, in the step of forming the protection layer 470 covering the sidewall of the sidewall structure 460, the material of the protection layer 470 includes amorphous silicon, polysilicon, a combination of polysilicon and silicon oxide and tungsten, or a combination of polysilicon and silicon oxide and titanium nitride.

[0148] The amorphous silicon, the polysilicon, the combination of polysilicon and silicon oxide and tungsten, or the combination of polysilicon and silicon oxide and titanium nitride is used to form the protection layer 470, which can play a good protection role, and after the channel column is formed, the protection layer 470 is reserved on both sides of the channel column without introducing other elements that are easy to contaminate, which is conducive to guaranteeing the basic working performance of the transistor.

[0149] Specifically, referring to Figure 6 , before the sidewall structure material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 is removed, the method further includes: forming a protection material layer 430 covering the sidewall structure material layer 400.

[0150] Specifically, the protection material layer 430 conformally covers the sidewall structure material layer 400, and the protection material layer 430 is used to form the protection layer 470.

[0151] Referring to Figure 7In the step of removing the sidewall structure material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the method further includes: removing the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200, and retaining the protective material layer 430 covering the sidewall of the sidewall structure 460 as a protective layer 470.

[0152] Specifically, in the embodiment, the dry etching process is used to remove the protective material layer 430 at the bottom of the opening 210 and the top of the gate structure 200.

[0153] In the embodiment, in the step of removing the sidewall structure material layer 400 at the bottom of the opening 210 and the top of the gate structure 200, the method further includes: removing the remaining thickness of the bottom dielectric layer 310 to expose the top surface of the substrate 100.

[0154] Specifically, in the embodiment, the remaining thickness of the bottom dielectric layer 310 is removed to expose the top surface of the source-drain doped layer 110 of the substrate 100, which prepares for the subsequent formation of the channel column in contact with the source-drain doped layer 110.

[0155] Reference Figure 8 After the sidewall structure material layer 400 at the bottom of the opening 210 and the top of the gate structure 200 is removed, before the subsequent gap compensation treatment at the corner of the bottom of the opening 210, the method further includes: cleaning the sidewall structure 460.

[0156] The process of forming the sidewall structure 460 is prone to residue residue, especially prone to residue residue at the bottom of the opening 210, especially for the embodiment, the dry etching process is used to form the sidewall structure 460 and the protective layer 470, which is prone to dry etching residue in the opening 210. Therefore, the sidewall structure 460 is cleaned to remove the residue in the opening 210 and reduce the pollution to the subsequent process, and a better process platform is provided for the subsequent process.

[0157] It should be noted that when the sidewall structure 460 is cleaned, the top and bottom of the sidewall structure 460 exposed to the protective layer 470 will be damaged. Specifically, the material of the first sidewall 440 is silicon nitride, and the material of the second sidewall 450 is silicon oxide, which is more prone to damage. Therefore, the cleaning process will remove part of the second sidewall 450 at the top of the sidewall structure 460 and part of the second sidewall 450 at the bottom of the sidewall structure 460. At the same time, the opening 210 also penetrates the bottom dielectric layer 310, that is, the opening 210 also exposes the bottom dielectric layer 310. Therefore, the cleaning process will also remove part of the bottom dielectric layer 310 at the corner of the bottom of the opening 210.

[0158] In the embodiment, the cleaning solution used in the cleaning process is a diluted hydrofluoric acid (DHF) solution.

[0159] The etching rate of the diluted hydrofluoric acid solution is slow and stable, which is conducive to better cleaning and less damage to the film layer. It should be noted that the fluorine-containing cleaning solution is easy to cause etching damage to silicon oxide.

[0160] Specifically, in the embodiment, the volume ratio of water to hydrofluoric acid in the diluted hydrofluoric acid solution is 100:1 to 2000:1.

[0161] In other embodiments, the cleaning solution used in the cleaning process can also be a diluted sulfuric acid hydrogen peroxide (DSP) mixed solution or an SST-A47 organic solution.

[0162] In combination with reference Figure 9 and Figure 10 At the bottom corner of the opening 210, a void compensation layer 510 is formed to fill the void at the bottom of the side wall structure 460 (as shown by the dashed line circle in FIG. 10B). Figure 10

[0163] The compensation layer 510 fills the bottom of the side wall structure 460 at the bottom corner of the opening 210, and a channel pillar will be subsequently formed in the opening 210. That is, the compensation layer 510 compensates for the void between the subsequently formed channel pillar and the gate structure 200, and is used to compensate for the isolation effect between the bottom of the side wall structure 460 and the gate structure 200 and the channel pillar.

[0164] In the embodiment, the void compensation process is performed at the bottom corner of the opening 210, and the compensation layer 510 can compensate for the isolation performance of the bottom of the side wall structure 460 to the gate structure 200 and the channel pillar 610, which is conducive to ensuring the insulation effect between the gate structure 200 and the channel pillar 610. Thus, it is conducive to reducing the probability of leakage current between the gate structure 200 and the channel pillar 610, ensuring that the threshold voltage of the semiconductor structure meets the process requirements, reducing the probability of the reduction of the barrier potential of the drain of the semiconductor structure, and further ensuring the working performance of the semiconductor structure.

[0165] In the embodiment, when the side wall structure 460 is cleaned, the bottom of the side wall structure 460 exposed by the protection layer 470 causes damage to the side wall structure 460. Therefore, in the step of performing the void compensation process at the bottom corner of the opening 210, the compensation layer 510 also fills the void at the bottom of the protection layer 470 at the bottom corner of the opening 210.

[0166] ​In the embodiment, the cleaning process also damages the side wall structure 460 at the top of the side wall structure 460 exposed by the protection layer 470. Therefore, in the step of performing the gap compensation process at the bottom corner of the opening 210, the compensation layer also fills the gap between the top of the side wall structure 460 and the protection layer 470.

[0167] Specifically, in the embodiment, the material of the second side wall 450 is silicon oxide and the material of the first side wall 440 is silicon nitride. Silicon oxide is easy to be damaged. Therefore, in the step of performing the gap compensation process at the bottom corner of the opening 210, the compensation layer 510 fills the gap between the bottom surface of the second side wall 450, the bottom surface of the protection layer 470, and the sidewall of the first side wall 440, and the compensation layer 510 also fills the gap between the top surface of the second side wall 450, the sidewall of the protection layer 470, and the sidewall of the first side wall 440.

[0168] In the embodiment, the cleaning process also removes part of the bottom dielectric layer 310 at the bottom corner of the opening 210. Therefore, in the step of performing the gap compensation process at the bottom corner of the opening 210, the compensation layer 510 also fills the gap between the bottom dielectric layer 310 at the bottom corner of the opening 210 and the substrate 100.

[0169] In the embodiment, in the step of forming the compensation layer 510 filling the gap at the bottom of the side wall structure 460, the material of the compensation layer 510 includes silicon nitride.

[0170] The use of silicon nitride to form the compensation layer 510 can achieve better isolation effect. In addition, silicon nitride has high hardness and is less damaged in semiconductor manufacturing process, which can ensure the isolation effect of the compensation layer 510.

[0171] Specifically, referring to Figure 9 In the step of performing the gap compensation process at the bottom corner of the opening 210 to form the compensation layer 510 filling the gap at the bottom of the side wall structure 460, the compensation material layer 500 is formed to cover the bottom of the opening 210, the sidewall of the side wall structure 460, the top of the gate structure 200, and the gap at the bottom of the side wall structure 460.

[0172] The compensation material layer 500 is used to form the compensation layer 510.

[0173] Specifically, in the embodiment, the compensation material layer 500 also fills the gap at the top of the side wall structure 460 and the gap of the bottom dielectric layer 310 at the bottom corner of the opening 210.

[0174] In the embodiment, in the step of forming the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 of the opening 210, the top of the gate structure 200, and the gap at the bottom of the sidewall structure 460, the thickness of the compensation material layer 500 is 1 nm to 10 nm.

[0175] The thickness of the compensation material layer 500 is 1 nm to 10 nm, so that the compensation material layer 500 can fill the gap more adequately, and unnecessary material waste is avoided.

[0176] In the embodiment, the atomic layer deposition (ALD) process is used to form the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 of the opening 210, the top of the gate structure 200, and the gap at the bottom of the sidewall structure 460.

[0177] The compensation material layer 500 formed by the atomic layer deposition process has good thickness uniformity and good step coverage capability, so that the compensation material layer 500 can well conformally cover the bottom of the opening 210, the sidewall of the sidewall structure 460 of the opening 210, the top of the gate structure 200, and the gap at the bottom of the sidewall structure 460.

[0178] In other embodiments, the low pressure chemical vapor deposition (LPCVD) process can also be used to form the compensation material layer covering the bottom of the opening, the sidewall of the sidewall structure, the top of the gate structure, and the gap at the bottom of the sidewall structure.

[0179] Reference Figure 10 The compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 of the opening 210, and the top of the gate structure 200 is removed, and the compensation material layer filling the gap at the bottom of the sidewall structure 460 is retained as the compensation layer 510.

[0180] Specifically, in the embodiment, the compensation material layer 500 filling the gap at the top of the sidewall structure 460 and the gap at the bottom of the corner of the bottom dielectric layer 310 at the bottom of the opening 210 is also retained as the compensation layer 510.

[0181] In the embodiment, the wet etching process is used to remove the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 of the opening 210, and the top of the gate structure 200.

[0182] The wet etching process has relatively low cost, simple operation steps, and can achieve a large etching selectivity, which is beneficial to reducing damage to other film layers in the process of removing the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 on the sidewall of the opening 210, and the top of the gate structure 200.

[0183] In this embodiment, the etching solution of the wet etching process includes a phosphoric acid solution.

[0184] The viscosity of phosphoric acid is relatively high, generally 37.10 mPa.s. That is, the viscosity of the phosphoric acid solution is relatively high, and the phosphoric acid solution is not easy to enter the gap, that is, the phosphoric acid solution is not easy to react with the compensation material layer 500 in the gap, so that the wet etching process is easy to retain the compensation material layer 500 in the gap when removing the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 on the sidewall of the opening 210, and the top of the gate structure 200, thereby facilitating the formation of the compensation layer 510.

[0185] In this embodiment, the mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%.

[0186] The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%, which is beneficial to completely removing the compensation material layer 500 covering the bottom of the opening 210, the sidewall of the sidewall structure 460 on the sidewall of the opening 210, and the top of the gate structure 200, and is easy to maintain a relatively high viscosity, so that the compensation material layer 500 in the gap is easy to be retained.

[0187] Specifically, in this embodiment, the mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 60wt%.

[0188] The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 60wt%, which is beneficial to reducing the etching rate, so that the wet etching is more easily controlled.

[0189] In this embodiment, the process temperature of the wet etching process is 100°C to 160°C.

[0190] The process temperature of the wet etching process is 100°C to 160°C, which can maintain high efficiency etching while maintaining good etching quality.

[0191] Specifically, in this embodiment, the process temperature of the wet etching process is 100°C to 130°C.

[0192] The process temperature of the wet etching process is 100°C to 130°C, which is beneficial to reducing the etching rate, so that the wet etching is more easily controlled.

[0193] In combination with reference Figure 11 and Figure 12A channel pillar 610 is formed in the opening 210, located on the substrate 100 and penetrating the gate structure 200.

[0194] The channel post 610 is used as the channel of the transistor.

[0195] Specifically, in this embodiment, the channel pillar 610 extends longitudinally through the gate structure 200 to form a vertical channel transistor (VCT). The vertical channel design improves the integration density of the transistor, allowing more transistors to be integrated on the same wafer area, thereby improving the performance and efficiency of the chip.

[0196] In this embodiment, the channel pillar 610 is made of silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, in this embodiment, the channel pillar 610 is made of silicon. In other embodiments, the material of the channel pillar is determined based on the type and performance of the transistor.

[0197] Accordingly, in this embodiment, during the step of forming a channel pillar 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210, the channel pillar 610 is in contact with the protective layer 470.

[0198] In this embodiment, the opening 210 exposes the top surface of the source / drain doped layer 110. Correspondingly, in the step of forming a channel pillar 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210, the channel pillar 610 is formed on the source / drain doped layer 110 and is in contact with the source / drain doped layer 110.

[0199] In this embodiment, in the step of forming a channel pillar 610 located on the substrate 100 and penetrating the gate structure 200 in the opening 210, the channel pillar 610 fills the opening 210.

[0200] Specifically, refer to Figure 11 The step of forming a channel pillar 610 in the opening 210 that is located on the substrate 100 and extends through the gate structure 200 includes forming a channel material layer 600 that fills the opening 210 and covers the top of the top dielectric layer 320.

[0201] The channel material layer 600 is used to form the channel column 610.

[0202] refer to Figure 12 Flatten the channel material layer 600, remove the channel material layer 600 above the top medium layer 320, and retain the channel material layer 600 filling the opening 210 as the channel column 610.

[0203] Figure 13 swine Figure 15is a structure diagram corresponding to each step in another embodiment of the forming method of the semiconductor structure.

[0204] The same as the foregoing embodiments, which will not be repeated here. The difference between this embodiment and the foregoing embodiments is that the structure of the channel pillar is different.

[0205] In combination with reference Figures 13 to 15 In the step of forming the channel pillar 611 on the substrate 101 and penetrating the gate structure 201 in the opening 211, a recess 620 in the channel pillar 611 at a partial height is formed on one side of the top of the channel pillar 611.

[0206] The channel pillar 611 does not fill the area between the openings 211, which is conducive to reducing the probability of the concave top surface of the formed channel pillar 611.

[0207] In this embodiment, the insulating layer 640 filling the recess 620 is formed.

[0208] Filling the insulating layer 640 in the recess 620 is conducive to obtaining a better surface flatness of the top surface of the channel pillar 611.

[0209] In this embodiment, in the step of forming the insulating layer 640 filling the recess 620, the material of the insulating layer 640 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0210] Specifically, referring to Figure 13 The channel material layer 601 covering the sidewall and bottom of the opening 211, and the top of the top dielectric layer 321 is formed, and the channel material layer 601 in the opening 211 surrounds the recess 620.

[0211] The channel material layer 601 is used to form the channel pillar 611.

[0212] Referring to Figure 14 The insulating material layer 630 filling the recess 620 and covering the channel material layer 601 is formed.

[0213] The insulating material layer 630 is used to form the insulating layer 640.

[0214] Referring to Figure 15 The insulating material layer 630 and the channel material layer 601 are planarized, and the insulating material layer 630 and the channel material layer 601 higher than the top dielectric layer 321 are removed, the channel material layer 601 in the opening 211 is retained as the channel pillar 611, and the insulating material layer 630 in the opening 211 is retained as the insulating layer 640.

[0215] Figure 16is a structure schematic diagram corresponding to each step in another embodiment of the forming method of the semiconductor structure.

[0216] The embodiment is the same as the foregoing embodiments, and details are not repeated. The embodiment is different from the foregoing embodiments in that the protective layer is removed.

[0217] Reference Figure 16 After the channel column 612 is formed in the opening 212 on the substrate 102 and penetrates the gate structure 202, the method further includes removing the protective layer to form an air gap 650 between the sidewall structure 462 and the sidewall of the channel column 612.

[0218] The air gap 650 is used to isolate the gate structure 202 and the channel column 612 together with the sidewall structure 462.

[0219] In the embodiment, the air gap 650 isolates the gate structure 202 and the channel column 612 together with the sidewall structure 462. The dielectric constant of air is low, so that the air gap 650 is used to isolate the gate structure 202 and the channel column 612 together with the sidewall structure 462, which is beneficial to reduce the overall dielectric constant of the isolation between the gate structure 202 and the channel column 612, thereby reducing the parasitic capacitance and improving the working performance of the semiconductor structure.

[0220] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a gate structure on the substrate; a channel pillar on the substrate and extending through the gate structure in a longitudinal direction; a sidewall structure extending between the sidewall of the channel pillar and the gate structure in the longitudinal direction; a compensation layer filled in a gap between the channel pillar and the gate structure at a bottom position of the sidewall structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a spacer layer between the sidewall structure and the sidewall of the channel pillar. The compensation layer is further filled in a gap between the channel pillar and the gate structure at a bottom position of the spacer layer.

3. The semiconductor structure of claim 2, wherein, The spacer layer is a protective layer covering the sidewall of the sidewall structure. Alternatively, The spacer layer is an air gap.

4. The semiconductor structure of claim 3, wherein, The spacer layer is a protective layer, and a material of the protective layer comprises amorphous silicon, polysilicon, a combination of polysilicon and silicon oxide, and a combination of polysilicon and titanium nitride.

5. The semiconductor structure of claim 2, wherein, The compensation layer is further filled in a gap between the top of the sidewall structure and the spacer layer.

6. The semiconductor structure of claim 5, wherein, The sidewall structure comprises a first sidewall covering the sidewall of the gate structure, and a second sidewall covering the sidewall of the first sidewall. At the bottom of the sidewall structure, the gap filled by the compensation layer is surrounded by the bottom surface of the second sidewall, the bottom surface of the spacer layer, the first sidewall, and the sidewall of the channel pillar. At the top of the sidewall structure, the gap filled by the compensation layer is surrounded by the top surface of the second sidewall, the sidewall of the spacer layer, and the sidewall of the first sidewall.

7. The semiconductor structure of claim 6, wherein, A material of the first sidewall comprises silicon nitride; and a material of the second sidewall comprises silicon oxide.

8. The semiconductor structure of claim 1, wherein, A material of the compensation layer comprises silicon nitride.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises a top dielectric layer covering the top surface of the gate structure; a bottom dielectric layer between the gate structure and the substrate; The channel pillar further extends through the top dielectric layer and the bottom dielectric layer; The sidewall structure further extends between the sidewall of the channel pillar and the top dielectric layer; The compensation layer is further filled in a gap between the channel pillar and the bottom dielectric layer.

10. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises source-drain doped layers in the substrate, and a top surface of the substrate exposes the source-drain doped layers; The channel pillar is on and in contact with the source-drain doped layers.

11. The semiconductor structure of claim 1, wherein, A groove in the channel pillar at a partial height is formed on one side of the top of the channel pillar, and the semiconductor structure further comprises an insulating layer filled in the groove.

12. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises: providing a substrate, and a gate structure is formed on the substrate; forming an opening extending through the gate structure; forming a sidewall structure covering the sidewall of the opening; performing gap compensation processing at a bottom corner of the opening to form a compensation layer filling a gap at the bottom of the sidewall structure; forming a channel pillar on the substrate and extending through the gate structure in the opening.

13. The method of forming a semiconductor structure of claim 12, wherein, Before the gap compensation processing at the bottom corner of the opening, the semiconductor structure further comprises forming a protective layer covering the sidewall of the sidewall structure; In the step of performing the gap compensation processing at the bottom corner of the opening, the compensation layer is further filled in a gap at the bottom of the protective layer at the bottom corner of the opening; In the step of performing the gap compensation processing at the bottom corner of the opening, the compensation layer is further filled in a gap at the bottom of the protective layer at the bottom corner of the opening; In the step of forming a channel pillar on the substrate and penetrating the gate structure in the opening, the channel pillar is in contact with the protection layer.

14. The method of forming a semiconductor structure of claim 13, wherein, After forming the channel pillar on the substrate and penetrating the gate structure in the opening, the method further comprises: removing the protection layer to form an air gap between the sidewall structure and the sidewall of the channel pillar.

15. The method of forming a semiconductor structure of claim 13, wherein, In the step of performing void compensation treatment at the bottom corner of the opening, the compensation layer also fills the void formed by the sidewall of the protection layer and the sidewall of the first sidewall.

16. The method of forming a semiconductor structure of claim 15, wherein, The step of forming the sidewall structure covering the sidewall of the opening comprises: forming a sidewall structure material layer covering the sidewall and bottom of the opening, and the top of the gate structure; The step of removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure comprises: removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure, and retaining the sidewall structure material layer covering the sidewall of the opening as the sidewall structure.

17. The method of forming a semiconductor structure of claim 16, wherein, In the step of providing the substrate, the top of the gate structure is further formed with a top dielectric layer, and the gate structure and the substrate are further formed with a bottom dielectric layer; In the step of forming the opening penetrating the gate structure, the opening further penetrates the top dielectric layer, and the opening further extends in a partial thickness of the bottom dielectric layer; In the step of removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure, the method further comprises: removing the remaining partial thickness of the bottom dielectric layer to expose the top surface of the substrate; In the step of performing void compensation treatment at the bottom corner of the opening, the compensation layer also fills the void formed by the bottom dielectric layer and the substrate at the bottom corner of the opening.

18. The method of forming a semiconductor structure of claim 16, wherein, The step of forming the sidewall structure material layer covering the sidewall and bottom of the opening, and the top of the gate structure comprises: forming a first sidewall material layer covering the sidewall and bottom of the opening, and the top of the gate structure; The step of forming the sidewall structure material layer covering the sidewall and bottom of the opening, and the top of the gate structure comprises: forming a first sidewall material layer covering the sidewall and bottom of the opening, and the top of the gate structure; In the step of removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure, the first sidewall material layer and the second sidewall material layer at the bottom of the opening and the top of the gate structure are removed, the first sidewall material layer covering the sidewall of the opening is retained as a first sidewall, and the second sidewall material layer covering the sidewall of the opening is retained as a second sidewall. In the step of performing void compensation treatment at the bottom corner of the opening, the compensation layer fills the void formed by the bottom surface of the second sidewall, the bottom surface of the protection layer, and the first sidewall, and the compensation layer also fills the void formed by the top surface of the second sidewall, the sidewall of the protection layer, and the sidewall of the first sidewall.

19. The method of forming a semiconductor structure of claim 16, wherein, Before the step of removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure, the method further comprises: forming a protection material layer covering the sidewall structure material layer; In the step of removing the sidewall structure material layer at the bottom of the opening and the top of the gate structure, the protection material layer at the bottom of the opening and the top of the gate structure is removed, and the protection material layer covering the sidewall of the sidewall structure is retained as the protection layer.

20. The method of forming a semiconductor structure of claim 19, wherein, The sidewall structure material layer at the bottom of the opening and the top of the gate structure is removed by a dry etching process; After removing the sidewall structure material layer of the opening bottom and the gate structure top, before the gap compensation treatment at the opening bottom corner, the method further comprises: performing a cleaning treatment on the sidewall structure.

21. The method of forming a semiconductor structure of claim 12, wherein, The step of performing a gap compensation treatment at the opening bottom corner to form a compensation layer filling the gap of the bottom of the sidewall structure comprises: forming a compensation material layer covering the opening bottom, the sidewall structure sidewall of the opening sidewall, the gate structure top, and filling the gap of the bottom of the sidewall structure. The compensation material layer covering the opening bottom, the sidewall structure sidewall of the opening sidewall, and the gate structure top is removed, and the compensation material layer filling the gap of the bottom of the sidewall structure is reserved as the compensation layer.

22. The method of forming a semiconductor structure of claim 21, wherein, The compensation material layer covering the opening bottom, the sidewall structure sidewall of the opening sidewall, the gate structure top, and filling the gap of the bottom of the sidewall structure is formed by an atomic layer deposition process or a low-pressure chemical vapor deposition process.

23. The method of forming a semiconductor structure of claim 21, wherein, The compensation material layer covering the opening bottom, the sidewall structure sidewall of the opening sidewall, and the gate structure top is removed by a wet etching process.

24. The method of forming a semiconductor structure of claim 23, wherein, The etching solution of the wet etching process comprises a phosphoric acid solution; The mass percentage of phosphoric acid in the phosphoric acid solution is 40wt% to 86wt%; The process temperature of the wet etching process is 100°C to 160°C.

25. The method of forming a semiconductor structure of claim 12, wherein, In the step of providing the substrate, an active source / drain doped layer is also formed in the substrate, and the top surface of the substrate exposes the source / drain doped layer; In the step of forming an opening penetrating the gate structure, the opening is formed above the source / drain doped layer; In the step of forming a channel column on the substrate and penetrating the gate structure in the opening, the channel column is formed on and in contact with the source / drain doped layer.

26. The method of forming a semiconductor structure of claim 12, wherein, In the step of forming a channel column on the substrate and penetrating the gate structure in the opening, the channel column fills the opening. Alternatively, in the step of forming a channel column on the substrate and penetrating the gate structure in the opening, a groove in the channel column is formed on one side of the top of the channel column. An insulating layer filling the groove is formed.

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