Method for improving electric leakage of device

Abstract

The invention provides a method for improving electric leakage of a device, which comprises the following steps of: providing a semiconductor substrate which is used for integrating an NMOS (N-channel Metal Oxide Semiconductor) device and a PMOS (P-channel Metal Oxide Semiconductor) device, firstly forming the NMOS device and then forming the PMOS device, enabling the NMOS device to at least comprise an ultrahigh-voltage NMOS device and an extra-high-voltage NMOS device, and when the NMOS device further comprises other NMOS devices, forming the PMOS device after forming the NMOS device; the PMOS devices at least comprise the ultrahigh-voltage PMOS device and the extra-high-voltage PMOS device, and when the PMOS devices further comprise the other PMOS devices, the other PMOS devices are firstly formed, and then the ultrahigh-voltage PMOS device and the extra-high-voltage PMOS device are formed; when the source and drain electrodes of the ultrahigh-voltage PMOS device and the extra-high-voltage PMOS device are formed through the ion implantation technology, fluorine ions are injected firstly, and then BF2 ions are injected. The problem that an existing extra-high voltage PMOS device and an existing extra-high voltage PMOS device are prone to electric leakage is solved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for improving device leakage. Background Art

[0002] The 28nm high-k metal gate process (28nmHKC+) platform customers have an increasingly urgent demand for low-power, high-speed products. However, electrical tests have found that ultra-high voltage devices and UHV devices have poor leakage performance. The reason is that the source, drain and substrate junctions become larger. The existence of this problem will not only make it impossible to meet the needs of customer terminal applications, but also make it impossible to meet the needs of platform construction models, resulting in the company encountering barriers in developing diversified target customers. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving device leakage, so as to solve the problem of leakage of existing UHV PMOS devices and ultra-high voltage PMOS devices.

[0004] To achieve the above-mentioned object and other related objects, the present invention provides a method for improving device leakage, the method comprising:

[0005] A semiconductor substrate is provided, wherein the semiconductor substrate is used to integrate an NMOS device and a PMOS device, and the NMOS device is formed first and then the PMOS device is formed, the NMOS device includes at least an ultra-high voltage NMOS device and an ultra-high voltage NMOS device, and when the NMOS device also includes other NMOS devices, the other NMOS devices are formed first and then the ultra-high voltage NMOS device and the ultra-high voltage NMOS device are formed, the PMOS device includes at least an ultra-high voltage PMOS device and the ultra-high voltage PMOS device, and when the PMOS device also includes other PMOS devices, the other PMOS devices are formed first and then the ultra-high voltage PMOS device and the ultra-high voltage PMOS device are formed;

[0006] When forming the source and drain of the ultra-high voltage PMOS device and the UHV PMOS device by an ion implantation process, fluorine ions are first implanted and then BF2 ions are implanted, and a larger implantation energy and implantation dose are used for the BF2 implantation.

[0007] Optionally, the implantation energy of BF2 includes 3.9KeV to 4.1KeV.

[0008] Optionally, the BF2 implantation dose includes 3E13 to 3.4E13.

[0009] Optionally, when forming the NMOS device and the PMOS device, a sacrificial layer is formed on the surface of the semiconductor substrate.

[0010] Optionally, when the ultra-high voltage PMOS device and the UHV PMOS device are finally formed, the thickness of the sacrificial layer is reduced to 70% of the original thickness.

[0011] Optionally, the sacrificial layer comprises an oxide layer.

[0012] Optionally, the material of the oxide layer includes silicon oxide.

[0013] Optionally, the other NMOS devices also include core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices and ultra low voltage NMOS devices, and the other PMOS devices include core PMOS devices, SRAM PMOS devices, high voltage PMOS devices, low voltage PMOS devices and ultra low voltage PMOS devices.

[0014] Optionally, when forming NMOS devices, they are formed in the order of core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices, ultra low voltage NMOS devices, ultra high voltage NMOS devices / UHV NMOS devices.

[0015] Optionally, when forming the PMOS device, core PMOS device, SRAM PMOS device, high voltage PMOS device, low voltage PMOS device, ultra low voltage PMOS device, ultra high voltage PMOS device / ultra high voltage PMOS device are formed in this order.

[0016] As described above, the method for improving device leakage of the present invention, when forming a PMOS device, can reduce the thickness of the sacrificial layer when performing ion implantation to form the source and drain by finally forming a high-voltage PMOS device and an ultra-high-voltage PMOS device, thereby increasing the effective ion implantation dose, reducing ion implantation scattering and reducing the channel effect, thereby reducing the channel resistance; and, the ion implantation depth can be controlled by adjusting the BF2 implantation energy, thereby reducing junction leakage and improving leakage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a flow chart of a method for improving device leakage according to the present invention. DETAILED DESCRIPTION

[0018] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0019] See also Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0020] like Figure 1 As shown, this embodiment provides a method for improving device leakage, the method comprising:

[0021] A semiconductor substrate is provided, wherein the semiconductor substrate is used to integrate an NMOS device and a PMOS device, and the NMOS device is formed first and then the PMOS device is formed, the NMOS device includes at least an ultra-high voltage NMOS device and an ultra-high voltage NMOS device, and when the NMOS device also includes other NMOS devices, the other NMOS devices are formed first and then the ultra-high voltage NMOS device and the ultra-high voltage NMOS device are formed, the PMOS device includes at least an ultra-high voltage PMOS device and the ultra-high voltage PMOS device, and when the PMOS device also includes other PMOS devices, the other PMOS devices are formed first and then the ultra-high voltage PMOS device and the ultra-high voltage PMOS device are formed;

[0022] When forming the source and drain of the ultra-high voltage PMOS device and the UHV PMOS device by an ion implantation process, fluorine ions are first implanted and then BF2 ions are implanted, and a larger implantation energy and implantation dose are used for the BF2 implantation.

[0023] Specifically, the implantation energy of BF2 includes 3.9KeV to 4.1KeV.

[0024] Specifically, the BF2 injection dose includes 3E13 to 3.4E13.

[0025] Specifically, when forming the NMOS device and the PMOS device, a sacrificial layer is formed on the surface of the semiconductor substrate.

[0026] Specifically, when the ultra-high voltage PMOS device and the UHV PMOS device are finally formed, the thickness of the sacrificial layer is reduced to 70% of the original thickness.

[0027] More specifically, the sacrificial layer includes an oxide layer.

[0028] As an example, the material of the oxide layer includes silicon oxide.

[0029] Specifically, the other NMOS devices also include core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices and ultra low voltage NMOS devices, and the other PMOS devices include core PMOS devices, SRAM PMOS devices, high voltage PMOS devices, low voltage PMOS devices and ultra low voltage PMOS devices.

[0030] More specifically, when forming NMOS devices, they are formed in the order of core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices, ultra low voltage NMOS devices, ultra high voltage NMOS devices / UHV NMOS devices.

[0031] More specifically, when forming the PMOS device, a core PMOS device, an SRAM PMOS device, a high voltage PMOS device, a low voltage PMOS device, an ultra low voltage PMOS device, an ultra high voltage PMOS device / an ultra high voltage PMOS device are formed in this order.

[0032] In this embodiment, the NMOS device and the PMOS device are formed in the above order so that the thickness of the sacrificial layer can be reduced.

[0033] In summary, the method for improving device leakage of the present invention can reduce the thickness of the sacrificial layer when performing ion implantation to form the source and drain by finally forming a high-voltage PMOS device and an ultra-high-voltage PMOS device when forming a PMOS device, thereby increasing the effective dose of ion implantation, reducing ion implantation scattering and reducing the channel effect, thereby reducing the channel resistance; and, by adjusting the BF2 implantation energy to control the ion implantation depth, reduce junction leakage, and thus improve leakage performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0034] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving device leakage, characterized in that: The method comprises: A semiconductor substrate is provided, wherein the semiconductor substrate is used to integrate an NMOS device and a PMOS device, and the NMOS device is formed first and then the PMOS device is formed, the NMOS device includes at least an ultra-high voltage NMOS device and an ultra-high voltage NMOS device, and when the NMOS device also includes other NMOS devices, the other NMOS devices are formed first and then the ultra-high voltage NMOS device and the ultra-high voltage NMOS device are formed, the PMOS device includes at least an ultra-high voltage PMOS device and the ultra-high voltage PMOS device, and when the PMOS device also includes other PMOS devices, the other PMOS devices are formed first and then the ultra-high voltage PMOS device and the ultra-high voltage PMOS device are formed; When forming the source and drain of the ultra-high voltage PMOS device and the UHV PMOS device by an ion implantation process, fluorine ions are implanted first and then BF2 ions are implanted, and a larger implantation energy and implantation dose are used for the BF2 implantation.

2. The method for improving device leakage according to claim 1, characterized in that: The implantation energy of BF2 includes 3.9KeV to 4.1KeV.

3. The method for improving device leakage according to claim 1, characterized in that: The BF2 implantation dose includes 3E13 to 3.4E13.

4. The method for improving device leakage according to claim 1, characterized in that: When forming the NMOS device and the PMOS device, a sacrificial layer is formed on the surface of the semiconductor substrate.

5. The method for improving device leakage according to claim 4, characterized in that: When the ultra-high voltage PMOS device and the UHV PMOS device are finally formed, the thickness of the sacrificial layer is reduced to 70% of the original thickness.

6. The method for improving device leakage according to claim 4 or 5, characterized in that: The sacrificial layer includes an oxide layer.

7. The method for improving device leakage according to claim 6, characterized in that: The material of the oxide layer includes silicon oxide.

8. The method for improving device leakage according to claim 1, characterized in that: The other NMOS devices also include core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices and ultra low voltage NMOS devices, and the other PMOS devices include core PMOS devices, SRAM PMOS devices, high voltage PMOS devices, low voltage PMOS devices and ultra low voltage PMOS devices.

9. The method for improving device leakage according to claim 8, characterized in that: When forming NMOS devices, they are formed in the order of core NMOS devices, low voltage NMOS devices, SRAM NMOS devices, high voltage NMOS devices, ultra low voltage NMOS devices, ultra high voltage NMOS devices / UHV NMOS devices.

10. The method for improving device leakage according to claim 9, characterized in that: When forming the PMOS device, a core PMOS device, an SRAM PMOS device, a high voltage PMOS device, a low voltage PMOS device, an ultra low voltage PMOS device, an ultra high voltage PMOS device / an ultra high voltage PMOS device are formed in this order.

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