ESD protection structure used for APD infrared detector reading circuit

Abstract

The invention discloses an ESD (Electro-Static Discharge) protection structure for a reading circuit of an APD (Avalanche Photo Diode) infrared detector. The ESD protection structure comprises a P-type substrate; the N-doped well formed in the substrate forms the body end of the PMOS; two P-doped active regions formed by the well form a source end and a drain end of the PMOS; and the grid end of the PMOS is connected with the source end and the body end through a resistor. The ESD protection structure is equivalent to that a PMOS (P-channel Metal Oxide Semiconductor) is connected in series with a parasitic diode formed by a body end and a substrate, when a protected PAD works under a voltage below a ground rail, the normal work of the PAD is not influenced by backward current, and the corresponding ESD protection capability can be achieved through an ESD protection design size recommended by a factory.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit protection, and in particular to an ESD protection structure for an APD infrared detector readout circuit. Background Art

[0002] With the development of integrated circuit manufacturing technology, the feature size continues to shrink, making the impact of ESD (Electro-Static Discharge) on integrated circuits increasingly greater. According to statistics, more than 1 / 3 of the failure of integrated circuits is caused by ESD. In order to reduce the impact of ESD on integrated circuits and improve the reliability of integrated circuits, the most effective way is to add ESD protection structures.

[0003] APD (Avalanche Photo-Diode) infrared detectors play a key role in the detection of weak infrared signals and space-time resolution, and have developed rapidly in recent years. The photoelectric conversion gain of the APD infrared detector is related to the reverse bias voltage. The larger the reverse bias voltage, the higher the gain. The APD infrared detector readout circuit is connected to the detector through an indium column, and provides a stable bias voltage for the APD infrared detector through the pixel input terminal and the detector common terminal, and performs photoelectric signal conversion, amplification filtering, quantization, and readout of the APD infrared detector in sequence. The pixel input voltage is determined by the polarity of the detector, and the voltage value is between the ground rail and the power rail. In applications, the APD infrared detector must meet the requirements of wide-range adjustable gain, that is, wide-range adjustable reverse bias voltage. The reverse bias voltage is adjusted by the detector common terminal voltage. For example: the pixel input voltage of a NonP polarity detector (N connected to the pixel input, P connected to the detector common terminal) is 1V. When it needs to work at a maximum reverse bias voltage of -6V, the detector common terminal voltage needs to be adjustable between -5 and 1V. Therefore, the APD infrared detector common terminal PAD (chip pad) port often needs to work at a voltage below the ground rail (negative voltage).

[0004] If the ESD protection structure of the APD infrared detector readout circuit does not have a corresponding negative pressure resistance design, a backflow current will appear from the chip to the PAD port. In severe cases, the readout circuit will fail during normal operation, thereby causing the entire detector to fail.

[0005] Although conventional ESD protection structures can achieve a higher level of protection capability, it is difficult to meet the negative pressure resistance requirements at the same time. Although negative pressure resistance design can be achieved by using back-to-back diodes, the diodes used as ESD protection structures have a large layout area, which is not conducive to chip integration.

[0006] CN117790498A discloses a negative voltage ESD protection circuit, including DNWELL and PWELL formed in DNWELL, PWELL as the body terminal of NMOS, the drain terminal of NMOS is connected to the PAD port to be protected, the gate terminal of NMOS is connected to the source terminal and PWELL through a resistor, and DNWELL is connected to PSUB and grounded. Its equivalent circuit is as follows: Figure 1 As shown, it is equivalent to an NMOS connected in series with a forward-biased diode to the ground. At this time, when the port is at a voltage lower than the ground rail, the parasitic diode is reversely cut off to prevent leakage. When an ESD event occurs, if it is a forward pulse, it directly triggers the drain / body diode avalanche breakdown, and then the ESD discharge is completed through the body / DNWELL diode. If it is a negative pulse, the body / DNWELL diode is reverse-biased and breaks down, and the ESD discharge is completed through the drain / body diode. It can be seen that although this structure can achieve a higher level of ESD protection capability and negative pressure resistance design, it requires an additional MASK (photolithography mask) compared to conventional ESD protection structures, such as DNWELL and PWELL, which is more expensive and has a larger layout area.

[0007] In summary, although conventional ESD protection structures can achieve a higher level of protection capability, it is difficult to meet the negative pressure resistance requirements at the same time; although negative pressure resistance design can be achieved by adopting back-to-back diodes, the diodes for ESD protection have a large layout area, which is not conducive to chip integration; although the existing ESD protection structure can achieve a higher level of protection capability and negative pressure resistance design at the same time, it requires additional MASKs, such as DNWELL and PWELL, compared with conventional ESD protection structures, which are more expensive and have a larger layout area. Summary of the invention

[0008] The technical problem to be solved by the present invention is to overcome the above-mentioned shortcomings and provide an ESD protection structure for an APD infrared detector readout circuit, which aims to solve the problem that the existing structure cannot simultaneously meet high-level ESD protection capability, negative pressure resistance, and small area and low cost.

[0009] The technical solution of the present invention is as follows:

[0010] The present invention provides an ESD protection structure for an APD infrared detector readout circuit, the ESD protection structure comprising a substrate, a well formed in the substrate, a first active region formed by the well, and a second active region formed by the well;

[0011] Furthermore, the substrate is P-doped, is a common substrate of the chip, and is grounded;

[0012] Further, the well is N-doped to form the body terminal of the PMOS;

[0013] Furthermore, the first active region and the second active region have the same doping type, both of which are P-doped, forming a source terminal and a drain terminal of a PMOS;

[0014] Further, the gate terminal of the PMOS is connected to the source terminal of the PMOS and the body terminal of the PMOS through a resistor;

[0015] Furthermore, the drain terminal of the PMOS is directly connected to the PAD port to be protected;

[0016] Furthermore, the layout of the PMOS adopts a multi-finger parallel layout structure;

[0017] Furthermore, the gate width-to-length ratio of the PMOS is a large width-to-length ratio, and the specific dimensions can refer to the dimensions recommended by the foundry for different ESD protection capabilities;

[0018] Furthermore, the resistor is used to couple voltage to the gate terminal of the PMOS when an ESD event occurs, turn on the PMOS channel, assist in the breakdown of the PMOS drain / body diode, and accelerate ESD discharge.

[0019] Beneficial effects of the present invention:

[0020] The technical solution provided by the present invention has at least the following advantages compared with the prior art:

[0021] (1) The present invention provides an ESD protection structure for an APD infrared detector readout circuit, which overcomes the problem that when the chip PAD port is at a negative voltage, a current flows back from the inside of the chip to the PAD port in the traditional ESD protection structure;

[0022] (2) The ESD protection structure for the APD infrared detector readout circuit provided by the present invention has a smaller layout area and is more conducive to integration compared with the method of using back-to-back diodes;

[0023] (3) Compared with the existing ESD protection structure, the ESD protection structure for the APD infrared detector readout circuit provided by the present invention does not require the use of an additional MASK, has a lower wafer production cost, and a smaller layout area;

[0024] (4) The ESD protection structure for the APD infrared detector readout circuit provided by the present invention is implemented based on the standard CMOS process, has a simple circuit structure, has no special requirements for the process, and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. 4 is an equivalent circuit diagram of an existing ESD protection structure.

[0026] Figure 2A schematic cross-sectional view of an ESD protection structure for an APD infrared detector readout circuit provided by the present invention.

[0027] Figure 3 The present invention provides a schematic cross-sectional diagram of an electrical connection of an ESD protection structure for an APD infrared detector readout circuit.

[0028] Figure 4 An equivalent circuit schematic diagram of an ESD protection structure for an APD infrared detector readout circuit provided by the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution in the embodiment of the present invention is clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without making creative work are all within the scope of protection of the present invention.

[0030] The present invention provides an ESD protection structure for an APD infrared detector readout circuit, the ESD protection structure comprising a substrate, a well formed in the substrate, a first active area formed by the well, and a second active area formed by the hydrazine; the substrate is P-doped, is a common substrate of a chip, and is grounded; the well is N-doped, forming a body end of a PMOS; the first active area and the second active area have the same doping type, both are P-doped, forming a source end and a drain end of the PMOS.

[0031] The structure is further described in conjunction with the cross-sectional schematic diagram of the ESD protection structure, such as Figure 2 As shown in the figure, Psub is the substrate, the P+ region in Psub is the substrate contact region (a in the figure), Nwell is the well, the N+ region in Nwell forms the body end of the PMOS (b in the figure), the two P+ regions in Nwell form the source end (c in the figure) and the drain end (d in the figure) of the PMOS, and e in the figure is the gate end contact region of the PMOS. The electrical connection cross-sectional diagram of the ESD protection structure of the present invention is shown in Figure 3 As shown, M in the figure is PMOS, the drain terminal of PMOS is directly connected to the protected PAD port, the gate terminal of PMOS is connected to the source terminal and the body terminal through a resistor R (R in the figure), the body terminal Nwell of PMOS forms a parasitic Nwell / Psub diode (D in the figure) with Psub, and Psub is grounded.

[0032] The equivalent circuit schematic diagram of an ESD protection structure for an APD infrared detector readout circuit provided by the present invention is as follows: Figure 4As shown, it is equivalent to a PMOS connected in series with a diode, the drain terminal of the PMOS is connected to the protected PAD terminal, the gate terminal of the PMOS is connected to the source terminal and the body terminal through the resistor R, Psub is grounded, and the Nwell and Psub of the PMOS form a parasitic Nwell / Psub diode.

[0033] In normal operation, when the PAD operates at the voltage from the ground rail to the power supply, the parasitic diode formed by Nwell and Psub is in a reverse bias state, which will not affect the normal operation of the PAD; when the PAD operates at a voltage lower than the ground rail, the parasitic diode formed by the drain of the PMOS and Nwell is in a reverse bias state, and no backflow current will be generated, thereby affecting the normal operation of the PAD;

[0034] When an ESD event occurs, when a positive ESD pulse occurs on the PAD, the parasitic diode formed by the drain of the PMOS and Nwell is forward biased, and the parasitic diode formed by Nwell and Psub undergoes avalanche breakdown to complete ESD discharge; when a negative ESD pulse occurs on the PAD, the parasitic diode formed by Nwell and Psub is forward biased, and the parasitic diode formed by the drain of the PMOS and Nwell undergoes avalanche breakdown to complete ESD discharge. When a negative ESD occurs, the ESD voltage can couple a certain voltage to the gate of the PMOS through the resistor R and the gate-drain capacitor, thereby opening the channel of the PMOS tube, assisting the avalanche breakdown of the drain of the PMOS and the Nwell diode, and accelerating ESD discharge.

[0035] In order to meet the corresponding ESD protection capabilities, the layout of PMOS adopts a multi-finger parallel layout structure. The gate width-to-length ratio of PMOS is a large aspect ratio. The specific dimensions can refer to the dimensions recommended by the foundry for different ESD capabilities.

[0036] In some specific embodiments, the ESD protection structure of the present invention can be manufactured using the xh018_CMOS process provided by Xfab. The 2000V electrostatic protection design dimensions recommended by the foundry are successfully implemented. When the PAD is -5V to the power supply voltage, the ESD protection structure works normally without leakage, and the electrostatic protection capability exceeds 2000V.

[0037] In summary, the present invention provides an ESD protection structure for the APD infrared detector readout circuit, which overcomes the problem that when the chip PAD end is at negative pressure, the current flows back from the inside to the PAD port in the traditional ESD structure; compared with the method of using back-to-back diodes, the layout area is smaller and more conducive to integration; compared with the existing ESD protection structure, no additional MASK is required, the chip production cost is lower, and the layout area is smaller; based on the standard CMOS process, the circuit structure is simple, there are no special requirements for the process, and the scope of use is wide. And the corresponding ESD protection capability can be achieved through the electrostatic protection design size recommended by the foundry, which significantly enhances the reliability of the integrated circuit.

Claims

1. An ESD protection structure for an APD infrared detector readout circuit, characterized in that: include: substrate; A well formed in the substrate, the well having a first active region and a second active region; The substrate is P-doped, serves as a common substrate of the chip and is grounded; The well is N-doped and is used to form the body terminal of the PMOS; The first active region and the second active region are P-doped and used to form a source terminal and a drain terminal of a PMOS. The gate terminal of the PMOS is connected to the source terminal of the PMOS and the body terminal of the PMOS through a resistor.

2. The ESD protection structure for an APD infrared detector readout circuit according to claim 1, characterized in that: The drain end of the PMOS is directly connected to the PAD of the APD infrared detector readout circuit that needs to be protected.

3. The ESD protection structure for an APD infrared detector readout circuit according to claim 1, characterized in that: The layout of the PMOS adopts a multi-finger parallel layout structure.

4. The ESD protection structure for an APD infrared detector readout circuit according to claim 1, characterized in that: The gate of the PMOS has a large width-to-length ratio.

5. The ESD protection structure for an APD infrared detector readout circuit according to claim 4, characterized in that: The width-to-length ratio of the gate of the PMOS is the size recommended by the foundry for different ESD protection capabilities.

6. An ESD protection structure for an APD infrared detector readout circuit according to any one of claims 1 to 5, characterized in that: The resistor is used to couple voltage to the gate terminal of the PMOS when a negative ESD event occurs, open the channel of the PMOS, and accelerate ESD discharge.

7. An ESD protection structure for an APD infrared detector readout circuit according to any one of claims 1 to 5, characterized in that: The design of the ESD protection structure is based on the xh018_CMOS process provided by Xfab.

8. The ESD protection structure for an APD infrared detector readout circuit according to claim 7, characterized in that: The 2000V electrostatic protection design size recommended by the foundry ensures that when the PAD is between -5V and the power supply voltage, the ESD protection structure does not leak and the electrostatic protection capability exceeds 2000V.

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