Deep trench resistor structure and method of forming same

Abstract

The invention relates to a deep trench resistor structure and a method of forming the same. Deep trench resistor structures and methods of forming the same are described. The structure includes a first trench in a first dielectric material; a first layer disposed over the first dielectric material; a second layer disposed on the first layer; a second dielectric material disposed over the second layer; and an adjustable device in contact with the first layer. The tunable device includes: a semiconductor-containing layer in contact with the first layer; a dielectric layer disposed on the semiconductor-containing layer; and a metal-containing layer disposed on the dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to deep trench resistor structures and methods of forming the same. Background Art

[0002] An integrated passive device (IPD) is a collection of one or more passive devices integrated on a semiconductor substrate. Passive devices may include, for example, capacitors, resistors, inductors, etc. IPDs are formed using semiconductor manufacturing processes and packaged as integrated circuits (ICs). This reduces size, reduces cost, and increases functional density compared to discrete passive devices. IPDs are also used in mobile devices and application processors, etc. Summary of the invention

[0003] According to one aspect of the present disclosure, a deep trench resistor structure is provided, comprising: a first trench located in a first dielectric material; a first layer disposed on the first dielectric material; a second layer disposed on the first layer; a second dielectric material disposed on the second layer; and an adjustable device in contact with the first layer, wherein the adjustable device comprises: a semiconductor-containing layer in contact with the first layer; a dielectric layer disposed on the semiconductor-containing layer; and a metal-containing layer disposed on the dielectric layer.

[0004] According to another aspect of the present disclosure, a deep trench resistor structure is provided, comprising: a first trench and a second trench, located in a first dielectric material, wherein the first trench and the second trench are separated by a first portion of the first dielectric material; a first layer, disposed on the first dielectric material; a second layer, disposed on the first layer; a second dielectric material, disposed on the second layer; a third dielectric material, surrounding and contacting the first layer, the second layer and the second dielectric material; a first adjustable device, disposed in the second dielectric material and contacting the first layer; and a first conductive feature, disposed in the third dielectric material, wherein the first conductive feature is electrically connected to the first adjustable device.

[0005] According to another aspect of the present disclosure, a method for forming a deep trench resistor structure is provided, comprising: forming at least one trench in a first dielectric material; depositing a first layer above the first dielectric material; depositing a second layer on the first layer; depositing a second dielectric material on the second layer; and forming an adjustable device in contact with the second layer, wherein forming the adjustable device comprises: depositing a semiconductor-containing layer in contact with the second layer; depositing a dielectric layer on the semiconductor-containing layer; and depositing a metal-containing layer on the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read together with the accompanying drawings, various aspects of the present disclosure can be best understood through the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A-11A are cross-sectional side views of various stages in fabricating a deep trench resistor structure according to some embodiments.

[0008] Figure 1B - Figure 11B is a top view of various stages in fabricating a deep trench resistor structure according to some embodiments.

[0009] Figure 8C and Fig. 9C According to some embodiments, Figure 8B 1 is a cross-sectional side view of the DTR structure 100 taken along line AA.

[0010] Fig. 12A is a circuit diagram of a deep trench resistor and a tunable device according to some embodiments.

[0011] Fig. 12B According to some embodiments Fig. 12A A graph of the relationship between temperature and resistance of a deep trench resistor.

[0012] Figures 13A to 20A are cross-sectional side views of various stages in fabricating a deep trench resistor structure according to an alternative embodiment.

[0013] Figure 13B-Figure 20B are top views of various stages in fabricating a deep trench resistor structure according to an alternative embodiment.

[0014] Fig.21A is a circuit diagram of a deep trench resistor and a tunable device according to an alternative embodiment.

[0015] Fig. 21B According to some embodiments Fig.21A A graph of the relationship between temperature and resistance of a deep trench resistor.

[0016] Fig.22A and Fig. 22B are various views of a deep trench resistor structure according to an alternative embodiment.

[0017] Fig.23A and Fig. 23B is a cross-sectional side view of a semiconductor device structure including a deep trench resistor structure according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are directly in contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "over," "up," "top," and the like may be used herein to describe the relationship of one element or feature relative to another element(s) or feature(s) as shown in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] An integrated passive device (IPD) may include a substrate and a deep trench resistor (DTR) disposed on the substrate. The DTR may increase device density. In addition, the resistance of the DTR may be independent of temperature. In some embodiments, the DTR may include a first layer having a positive temperature coefficient of resistance (TCR) and a second layer having a negative TCR. In addition, in order to achieve the pseudo zero TCR performance of the DTR, an adjustable device is connected to the DTR. The adjustable device may be used to adjust the resistance of the DTR.

[0021] Figures 1A-11A are cross-sectional side views of various stages in fabricating a deep trench resistor (DTR) structure 100 in accordance with some embodiments. Figure 1B - Figure 11B According to some embodiments of the invention Figures 1A-11A The corresponding top view of each stage of the DTR structure 100 is shown in FIG. Figure 1A-11B Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or deleted. The order of operations / processes is not limiting and may be interchangeable.

[0022] like Figure 1A and Figure 1BAs shown, the DTR structure includes a dielectric material 104 deposited on an etch stop layer 102. In some embodiments, the dielectric material 104 is an intermetallic dielectric (IMD) layer, and the dielectric material 104 and the etch stop layer 102 are part of an interconnect structure disposed on a substrate on which a plurality of devices are formed. The dielectric material 104 may include any suitable dielectric material, such as SiO x 、SiO x C y H z or SiO x C y , where x, y and z are integers or non-integers. In some embodiments, dielectric material 104 includes a low-k dielectric material having a k value less than the k value of silicon oxide. In some embodiments, dielectric material 104 has a k value ranging from about 1.5 to about 3.9. Dielectric material 104 can be deposited by any suitable process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). Etch stop layer 102 can include any suitable material, such as SiN, AlN or Al2O3. Etch stop layer 102 can be formed by any suitable process. In some embodiments, etch stop layer 102 is a conformal layer and is formed by ALD.

[0023] like Figure 2A and Figure 2B As shown, trenches 106 are formed in dielectric material 104 to expose portions of etch stop layer 102. Trench 106 may be formed using any suitable method. In some embodiments, trench 106 is formed using a photolithography and etching process. A resist layer (not shown) is patterned by a photolithography process, and the pattern of the resist is transferred to dielectric material 104 by an etching process to form trench 106. The etching process may be a dry etching process, a wet etching process, or a combination thereof. The trenches are separated by portions 104a of dielectric material 104. Portions of etch stop layer 102 are exposed at the bottom of trench 106, as shown in FIG. Figure 2A and Figure 2B The groove 106 may have a dimension in the range of about 10 nm to about 1 micron along the X direction, and a dimension in the range of about 10 nm to about 1 micron along the Y direction. In some embodiments, the dimension in the Y direction is significantly greater than the dimension in the X direction, such as Figure 2B In some embodiments, the depth of the trench 106 along the Z direction is in a range from about 100 nm to about 10 microns.

[0024] like Figure 3A and Figure 3BAs shown, a first layer 108 is deposited on the dielectric material 104 and in the trench 106, and a second layer 110 is deposited on the first layer 108. In some embodiments, the first layer 108 includes a first material having a positive TCR, and the second layer 110 includes a second material having a negative TCR. In some embodiments, the first layer 108 includes the second material, and the second layer 110 includes the first material. The first material may include a metal, such as Au, Pt, Cr, Ti, Ta, Cu, Ag, Co, Ni, Fe, Pb, Al, Ru, RuO2, Ir, IrO2, Mo, W, TiN, TaN, WN, MoN, TiAl, TiAlC, TaAl, TaAlC, TiAlN, TaAlN, metal alloys, metal oxides, metal nitrides, metal carbides, or other suitable metal-containing materials. The second material may include a semiconductor, such as Si, Ge, SiGe, GaN, InN, InGaN, GaAs, InAs, InGaAs, InGaZnO, CuO, InZnO, GaZnO, and compounds thereof. In some embodiments, the semiconductor is a doped semiconductor, and the dopant includes B, P, N, O, C, or other suitable dopants. In some embodiments, the semiconductor is a polycrystalline semiconductor. The first layer 108 and the second layer 110 may be formed by any suitable method. In some embodiments, the first layer 108 and the second layer 110 are conformal layers and are formed by a conformal process such as ALD. The first layer 108 and the second layer 110 may form one or more DTRs. In some embodiments, a single layer such as the first layer 108 or the second layer 110 forms one or more DTRs. In some embodiments, Figure 3A As shown, the first layer 108 and the second layer 110 (or either the first layer 108 or the second layer 110 ) do not fill the trench 106 .

[0025] like Figure 4A and Figure 4B As shown, dielectric material 112 is formed on second layer 110 and fills trench 106. Dielectric material 112 can be any suitable dielectric material. In some embodiments, dielectric material 112 includes SiN. In some embodiments, dielectric material 112 can be formed by a conformal process (e.g., ALD) to avoid forming seams or voids in trench 106.

[0026] like Figure 5A and Figure 5B As shown, an opening 114 is formed in the dielectric material 112. In some embodiments, the opening 114 is a trench. Figure 5A and Figure 5BAs shown, the size of the opening 114 along the X direction can be significantly larger than the size of the groove 106 along the X direction, and the size of the opening 114 along the Y direction can be substantially the same as the size of the groove 106 along the Y direction. In some embodiments, a portion of the second layer 110 and a portion of the dielectric material 112 disposed between these portions of the second layer 110 are exposed in the opening 114. The opening 114 can be formed by any suitable method. In some embodiments, the opening 114 is formed using a photolithography and etching process. A resist layer (not shown) is patterned by a photolithography process, and the pattern of the resist is transferred to the dielectric material 112 by an etching process to form the opening 114. The etching process can be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, a portion of the second layer 110 is removed by an etching process, and the thickness of the portion of the second layer 110 exposed in the opening 114 can be significantly less than the thickness of the portion of the second layer 110 covered by the dielectric material 112. In some embodiments, the size of the opening 114 along the X direction is smaller than the sum of the sizes of the two portions 104 a of the dielectric material 104 and the trench 106 along the X direction. In some embodiments, the size of the opening 114 along the X direction is larger than the sum of the sizes of the two portions 104 a of the dielectric material 104 and the trench 106 along the X direction. In other words, the opening 114 may extend over one or more trenches 106.

[0027] like Fig. 6A and Figure 6B As shown, the adjustable device 116 is formed in the opening 114. In some embodiments, the adjustable device 116 includes a first layer 118, a second layer 120 deposited on the first layer 118, and a third layer 122 deposited on the second layer 120. The first layer 118 can be a semiconductor-containing layer. In some embodiments, the first layer 118 includes Si, SiGe, InGaZnO, InGaO, InGaSnO, CuO, SnO, NiO, CrO, GaAs, InGaAs, InP, InGaP, GaP, GaN, InGaN or a compound thereof. The first layer 118 can be deposited by any suitable method. In some embodiments, the first layer 118 is a conformal layer and is formed by a conformal process (e.g., ALD). The first layer 118 can be deposited on the dielectric material 112 and in the opening 114. Next, the second layer 120 is deposited on the first layer 118 located above the dielectric material 112 and in the opening 114. The second layer 120 can be a dielectric layer. In some embodiments, the second layer 120 includes SiN, SiO x , SiON, SiCN, SiOCN, HfO2, HfZrO, HfAlO, AlO x 、TaO x, HfTaO, TiO2, HfTiO, TaAlO, ZrAlO or a compound thereof. The second layer 120 can be deposited by any suitable method. In some embodiments, the second layer 120 is a conformal layer and is formed by a conformal process (e.g., ALD). Next, a third layer 122 is deposited on the second layer 120 located above the dielectric material 112 and in the opening 114. The third layer 122 can be a metal-containing layer. In some embodiments, the third layer 122 includes Au, Pt, Cr, Ti, Ta, Cu, Ag, Co, Ni, Fe, Pb, Al, Ru, RuO2, Ir, IrO2, Mo, W, TiN, TaN, WN, MoN, TiAl, TiAlC, TaAl, TaAlC, TiAlN, TaAlN or a compound thereof. The third layer 122 can be deposited by any suitable method. In some embodiments, the third layer 122 is a conformal layer and is formed by a conformal process (e.g., ALD). After depositing first layer 118, second layer 120, and third layer 122, a planarization process, such as a CMP process, may be performed to expose dielectric material 112. Portions of first layer 118, second layer 120, and third layer 122 formed on dielectric material 112 may be removed by the planarization process.

[0028] In some embodiments, the first layer 108 and the second layer 110 form a DTR. The DTR includes a first segment 109 disposed in one or more trenches 106 below the adjustable device 116, and a second segment 111 disposed in one or more trenches 106 not below the adjustable device 116. Therefore, the resistance of the DTR is the sum of the resistances of the first segment 109 and the second segment 111. The resistance of the first segment 109 can be adjusted by the adjustable device 116.

[0029] Even if the first layer 108 and the second layer 110 are positive TCR and negative TCR (or vice versa), the resistance of the DTR may still change based on temperature. In other words, the resistance of the DTR including the first layer 108 and the second layer 110 may still be temperature-dependent. The adjustable device 116 helps to reduce the temperature dependence of the resistance of the DTR. In some embodiments, the third layer 122 is used as a control gate electrode, and the first layer 118 is used as a channel. The portion of the second layer 110 that contacts the edge portion of the adjustable device 116 can be used as a source / drain region. As a result, the adjustable device 116 can be a transistor connected in parallel to the first section 109 of the DTR. In some embodiments, when the adjustable device 116 is turned off, the first layer 118 is an insulator having a resistance significantly greater than the resistance of the first section 109, and current flows from the second section 111 to the first section 109. When the adjustable device 116 is partially turned on, a first voltage is applied to the adjustable device 116, and the first layer 118 has a resistance substantially the same as the resistance of the first section 111 of the DTR. Therefore, current flows from the second segment 111 to both the first segment 109 and the first layer 118. As a result, the resistance of the first segment 109 decreases. When the adjustable device 116 is fully turned on, a second voltage significantly greater than the first voltage is applied to the adjustable device 116, and the resistance of the first layer 118 is significantly less than the resistance of the first segment 109, and current flows from the second segment 111 to the first layer 118, completely bypassing the first segment 109. As a result, the resistance of the first segment 109 becomes zero. In some embodiments, the resistance of the DTR increases as the temperature increases. The adjustable device 116 can be turned on to reduce the resistance of a segment of the DTR connected in parallel thereto (e.g., the first segment 109) to keep the resistance of the DTR substantially constant as the temperature increases. Details of how the adjustable device 116 adjusts the resistance of the DTR at different temperatures are described below. Fig. 12A and Fig. 12B shown.

[0030] Fig. 12A is a circuit diagram of DTR and adjustable device 116, and Fig. 12B is a graph showing the relationship between temperature and resistance of a DTR. As described above, in some embodiments, the DTR may be a two-layer structure including a first layer 108 and a second layer 110. In some embodiments, the DTR is a single layer including the first layer 108 or the second layer 110. Fig. 12A As shown, the adjustable device 116 is connected in parallel with the first section 109 of the DTR. The first section 109 of the DTR has a resistance ΔR at a temperature t1. The second section 111 of the DTR has a resistance R at a temperature t1. Fig. 12BAs shown, the temperature and resistance of the second section 111 of the DTR have a linear relationship 201. For example, at temperature t1, the resistance R of the second section 111 of the DTR is equal to R1. At temperature t2, the resistance R of the second section 111 of the DTR is equal to R2. At temperature t3, the resistance R of the second section 111 of the DTR is equal to R3. Therefore, at temperature t1, the resistance of the DTR is equal to R1 plus ΔR, and R1 plus ΔR is equal to R2, as shown in FIG. Fig. 12B As shown. At temperature t1, the adjustable device 116 is turned off. At temperature t3, the adjustable device 116 is partially turned on, so the resistance of the first segment 109 is equal to a percentage of ΔR, which is ΔR1. Therefore, the resistance of DTR is equal to R3 plus ΔR1, and R3 plus ΔR1 is equal to R2. At temperature t2, the adjustable device 116 is fully turned on, so the resistance of the first segment 109 is equal to zero. As a result, the resistance of DTR is equal to R2. By utilizing the adjustable device 116, when the temperature increases from t1 to t2, the resistance of DTR, which is the sum of the resistance of the first segment 109 and the resistance of the second segment 111, remains substantially constant (e.g., at R2).

[0031] refer to Fig. 7A and Figure 7B , after forming the tunable device 116, portions of the dielectric material 112, the second layer 110, and the first layer 108 are removed along the X direction. In other words, the dielectric material 112, the second layer 110, and the first layer 108 are recessed along the X direction. In some embodiments, a first mask layer (not shown) is formed on the remaining portions of the dielectric material 112 and the tunable device 116, and a plurality of etching processes are performed to remove the exposed portions of the dielectric material 112, and the portions of the first layer 108 and the second layer 110 located under the exposed portions of the dielectric material 112. Next, as Fig. 8A and Figure 8B As shown, portions of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are removed along the Y direction. In other words, the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are recessed along the Y direction. If the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are not recessed along the Y direction, current may flow around the adjustable device 116. As a result, the adjustable device 116 cannot adjust the resistance of DTR. In some embodiments, the size of the adjustable device 116 along the Y direction is substantially equal to or greater than the size of the first layer 108 and the second layer 110 along the Y direction. Figure 8C It is along Figure 8B A cross-sectional side view of the DTR structure 100 taken along line AA. Figure 8B and Figure 8CAs shown, portions of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 located in the trench 106 may be removed. Therefore, each trench 106 includes portions of the first layer 108, the second layer 110, and the dielectric material 112 located between the two openings, and the adjustable device 116 is disposed on the dielectric material 112. Portions of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 may be removed along the Y direction by any suitable method. In some embodiments, a second mask layer (not shown) is formed on the remaining portions of the dielectric material 112 and the adjustable device 116, and a plurality of etching processes are performed to remove the dielectric material 112, the exposed portions of the adjustable device 116, and the portions of the first layer 108 and the second layer 110 located under the exposed portions of the dielectric material 112 and the adjustable device 116. The etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the recessing of the dielectric material 112, the second layer 110, and the first layer 108 along the X direction and the recessing of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 along the Y direction are performed by a single photolithography process with multiple etching processes. In other words, instead of the first mask layer and the second mask layer, a single mask layer (not shown) is formed on the remaining portions of the dielectric material 112 and the adjustable device 116, and multiple etching processes are performed to remove portions of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116.

[0032] like Figure 9A-9C As shown, dielectric material 124 is formed on dielectric material 112, adjustable device 116, and in trench 106 to fill trench 106. In some embodiments, an etch stop layer may be first deposited on the surface of DTR structure 100, and dielectric material 124 is deposited on the etch stop layer. Dielectric material 124 may include any suitable dielectric material. In some embodiments, dielectric material 124 includes the same material as dielectric material 104.

[0033] like Fig. 10A and Fig. 10B As shown, openings 126 are formed in dielectric materials 124, 112. In some embodiments, openings 126 located above first section 109 of the DTR expose third layer 122 of tunable device 116, and openings 126 located above second section 111 of the DTR expose portions of second layer 110. Next, as Fig.11A and Fig. 11BAs shown, a conductive feature 128 is formed in the opening 126. The conductive feature 128 includes a conductive material, such as a metal. In some embodiments, the conductive feature 128 may be or include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, or the like, or a combination thereof, and may be deposited by CVD, ALD, PVD, or other deposition techniques. Fig.11A As shown, in some embodiments, the conductive feature 128 is in contact with the second layer 110 and the third layer 122. In some embodiments, the conductive feature 128 is electrically connected to the tunable device 116.

[0034] Figures 13A to 20A are cross-sectional side views of various stages of fabricating a DTR structure 100 according to an alternative embodiment, and Figure 13B-Figure 20B is manufactured according to an alternative embodiment Figures 13A to 20A The corresponding top view of each stage of the DTR structure 100 is shown in FIG. Figures 13A-20B Additional operations are provided before, during, and after the processes shown, and some operations described below may be replaced or deleted. The order of operations / processes is not limited and may be interchanged.

[0035] like Fig.13A and Fig. 13B As shown, a dielectric material 112 is formed on the second layer 110 and in the trench 106 . Fig.13A and Fig. 13B The DTR structure 100 shown can be used with Figure 4A and Figure 4B The DTR structure 100 shown in FIG. Fig.14A and Fig. 14B As shown, an opening 130 is formed in the dielectric material 112, the second layer 110, and the first layer 108, and exposes a portion 104a of the dielectric material 104. In some embodiments, the opening 130 is a trench. Fig.14A and Fig. 14B As shown, the size of the opening 130 along the X direction can be the same as or significantly larger than the size of the portion 104a along the X direction, and the size of the opening 130 along the Y direction can be substantially the same as the size of the groove 106 along the Y direction. In some embodiments, the portion of the first layer 108 located on the opposite side of the portion 104a is exposed in the opening 130. The opening 130 can be formed by any suitable method. In some embodiments, the opening 130 is formed using photolithography and one or more etching processes. A resist layer (not shown) is patterned by a photolithography process, and the pattern of the resist layer is transferred to the dielectric material 112, the second layer 110, and the first layer 108 by one or more etching processes to form the opening 130.

[0036] like Fig.15A and Fig. 15B As shown, the adjustable device 116 is formed in the opening 130. The adjustable device 116 can be formed by Fig. 6A and Figure 6B The same process as described in is formed. Fig.15A As shown, the first layer 118 of the adjustable device 116 contacts the portion 104a of the dielectric material 104, the first layer 108, and the second layer 110. In some embodiments, the adjustable device 116 physically and electrically separates the DTR into a first section 132 and a second section 134. The first section 132 may be upstream of the adjustable device 116, and the second section 134 may be downstream of the adjustable device 116. The adjustable device 116 helps to reduce the temperature dependence of the resistance of the DTR. In some embodiments, the third layer 122 is used as a control gate electrode, and the first layer 118 is used as a channel. In some embodiments, the adjustable device 116 is connected in series to the first section 132 and the second section 134 of the DTR. In some embodiments, when the adjustable device 116 is turned off, the first layer 118 is an insulator having a first resistance, and the resistance of the DTR is equal to the sum of the resistance of the first section 132, the first resistance of the first layer 118, and the resistance of the second section 134. When the adjustable device 116 is partially turned on, a first voltage is applied to the adjustable device 116, and the first layer 118 has a second resistance that is significantly less than the first resistance. The resistance of DTR is equal to the sum of the resistance of the first segment 132, the second resistance, and the resistance of the second segment 134. When the adjustable device 116 is fully turned on, a second voltage that is significantly greater than the first voltage is applied to the adjustable device 116, and the first layer 118 has a third resistance that is significantly less than the second resistance. In some embodiments, the third resistance is zero. As a result, the resistance of DTR is equal to the sum of the resistance of the first segment 132 and the resistance of the second segment 134. In some embodiments, the resistance of DTR increases as temperature increases. The adjustable device 116 can be turned on to reduce the resistance of the first layer 118 of the adjustable device to keep the resistance of DTR substantially constant as the temperature increases. Details of how the adjustable device 116 adjusts the resistance of DTR at different temperatures are described below. Fig.21A and Fig. 21B shown.

[0037] Fig.21A is a circuit diagram of the first section 132 of DTR and the adjustable device 116, and Fig. 21B is a graph showing the relationship between the temperature and resistance of DTR. Fig.21A As shown, the adjustable device 116 and the first section 132 of the DTR are connected in series. At temperature t1, the first section 132 of the DTR has a resistance R. At temperature t1, the adjustable device 116 (or the first layer 118 of the adjustable device 116) has a resistance ΔR. Fig. 21B As shown, the temperature and resistance of the first section 132 of the DTR have a linear relationship 301. For example, at temperature t1, the resistance R of the first section 132 of the DTR is equal to R1. At temperature t2, the resistance R of the first section 132 of the DTR is equal to R2. At temperature t3, the resistance R of the first section 132 of the DTR is equal to R3. Therefore, at temperature t1, the combined resistance of the first section 132 and the adjustable device 116 is equal to R1 plus ΔR, and R1 plus ΔR is equal to R2, as shown in FIG. Fig. 21B As shown. At temperature t1, the adjustable device 116 is turned off. At temperature t3, the adjustable device 116 is partially turned on, so the resistance of the first layer 118 of the adjustable device 116 is equal to a percentage of ΔR, which is ΔR1. As a result, the combined resistance of the first segment 132 and the adjustable device 116 is equal to R3 plus ΔR1, and R3 plus ΔR1 is equal to R2. At temperature t2, the adjustable device 116 is fully turned on, so the resistance of the first layer 118 of the adjustable device 116 is equal to zero. As a result, the combined resistance of the first segment 132 and the adjustable device 116 is equal to R2. By utilizing the adjustable device 116, when the temperature increases from t1 to t2, the combined resistance of the first segment 132 of DTR and the adjustable device 116 remains substantially constant (e.g., at R2).

[0038] refer to Fig.16A and Fig. 16B After forming the adjustable device 116, portions of the dielectric material 112, the second layer 110, and the first layer 108 are removed along the X direction. In other words, the dielectric material 112, the second layer 110, and the first layer 108 are recessed along the X direction. Next, as Fig.17A and Fig. 17B As shown, portions of the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are removed along the Y direction. In other words, the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are recessed along the Y direction. If the dielectric material 112, the second layer 110, the first layer 108, and the adjustable device 116 are not recessed along the Y direction, current may flow around the adjustable device 116. As a result, the adjustable device 116 cannot adjust the resistance of DTR. In some embodiments, the dimension of the adjustable device 116 along the Y direction is substantially equal to or greater than the dimension of the first layer 108 and the second layer 110 along the Y direction. Similar to Figure 8B and Figure 8CThe DTR structure 100 shown may remove portions of the dielectric material 112, the second layer 110, and the first layer 108 located in the trenches 106. Therefore, each trench 106 includes portions of the first layer 108, the second layer 110, and the dielectric material 112 located between two openings. In some embodiments, the recessing of the dielectric material 112, the second layer 110, and the first layer 108 along the X direction and the recessing of the dielectric material 112, the second layer 110, the first layer 108, and the tunable device 116 along the Y direction are performed by a single photolithography process with multiple etching processes.

[0039] like Fig.18A and Fig.18B As shown, a dielectric material 124 is formed on the dielectric material 112, the tunable device 116, and in the trench 106 to fill the trench 106. In some embodiments, an etch stop layer may be first deposited on the surface of the DTR structure 100, and the dielectric material 124 is deposited on the etch stop layer. Fig.19A and Fig.19B As shown, openings 126 are formed in dielectric materials 124, 112. In some embodiments, openings 126 located above first segment 132 and second segment 134 of the DTR expose second layer 110, and openings 126 located above tunable device 116 expose third layer 122. In some embodiments, second layer 120 may also be exposed in openings 126 located above tunable device 116. Next, as Fig. 20A and Fig. 20B As shown, conductive features 128 are formed in openings 126 .

[0040] Fig.22A and Fig. 22B 1 are various views of a DTR structure 100 according to alternative embodiments. In some embodiments, a plurality of adjustable devices 116 are formed in the DTR to adjust the resistance of the DTR. Fig.22A and Fig. 22B As shown, a second adjustable device 116 is formed on portion 104a. In some embodiments, the DTR includes N trenches 106 and N-1 portions 104a, and an adjustable device 116 is formed on each portion 104a. Therefore, in some embodiments, the DTR includes N trenches 106, and the number of adjustable devices 116 ranges from about 1 to about N-1.

[0041] Fig.23A and Fig. 23B is a cross-sectional side view of a semiconductor device structure 160 including a DTR structure 100 according to some embodiments. Fig.23AAs shown, in some embodiments, the semiconductor device structure 160 includes a substrate 162, a device 164 formed on the substrate 162, and an interconnect structure 166 formed on the substrate 162. The substrate 162 may be or may include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. In some embodiments, the semiconductor material of the substrate 162 may include: an elemental semiconductor, such as silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof. In some embodiments, the substrate 162 includes Si, Ge, Ga, Zn, In, O, N, B, or P. The device 164 may be any suitable device, such as a transistor, a sensor, or a diode. In some embodiments, the device 164 is a logic device, such as a planar FET, a FinFET, a gate all around (GAA) FET, a 2D material device, a graphene device. In some embodiments, the device 164 is a planar transistor, including a source / drain region 176, a gate structure 174, and a channel region 178, such as Fig.23A As shown. In some embodiments, the source / drain region 176 includes Si, Ge, C, P, B or a compound thereof. The gate structure 174 may include a gate electrode layer and a gate dielectric layer. In some embodiments, the gate electrode layer includes polysilicon, amorphous silicon, Si, Ti, Ta, Al, W, N, Zn, In, Ga, Ge, C or a compound thereof, and the gate dielectric layer includes SiO2, HfO, La, SiON, SiCON, Zn, Zr or a compound thereof. In some embodiments, an isolation structure may be formed in the substrate 162 to separate the device 164. The isolation structure may be a local oxidation of silicon (LOCOS), a shallow trench isolation (STI) or a deep trench isolation (DTI).

[0042] The interconnect structure 166 includes a plurality of intermetal dielectric (IMD) layers 168 and a plurality of conductive features 170 formed in the IMD layers 168. The DTR structure 100 may be located in the interconnect structure 166 and between vertically adjacent IMD layers 168. The conductive features 172 extend through the IMD layers 168 in which the DTR structure 100 is located to electrically connect the conductive features 170 in the IMD layers 168 located above and below the DTR structure 100. In some embodiments, the adjustable device 116 in the DTR structure 100 may be connected to a sensing circuit for pseudo TCR control.

[0043] Fig. 23B1 is a cross-sectional side view of a semiconductor device structure 160 including a DTR structure 100 according to an alternative embodiment. In some embodiments, the device 164 is a GAA FET. The GAA FET may include a source / drain region 192, a channel region 196, and a gate structure 198 surrounding the channel region 196. In some embodiments, the semiconductor device structure 160 includes an interconnect structure 166 formed on the front side of a substrate 162 (which is subsequently removed), and a backside interconnect structure 167 formed on the back side of the substrate 162. The interconnect structure 166 may be bonded to the substrate 161. In some embodiments, the DTR structure 100 is formed in the backside interconnect structure 167. The backside interconnect structure 167 also includes a plurality of IMD layers 168, and a plurality of conductive features 170 formed in the IMD layers. The DTR structure 100 may be formed between vertically adjacent IMD layers 168 in the backside interconnect structure 167. The conductive features 172 extend through the IMD layer 168 in which the DTR structure 100 is located to electrically connect the conductive features 170 in the IMD layer 168 located above and below the DTR structure 100. In some embodiments, the backside interconnect structure 167 includes one or more backside power rails 199 for providing power to the device 164 from the backside. The DTR structure 100 can be disposed on the backside power rails 199, such as Fig. 23B In some embodiments, the adjustable device 116 in the DTR structure 100 can be connected to a sensing circuit for pseudo TCR control.

[0044] Embodiments of the present disclosure provide a DTR device structure 100 and a method for forming the same. In some embodiments, the DTR structure 100 includes a DTR including a layer 108, a layer 110, or a combination of layers 108 and 110. An adjustable device 116 can be formed in parallel or in series with a segment of the DTR. Some embodiments can achieve advantages. For example, the adjustable device 116 can adjust the resistance of a segment of the DTR to achieve pseudo-TCR control.

[0045] One embodiment is a DTR structure. The structure includes: a first trench in a first dielectric material; a first layer disposed on the first dielectric material; a second layer disposed on the first layer; a second dielectric material disposed on the second layer; and a tunable device in contact with the first layer. The tunable device includes: a semiconductor-containing layer in contact with the first layer; a dielectric layer disposed on the semiconductor-containing layer; and a metal-containing layer disposed on the dielectric layer.

[0046] Another embodiment is a DTR structure. The structure includes: a first trench and a second trench located in a first dielectric material, and the first trench and the second trench are separated by a first portion of the first dielectric material; a first layer disposed on the first dielectric material; a second layer disposed on the first layer; a second dielectric material disposed on the second layer; a third dielectric material surrounding and contacting the first layer, the second layer, and the second dielectric material; a first tunable device disposed in the second dielectric material and contacting the first layer; and a first conductive feature disposed in the third dielectric material. The first conductive feature is electrically connected to the first tunable device.

[0047] Another embodiment is a method. The method includes: forming at least one trench in a first dielectric material; depositing a first layer over the first dielectric material; depositing a second layer over the first layer; depositing a second dielectric material over the second layer; and forming a tunable device in contact with the second layer. Forming the tunable device includes: depositing a semiconductor-containing layer in contact with the second layer; depositing a dielectric layer over the semiconductor-containing layer; and depositing a metal-containing layer over the dielectric layer.

[0048] The features of several embodiments have been summarized above so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various modifications, substitutions, and changes to this document without departing from the spirit and scope of the present disclosure.

[0049] Example 1. A deep trench resistor structure, comprising: a first trench located in a first dielectric material; a first layer disposed on the first dielectric material; a second layer disposed on the first layer; a second dielectric material disposed on the second layer; and an adjustable device in contact with the first layer, wherein the adjustable device comprises: a semiconductor-containing layer in contact with the first layer; a dielectric layer disposed on the semiconductor-containing layer; and a metal-containing layer disposed on the dielectric layer.

[0050] Example 2. The deep trench resistor structure of Example 1, wherein the first layer comprises a metal and the second layer comprises a semiconductor.

[0051] Example 3. The deep trench resistor structure of Example 1, wherein the first layer and the second layer and the second dielectric material are disposed in the first trench.

[0052] Example 4. The deep trench resistor structure of Example 3, wherein the tunable device is disposed in the second dielectric material above the first trench.

[0053] Example 5. The deep trench resistor structure of Example 1 further includes a second trench formed in the first dielectric material.

[0054] Example 6. The deep trench resistor structure of Example 5, wherein the first trench and the second trench are separated by a portion of the first dielectric material.

[0055] Example 7. The deep trench resistor structure of Example 6, wherein the tunable device is disposed over the portion of the first dielectric material.

[0056] Example 8. The deep trench resistor structure of Example 7, wherein the tunable device contacts the portion of the first dielectric material.

[0057] Example 9. A deep trench resistor structure, comprising: a first trench and a second trench, located in a first dielectric material, wherein the first trench and the second trench are separated by a first portion of the first dielectric material; a first layer, disposed on the first dielectric material; a second layer, disposed on the first layer; a second dielectric material, disposed on the second layer; a third dielectric material, surrounding and contacting the first layer, the second layer and the second dielectric material; a first adjustable device, disposed in the second dielectric material and contacting the first layer; and a first conductive feature, disposed in the third dielectric material, wherein the first conductive feature is electrically connected to the first adjustable device.

[0058] Example 10. The deep trench resistor structure of Example 9, wherein the first tunable device comprises a semiconductor-containing layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

[0059] Example 11. The deep trench resistor structure of Example 9, wherein the first tunable device is disposed on the first portion of the first dielectric material.

[0060] Example 12. The deep trench resistor structure of Example 11 further includes a third trench disposed in the first dielectric material, wherein the third trench and the second trench are separated by a second portion of the first dielectric material.

[0061] Example 13. The deep trench resistor structure of Example 12, further comprising a second tunable device disposed on the second portion of the first dielectric material.

[0062] Example 14. The deep trench resistor structure of Example 9, wherein the first tunable device is disposed above the second trench.

[0063] Example 15. The deep trench resistor structure of Example 14, further comprising a second conductive feature disposed above the first dielectric material, wherein the second conductive feature contacts the second layer.

[0064] Example 16. The deep trench resistor structure of Example 15, further comprising a third conductive feature disposed in the third dielectric material, wherein the second conductive feature and the third conductive feature are aligned in a first direction.

[0065] Example 17. The deep trench resistor structure of Example 16 further includes a fourth conductive feature disposed in the third dielectric material, wherein the second conductive feature and the fourth conductive structure are aligned in a second direction perpendicular to the first direction.

[0066] Example 18. A method for forming a deep trench resistor structure, comprising: forming at least one trench in a first dielectric material; depositing a first layer above the first dielectric material; depositing a second layer on the first layer; depositing a second dielectric material on the second layer; and forming an adjustable device in contact with the second layer, wherein forming the adjustable device comprises: depositing a semiconductor-containing layer in contact with the second layer; depositing a dielectric layer on the semiconductor-containing layer; and depositing a metal-containing layer on the dielectric layer.

[0067] Example 19. The method of Example 18, further comprising forming an opening in the second dielectric material, wherein the tunable device is formed in the opening.

[0068] Example 20. The method of Example 19, wherein the opening extends through the second layer.

Claims

1. A deep trench resistor structure, comprising: a first trench disposed in the first dielectric material; a first layer disposed on the first dielectric material; a second layer, disposed on the first layer; a second dielectric material disposed on the second layer; as well as An adjustable device in contact with the first layer, wherein the adjustable device comprises: A semiconductor layer in contact with the first layer; a dielectric layer disposed on the semiconductor-containing layer; and The metal-containing layer is disposed on the dielectric layer.

2. The deep trench resistor structure according to claim 1, wherein: The first layer includes a metal, and the second layer includes a semiconductor.

3. The deep trench resistor structure according to claim 1, wherein: The first layer and the second layer and the second dielectric material are disposed in the first trench.

4. The deep trench resistor structure according to claim 3, wherein: The tunable device is disposed in the second dielectric material above the first trench. 5 . The deep trench resistor structure of claim 1 , further comprising a second trench formed in the first dielectric material.

6. The deep trench resistor structure according to claim 5, wherein: The first trench and the second trench are separated by a portion of the first dielectric material.

7. The deep trench resistor structure according to claim 6, wherein: The tunable device is disposed over the portion of the first dielectric material.

8. The deep trench resistor structure according to claim 7, wherein: The tunable device is in contact with the portion of the first dielectric material.

9. A deep trench resistor structure, comprising: a first trench and a second trench in a first dielectric material, wherein the first trench and the second trench are separated by a first portion of the first dielectric material; a first layer disposed on the first dielectric material; a second layer, disposed on the first layer; a second dielectric material disposed on the second layer; a third dielectric material surrounding and contacting the first layer, the second layer, and the second dielectric material; a first tunable device disposed in the second dielectric material and in contact with the first layer; and A first conductive feature is disposed in the third dielectric material, wherein the first conductive feature is electrically connected to the first tunable device.

10. A method for forming a deep trench resistor structure, comprising: forming at least one trench in the first dielectric material; depositing a first layer over the first dielectric material; depositing a second layer on the first layer; depositing a second dielectric material on the second layer; as well as Forming an adjustable device in contact with the second layer, the forming of the adjustable device comprising: depositing a semiconductor-containing layer in contact with the second layer; depositing a dielectric layer on the semiconductor-containing layer; and A metal-containing layer is deposited on the dielectric layer.

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