Direct dual pad for circuits
By using split lead frames and single-layer copper die attachment pads in high-power semiconductor device modules, combined with molded plastic packaging and dam bar restrictions, the problem of difficult die isolation at high voltage is solved, and high efficiency and reliability are achieved package and reduce costs.
Patent Information
- Application Number
- CN202380048988.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-03-10
- Filing Date
- 2023-12-18
- Publication Date
- 2025-02-07
AI Technical Summary
The prior art is difficult to effectively isolate the dies in high-power semiconductor device modules at high voltages, resulting in high packaging costs and insufficient reliability.
The split lead frame and single-layer copper die attachment pads are used to limit the flow of molded materials through molded materials packages and dam rods to achieve physical and electrical isolation between the dies.
Improves performance and reliability of semiconductor device modules at voltages up to about 600V, reduces packaging costs, and can operate at higher voltages such as 1700V by increasing isolation of multi-layer split lead frames and RCC layers.
Smart Images
Figure CN119404309A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS
[0002] This patent application claims the benefit of U.S. non-provisional patent application No. 18 / 181,950, filed on March 10, 2023, and entitled “Discrete Dual Pads for a Circuit,” which is incorporated herein by reference in its entirety. Technical Field
[0003] The present description relates to assembling and packaging semiconductor device modules, such as semiconductor device assemblies, semiconductor device module assemblies, etc. More particularly, the present description relates to high power semiconductor device modules designed to operate at high voltages with improved performance and reliability. Background Art
[0004] A semiconductor device assembly, such as an assembly including a power semiconductor device, may be implemented using a plurality of semiconductor dies, substrates (e.g., direct bond metal substrates, die attach pads (DAPs)), electrical interconnects, and molding compounds. Power transistors may include, for example, insulated gate bipolar transistors (IGBTs), power metal oxide semiconductor field effect transistors (MOSFETs), and the like. Electrical interconnects within a high power semiconductor device module may include, for example, bonding wires, conductive spacers, and conductive clips. Polymer molding compounds may be used as sealants to protect components of the device assembly. Such power transistor devices may be used in a variety of applications, including automotive and / or industrial applications. Summary of the invention
[0005] In some aspects, a device includes: a split lead frame having split lead frame body sections separated by isolation regions; an electronic circuit including a first device in a first die coupled to a second device in a second die, the first die and the second die being arranged side by side on an upper surface, the first die being disposed on the first section, and the second die being disposed on the second section; and an insulator contacting the upper and lower surfaces of the split lead frame.
[0006] In some aspects, the first die is made of silicon and the second die is made of silicon carbide (SiC).
[0007] In some aspects, the insulator is a molding compound disposed within the isolation region.
[0008] In some aspects, dam bars are provided in each of the two sections to block the flow of the molding compound.
[0009] In some aspects, the width of the isolation region is less than or equal to 2.0 mm.
[0010] In some aspects, the electronic circuit is configured to operate at voltages up to about 600V.
[0011] In some aspects, the electronic circuit is a two-stage amplifier.
[0012] In some aspects, the electronic circuit is a SiC based cascode circuit.
[0013] In some aspects, a device includes: a lead frame body having an upper surface and a lower surface, the lead frame body being divided into a first section and a second section separated by a gap; an electronic circuit coupled to the upper surface, the electronic circuit including a first device included in a first die, the first device coupled to a second device included in a second die, the first die coupled to a die attach pad (DAP) in the first section of the lead frame body, and the second die coupled to the DAP in the second section of the lead frame body; and an insulating layer coupled to the lower surface of the lead frame body.
[0014] In some aspects, the insulating layer is a copper layer coated with a resin.
[0015] In some aspects, the apparatus further includes a backplate coupled to the insulating layer.
[0016] In some aspects, the gap is an isolated region filled with molding compound.
[0017] In some aspects, the width of the isolation region is less than or equal to 2.0 mm.
[0018] In some aspects, the electronic circuit is an amplifier circuit configured to operate at a high voltage up to about 1700V.
[0019] In some aspects, the device also includes a Kelvin temperature sensor.
[0020] In some aspects, a method includes: forming a lead frame having a split lead frame body in which an insulator separates a first side of the split lead frame body from a second side; attaching a first semiconductor die to a die attach pad (DAP) on the first side of the split lead frame body, and attaching a second semiconductor die to the DAP on the second side of the split lead frame body; coupling the first semiconductor die to the second semiconductor die to form a two-stage amplifier circuit; and encapsulating the two-stage amplifier circuit with a molding compound to form a package around the split lead frame body.
[0021] In some aspects, the method further includes, prior to encapsulation, attaching a resin coated copper (RCC) layer to the split leadframe body.
[0022] In some aspects, the method further includes attaching a backing plate to the RCC layer.
[0023] In some aspects, the method further includes forming a dam bar attached to the lead frame body to restrict molding compound flow. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1A is a plan view (eg, a top side plan view) of a simplified block diagram representing a high power semiconductor device module according to an implementation of the present disclosure.
[0025] Figure 1B According to the specific implementation of the present disclosure Figure 1A A cross-sectional view of a simplified block diagram is shown.
[0026] Figure 2 It is a schematic diagram of a two-stage amplifier in the form of a common-source and common-gate circuit.
[0027] Figure 3A is a top side perspective view of a packaged high power semiconductor device module according to an implementation of the present disclosure.
[0028] Figure 3B According to the specific implementation of the present disclosure Figure 3A A bottom side cross-sectional view of the high-power semiconductor device module along the 3B-3B section is shown.
[0029] Figure 3C is a top side perspective view of a packaged high power semiconductor device module according to an implementation of the present disclosure.
[0030] Figure 3D According to the specific implementation of the present disclosure Figure 3C A bottom side cross-sectional view of a high-power semiconductor device module along a 3D-3D cut plane is shown.
[0031] Figure 4A is an external view of a packaged high power semiconductor device module according to a specific implementation of the present disclosure.
[0032] Figure 4B It is a specific implementation according to the present disclosure. Figure 4A The internal structure of the high-power semiconductor device module shown is a rotated and enlarged cross-sectional view along the 4B,C - 4B,C section.
[0033] Figure 4C According to the specific implementation of the present disclosure Figure 4A A rotated high-level cross-sectional view of the high-power semiconductor device module shown along the 4B,C - 4B,C section.
[0034] Figure 5Ais an external view of a packaged high power semiconductor device module according to a specific implementation of the present disclosure.
[0035] Figure 5B According to the specific implementation of the present disclosure Figure 5A The high-power semiconductor device module is shown in a rotated and enlarged cross-sectional view along the 5B,C-5B,C section.
[0036] Figure 5C According to the specific implementation of the present disclosure Figure 5A A rotated high-level cross-sectional view of the high-power semiconductor device module shown along the 5B,C-5B,C section.
[0037] Fig. 6A is an exploded view of a multi-layer split lead frame body according to a specific implementation of the present disclosure.
[0038] Figure 6B According to the specific implementation of the present disclosure Fig. 6A A perspective view of a multi-layer split lead frame body is shown.
[0039] Fig. 7A is an external view of a packaged high power semiconductor device module according to a specific implementation of the present disclosure.
[0040] Figure 7B is an external view of a packaged high power semiconductor device module according to a specific implementation of the present disclosure.
[0041] Figure 7C is a cross-sectional view along the 7C-7C section of a portion of a packaged high-power semiconductor device module according to a specific implementation of the present disclosure.
[0042] Fig. 8A yes Figure 6B A top perspective view of a multi-layer split lead frame body is shown.
[0043] Figure 8B According to the specific implementation of the present disclosure Fig. 6A and Figure 6B A cross-sectional view along section 8B-8B of a portion of a packaged high-power semiconductor device module featuring a multi-layer split lead frame body is shown.
[0044] Fig. 9 is shown for producing Figure 4A , Figure 5A or Fig. 6A Flowchart of a method for manufacturing a high-power semiconductor device module such as the module shown.
[0045] When read together with the accompanying drawings, the various aspects of the present disclosure are better understood from the following detailed description. It should be noted that, according to the conventions in the industry, various features are not necessarily drawn to scale. For the clarity of discussion, the sizes of various features can be increased or reduced arbitrarily. In the accompanying drawings, the same reference symbol can indicate the same and / or similar parts (elements, structures, etc.) in different views. The accompanying drawings generally illustrate various specific implementations discussed in the present disclosure by way of example and not limitation. The reference symbols shown in one figure may not be repeated for the same and / or similar elements in the related views. The reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for the context between the related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols when illustrating multiple instances of the element. DETAILED DESCRIPTION
[0046] The present disclosure relates to specific implementations of semiconductor device assemblies that include power transistor assemblies for use in power amplifier circuits such as, for example, cascode circuits. In some implementations, the power amplifier circuit device components are on separate semiconductor dies attached to discrete dual die attach pads. The spacing between the die attach pads allows sufficient isolation between the dies to enable operation at high voltages without relying on thick multi-layer direct bonded copper (DBC) structures. In some implementations, operation at higher voltages can be supported by thin multi-layer DAPs in which the top layers are separated. Such modifications to the die attach pad structure can reduce packaging costs.
[0047] In the assembly process of the semiconductor device module, the semiconductor die containing one or more transistor devices is first attached to the die attach pad of the lead frame. Then the contact pad or bonding pad of the semiconductor die is separately attached to the contact pad at the end of the lead of the lead frame by wire bonding. After the wire bonding operation is completed, the lead frame is placed in a mold. The mold is provided with a container for accommodating a certain amount of insulating molding compound. The molding compound is then injected into the mold to encapsulate the die attach pad and the semiconductor die.
[0048] In some applications, power transistor devices can be used to implement electronic circuits used in electric vehicles (EV) and / or hybrid electric vehicles (HEV), such as inverters or power amplifiers. However, in some semiconductor device assemblies, each device can be formed on a separate die. For example, two dies stacked or arranged in parallel can be used to implement a two-stage electronic circuit. The stacked arrangement has the advantage of greater isolation between the dies. However, the size requirements of the stacked die are higher, which incurs more cost. On the other hand, if sufficient isolation cannot be achieved between the two high-power devices, the parallel arrangement may not be feasible.
[0049] Figure 1A A top plan view of a high-power semiconductor device module 100 according to some specific implementations of the present disclosure is shown. The high-power semiconductor device module 100 includes a lead frame 102, one or more semiconductor dies 104 (two are shown, namely 104a and 104b), and a molding compound 106 that encapsulates the semiconductor dies 104 and a portion of the lead frame 102. The lead frame 102 includes a split lead frame body 108 having two sections 108a and section 108b, one or more die attach pads (DAPs) 109 (two are shown, namely 109a and 109b), and leads 110 (four are shown) that provide signal paths to and from each semiconductor die 104. The lead frame 102 can be formed from a thin sheet of metal such as copper (e.g., manufactured by cutting, stamping, etc.).
[0050] In some implementations, each of the DAPs 109 may be a multi-layer DAP of the direct bond copper (DBC) type or alternatively a multi-layer DAP of the direct plated copper (DPC) type, both of which provide an isolation substrate beneath the attached semiconductor die 104. The DBC and / or DPC type die attach pads may include three layers: a top layer and a bottom layer made of copper, and an insulating layer, such as an aluminum oxide (Al2O3) ceramic layer, between the two copper layers. Each die attach pad 109 may also serve as a heat sink to dissipate heat generated by the semiconductor die 104. However, because these multi-layer isolation substrates are quite expensive and they occupy more volume in the encapsulated package, it may be advantageous to use thinner die attach pads 109 made of a single layer of copper, while isolating the DAPs from each other using alternative techniques.
[0051] In some implementations, the first semiconductor die 104a attached to the DAP 109a can be disposed within and aligned along the plane of the lead frame body section 108a. Similarly, the second die 104b attached to the DAP 109b can be disposed within and aligned along the plane of the lead frame body section 108b such that the die 104a and the die 104b are juxtaposed.
[0052] The two lead frame body sections 108a, 108b may be separated by a gap g, which forms an isolation region to physically and electrically isolate the DAPs 109a, 109b from each semiconductor die 104a, 104b. When the molding compound 106 is added to complete the package, the molding compound 106 will fill the gap g. Such isolation allows the semiconductor device in the die 104 to operate safely and reliably at voltages suitable for high-power applications such as power amplifiers used in electric vehicles. Such operating voltages may range from hundreds of volts to thousands of volts, maintained by gaps with a width in the range of about 1.2 mm to about 1.6 mm. Smaller gaps may be sufficient to maintain smaller voltages, for example, up to about 400V to about 600V, while larger gaps may be required to maintain higher voltages above about 1500V to about 1700V. The size, area or shape of the lead frame body sections 108a, 108b may be substantially equal or different, as long as a gap g of at least 1.6 mm is maintained along the length of the lead frame body section 108 in the y direction. Likewise, the size, area or shape of the DAPs 109a, 109b may be substantially equal or different.
[0053] Figure 1B Some specific implementations of the present disclosure are shown. Figure 1A A side cross-sectional view of a high-power semiconductor device module 100 is shown. Figure 1B The cross-sectional view shown is a cross-sectional view taken along the 1B-1B cut plane parallel to the yz plane. Figure 1B The semiconductor dies 104 a , 104 b are shown attached (eg, mounted) to upper surfaces of single layer copper split leadframe sections 108 a , 108 b of the leadframe 102 . Figure 1B Also shown is a molding compound 106 surrounding and insulating both the upper and lower surfaces of the semiconductor die 104 and the die attach pads 109a, 109b, with leads 110 extending from the molded package. The use of a single layer of die attach pads 109a, 109b ensures that there is sufficient clearance between the power-on elements of the high power semiconductor device module 100 and the top and bottom outer surfaces of the molding compound 106.
[0054] Figure 2A schematic diagram of a cascode circuit 200 according to some specific implementations of the present disclosure is shown. The cascode circuit 200 is a two-stage amplifier circuit including a first transistor device 202 and a second transistor device 204 that can be configured to produce high gain and high bandwidth. The cascode circuit 200 has three terminals a, b, and c. In some specific implementations, terminal a can be coupled to a power supply, terminal b can be grounded, and a control signal can be applied to terminal c. In the cascode circuit 200, the first transistor device 202 can be coupled in parallel with the second transistor device 204 at terminal b and at point d.
[0055] In some specific implementations, the first transistor device 202 can be manufactured in ( Figure 1A The first semiconductor die 104a shown in FIG. 1 , and the second transistor device 204 may be fabricated in ( Figure 1A ) second semiconductor die 104b for attachment to ( Figure 1A 1 and 10. In some embodiments, the two semiconductor dies 104a and 104b may include different substrate materials. For example, the first transistor device 202 may be fabricated on a silicon substrate of the semiconductor die 104a, while the second transistor device 204 may be fabricated on a silicon carbide (SiC) substrate of the semiconductor die 104b. Alternatively, the cascode circuit may be a SiC-based cascode circuit such that both dies have a SiC substrate. Other semiconductor materials may be used for either or both substrates, for example, gallium (Ga), gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), etc.
[0056] Figure 3A and Figure 3B Some specific implementations of the present disclosure are shown respectively. Figure 1A and Figure 1B A perspective view and a cross-sectional view of an example 100 a of a high-power semiconductor device module 100 are shown. Figure 3A The outer package of the high power semiconductor device module 100 a encapsulated by the molding compound 106 is shown. Figure 3B The cross-sectional view shown is a cross-sectional view taken along a 3B-3B cut plane parallel to the xy plane, as viewed from the back side of the high-power semiconductor device module 100 a . Figure 3B It is illustrated that in the exemplary high power semiconductor device module 100a, the lead frame body sections 108a, 108b are bent around the keyhole-shaped cutout 300. The keyhole-shaped cutout 300 includes a gap g and a screw hole 302 that penetrates the entire package (e.g., it has an opening on each of the packages and an inner cavity between these openings), including the full thickness of the molding compound 106. Figure 3B The bottom side of the split pad arrangement is shown, in which the gap g and the screw hole 302 are both used to isolate the split lead frame body sections 108a and 108b from each other. In this example, the split lead frame body sections 108a and 108b are formed to surround the screw hole 302, while also retaining an isolation area in the gap g around the screw hole 302. The screw hole 302 can accommodate a screw for mounting the high power semiconductor device module 100. As shown in FIG. Figure 3B As indicated, the perimeter of the screw head may contact and apply pressure to the molding compound 106 to hold the high power semiconductor device module 100 in place.
[0057] Figure 3A The package shown also includes two recesses 304. The recesses 304 penetrate the upper portion of the thickness of the molding compound 106. The recesses 304 accommodate back-off pins in the mold that support each side of the split lead frame body sections 108a, 108b to hold the mold in place while the molding compound 106 is set.
[0058] Figure 3C and Figure 3D Some specific implementations of the present disclosure are shown respectively. Figure 1A and Figure 1B A perspective view and a cross-sectional view of an example 100 b of a high-power semiconductor device module 100 are shown. Figure 3C The outer package of the high power semiconductor device module 100 b encapsulated by the molding compound 106 is shown. Figure 3D The cross-sectional view shown is a cross-sectional view taken along a 3D-3D cut plane parallel to the xy plane, as seen from the back side of the high-power semiconductor device module 100 b . Figure 3C The package shown includes a single recess 304 that penetrates an upper portion of the thickness of the molding compound 106. The single recess 304 accommodates a center back-off pin to hold the split die attach pads 108a, 108b in place. Figure 3C The package shown does not include screw holes. Figure 3D A split pad arrangement structure is shown in which a gap g is used to isolate the split lead frame body sections 108a and 108b from each other. In this example, the split lead frame body sections 108a, 108b are approximately rectangular in shape.
[0059] In some implementations, the high power semiconductor device module 100 includes a notch 306 in the molding compound 106. The notch 306 can enable additional isolation between selected leads 110.
[0060] FIG. 4A to FIG. 4C The above-mentioned embodiments according to some specific implementations of the present disclosure are respectively shown. Figure 3A and Figure 3B A perspective view and two cross-sectional views of an exemplary high-power semiconductor device module 100 a including screw holes 302 are shown. Figure 4A Reappeared Figure 3A . Figure 4B yes Figure 4C Magnified view of. Figure 4B and Figure 4C The cross-sectional view shown is a cross-sectional view taken along a 4B,C - 4B,C cut plane parallel to the xy plane, as seen from the top side of the high-power semiconductor device module 100 a. Figure 4B and Figure 4C Rotate 180 degrees so that lead 110 extends upward instead of Figure 4A As shown extending downward.
[0061] Figure 4B and Figure 4C Details of a high power semiconductor device module 100a as a specific implementation of the common source and common gate circuit 200 are shown. Four leads 110 are aligned with the y-axis of the package. Leads 110a achieve a connection path to the die 104a via the split lead frame section 108a and the die attach pad 109a. DAP 109b is coupled to a dummy lead 410, which may extend slightly beyond the outer edge of the molding compound 106. Dummy leads 410 may provide structural support for the split lead frame body section 108b. Dummy leads 410 fill the space between adjacent leads, otherwise there would be empty space between these adjacent leads. Through holes 412 (three are shown) are provided for filling the molding compound 106 so that the leads 110 will interlock with the molding compound 106.
[0062] At least three of the leads 110 are configured to accept external connections. One of the leads 110 may enable a power connection to terminal a of the cascode circuit 200; another of the leads 110 may transmit a control signal to terminal c of the cascode circuit 200; another of the leads 110 may enable a connection between terminal b of the cascode circuit 200 and a Kelvin temperature sensor on the second die 104b. In some implementations, the lead coupled to terminal b is used as a sensing connector for a Kelvin temperature sensor that enables high switching speeds with low losses and high efficiency. In some implementations, the wiring pattern of such connections may be arranged so that the angle of the wire relative to the + / -y axis and therefore relative to the lead is in the range of about 12 degrees to about 106 degrees.
[0063] In a specific non-limiting example, Figure 4BThe elements of the illustrated high power semiconductor device module 100a may have dimensions as specified below. Of course, in other implementations, other dimensions may be used, and the following discussion is provided by way of example and for purposes of illustration.
[0064] In some implementations, the radius of each recess 304 is in the range of about 0.9 mm to about 1.1 mm, and the center-to-center distance d1 between the screw hole 302 and the recess 304 in the y direction is in the range of about 5.0 mm to about 6.0 mm. In some implementations, the center of the recess 304 is located at a distance of about 2.0 mm to about 3.0 mm from the center of the gap g. In some implementations, the semiconductor dies 104a, 104b are centered on their respective discrete die attach pads 109a, 109b such that there is a gap d2 between the edge of each die 104 and the nearest edge of the corresponding die attach pad 109 between about 1.5 mm and about 2.0 mm. In some implementations, the overall xyz dimensions of the molded package of the high-power semiconductor device module 100a can be in the range of about 15.0 mm x 22.0 mm x 4.0 mm to about 16.0 mm x 23.0 mm x 6.0 mm. In some implementations, the xy area dimensions of each of the split lead frame body sections 108a, 108b of the high-power semiconductor device module 100b can be about 5.0 mm x 16.0 mm to about 6.0 mm x 17.0 mm. In some implementations, the pitch of the leads 110 can be about 2.2 mm, 4.42 mm, or 5.08 mm.
[0065] FIG. 5A to FIG. 5C The above-mentioned embodiments according to the specific implementation of the present disclosure are respectively shown. Figure 3C and Figure 3D A perspective view and two cross-sectional views of an exemplary high-power semiconductor device module 100 b are shown. Figure 5A Reappeared Figure 3C . Figure 5B yes Figure 5C Magnified view of. Figure 5B and Figure 5C The cross-sectional view shown is a cross-sectional view taken along a 5B,C - 5B,C cut plane parallel to the xy plane, as seen from the top side of the high-power semiconductor device module 100 a. Figure 5B and Figure 5C Rotate 180 degrees so that lead 110 extends upward instead of Figure 5A As shown extending downward.
[0066] Figure 5B and Figure 5CDetails of a high power semiconductor device module 100b are shown as an implementation of the cascode circuit 200. In some implementations, the volume of the molding compound 106 forming the package around the high power semiconductor device module 100b can be smaller than the corresponding package of the high power semiconductor device module 100a.
[0067] Figure 5C The dam bar 500 indicated by the dashed line is shown temporarily in place. The dam bar 500 can be used during the injection molding process of forming a package around the high-power semiconductor device module 100b. The dam bar 500 can be arranged to limit or block the flow of a sealant such as a liquid epoxy molding compound (EMC) out of the mold before the molding compound 106 is cured. As described below, during the manufacturing process, the dam bar 500 can be removed, for example, by a trimming tool, so that the dam bar 500 is not present in the finished high-power semiconductor device module 100b.
[0068] exist Figure 5B and Figure 5C , the lead 110 may be substantially aligned with the y-axis of the package. The lead 110b provides a connection path to the die attach pad 109a. In some implementations, the die attach pad 109b is not coupled to the lead. Three of the leads 110 may be configured to accept external connections. For example, the first lead 110 may enable a ground connection to the terminal b of the cascode circuit 200; the second lead 110 may enable a power connection to the terminal a of the cascode circuit 200; and the third lead 110 may transmit a control signal to the terminal c of the cascode circuit 200. In some implementations, the wiring pattern of such connections may be arranged so that the angle of the wire relative to the y-axis and therefore relative to the lead 110 is in the range of about 20 degrees to about 106 degrees.
[0069] In a specific non-limiting example, Figure 5B The elements of the illustrated high power semiconductor device module 100b may have dimensions as specified below. Of course, in other implementations, other dimensions may be used, and the following discussion is provided by way of example and for purposes of illustration.
[0070] In some implementations, the radius of the recess 304 is in the range of about 1.0 mm to about 2.0 mm, and the distance from the center of the recess 304 to the edge of the package is in the range of about 5.0 mm to about 7.0 mm. In some implementations, the recess 304 is centered on the gap g. In some implementations, the semiconductor dies 104a, 104b are centered on their respective discrete die attach pads 108a, 108b such that there is a gap of about 1.5 mm to 2.0 mm between the edge of each die and the nearest edge of the corresponding die attach pad. In some implementations, the overall xyz dimensions of the molded package of the high power semiconductor device module 100b are in the range of about 15.0 mm x 175.0 mm x 4.0 mm to about 16.0 mm x 180.0 mm x 6.0 mm. In some implementations, the area size of each split lead frame body section 108a, 108b of the high power semiconductor device module 100b is in the range of about 5.0mm x 11.0mm to about 6.0mm x 12.0mm. In some implementations, the pitch of the leads 110 is in the range of about 2.0mm to about 3.0mm, and the pitch of the leads 110a is in the range of about 4.5mm to about 5.5mm.
[0071] In some implementations, such as according to examples 100a and 100b shown above, the high power semiconductor device module 100 is designed to operate at voltages up to about 400 V to about 600 V. For operating voltages exceeding about 600 V, additional isolation may be required, as will be described below.
[0072] Fig. 6A and Figure 6B 1 shows a lead frame of a high-power semiconductor device module 100c according to some specific implementations of the present disclosure. When additional isolation is achieved through the multi-layer split lead frame body 600, the high-power semiconductor device module 100c can operate at a voltage of up to about 1500V to about 1700V. In some specific implementations, the outer encapsulation package of the high-power semiconductor device module 100c is similar to Figure 3A and Figure 4A An example of a high power semiconductor device module 100 a including screw holes 302 is shown. Fig. 6A is an exploded view of a multi-layer split lead frame body 600; Figure 6BThe multi-layer split lead frame body 600 after assembly is shown. The multi-layer split lead frame body 600 includes split lead frame body sections 108a, 108b as the top layer. In addition, the multi-layer split lead frame body 600 includes a resin layer 602 and an additional copper layer 604 that together form a resin-coated copper (RCC) layer 606. In some specific implementations, the thickness of the RCC layer 606 is in the range of about 0.1 mm to about 0.2 mm. In some specific implementations, the resin layer 602 can be made of an insulator such as a polymer material, polyimide or epoxy resin with a thickness in the range of about 0.05 mm to about 0.3 mm. The split lead frame body sections 108a, 108b and the RCC layer 606 form the multi-layer split lead frame body 600. The outer dimensions of the RCC layer 606 are substantially matched with the outer dimensions of the split lead frame body sections 108a, 108b.
[0073] In some implementations, the RCC layer 606 can be attached to the split lead frame body sections 108a, 108b by an adhesive. In some implementations, the RCC layer 606 is continuous across the gap g, that is, the RCC layer is integral (not separated). In some implementations, the screw hole 302 extends through the multi-layer split lead frame body 600, so that when the package is completed, the molding compound 106 will close the screw hole 302 to achieve isolation between the two sections of the split lead frame body sections 108a, 108b.
[0074] Fig. 7A and Figure 7B Reproduced as Figure 4A and Figure 5A External views of high-power semiconductor device modules 100a and 100b are shown. Figure 7C 1 shows a cross-sectional view of high-power semiconductor device modules 100a and 100b along a 7C-7C cut plane parallel to the yz plane according to some specific implementations of the present disclosure. Specifically, Figure 7C100a and 100b are shown with a single-layer DAP, where the cut plane 7C-7C intersects the lead 110. In each of these implementations, there is a sufficient gap between the upper surface 700 of the lead frame body 108 and the upper surface of the molding compound 106 to provide space for attaching the lead 110. In some implementations, the curved lead frame portion 702 can couple the lead 110 to the lead frame body 108, which can be above or below the plane of the lead 110. The molding compound 106 surrounds the lead frame body 108 so that the molding compound 106 contacts the lower surface 704 and the upper surface 700 of the lead frame body 108. In some implementations, each of the lead frame body sections 108a, 108b can incorporate a mold locking feature 706 for securing the mold during the injection molding process.
[0075] Fig. 8A A perspective view of the assembled multilayer DAP is reproduced, as Figure 6B shown. Figure 8B FIG. 1 shows a cross-sectional view of a high-power semiconductor device module 100c along a cutting line AA′ according to a specific implementation of the present disclosure. Specifically, Figure 8B 1 represents a high power semiconductor device module 100c having three layers of DAP. In this example, Figure 7C In the above example, there is enough gap between the upper surface 800 of the multilayer DAP 600 and the upper surface of the molding compound 106 to provide space for attaching the leads 110. The molding compound 106 surrounds the multilayer DAP 600 so that the molding compound 106 contacts the lower surface 802 and the upper surface 800 of the multilayer DAP 600.
[0076] Fig. 9 is a flow chart illustrating a method 900 for manufacturing a high-power semiconductor device module 100 according to some specific implementations of the present disclosure. The operations of the method 900 may be performed in a different order, or not performed at all, depending on the specific application. It should be noted that the method 900 may not produce a complete high-power semiconductor device module 100. Therefore, it should be understood that additional processes may be provided before, during, or after the method 900, and some of these additional processes may be briefly described herein.
[0077] According to some implementations as described above, operations 902 to 908 may be performed to form high-power semiconductor device modules 100a and 100b. According to some implementations as described above, operations 902 to 912 may be performed to form high-power semiconductor device module 100c.
[0078] At 902, the method 900 includes forming a lead frame 102 with split lead frame body sections 108a, 108b. The lead frame 102 may be made of a rolled metal sheet, such as rolled copper or aluminum, wherein the lead frame 102 is formed of a rolled metal sheet such as rolled copper or aluminum. Figure 1A or Fig. 6A The rolled metal sheet is cut or stamped in a repeating pattern such as the illustrated repeating pattern of the lead frame 102. A sheet of lead frames 102 can then be separated into individual lead frames 102 by cutting or scoring. Individual die attach pads 109a, 109b are formed on the corresponding top surfaces of the lead frame body sections 108a, 108b.
[0079] At 904, the method 900 includes attaching the semiconductor die 104 to each of the die attach pads 109a, 109b on each of the split lead frame body sections 108a, 108b of the lead frame 102. In some implementations, attaching the semiconductor die 104 can be accomplished by, for example, mounting or bonding the die to the die attach pads 109a using a bonding adhesive such as a conductive bonding adhesive. In some implementations, the semiconductor die 104 can be coupled to the die attach pads 109 using, for example, a solder reflow process, a sintering process, or other suitable process.
[0080] At 906, method 900 includes coupling semiconductor die 104a to semiconductor die 104b to form a two-stage amplifier circuit such as cascode circuit 200. Method 900 includes forming corresponding wire bonds to achieve electrical connections from corresponding signal terminals (signal pins, etc.) or leads 110 of lead frame 102 to device terminals of transistors and diodes formed on corresponding semiconductor die 104. Figure 2 The circuit design shown and described above can realize the connection of the cascode circuit 200.
[0081] At 908, the method 900 includes encapsulating the two-stage amplifier circuit with the molding compound 106, for example, using an injection molding process. In some implementations, such as the high-power semiconductor device module 100b, the dam bar 500 can be configured to restrict or block the flow of liquid molding compound out of the mold before the molding compound 106 is cured. After the encapsulation operation is completed, the dam bar 500 can be removed, for example, by cutting using a trimming tool.
[0082] At 910, method 900 includes attaching a resin coated copper (RCC) layer 602 to the split lead frame body sections 108a, 108b of the lead frame 102 using, for example, an epoxy adhesive. In some examples, the adhesive can be a thermally and electrically conductive epoxy, such as an epoxy filled with silver. In other implementations, the adhesive can be a thermally conductive but electrically insulating adhesive material, such as a thermal interface material. In some implementations, such as the example shown, the RCC layer 602 includes a screw hole 302. In some implementations, the RCC layer 602 is not separated. That is, the RCC layer 602 is an integral continuous layer spanning the gap g.
[0083] At 912, method 900 includes attaching back plate 604 to RCC layer 602 using, for example, an epoxy adhesive. In some examples, the adhesive can be a thermally and electrically conductive epoxy, such as an epoxy filled with silver. In other implementations, the adhesive can be a thermally conductive but electrically insulating adhesive material, such as a thermal interface material. In some implementations, such as the example shown, back plate 604 includes screw holes 302. In some implementations, back plate 604 is not separated. That is, back plate 604 is a one-piece continuous plate spanning gap g.
[0084] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, an element that is shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the drawings.
[0085] As used in this specification, unless the context clearly indicates a particular case, the singular form may include the plural form. In addition to the orientations depicted in the drawings, spatial relative terms (e.g., above, above, above, below, below, below, below, at the top, at the bottom, etc.) are intended to cover different orientations of the device in use or operation. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent may include lateral adjacent or horizontal adjacent.
[0086] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor device processing technologies associated with semiconductor substrates including, but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.
[0087] Although certain features of the described implementations have been illustrated as described herein, those skilled in the art will now expect many modifications, alternatives, variations, and equivalents. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.
Claims
1. A device, comprising: A split lead frame (102), the split lead frame having split lead frame body sections (108a, 108b) separated by an isolation region (g); a die attach pad (DAP) (109) on an upper surface of each of the split lead frame body sections (108a, 108b); An electronic circuit comprising a first device in a first tube die (104a), the first device being coupled to a second device in a second tube die (104b), the first tube die (104a) and the second tube die (104b) being arranged in parallel on the upper surface (700), the first tube die (104a) being arranged on the first section (108a), and the second tube die (104b) being arranged on the second section (108b); and An insulator is in contact with the upper surface (700) and the lower surface (704) of the split lead frame (102).
2. The device according to claim 1, wherein The first die (104a) is made of silicon, and the second die (104b) is made of silicon carbide (SiC).
3. The device according to claim 1, wherein: The insulator is a molding compound (106) disposed in the isolation region (g).
4. The apparatus according to claim 3, further comprising a dam bar (500) disposed in each of the two split lead frame body sections (108a, 108b) to block the flow of the molding compound (106).
5. The device according to claim 1, wherein: The width of the isolation region (g) is less than or equal to 2.0 mm.
6. The device according to claim 1, wherein: The electronic circuit is configured to operate at voltages up to about 600 V.
7. The device according to claim 1, wherein: The electronic circuit is a two-stage amplifier.
8. The device according to claim 1, wherein: The electronic circuit is a SiC-based cascode circuit (200).
9. The device according to claim 1, wherein: The first section (108a) of the lead frame body and the second section (108b) of the lead frame body define a single DAP (109).
10. A device, comprising: A lead frame body (108) having an upper surface (700) and a lower surface (704), the lead frame body (108) being divided into a first section (108a) and a second section (108b) separated by a gap (g); an electronic circuit coupled to the upper surface (700), the electronic circuit comprising a first device included in a first die (104a), the first device coupled to a second device included in a second die (104b), the first die coupled to a die attach pad (DAP) (109a) in the first section (108a) of the lead frame body, and the second die (104b) coupled to a DAP (109b) in the second section (108b) of the lead frame body; and An insulating layer (602) is coupled to the lower surface of the lead frame body (108).
11. The device according to claim 10, wherein: The insulating layer (602) is a copper layer coated with resin.
12. The device of claim 10, further comprising a backplate (604) coupled to the insulating layer.
13. The apparatus according to claim 10, wherein: The gap (g) is an isolation area filled with a molding compound (106).
14. The device according to claim 13, wherein: The width of the isolation region (g) is less than or equal to 2.0 mm.
15. The apparatus according to claim 10, wherein: The electronic circuit is an amplifier circuit configured to operate at high voltages up to about 1700V.
16. The device of claim 10, further comprising a Kelvin temperature sensor.
17. A method comprising: forming a lead frame (102) having a split lead frame body in which an insulator separates a first side (108a) of the split lead frame body from a second side (108b) of the split lead frame body; attaching a first semiconductor die (104a) to the first side (108a) of the split lead frame body, and attaching a second semiconductor die (104b) to the second side (108b) of the split lead frame body; coupling the first semiconductor die (104a) and the second semiconductor die (104b) to form a two-stage amplifier circuit; as well as The two-stage amplifier circuit is encapsulated with a molding compound (106) to form a package surrounding the split lead frame body (108).
18. The method of claim 17, further comprising attaching a resin coated copper (RCC) layer (602) to the leadframe body (108) prior to encapsulation.
19. The method of claim 18, further comprising attaching a backing plate (604) to the RCC layer (602).
20. The method of claim 17, further comprising forming a dam bar (500) attached to the lead frame (102) to restrict flow of the molding compound (106) during encapsulation.