Gate drive circuit, power conversion device, and method for controlling gate drive circuit

Abstract

A gate drive circuit is provided with modulation circuits 2 and 3, an ON-side rectifier circuit 4, and an OFF-side rectifier circuit 5. The modulation circuits (2, 3) change the frequencies of the first modulation signal (vTr1) and the second modulation signal (vTr2) in accordance with the ON command width and the OFF command width of the gate command. The first modulation signal vTr1 and the second modulation signal vTr2 are configured such that the ON command width is the same as the period of one positive pulse of the first modulation signal vTr1 and the ON command width is the same as the period of one negative pulse of the first modulation signal vTr1, and the positive pulse and the negative pulse of the first modulation signal vTr1 are alternately output every time the ON command is received. When a pulse transformer is driven by a DC / AC modulation circuit, the limitation of the minimum ON pulse width is relaxed while magnetic bias is suppressed.

Description

Technical Field

[0001] The invention relates to a modulation method for a gate drive circuit of a power converter that is driven in series and simultaneously. Background Art

[0002] In a circuit that drives semiconductor devices in series, a pulse transformer is used for gate driving in order to ensure simultaneous switching.

[0003] However, when a DC / AC modulation circuit is used to drive a pulse transformer, in order to cope with bias magnetization, the time periods of the output positive pulse and negative pulse need to be equalized.

[0004] Fig.17 This is the operating waveform when the minimum on-pulse width is limited due to the influence of hardware such as the driver IC in the drive of the DC / AC modulation circuit. Since the positive and negative are limited, the minimum on-pulse width is twice the time. For example, when the minimum pulse width is set to 100ns, the modulation circuit cannot output pulses below 200ns, which limits the command value.

[0005] This results in an increase in the error between the gate control command and the actual switching action of the semiconductor device, that is, the output voltage accuracy of the inverter deteriorates.

[0006] In view of the above circumstances, it is a technical problem to provide a gate drive circuit that relaxes the restriction on the minimum on-pulse width while suppressing the bias magnetization when driving a pulse transformer by a DC / AC modulation circuit.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2006-271041 Summary of the invention

[0010] The present invention is developed in view of the above-mentioned existing problems, and one of its modes is a gate drive circuit, characterized in that the gate drive circuit comprises: a modulation circuit, which outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of a gate control instruction; an on-side rectifier circuit, which comprises: a first pulse transformer, which has an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit, which rectifies the output of the on-side secondary winding; and a second diode circuit, which rectifies the output of the on-side tertiary winding; and an off-side rectifier circuit, which comprises: a second pulse transformer, which has an off-side primary winding to which the second modulation signal is applied, and an off-side primary winding for transforming and outputting a voltage applied to the off-side primary winding. The voltage of the disconnected side secondary winding and the disconnected side tertiary winding is transformed and output; the third diode circuit rectifies the output of the disconnected side secondary winding; and the fourth diode circuit rectifies the output of the disconnected side tertiary winding, the gate drive circuit controls the semiconductor element as the driving object according to the output of the first diode circuit to the fourth diode circuit, wherein the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the on-command width the same as the time period of a positive pulse of the first modulation signal, and makes the on-command width the same as the time period of a negative pulse of the first modulation signal, and whenever the on-command is reached, the positive pulse and the negative pulse of the first modulation signal are output alternately.

[0011] In addition, as another embodiment, there is a gate drive circuit, characterized in that the gate drive circuit comprises: a modulation circuit, which outputs a first modulation signal and a second modulation signal based on a turn-on instruction and a turn-off instruction of a gate control instruction; a turn-on side rectifier circuit, which comprises: a first pulse transformer, which has a turn-on side primary winding to which the first modulation signal is applied, and a turn-on side secondary winding and a turn-on side tertiary winding for transforming and outputting a voltage applied to the turn-on side primary winding; a first diode circuit, which rectifies the output of the turn-on side secondary winding; and a second diode circuit, which rectifies the output of the turn-on side tertiary winding; and a turn-off side rectifier circuit, which comprises: a second pulse transformer, which has a turn-off side primary winding to which the second modulation signal is applied, and a turn-off side primary winding for transforming and outputting a voltage applied to the turn-off side primary winding. and output of the disconnected side secondary winding and the disconnected side tertiary winding; a third diode circuit, which rectifies the output of the disconnected side secondary winding; and a fourth diode circuit, which rectifies the output of the disconnected side tertiary winding, the gate drive circuit controls the semiconductor element as the driving object according to the output of the first diode circuit to the fourth diode circuit, wherein the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the off-command width the same as the time period of a positive pulse of the second modulation signal, and makes the off-command width the same as the time period of a negative pulse of the second modulation signal, and whenever the off-command is reached, the positive pulse and the negative pulse of the second modulation signal are output alternately.

[0012] In addition, as one method, it is characterized in that the modulation circuit comprises: a rising edge detection circuit, which detects the rising of the gating instruction; a latch circuit, which latches at the timing of detecting the rising edge of the gating instruction, and releases the latch at the timing when the rising edge of the gating instruction is detected again in the latched state; a first AND circuit, which outputs the logical AND of the gating instruction and the output of the latch circuit; a NOT circuit, which inverts the output of the latch circuit; a second AND circuit, which outputs the logical AND of the gating instruction and the output of the NOT circuit; a driver IC, which controls the DC / AC modulation circuit based on the output of the first AND circuit and the output of the second AND circuit; and the DC / AC modulation circuit outputs the first modulation signal based on the control of the driver IC.

[0013] In addition, as another embodiment, there is a gate drive circuit, characterized in that the gate drive circuit comprises: a modulation circuit, which outputs a first modulation signal and a second modulation signal based on a connection instruction and a disconnection instruction of a gate control instruction; a connection-side rectifier circuit, which comprises: a first pulse transformer, which has a connection-side primary winding to which the first modulation signal is applied, and a connection-side secondary winding and a connection-side tertiary winding for transforming and outputting a voltage applied to the connection-side primary winding; a first diode circuit, which rectifies the output of the connection-side secondary winding; and a second diode circuit, which rectifies the output of the connection-side tertiary winding; and a disconnection-side rectifier circuit, which comprises: a second pulse transformer, which has a disconnection-side primary winding to which the second modulation signal is applied, and a disconnection-side primary winding for transforming and outputting a voltage applied to the disconnection-side primary winding. side secondary winding and disconnected side tertiary winding; a third diode circuit, rectifying the output of the disconnected side secondary winding; and a fourth diode circuit, rectifying the output of the disconnected side tertiary winding, the gate drive circuit controls the semiconductor element as the driving object according to the output of the first diode circuit to the fourth diode circuit, wherein the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the first modulation signal during the on-command period of the gating instruction, reverses the polarity of the output of the first modulation signal at the start of each cycle of the gating instruction, and reverses the polarity of the first modulation signal when the output period of the first modulation signal has passed a predetermined time.

[0014] In addition, as another embodiment, there is a gate drive circuit, characterized in that the gate drive circuit comprises: a modulation circuit, which outputs a first modulation signal and a second modulation signal based on a connection instruction and a disconnection instruction of a gate control instruction; a connection-side rectifier circuit, which comprises: a first pulse transformer, which has a connection-side primary winding to which the first modulation signal is applied, and a connection-side secondary winding and a connection-side tertiary winding for transforming and outputting a voltage applied to the connection-side primary winding; a first diode circuit, which rectifies the output of the connection-side secondary winding; and a second diode circuit, which rectifies the output of the connection-side tertiary winding; and a disconnection-side rectifier circuit, which comprises: a second pulse transformer, which has a disconnection-side primary winding to which the second modulation signal is applied, and a disconnection-side primary winding for transforming and outputting a voltage applied to the disconnection-side primary winding. side secondary winding and disconnected side tertiary winding; a third diode circuit, rectifying the output of the disconnected side secondary winding; and a fourth diode circuit, rectifying the output of the disconnected side tertiary winding, the gate drive circuit controls the semiconductor element as the driving object according to the output of the first diode circuit to the fourth diode circuit, wherein the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the second modulation signal during the off-command period of the gating instruction, reverses the polarity of the output of the second modulation signal at the start of each cycle of the gating instruction, and reverses the polarity of the second modulation signal when the output period of the second modulation signal has passed a predetermined time.

[0015] In addition, as one embodiment, it is characterized by comprising: an inversion permission signal generating unit, which generates an inversion permission signal that switches between "1" and "0" at the falling edge of the gating instruction; a gating signal generating unit, which generates a gating signal GATE1 and a gating signal GATE2, wherein the gating signal GATE1 outputs "1" when the gating instruction is turned on and a predetermined time has passed since the gating instruction output is turned on, and is "0" otherwise; and the gating signal GATE2 outputs "1" when the gating instruction is turned on and a predetermined time has passed since the gating instruction output is turned on, and is "0" otherwise; and a polarity selector unit, which, when the inversion permission signal is "0", makes the positive output gating signal GATE_P "1" when the gating signal GATE1 is "1", and makes the positive output gating signal GATE_P "1" when the gating signal GATE2 is "1". When the inversion permission signal is "1", the negative output gating signal GATE_N is "1", and otherwise, the positive output gating signal GATE_P and the negative output gating signal GATE_N are "0". When the inversion permission signal is "1", the negative output gating signal GATE_N is "1" when the gating signal GATE1 is "1", and the positive output gating signal GATE_P is "1" when the gating signal GATE2 is "1", and otherwise, the positive output gating signal GATE_P and the negative output gating signal GATE_N are "0"; a driver IC controls a DC / AC modulation circuit based on the positive output gating signal GATE_P and the negative output gating signal GATE_N; and the DC / AC modulation circuit outputs the first modulation signal based on the control of the driver IC.

[0016] In addition, as one mode, it is characterized in that the DC / AC modulation circuit is a modulation signal generating circuit, and the modulation circuit comprises: a synchronization circuit, which synchronizes the gating instruction with the clock signal; a rising edge detection unit, which detects the rising edge of the output of the synchronization circuit; a falling edge detection unit, which detects the falling edge of the output of the synchronization circuit; an off-pulse width measurement unit, which starts counting when the falling edge of the output of the synchronization circuit is detected, stops counting when the rising edge of the output of the synchronization circuit is detected, and adds the count value each time the clock signal is input; and a 1-bit shift circuit on the off side, which makes the input of the off-pulse width measurement unit The output becomes 1 / 2; the disconnected side latch circuit latches the output of the disconnected side 1-bit shift circuit at the timing of the rising edge of the output of the synchronization circuit; the first down-counter inputs the output of the disconnected side latch circuit and the clock signal, and subtracts the count value every time the clock signal is input; the second down-counter inputs the output of the disconnected side latch circuit, the output of the first down-counter and the clock signal, and subtracts the count value every time the clock signal is input, wherein the modulation signal generating circuit outputs the second modulation signal until the counters of the first down-counter and the second down-counter become zero.

[0017] In addition, as one embodiment, it is characterized in that the DC / AC modulation circuit comprises: a capacitor; a full-bridge circuit for generating a connection signal, having a first and second semiconductor elements on the connection side connected in series between the two ends of the capacitor and a third and fourth semiconductor elements on the connection side connected in series between the two ends of the capacitor; and a full-bridge circuit for generating a disconnection signal, having a first and second semiconductor elements on the disconnection side connected in series between the two ends of the capacitor and a third and fourth semiconductor elements on the disconnection side connected in series between the two ends of the capacitor, wherein the connection side primary winding of the first pulse transformer is connected between the connection point of the first and second semiconductor elements on the connection side and the connection point of the third and fourth semiconductor elements on the connection side, and the disconnection side primary winding of the second pulse transformer is connected between the connection point of the first and second semiconductor elements on the disconnection side and the connection point of the third and fourth semiconductor elements on the disconnection side.

[0018] In addition, as one mode, it is characterized in that the modulation circuit comprises: a synchronization circuit, which synchronizes the gating instruction with the clock signal; a rising edge detection unit, which detects the rising edge of the output of the synchronization circuit; a falling edge detection unit, which detects the falling edge of the output of the synchronization circuit; an off-pulse width measurement unit, which starts counting when the falling edge of the output of the synchronization circuit is detected, stops counting when the rising edge of the output of the synchronization circuit is detected, and adds the count value each time the clock signal is input; a 1-bit shift circuit on the off side, which changes the output of the off-pulse width measurement unit to 1 / 2; and a latch circuit on the off side, which latches the output of the synchronization circuit at the off-pulse width measurement unit. The output of the 1-bit shift circuit on the disconnected side is latched at the timing of the rising edge of the output of the circuit; the first down-counter inputs the output of the latch circuit on the disconnected side and the clock signal, subtracts the count value each time the clock signal is input, and outputs the gating instructions of the first and fourth semiconductor elements on the disconnected side until the count value becomes 0; the second down-counter inputs the output of the latch circuit on the disconnected side, the output of the first down-counter and the clock signal, subtracts the count value each time the clock signal is input, and outputs the gating instructions of the second and third semiconductor elements on the disconnected side until the count value becomes 0.

[0019] In addition, as one embodiment, it is characterized in that the off-pulse width measuring unit has an n-stage (n: an integer greater than or equal to 1) structure, and in the first stage, it has: a first on-side D flip-flop circuit, the clock signal is input to the D-FF terminal, the output of the / Q terminal of the first on-side D flip-flop circuit is input to the D terminal, and the output of the Q terminal is a 1-bit signal; in the second stage, it has: a second on-side exclusive OR (XOR) circuit, the output of the Q terminal of the first on-side D flip-flop circuit and the output of the Q terminal of the second on-side D flip-flop circuit are input; and the second on-side D flip-flop circuit, the clock signal is input to the D-FF terminal, the output of the second on-side exclusive OR circuit is input to the D terminal, and the output of the Q terminal is a 2-bit signal; in the third stage, it has: a third on-side AND circuit, the output of the Q terminal of the first on-side D flip-flop circuit and the output of the second on-side the output of the Q terminal of the side D flip-flop circuit; the 3rd on-side XOR circuit, which inputs the output of the 3rd on-side AND circuit and the output of the Q terminal of the 3rd on-side D flip-flop circuit; and the 3rd on-side D flip-flop circuit, which inputs the clock signal to the D-FF terminal, inputs the output of the 3rd on-side XOR circuit to the D terminal, and the output of the Q terminal is a 3-bit signal. In the 4th to nth stages, there are: the kth on-side AND circuit, which inputs a k (k: an integer from 4 to n)-1 bit signal and a (k-2)-bit·(k-3)-bit·…2-bit·1-bit signal; the kth on-side XOR circuit, which inputs the output of the kth on-side AND circuit and the output of the Q terminal of the kth on-side D flip-flop circuit; and the kth on-side D flip-flop circuit, which inputs the clock signal to the D-FF terminal, inputs the output of the kth on-side XOR circuit to the D terminal, and the output of the Q terminal is a k-bit signal.

[0020] In addition, as one embodiment, it is characterized in that the first down counter and the second down counter are n (n: an integer greater than 1) stage structures, and in the first stage, there are: the first disconnected side D flip-flop circuit, the clock signal is input to the D-FF terminal, the output of the / Q terminal of the first disconnected side D flip-flop circuit is input to the D terminal, and the output of the Q terminal is a 1-bit signal; in the second stage, there are: the second disconnected side XOR circuit, the output of the / Q terminal of the first disconnected side D flip-flop circuit and the output of the / Q terminal of the second disconnected side D flip-flop circuit are input; and the second disconnected side D flip-flop circuit, the clock signal is input to the D-FF terminal, the output of the second disconnected side XOR circuit is input to the D terminal, and the output of the Q terminal is a 2-bit signal; in the third stage, there are: the third disconnected side AND circuit, the output of the / Q terminal of the first disconnected side D flip-flop circuit and the output of the / Q terminal of the second disconnected side D flip-flop circuit are input. The output of the / Q terminal of the trigger circuit; the 3rd disconnected side XOR circuit, which inputs the output of the 3rd disconnected side AND circuit and the output of the / Q terminal of the 3rd disconnected side D trigger circuit; and the 3rd disconnected side D trigger circuit, which inputs the clock signal to the D-FF terminal, inputs the output of the 3rd disconnected side XOR circuit to the D terminal, and the output of the Q terminal is a 3-bit signal. In the 4th to nth stages, there are: the kth disconnected side AND circuit, which inputs a / k (k: an integer from 4 to n)-1 bit signal and a / (k-2) bit· / (k-3) bit... / 2 bit· / 1 bit signal; the kth disconnected side XOR circuit, which inputs the output of the kth disconnected side AND circuit and the output of the / Q terminal of the kth disconnected side D trigger circuit; and the kth disconnected side D trigger circuit, which inputs the clock signal to the D-FF terminal, inputs the output of the kth disconnected side XOR circuit to the D terminal, and the output of the Q terminal is a k-bit signal.

[0021] According to the present invention, it is possible to provide a gate drive circuit that suppresses bias magnetization and relaxes the restriction on the minimum on-pulse width when a pulse transformer is driven by a DC / AC modulation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a circuit diagram showing a gate drive circuit according to the first and second embodiments.

[0023] Figure 2 A timing diagram showing waveforms of the gate drive circuit.

[0024] Figure 3 This is a block diagram showing the modulation circuit 3 according to the first and second embodiments.

[0025] Figure 4 It is a timing chart showing each waveform of the modulation circuit 3 in the first and second embodiments.

[0026] Figure 5This is a diagram showing an OFF pulse width measuring unit (n-stage up counter).

[0027] Figure 6 is a diagram showing an n-stage down counter.

[0028] Figure 7 This is a diagram showing another example of the modulation circuits 2 and 3 according to the first and second embodiments.

[0029] Figure 8 1 is a block diagram showing a control unit of the modulation circuit 3 according to the first and second embodiments.

[0030] Fig. 9 1 is a timing chart showing waveforms of the control unit of the modulation circuit 3 according to the first and second embodiments.

[0031] Fig.10 A diagram showing a conventional modulation signal and a modulation signal according to Embodiment 1.

[0032] Fig.11 1 is a block diagram showing a control unit of the modulation circuit 2 according to the first embodiment.

[0033] Fig.12 1 is a timing chart showing waveforms of the control unit of the modulation circuit 2 according to the first embodiment.

[0034] Fig.13 To show Figure 2 , Fig.12 Figure 2. Output waveform and characteristics of the modulation circuit.

[0035] Fig.14 1 is a block diagram showing a control unit of a modulation circuit 2 according to a second embodiment.

[0036] Fig.15 3 is a timing chart showing waveforms of the modulation circuit 2 according to the second embodiment.

[0037] Fig.16 This is a timing chart showing another example of each waveform of the modulation circuit 2 according to the second embodiment.

[0038] Fig.17 FIG. 4 is a timing diagram showing existing gating instructions and modulation signals. DETAILED DESCRIPTION

[0039] The following is based on Figure 1 to Figure 16 Embodiments 1 and 2 of the gate drive circuit of the present invention will be described in detail. [Implementation Method 1]

[0040] In the first embodiment, by measuring the gating command and changing the driving frequency of the pulse transformer according to its pulse width, the time resolution of the output pulse (pulse width of the gating command) of the device is improved without increasing the switching loss of the modulation circuit.

[0041] Figure 1 A circuit diagram of a gate drive circuit according to the first embodiment is shown. Figure 2 A timing diagram showing various waveforms of the gate drive circuit is shown. Figure 3 shows a block diagram of the modulation circuit, Figure 4 A timing diagram showing the waveforms of the modulation circuit.

[0042] First of all, Figure 1 The gate drive circuit is described below. Figure 1 As shown, the gate driving circuit of the present embodiment 1 includes modulation circuits 2 and 3, an on-side rectifying circuit 4, an off-side rectifying circuit 5, a demodulation circuit 6 and a gate circuit 7, and the gate driving circuit controls a semiconductor element 8 as a driven object.

[0043] The on command of the gating control command is output to the modulation circuit 2. In addition, the off command of the gating control command is output to the modulation circuit 3. Figure 1 Although the modulation circuit 2 to which the on command is inputted and the modulation circuit 3 to which the off command is inputted are shown, the on command and the off command may be inputted to one modulation circuit.

[0044] The primary winding on the connection side of the first pulse transformer Tr1 of the connection side rectifier circuit 4 is connected to the modulation circuit 2. The first pulse transformer Tr1 has a primary winding on the connection side, a secondary winding on the connection side that transforms and outputs the voltage applied to the primary winding on the connection side, and a tertiary winding on the connection side. The first diode circuit db1 is connected to the secondary winding on the connection side of the first pulse transformer Tr1, and the second diode circuit db2 is connected to the tertiary winding on the connection side of the first pulse transformer Tr1.

[0045] The disconnected side primary winding of the second pulse transformer Tr2 of the disconnected side rectifier circuit 5 is connected to the modulation circuit 3. The second pulse transformer Tr2 has a disconnected side primary winding, a disconnected side secondary winding that transforms and outputs the voltage applied to the disconnected side primary winding, and a disconnected side tertiary winding. The third diode circuit db3 is connected to the disconnected side secondary winding of the second pulse transformer Tr2, and the fourth diode circuit db4 is connected to the disconnected side tertiary winding of the second pulse transformer Tr2. The first to fourth diode circuits db1 to db4 are, for example, full-bridge circuits.

[0046] Next, the demodulation circuit 6 is described. The anode of the first diode D1 is connected to one terminal of the first diode circuit db1. The anode of the second diode D2 is connected to one terminal of the second diode circuit db2. The anode of the third diode D3 is connected to one terminal of the third diode circuit db3. The anode of the fourth diode D4 is connected to one terminal of the fourth diode circuit db4.

[0047] The first and second capacitors C1 and C2 are connected in series between the cathodes of the first and third diodes D1 and D3 and the other terminals of the second and fourth diode circuits db2 and db4. The other terminals of the first and third diode circuits db1 and db3 are connected to the connection point of the first and second capacitors C1 and C2. In addition, the cathodes of the second diode D2 and the fourth diode D4 are connected to the connection point of the first and second capacitors C1 and C2.

[0048] One end of the first resistor R1 is connected to the anode of the first diode D1 , and the other end of the first resistor R1 is connected to the second terminal (drain terminal) of the second semiconductor element Q2 , the first terminal (gate terminal) of the third semiconductor element Q3 , and the first terminal (gate terminal) of the fourth semiconductor element Q4 .

[0049] One end of the fourth resistor R4 and the first terminal (gate terminal) of the first semiconductor element Q1 are connected to the anode of the second diode D2. The other end of the fourth resistor R4 is connected to the other terminals of the second and fourth diode circuits db2 and db4.

[0050] One end of the second resistor R2 is connected to the anode of the fourth diode D4. The other end of the second resistor R2 is connected to the second terminal (drain terminal) of the first semiconductor element Q1 and one end of the third resistor R3. The third terminal (source terminal) of the first semiconductor element Q1 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0051] The other end of the third resistor R3 is connected to one end of the fifth resistor R5 and the first terminal (gate terminal) of the second semiconductor element Q2. The other end of the fifth resistor R5 is connected to the other terminal of the second and fourth diode circuits db2 and db4. The third terminal (source terminal) of the second semiconductor element Q2 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0052] Next, the gate circuit 7 is described. The first terminal (gate terminal) of the third semiconductor element Q3 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the third semiconductor element Q3 is connected to the cathode of the first diode D1. The third terminal (source terminal) of the third semiconductor element Q3 is connected to one end of the on-side resistor Ron.

[0053] The first terminal (gate terminal) of the fourth semiconductor element Q4 is connected to the other end of the first resistor R1 and the second terminal (drain terminal) of the second semiconductor element Q2. The second terminal (drain terminal) of the fourth semiconductor element Q4 is connected to one end of the off-side resistor Roff. The third terminal (source terminal) of the fourth semiconductor element Q4 is connected to the other terminal of the second and fourth diode circuits db2 and db4.

[0054] The other ends of the ON-side resistor Ron and the OFF-side resistor Roff are connected to the first terminal (gate terminal) of the driven semiconductor element 8. The third terminal (source terminal) of the driven semiconductor element 8 is connected to the cathodes of the second and fourth diodes D2 and D4.

[0055] Here, the first modulation signal (voltage) applied to the primary winding on the ON side of the first pulse transformer Tr1 is set to vTr1, and the second modulation signal (voltage) applied to the primary winding on the OFF side of the second pulse transformer Tr2 is set to vTr2. In addition, the voltage of the first capacitor C1 is set to Vg+, and the voltage of the second capacitor C2 is set to Vg-. Furthermore, the gate voltage (gate-source voltage) of the semiconductor element 8 as the driving object is set to Vgs.

[0056] As in Patent Document 1, Figure 1 The circuit drives the first and second pulse transformers Tr1 and Tr2 by modulating the on-signal and off-signal at the frequency of driving the first and second pulse transformers Tr1 and Tr2, and transmits the on-off instruction to the gate circuit 7 by inputting a signal to the demodulation circuit 6 while transmitting power. At this time, the pulse width input as the gate control instruction is measured by a counter, and the second pulse transformer Tr2 is driven at a frequency with the width as 1 cycle, and the first pulse transformer Tr1 is driven at a frequency with the width as 1 / 2 cycle, thereby modulating the first and second pulse transformers Tr1 and Tr2 at a frequency suitable for the pulse width of the gate control instruction, so that high resolution can be achieved.

[0057] Figure 1 The circuit is characterized in that it includes a first pulse transformer Tr1 for generating a gated on command and a second pulse transformer Tr2 for generating a gated off command. When an on command is to be sent, a voltage is applied to the first pulse transformer Tr1, and when an off command is to be sent, a voltage is applied to the second pulse transformer Tr2.

[0058] By providing a tertiary winding for the first and second pulse transformers Tr1 and Tr2, a negative bias can be applied to the gate voltage Vgs. Vg+ is the voltage after rectification of the voltage of the secondary winding, and Vg- is the voltage after rectification of the voltage of the tertiary winding. The magnitude of the voltages Vg+ and Vg- can be adjusted by the turns ratio of the first and second pulse transformers Tr1 and Tr2 and the voltages (first and second modulation signals) vTr1 and vTr2 applied to the first and second pulse transformers Tr1 and Tr2.

[0059] Assume that the outputs of the third and fourth semiconductor elements Q3 and Q4 constituting the push-pull circuit are connected via resistors to omit diodes by dividing the gate resistance values ​​between the on side and the off side. The output of the push-pull circuit may be connected without a resistor.

[0060] First, the operation at the time of connection is outlined. Figure 2 The working timing diagram is shown. Figure 2 In the timing diagram of , for the sake of simplicity, it is assumed that the gate voltage thresholds of the first to fourth semiconductor elements Q1, Q2, Q3, and Q4 are ignored. Figure 2 As shown, when the gate control command is high, the voltage of the first modulation signal vTr1 is applied to the first pulse transformer Tr1, and the first and second capacitors C1 and C2 are charged via the first and second diode circuits db1 and db2.

[0061] At this time, a voltage is applied between the gate and source of the first semiconductor element Q1, the first semiconductor element Q1 is turned on, and the second semiconductor element Q2 is turned off. Since the second semiconductor element Q2 is turned off, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 are charged via the first resistor R1. As a result, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the first capacitor C1, the third semiconductor element Q3 is turned on, and the gate voltage Vgs rises to the charging voltage vg+ of the first capacitor C1.

[0062] Next, we will outline the disconnection behavior. Figure 2 As shown, when the gate control command is low, the voltage of the second modulation signal vTr2 is applied to the second pulse transformer Tr2, and the first and second capacitors C1 and C2 are charged via the third and fourth diode circuits db3 and db4.

[0063] At this time, the gate-source of the second semiconductor element Q2 is charged via the second resistor R2, so the second semiconductor element Q2 is turned on. Then, the gate voltages of the third and fourth semiconductor elements Q3 and Q4 become the same potential as the second capacitor C2, so the fourth semiconductor element Q4 is turned on, and the gate voltage Vgs decreases to the charging voltage -vg- of the second capacitor C2. By setting the above action as one cycle, the on-off action of the semiconductor element 8 as the driving object can be controlled.

[0064] Next, a method for generating the second modulation signal vTr2 according to the first embodiment is described. The second modulation signal vTr2 can be generated by Figure 3 The modulation circuit 3 shown in the figure is implemented. Figure 4 A timing chart showing waveforms of the modulation circuit 3 is shown.

[0065] The gating command (transmitter output) and the clock signal are input to the synchronization circuit 9, so that the gating command (oscillator output) is synchronized with the clock signal. The rising edge detection unit 10 detects the rising edge of the synchronization circuit 9. The falling edge detection unit 11 detects the falling edge of the synchronization circuit 9.

[0066] When the falling edge of the synchronization circuit 9 is detected, the pulse width measuring unit (up counter) 12 starts counting, and when the rising edge is detected, the counting is stopped, and the count value is added every time the clock signal is input.

[0067] At this time, it is assumed that the rising edge and the falling edge are synchronized with the clock signal by the operation of the synchronization circuit 9. Based on this, the OFF pulse width can be measured.

[0068] The output (count value) of the OFF pulse width measuring unit 12 is halved by the OFF-side 1-bit shift circuit 13 .

[0069] The OFF-side latch circuit 14 latches the output of the OFF-side 1-bit shift circuit 13 at the timing of detecting the rising edge.

[0070] The output of the OFF-side latch circuit 14 and the clock signal are input to the modulation signal generation counter (first down counter) 15, and the count value is subtracted every time the clock signal is input. The output of the OFF-side latch circuit 14, the output of the first down counter 15, and the clock signal are input to the modulation signal generation counter (second down counter) 16, and the count value is subtracted every time the clock signal is input.

[0071] In the modulation signal generating circuit 17, a circuit (AC / DC conversion circuit) is configured in such a manner that the outputs of the first and second down counters 15 and 16 are input and a modulation signal is output until the count value becomes 0, thereby being able to generate a second modulation signal vTr2 having a duty ratio (duty) of 50% with a pulse width of 1 cycle as an instruction.

[0072] Therefore, the frequency of the second modulation signal vTr2 can be suppressed to twice the switching frequency of the semiconductor element 8 as the driven object, and the time resolution of the pulse width of the gate control instruction can be improved without increasing the driving frequency of the second pulse transformer Tr2.

[0073] Next, the off pulse width measuring unit 12 (up counter) will be described. As an example, Figure 5 An up-counter having an n-level (n: an integer greater than or equal to 1) structure is shown.

[0074] In the first stage, the clock signal CLK is input to the D-FF terminal of the first on-side D flip-flop circuit 18a. The output of the / Q terminal of the first on-side D flip-flop circuit 18a is input to the D terminal. The output of the Q terminal of the first on-side D flip-flop circuit 18a is output as a 1-bit signal.

[0075] In the second stage, the output of the Q terminal of the first on-side D flip-flop circuit 18a and the output of the Q terminal of the second on-side D flip-flop circuit 18b are input to the second on-side XOR circuit 19b.

[0076] The clock signal CLK is input to the D-FF terminal of the second on-side D flip-flop circuit 18b, and the output of the second on-side XOR circuit 19b is input to the D terminal. The output of the Q terminal of the second on-side D flip-flop circuit 18b is output as a 2-bit signal.

[0077] In the third stage, a 1-bit signal and a 2-bit signal are input to the third on-side AND circuit 20c.

[0078] The output of the third on-side AND circuit 20c and the output of the Q terminal of the third on-side D flip-flop circuit 18c are input to the third on-side XOR circuit 19c.

[0079] The third on-side D flip-flop circuit 18c receives a clock signal CLK at its D-FF terminal and receives an output of the third on-side XOR circuit 19c at its D terminal. The output of the Q terminal of the third on-side D flip-flop circuit 18c is output as a 3-bit signal.

[0080] Thus, the up counter is composed of n stages. In the kth stage (k: an integer from 4 to n), the kth AND circuit 20k receives a k-1-bit signal and (k-2)-bit, (k-3)-bit, ... 2-bit, 1-bit signals.

[0081] The kth exclusive OR circuit 19k receives the output signal of the kth AND circuit 20k and the output of the Q terminal of the kth D flip-flop circuit 18k.

[0082] The kth D flip-flop circuit 18k receives a clock signal CLK at its D-FF terminal and receives an output signal of the kth exclusive OR circuit 19k at its D terminal. The output of the Q terminal of the kth D flip-flop circuit 18k is a k-bit signal.

[0083] Next, the first and second down counters 15 and 16 will be described. Figure 6 A down counter of n-stage structure is shown.

[0084] In the first stage, the clock signal CLK is input to the D-FF terminal of the first OFF-side D flip-flop circuit 21a, and the output of the / Q terminal of the first OFF-side D flip-flop circuit 21a is input to the D terminal. The output of the Q terminal of the first OFF-side D flip-flop circuit 21a is output as a 1-bit signal.

[0085] In the second stage, the output of the / Q terminal of the first OFF-side D flip-flop circuit 21a and the output of the / Q terminal of the second OFF-side D flip-flop circuit 21b are input to the second OFF-side XOR circuit 22b.

[0086] The clock signal CLK is input to the D-FF terminal of the second OFF-side D flip-flop circuit 21b, and the output of the second OFF-side XOR circuit 22b is input to the D terminal. The output of the Q terminal of the second OFF-side D flip-flop circuit 21b is output as a 2-bit signal.

[0087] In the third stage, the output of the / Q terminal of the first OFF-side D flip-flop circuit 21a and the output of the / Q terminal of the second OFF-side D flip-flop circuit 21b are input to the third OFF-side AND circuit 23c.

[0088] The output of the third off-side AND circuit 23c and the output of the / Q terminal of the third off-side D flip-flop circuit 21c are input to the third off-side XOR circuit 22c.

[0089] The third OFF-side D flip-flop circuit 21c receives the clock signal CLK at its D-FF terminal and receives the output of the third OFF-side XOR circuit 22c at its D terminal. The output of the Q terminal of the third OFF-side D flip-flop circuit 21c is output as a 3-bit signal.

[0090] Thus, the down counter includes n stages. In the kth stage (k: an integer from 4 to n), the kth AND circuit 23k receives input of a / k-1 bit signal and a / (k-2) bit, / (k-3) bit, ... / 2 bit, / 1 bit signal.

[0091] The kth exclusive OR circuit 22k receives the output signal of the kth AND circuit 23k and the output of the / Q terminal of the kth D flip-flop circuit 21k.

[0092] The kth D flip-flop circuit 21k receives a clock signal CLK at its D-FF terminal and receives an output signal of the kth exclusive OR circuit 22k at its D terminal. The output of the Q terminal of the kth D flip-flop circuit 26k is a k-bit signal.

[0093] Figure 5 , Figure 6 The up-counter and down-counter are structures whose count values ​​are changed when a clock signal is input. Figure 5 In , each time a bit is added when counting, Figure 6 In the example, the count value is subtracted each time a count is performed.

[0094] The pulse width can be determined by reading the binary output (1 to n bits) and multiplying it by the clock cycle. The number of counter stages can be increased according to the pulse width to be measured.

[0095] By using the circuit configuration and control method as described above, it is possible to output a gate voltage with high resolution in response to a gate control command.

[0096] Next, apply Figure 7 The structure is described as the case of the modulation circuit of embodiment 1. It is characterized by comprising: a full-bridge circuit 24 for generating a make signal, driving a first pulse transformer Tr1 for transmitting a make signal; and a full-bridge circuit 25 for generating a break signal, driving a second pulse transformer Tr2 for transmitting a break signal.

[0097] The full bridge circuit 24 for generating an on signal and the full bridge circuit 25 for generating an off signal are connected in parallel to the capacitor C. The first and second semiconductor elements S1on and S2on on the on side are connected in series between the two ends of the capacitor C. In addition, the third and fourth semiconductor elements S3on and S4on on the on side are connected in series between the two ends of the capacitor C. The first to fourth semiconductor elements S1on to S4on on the on side constitute the full bridge circuit 24 for generating an on signal.

[0098] The capacitor Ch1 and the on-side primary winding of the first pulse transformer Tr1 are connected between a connection point of the on-side first and second semiconductor elements S1on and S2on and a connection point of the on-side third and fourth semiconductor elements S3on and S4on.

[0099] The first and second semiconductor elements S1off and S2off on the off side are connected in series between both ends of the capacitor C. In addition, the third and fourth semiconductor elements S3off and S4off on the off side are connected in series between both ends of the capacitor C. The first to fourth semiconductor elements S1off to S4off on the off side constitute a full bridge circuit 25 for generating an off signal.

[0100] The capacitor Ch2 and the off-side primary winding of the second pulse transformer Tr2 are connected between a connection point of the off-side first and second semiconductor elements S1off and S2off and a connection point of the off-side third and fourth semiconductor elements S3off and S4off.

[0101] The capacitors Ch1 and Ch2 cut off the DC component and are connected to prevent magnetic saturation of the first and second pulse transformers Tr1 and Tr2, but they may be omitted.

[0102] The second modulation signal vTr2 can be generated by using Figure 8 The control unit shown controls the generation of the off signal to be realized by the full bridge circuit 25 . Fig. 9 The basic operation is shown in the working timing diagram. Figure 3 , Figure 4 It's the same.

[0103] When the falling edge of the synchronization circuit 9 is detected, Figure 8 The off pulse width measuring unit (up counter) 12 shown starts counting, stops counting when a rising edge is detected, and adds the count value each time a clock signal is input. At this time, it is assumed that the rising edge and the falling edge are synchronized with the clock through the operation of the synchronization circuit 9.

[0104] The OFF pulse width can be measured by this. Then, the count value is reduced to 1 / 2 by the OFF-side 1-bit shift circuit 13.

[0105] The OFF-side latch circuit 14 latches the output of the OFF-side 1-bit shift circuit 13 at the timing of detecting the rising edge.

[0106] The circuit is configured so that the output of the off-side latch circuit 14 is input to the gate generation counters (first and second down counters) 15 and 16 of the subsequent stage and the gate command is output until the count value becomes 0, thereby being able to generate a modulation signal with a duty ratio of 50% with a pulse width of 1 cycle as the command.

[0107] As a specific action, when a disconnection signal is generated, during the period when the first down counter 15 is counting (until the count value becomes 0), the gating instructions of the first and fourth semiconductor elements S1off and S4off on the disconnection side are set to high, and the gating instructions of the second and third semiconductor elements S2off and S3off on the disconnection side are set to low.

[0108] While the second down counter 16 is counting (until the count value becomes 0), the gate control commands of the second and third semiconductor elements S2off and S3off on the off side are set to high, and the gate control commands of the first and fourth semiconductor elements S1off and S4off on the off side are set to low.

[0109] Accordingly, the frequency of the second modulation signal vTr2 can be suppressed to twice the switching frequency of the driven object, and the time resolution of the pulse width of the gate control instruction can be improved without increasing the driving frequency of the second pulse transformer Tr2, thereby reducing the loss of the full-bridge circuit and improving the resolution.

[0110] Next, a method of generating the first modulation signal vTr1 will be described. Fig.10 The operation waveform of the DC / AC modulation circuit of the first embodiment is shown. Figure 2 In the embodiment 1, the positive pulse and negative pulse of the first modulation signal vTr1 are output once for each cycle of the on command, while in the first embodiment, the output of each positive pulse and negative pulse of the first modulation signal vTr1 is divided into two on commands. That is, the on command width is made the same as the period of one positive pulse of the first modulation signal vTr1, and the on command width is made the same as the period of one negative pulse of the first modulation signal vTr1, and the positive pulse and the negative pulse are alternately output each time the on command is issued. According to this, the limitation of the first modulation signal vTr1 limited by the minimum on pulse width can be minimized.

[0111] Fig.11 An example of generation of a gating instruction of the DC / AC modulation circuit according to the first embodiment is shown. Fig.12 for Fig.11 The latch circuit is used to generate an enable signal for the gated instruction, and the original instruction is logically ANDed to generate a signal for the driver IC.

[0112] exist Fig.11 In the embodiment, the rising edge detection circuit 26 detects the rising edge of the gating control instruction. The latch circuit 27 latches at the timing of detecting the rising edge, and releases the latch at the timing when a rising edge is newly detected in the latched state.

[0113] The AND circuit 28 outputs a logical AND of the gate control instruction and the output of the latch circuit 27. The NOT circuit 29 inverts the output of the latch circuit 27. The AND circuit 30 outputs a logical AND of the gate control instruction and the output of the NOT circuit 29.

[0114] The driver IC 31 outputs a gate control instruction of the DC / AC modulation circuit based on the outputs of the AND circuits 28 and 30 .

[0115] The DC / AC modulation circuit is Figure 3 The modulation signal generating circuit 17 or Figure 7 The modulation circuit (the full-bridge circuit 24 for turning on the signal generation) outputs the first modulation signal vTr1 according to the gate control command output from the driver IC.

[0116] In the first embodiment, when the minimum pulse width is set to 100 ns, for example, the modulation circuit can output a pulse of 100 ns or longer. Therefore, the semiconductor element can perform a switching operation closer to the gate control command, and the output voltage accuracy of the inverter can be improved.

[0117] In addition, when the frequency and duty cycle of the gate control command change in a ramp-like manner, the excitation current will be biased to one of the positive and negative directions, and a countermeasure can be taken by inserting capacitors ch1 and ch2 in series on the primary side of the first pulse transformer Tr1. However, capacitors ch1 and ch2 can cut off the DC component to the pulse transformer, but on the other hand, when DC is applied for a long time, the charge will be charged to the capacitor itself, so it is effective only when the excitation component is biased for a short period of time.

[0118] As described above, according to the first embodiment, the frequencies of the first and second modulation signals vTr1 and vTr2 can be made variable according to the gate control signal. As a result, the magnetic saturation of the first and second pulse transformers Tr1 and Tr2 can be suppressed, and the switching loss of the modulation signal generating circuit (DC / AC conversion circuit) driving the first and second pulse transformers Tr1 and Tr2 can be suppressed to the necessary minimum. Furthermore, since the time resolution of the pulse width of the gate control command is not reduced, the command pulse can be reproduced and output with higher accuracy.

[0119] In addition, the limitation of the first modulation signal vTr1 which is limited by the minimum on-pulse width can be minimized. [Implementation Method 2]

[0120] exist Figure 2 In order to deal with the bias magnetization, the positive pulse and negative pulse of the first modulation signal vTr1 are output once each in the pulse width (on command) of the X gate control command, and the time periods of the positive pulse and the negative pulse are made the same within one cycle of the on command of the X gate control command. In this way, the bias magnetization can be eliminated within one cycle of the on command of the X gate control command, but since one positive pulse and one negative pulse are output, a shorter gate control pulse width cannot be output.

[0121] On the other hand, Fig.12 In the method, the output of the positive pulse and the negative pulse of the first modulation signal vTr1 is divided into two pulse widths of the X gate control command (on command). This is advantageous when the pulse width of the X gate control command is short, but when the pulse width of the X gate control command is long, the application time of the primary side voltage of the transformer is also long, so it is easy to cause damage due to magnetic saturation.

[0122] Fig.13 It is summarized in Figure 2 , Fig.12In addition to these characteristics, there is also a period Ton (refer to Figure 2 ) becomes longer, the accuracy of the pulse width of the gate voltage Vgs decreases due to the back electromotive force of the first pulse transformer Tr1, which applies an unexpected voltage to the secondary side, or the pulse transformer is enlarged in order to increase the saturation flux density or cope with heat.

[0123] In order to solve these two problems, it is necessary to set a limit on the length of the output period Ton of the first modulation signal Vtr1. For example, when a DC / AC modulation circuit is used as the modulation circuit 2, the following control is required: without being affected by the length of the pulse width of the X-gate control instruction, the magnetic saturation of the pulse transformer caused by the bias magnetization (the bias of the time integral of the voltage to a single polarity above a certain value) is prevented and the operation is performed in the shorter output period Ton of the first modulation signal Vtr1.

[0124] In this embodiment 2, in order to solve the above-mentioned problem, Figure 2 , Fig.12 The superiority method.

[0125] In this second embodiment, in order to take into account Figure 2 , Fig.12 By taking advantage of the advantages of the first modulation signal vTr1, the polarity is reversed according to the pulse width of the X gate control command. By reversing the output polarity of the DC / AC modulation circuit under the following two conditions, it is possible to prevent the pulse transformer from being magnetized without setting a limit on the pulse width of the X gate control command.

[0126] (1) Gate instruction every 1 cycle ( Figure 2 of X-gated instructions every 1 cycle).

[0127] (2) When the output period Ton has passed a predetermined time.

[0128] That is, in the modulation circuit 2 of the second embodiment, a positive pulse or a negative pulse is output as the first modulation signal vTr1 during the period of the on command of the X gate control command, and the polarity of the first modulation signal vTr1 at the start of output is reversed every cycle of the X gate control command. When the output period Ton of the first modulation signal vTr1 has passed a predetermined time, the polarity of the first modulation signal vTr1 is reversed.

[0129] Fig.14 A control block diagram of the second embodiment is shown. Fig.14 The block diagram has: an inversion permission signal generating section 32, which generates an inversion permission signal for operating the output polarity under the above conditions (1) and (2); a gating signal generating section 33, which writes an X gating instruction according to a provided cycle instruction; and a polarity selector section 34.

[0130] X-gated instructions and Figure 2 The same as in is the instruction signal for the modulation circuit 2. The cycle instruction Tinv is a constant predetermined by the designer. The output period Ton of the modulation circuit 2 (the first modulation signal vTr1) is Tinv / 2. The cycle instruction Tinv is set to a length that does not cause magnetic saturation of the pulse transformer even if a DC is applied.

[0131] like Fig.14 As shown, the inversion permission signal generating unit 32 uses the cycle counter 35 to count the cycle instruction Tinv during the period when the X gate control instruction is "1", and clears it when the X gate control instruction is "0". The negative edge detection unit 36 ​​detects the falling edge of the cycle counter 35. The negative edge detection unit 37 detects the falling edge of the X gate control instruction.

[0132] The output of the negative edge detection unit 36 ​​is input to the C terminal of the multiplexer 38. The buffer 39 outputs the value of the output of the multiplexer 38 one operation time ago. The NOT circuit 40 inverts the output of the buffer 39. The output of the buffer 39 is input to the 0 terminal of the multiplexer 38, and the output of the NOT circuit 40 is input to the 1 terminal of the multiplexer 38.

[0133] The output of the negative edge detection unit 37 is input to the C terminal of the multiplexer 41. The buffer 42 outputs the value of the output of the multiplexer 41 one operation time ago. The output of the buffer 42 is input to the 0 terminal of the multiplexer 41, and the output of the multiplexer 38 is input to the 1 terminal of the multiplexer 41. The output of the multiplexer 41 is the inversion permission signal EN_POL. That is, the inversion permission signal generation unit 32 generates the inversion permission signal EN_POL that switches between "1" and "0" at the falling edge of the X gate instruction.

[0134] The gate control signal generating unit 33 uses the divider 43 to reduce the cycle instruction Tinv to 1 / 2. The comparator 44 compares the output of the divider 43 with the output of the cycle counter 35, and outputs "1" if the output of the divider 43 is larger, and outputs "0" if it is smaller. The comparator 45 compares the output of the cycle counter 35 with the output of the divider 43, and outputs "1" if the output of the cycle counter 35 is larger, and outputs "0" if it is smaller.

[0135] The output of the comparator 44 and the X gate control instruction are input to the AND circuit 46, and when both are "1", "1" is output, and otherwise "0" is output as the gate signal GATE1. The output of the comparator 45 and the X gate control instruction are input to the AND circuit 47, and when both are "1", "1" is output, and otherwise "0" is output as the gate signal GATE2.

[0136] That is, the gate signal generating unit 33 generates the gate signal GATE1 and the gate signal GATE2, wherein the gate signal GATE1 is “1” when the X gate command is turned on and the X gate command output is turned on until a predetermined time (1 / 2 of the cycle command Tinv) has passed, and the gate signal GATE2 is “1” when the X gate command is turned on and the X gate command output is turned on after a predetermined time (1 / 2 of the cycle command Tinv) has passed, and the gate signal GATE2 is “0” otherwise.

[0137] The polarity selector section 34 includes a multiplexer 48 and a multiplexer 49. The inversion permission signal EN_POL is input to the C terminal of the multiplexer 48, the gate signal GATE1 is input to the 0 terminal of the multiplexer 48, and the gate signal GATE2 is input to the 1 terminal of the multiplexer 48. The inversion permission signal EN_POL is input to the C terminal of the multiplexer 49, the gate signal GATE2 is input to the 0 terminal of the multiplexer 49, and the gate signal GATE1 is input to the 1 terminal of the multiplexer 49. The output of the multiplexer 48 is the positive output gate signal GATE_P, and the output of the multiplexer 49 is the negative output gate signal GATE_N.

[0138] That is, when the inversion permission signal is "0", the polarity selector section 34 sets the positive output gate signal GATE_P to "1" when the gate signal GATE1 is "1", sets the negative output gate signal GATE_N to "1" when the gate signal GATE2 is "1", and otherwise sets the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0". When the inversion permission signal is "1", when the gate signal GATE1 is "1", sets the negative output gate signal GATE_N to "1", and when the gate signal GATE2 is "1", sets the positive output gate signal GATE_P to "1", and otherwise sets the positive output gate signal GATE_P and the negative output gate signal GATE_N to "0".

[0139] The driving IC 50 outputs a gate control instruction of the DC / AC modulation circuit based on the positive output gate control signal GATE_P and the negative output gate control signal GATE_N.

[0140] Here, multiplexers 38, 41, 48, and 49 are constructed as follows. NOT circuit 51 inverts the signal input to terminal C. AND circuit 52 inputs the output signal of NOT circuit 51 and the signal input to terminal 0, and outputs "1" when both are "1", and outputs "0" otherwise. AND circuit 53 inputs the signal input to terminal C and the signal input to terminal 1, and outputs "1" when both are "1", and outputs "0" otherwise. OR circuit 54 inputs the output signal of AND circuit 52 and the output signal of AND circuit 53, and outputs "1" when at least one of them is "1", and outputs "0" when both are "0". The output of OR circuit 54 is the output signal of the multiplexer.

[0141] Fig.15 The following are signals of various parts of the control circuit according to Embodiment 2. The inversion permission signal generation unit 32 and the polarity selector unit 34 are control blocks for satisfying the polarity inversion condition (1).

[0142] The inversion permission signal EN_POL is switched when the cycle counter 35 is cleared (falling), and updating of the inversion permission signal EN_POL is permitted only at the falling edge of the gating instruction. The inversion permission signal EN_POL is used to invert the positive and negative outputs in the polarity selector section 34 .

[0143] On the other hand, the gate signal generation unit 33 is a control block for satisfying the polarity inversion condition (2). It generates a signal corresponding to the output period Ton by performing a comparison operation on half of the cycle instruction Tinv and the output of the cycle counter 35, and generates gate signals GATE1 and GATE2 by performing AND operation on the signal and the X gate instruction.

[0144] The polarity selector section 34 determines the positive output gate signal GATE_P and the negative output gate signal GATE_N of the DC / AC modulation circuit based on the gate signals GATE1 and GATE2 and the inversion permission signal EN_POL.

[0145] When the pulse width of the gated instruction is long, such as Figure 2 As shown, the positive and negative pulses of the first modulation signal vTr1 are alternately output in the on pulse width of the X gate control instruction. When the pulse width of the X gate control instruction is short, the Fig.12 As shown, two cycles are used to realize the positive control of the first modulation signal. As a result, both Figure 2 , Fig.12 The advantage of this is that it can expand the setting range of the pulse width and miniaturize the pulse transformer without relying on the pulse width length of the gate control instruction.

[0146] As shown in the following formula (1), the bias is the case where the time integral of the voltage is biased. The amount equivalent to the bias caused by only one cycle instruction Tinv is within the allowable range, and the problem is caused by it being accumulated. In the present embodiment 2, when the pulse width of the X-gating instruction is an even number of Tinv / 4, if the odd number of Tinv / 4 repeats an even number of cycles within its cycle, then within this range, even if the odd number of Tinv / 4 reaches an odd number of cycles, it can be handled when it reaches an odd number of times again.

[0147] [Mathematical formula 1]

[0148] …… (1)

[0149] Fig.16 In the example of the X gate control instruction with an on pulse width of 3 scales, 3 scales, and 4 scales, 1 scale = Tinv / 4 is assumed.

[0150] When the initial X-gating instruction is on, the first modulation signal vTr1 outputs a positive pulse because the output of the cycle counter 35 is less than 1 / 2 of the cycle instruction Tinv before the second scale. After the second scale, the output of the cycle counter 35 becomes greater than 1 / 2 of the cycle instruction Tinv, so the first modulation signal vTr1 reverses its polarity and outputs a negative pulse.

[0151] When the second X gating instruction is turned on, the output of the cycle counter 35 is less than 1 / 2 of the cycle instruction Tinv before the second tick. Here, the polarity at the start of the output changes every cycle of the X gating instruction, so the first modulation signal vTr1 outputs a negative pulse. After the second tick, the output of the cycle counter 35 becomes greater than 1 / 2 of the cycle instruction Tinv, so the first modulation signal vTr1 reverses its polarity and outputs a positive pulse. When the third X gating instruction is turned on, Fig.15 same.

[0152] In this way, even if the pulse width of the X gate control instruction is not 1 / 4 of the even-numbered cycle instruction Tinv, the flux deviation can be eliminated in two cycles. In addition, even if it is an odd cycle instead of an even cycle, the flux deviation can be eliminated when it becomes an odd cycle again. Even if there are no more odd cycles, there is no problem as long as the flux deviation is not accumulated.

[0153] The reason for preventing demagnetization is to prevent damage due to heat or magnetic saturation, so there is no problem as long as the average value of the excitation current is 0 over a long period of time longer than one cycle (or as long as the current does not increase too much periodically).

[0154] As described above, according to the second embodiment, in a high-voltage high-frequency pulse power supply having a driver that drives a pulse transformer by a DC / AC modulation circuit, it is possible to cope with a short gated pulse width and achieve a high-precision gated pulse width while preventing magnetization of the pulse transformer.

[0155] In the above, only the specific examples described in the present invention have been described in detail, but it is obvious to those skilled in the art that various changes and modifications can be made within the scope of the technical concept of the present invention, and such changes and modifications naturally belong to the scope of the claims.

[0156] For example, the semiconductor element 8 to be driven in the first and second embodiments is used in a power conversion device (a converter, an inverter, or the like).

[0157] In addition, the control method of the first modulation signal vTr1 in the first and second embodiments can also be applied to the second modulation signal vTr2. It can be applied to either the first embodiment or the second embodiment, or to both of them.

[0158] When the control method of implementation mode 1 is applied to the second modulation signal vTr2, the disconnection instruction width is made the same as the time period of a positive pulse of the second modulation signal vTr2, and the disconnection instruction width is made the same as the time period of a negative pulse of the second modulation signal vTr2. Whenever the disconnection instruction is issued, the positive pulse and the negative pulse of the second modulation signal vTr2 are output alternately.

[0159] When the control method of implementation mode 2 is applied to the second modulation signal vTr2, a positive pulse or a negative pulse is output as the second modulation signal during the period of the disconnection instruction of the gating instruction, and the polarity of the second modulation signal vTr2 at the beginning of the output is reversed in each cycle of the gating instruction. When the output period of the second modulation signal vTr2 has passed a predetermined time, the polarity of the second modulation signal vTr2 is reversed.

Claims

1. A gate drive circuit, characterized in that: have: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. Among them, the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the on-command width the same as the time period of a positive pulse of the first modulation signal, and makes the on-command width the same as the time period of a negative pulse of the first modulation signal, and whenever the on-command is received, the positive pulse and the negative pulse of the first modulation signal are output alternately.

2. A gate drive circuit, characterized in that: have: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. Among them, the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the off-command width the same as the time period of a positive pulse of the second modulation signal, and makes the off-command width the same as the time period of a negative pulse of the second modulation signal, and whenever the off-command is received, the positive pulse and the negative pulse of the second modulation signal are output alternately.

3. The gate driving circuit according to claim 1, characterized in that: The modulation circuit has: A rising edge detection circuit, for detecting the rising edge of the gating instruction; A latch circuit that latches at the timing of detecting the rising edge of the gating instruction, and releases the latch at the timing when the rising edge of the gating instruction is detected again in the latched state; A first AND circuit, outputting a logical AND of the gating instruction and the output of the latch circuit; a NOT circuit for inverting the output of the latch circuit; A second AND circuit, outputting a logical AND of the gating instruction and the output of the NOT circuit; A driver IC that controls a DC / AC modulation circuit based on an output of the first AND circuit and an output of the second AND circuit; as well as The DC / AC modulation circuit outputs the first modulation signal based on the control of the driving IC.

4. A gate drive circuit, characterized in that: have: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the first modulation signal during the on-command period of the gating instruction, reverses the polarity of the output of the first modulation signal at the start of each cycle of the gating instruction, and reverses the polarity of the first modulation signal when a predetermined time has passed during the output period of the first modulation signal.

5. A gate drive circuit, characterized in that: have: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. Among them, the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the second modulation signal during the off-command period of the gating instruction, reverses the polarity of the output of the second modulation signal at the beginning of each cycle of the gating instruction, and reverses the polarity of the second modulation signal when the output period of the second modulation signal has passed a predetermined time.

6. The gate driving circuit according to claim 4, characterized in that: have: an inversion permission signal generating unit, generating an inversion permission signal that switches between "1" and "0" at a falling edge of the gating instruction; a gating signal generating unit, generating a gating signal GATE1 and a gating signal GATE2, wherein the gating signal GATE1 outputs "1" when the gating instruction is turned on and a predetermined time has passed since the gating instruction output is turned on, and is "0" otherwise; and the gating signal GATE2 outputs "1" when the gating instruction is turned on and a predetermined time has passed since the gating instruction output is turned on, and is "0" otherwise; a polarity selector section, which, when the inversion permission signal is "0", makes the positive output gate signal GATE_P "1" when the gate signal GATE1 is "1", makes the negative output gate signal GATE_N "1" when the gate signal GATE2 is "1", and otherwise makes the positive output gate signal GATE_P and the negative output gate signal GATE_N "0", and when the inversion permission signal is "1", makes the negative output gate signal GATE_N "1" when the gate signal GATE1 is "1", makes the positive output gate signal GATE_P "1" when the gate signal GATE2 is "1", and otherwise makes the positive output gate signal GATE_P and the negative output gate signal GATE_N "0"; A driver IC, controlling a DC / AC modulation circuit based on the positive output gate signal GATE_P and the negative output gate signal GATE_N; as well as The DC / AC modulation circuit outputs the first modulation signal based on the control of the driving IC.

7. The gate driving circuit according to claim 3 or 6, characterized in that: The DC / AC modulation circuit is a modulation signal generation circuit. The modulation circuit has: A synchronization circuit, synchronizing the gating instruction with a clock signal; A rising edge detection unit, detecting a rising edge of an output of the synchronization circuit; A falling edge detection unit, which detects a falling edge of the output of the synchronization circuit; The pulse width measuring unit is disconnected, starts counting when a falling edge of the output of the synchronization circuit is detected, stops counting when a rising edge of the output of the synchronization circuit is detected, and adds the count value each time the clock signal is input; A 1-bit shift circuit on the disconnecting side changes the output of the disconnecting pulse width measuring unit to 1 / 2; A disconnected-side latch circuit latches the output of the disconnected-side 1-bit shift circuit at the timing of the rising edge of the output of the synchronization circuit; a first down counter, which inputs the output of the disconnected side latch circuit and the clock signal, and subtracts the count value whenever the clock signal is input; as well as a second down-counter which receives the output of the disconnected latch circuit, the output of the first down-counter and the clock signal, and subtracts the count value whenever the clock signal is input; The modulation signal generating circuit outputs the second modulation signal until the counters of the first down-counter and the second down-counter reach zero.

8. The gate driving circuit according to claim 3 or 6, characterized in that: The DC / AC modulation circuit has: Capacitors; A full-bridge circuit for generating an on-signal, comprising first and second on-side semiconductor elements connected in series between the two ends of the capacitor and third and fourth on-side semiconductor elements connected in series between the two ends of the capacitor; as well as The full-bridge circuit for generating an off signal comprises first and second off-side semiconductor elements connected in series between the two ends of the capacitor and third and fourth off-side semiconductor elements connected in series between the two ends of the capacitor. Among them, the primary winding on the connection side of the first pulse transformer is connected between the connection point of the first and second semiconductor elements on the connection side and the connection point of the third and fourth semiconductor elements on the connection side, and the primary winding on the disconnection side of the second pulse transformer is connected between the connection point of the first and second semiconductor elements on the disconnection side and the connection point of the third and fourth semiconductor elements on the disconnection side.

9. The gate driving circuit according to claim 8, characterized in that: The modulation circuit has: A synchronization circuit, synchronizing the gating instruction with a clock signal; A rising edge detection unit, detecting a rising edge of an output of the synchronization circuit; A falling edge detection unit, which detects a falling edge of the output of the synchronization circuit; The pulse width measuring unit is disconnected, starts counting when a falling edge of the output of the synchronization circuit is detected, stops counting when a rising edge of the output of the synchronization circuit is detected, and adds the count value each time the clock signal is input; A 1-bit shift circuit on the disconnecting side changes the output of the disconnecting pulse width measuring unit to 1 / 2; A disconnected-side latch circuit latches the output of the disconnected-side 1-bit shift circuit at the timing of the rising edge of the output of the synchronization circuit; a first down counter, which inputs the output of the disconnected side latch circuit and the clock signal, subtracts the count value each time the clock signal is input, and outputs a gating instruction for the first and fourth semiconductor elements on the disconnected side until the count value becomes 0; as well as The second down counter inputs the output of the disconnected side latch circuit, the output of the first down counter and the clock signal, subtracts the count value each time the clock signal is input, and outputs the gating instructions of the second and third semiconductor elements on the disconnected side until the count value becomes 0.

10. The gate driving circuit according to claim 7, characterized in that: The off pulse width measuring unit has an n-level structure, wherein n is an integer greater than 1. At level 1, have: The first on-side D flip-flop circuit has the clock signal input to the D-FF terminal, and the output of the / Q terminal of the first on-side D flip-flop circuit is input to the D terminal, and the output of the Q terminal is a 1-bit signal. At level 2, have: a second ON-side XOR circuit, which inputs the output of the Q terminal of the first ON-side D flip-flop circuit and the output of the Q terminal of the second ON-side D flip-flop circuit; as well as The second on-side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the second on-side XOR circuit to the D terminal, and the output of the Q terminal is a 2-bit signal. At level 3, have: a third on-side AND circuit, which inputs the output of the Q terminal of the first on-side D flip-flop circuit and the output of the Q terminal of the second on-side D flip-flop circuit; a third connection-side XOR circuit, which inputs the output of the third connection-side AND circuit and the output of the Q terminal of the third connection-side D flip-flop circuit; as well as The third on-side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the third on-side XOR circuit to the D terminal, and the output of the Q terminal is a 3-bit signal. At level 4 to level n, it has: The k-th connected side AND circuit inputs a k-1 bit signal and a (k-2) bit·(k-3) bit·…2 bit·1 bit signal, where k is an integer from 4 to n; A k-th connected-side XOR circuit, inputting the output of the k-th connected-side AND circuit and the output of the Q terminal of the k-th connected-side D flip-flop circuit; as well as The k-th on-side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the k-th on-side XOR circuit to the D terminal, and the output of the Q terminal is a k-bit signal.

11. The gate driving circuit according to claim 7, characterized in that: The first down counter and the second down counter are of n-level structure, wherein n is an integer greater than 1, At level 1, have: The first disconnected side D flip-flop circuit inputs the clock signal to the D-FF terminal, and inputs the output of the / Q terminal of the first disconnected side D flip-flop circuit to the D terminal, the output of the Q terminal being a 1-bit signal. At level 2, have: a second disconnected-side XOR circuit, inputting the output of the / Q terminal of the first disconnected-side D flip-flop circuit and the output of the / Q terminal of the second disconnected-side D flip-flop circuit; as well as The second disconnected side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the second disconnected side XOR circuit to the D terminal, and the output of the Q terminal is a 2-bit signal. At level 3, have: a third disconnected-side AND circuit, which inputs the output of the / Q terminal of the first disconnected-side D flip-flop circuit and the output of the / Q terminal of the second disconnected-side D flip-flop circuit; a third disconnected side XOR circuit, inputting the output of the third disconnected side AND circuit and the output of the / Q terminal of the third disconnected side D flip-flop circuit; as well as The third disconnected side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the third disconnected side XOR circuit to the D terminal, and the output of the Q terminal is a 3-bit signal. At level 4 to level n, it has: The k-th disconnected side AND circuit is input with / k-1 bit signal and / (k-2) bit· / (k-3) bit... / 2 bit· / 1 bit signal, where k is an integer from 4 to n; A k-th disconnected side XOR circuit, inputting the output of the k-th disconnected side AND circuit and the output of the / Q terminal of the k-th disconnected side D flip-flop circuit; as well as The k-th disconnected side D flip-flop circuit inputs the clock signal to the D-FF terminal, inputs the output of the k-th disconnected side XOR circuit to the D terminal, and the output of the Q terminal is a k-bit signal.

12. A power conversion device, characterized in that: A semiconductor element as a driven object according to any one of claims 1 to 2 and 4 to 5 is provided.

13. A control method for a gate drive circuit, characterized in that: The gate drive circuit comprises: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. Among them, the modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the on-command width the same as the time period of a positive pulse of the first modulation signal, and makes the on-command width the same as the time period of a negative pulse of the first modulation signal, and whenever the on-command is received, the positive pulse and the negative pulse of the first modulation signal are output alternately.

14. A control method for a gate drive circuit, characterized in that: The gate drive circuit comprises: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the on-side tertiary winding. The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating command, makes the off-command width the same as the time period of a positive pulse of the second modulation signal, and makes the off-command width the same as the time period of a negative pulse of the second modulation signal, and whenever the off-command is issued, the positive pulse and the negative pulse of the second modulation signal are output alternately.

15. A control method for a gate drive circuit, characterized in that: The gate drive circuit comprises: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the first modulation signal during the on-command period of the gating instruction, reverses the polarity of the output of the first modulation signal at the start of each cycle of the gating instruction, and reverses the polarity of the first modulation signal when a predetermined time has passed during the output period of the first modulation signal.

16. A control method for a gate drive circuit, characterized in that: The gate drive circuit comprises: The modulation circuit outputs a first modulation signal and a second modulation signal based on an on instruction and an off instruction of the gate control instruction; The on-side rectifier circuit comprises: a first pulse transformer having an on-side primary winding to which the first modulation signal is applied, and an on-side secondary winding and an on-side tertiary winding for transforming and outputting a voltage applied to the on-side primary winding; a first diode circuit for rectifying the output of the on-side secondary winding; and a second diode circuit for rectifying the output of the tertiary winding on the connected side; as well as The disconnected-side rectifying circuit comprises: a second pulse transformer having a disconnected-side primary winding to which the second modulation signal is applied, and a disconnected-side secondary winding and a disconnected-side tertiary winding for transforming and outputting a voltage applied to the disconnected-side primary winding; and a third diode circuit for rectifying the output of the disconnected-side secondary winding; and a fourth diode circuit for rectifying the output of the disconnected side tertiary winding, The gate drive circuit controls the semiconductor element as a drive object according to the output of the first to fourth diode circuits. The modulation circuit makes the frequencies of the first modulation signal and the second modulation signal variable according to the on-command width and the off-command width of the gating instruction, outputs a positive pulse or a negative pulse as the second modulation signal during the off-command period of the gating instruction, reverses the polarity of the output of the second modulation signal at the start of each cycle of the gating instruction, and reverses the polarity of the second modulation signal when a predetermined time has passed during the output period of the second modulation signal.

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