Current sense amplifier with offset cancellation

Abstract

An integrated current sense amplifier with offset cancellation implemented with GaN technology. A current sense amplifier senses a current flowing through either the low-side power FET or the high-side power FET of the half-bridge circuit. The current sense amplifier stores the amplifier input offset voltage using the off-time of the power FET. The stored amplifier input offset voltage is then used to cancel the amplifier input offset voltage during the on-time of the power FET, which is the time interval where current sensing is required.

Description

Background Art

[0001] Many power converters require current sensing in order to detect overcurrent conditions and improve voltage regulation in closed-loop control. Current sensing can be implemented using different methods, such as measuring the R DS(on) , inductive coupling, using a small sense FET in parallel with the power FET, or using a current sense resistor. Using a current sense resistor is the most common method.

[0002] When using a sense resistor, the current sense resistor, the current sense resistor R S Can be placed in series with the inductor of the power converter. The current sensing resistor R S It may also be placed in series with a high-side (HS) power FET of a half-bridge connected to a supply voltage and / or in series with a low-side (LS) power FET of a half-bridge connected to ground, as shown in FIG. 1A .

[0003] The current sensing resistor can also be placed in series with the small sense FET 100 to the power FET, as shown in FIG. 1B . In this case, the power loss caused by the current sensing resistor is minimized. However, the current sensing accuracy will depend on the matching between the small sense FET 100 and the power FET 102.

[0004] If the current sensing resistor Rs is connected in series with the power FET (FIG. 1A) or the small sensing FET (FIG. 1B), the voltage across the current sensing resistor must be minimized to reduce power dissipation, which requires the current sensing resistor to be small. Therefore, a current sensing amplifier 106 is required to amplify the voltage at the current sensing input Si. Since the current sensing amplifier 106 amplifies the voltage at the sensing input Si, any voltage offset at the input Si of the current sensing amplifier 106 will reduce the accuracy of the current sensing, that is, the output S of the current sensing amplifier 106. O The accuracy of the place.

[0005] Figure 2 shows a conventional low-side current sensing circuit using a resistor and an operational amplifier. The sense voltage output So of the operational amplifier is equal to Id·Rs·R2 / R1+Vref. The circuit of Figure 2 has the following disadvantages:

[0006] 1. If the input offset voltage of the operational amplifier is V OS , then the output So will have an additional output offset equal to V OS (1+R2 / R1). Operational amplifiers implemented in GaN technology typically have a high voltage offset V OS , which is due to the high FET threshold voltage shift and mismatch in GaN technology.

[0007] 2. Common-mode voltage V at the operational amplifier input CMI close to the ground for low-side current sensing. This is not suitable for an enhancement-mode NFET differential input stage. Therefore, the required op amp is difficult to implement in GaN technology, as only enhancement-mode GaN NFETs are currently available.

[0008] FIG3 shows a conventional high-side current sensing circuit 300. Due to the operational amplifier feedback loop, the voltage across R1 is equal to the sensing voltage R S The PFET 302 is used to transfer the current on R1 to the grounded R2. As the current flows through the PFET 302, the output voltage V O Equal to I HS ·R S ·R2 / R1.

[0009] The high-side current sensing circuit 300 of FIG. 3 has the following disadvantages:

[0010] 1. Common-mode voltage V at the operational amplifier input CMI Approximately equal to V in Therefore, the op amp supply voltage must be within V in Between and ground. For large V in , the operational amplifier will have a high power dissipation. In addition, the operational amplifier of FIG. 3 (which includes a PFET) is difficult to implement with GaN technology because only NFETs are currently available in GaN.

[0011] 2. If the op amp power supply is floating with the SW node (between V in and ground), a wider op amp input common-mode range is required.

[0012] 3. As in the current sensing circuit of Figure 2, the operational amplifier offset voltage will be at the output V O is amplified, which will affect V O adversely affect the accuracy. Summary of the invention

[0013] Therefore, it is desirable to provide a current sense amplifier with offset cancellation using GaN technology that overcomes the above-mentioned shortcomings of the prior art.

[0014] More specifically, the present invention utilizes the fact that the drive current I flowing through the power FET needs to be sensed only when the power FET is turned on. D The present invention uses the off-time to store the amplifier input offset on a capacitor. The stored offset is then used to cancel the amplifier input offset during the power FET on-time (which is the time interval when current sensing is required).

[0015] The amplifier offset cancellation technique of the present invention is used to sense low-side and high-side currents in a half-bridge power converter. For high-side current sensing, an off-chip PFET can be used to transfer the sensed current to a ground reference resistor. Alternatively and preferably, to allow the current sense amplifier to be fully integrated in GaN (where PFETs are not yet available), the off-chip PFET is replaced with a GaN FET, and the control voltage applied to the gate of the GaN FET is level shifted down to near ground.

[0016] The advantages and additional features of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be learned through the practice of the present invention. The features and advantages of the present invention may be realized and obtained through the measures and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and the appended claims, or may be learned through the practice of the present invention set forth hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Advantages and features of the present invention will become apparent when the following description of the preferred embodiments of the present invention is read in conjunction with the accompanying drawings, in which:

[0018] FIG. 1A shows a conventional low-side current sensing circuit in which a current sensing resistor is connected in series with a low-side power FET.

[0019] FIG. 1B shows a conventional low-side current sensing circuit in which a current sensing resistor is placed in series with a small sense FET.

[0020] Figure 2 shows a conventional low-side current sensing circuit using a resistor and an operational amplifier.

[0021] FIG3 shows a conventional high-side current sensing circuit with a resistor and an operational amplifier.

[0022] Figure 4 An integrated low-side current sense amplifier with offset cancellation according to the present invention is shown, Figure 4A shows the current sensing circuit and amplifier input offset voltage, Figure 4B shows the time period for the Figure 4A The integrated low-side current sense amplifier current sensing circuit and Figure 4C and Figure 4D The diagrams for the on-time (sense time) are shown in the absence and presence of an input signal. Figure 4A The integrated low-side current sense amplifier is a current sensing circuit.

[0023] Figure 5A The low-side current sensing circuit system of the present invention with a capacitor reset gain circuit is shown, and Figure 5Band Figure 5C The current sensing circuit during the reset phase and the current sensing phase are shown respectively.

[0024] Figure 6 A high-side current sense amplifier with offset cancellation of the present invention is shown, and Fig. 6A Circuitry for a power supply and clock generator used in a high-side current sensing circuit is shown.

[0025] Figure 7 shows a high-side current sense amplifier using an off-chip P-MOSFET, and Fig. 7A and Figure 7B The current sensing circuit during the reset phase and the current sensing phase are shown respectively.

[0026] Figure 8 A high-side current sense amplifier is shown without using a P-MOSFET. Fig. 8A shows the circuitry of the off-state SO and VB generators used in the circuit, and Figure 8B and Figure 8C The current sensing circuit during the reset phase and the current sensing phase are shown respectively.

[0027] Fig. 9 An integrated high-side current sense amplifier with a sense FET is shown.

[0028] Fig.10 Shown for Fig. 9 The high-side current sense amplifier circuitry of the integrated circuit, and Fig. 10A and Fig. 10B The current sensing circuit during the reset phase and the current sensing phase are shown respectively. DETAILED DESCRIPTION

[0029] It should be understood that the drawings and description of the present invention have been simplified to illustrate only the elements relevant to a clear understanding of the embodiments of the present invention. Those of ordinary skill in the art will recognize that other elements may be desired and / or required to implement the embodiments of the present invention. It should also be understood that the drawings included herein only provide schematic representations of the presently preferred embodiments of the present invention. Reference will now be made to the accompanying drawings, in which the same structures will be provided with the same reference numerals.

[0030] Low-Side Current Sensing Architecture

[0031] Figure 4A4 is a circuit diagram of an integrated low-side current sense amplifier with offset cancellation of the present invention, generally identified by reference numeral 400. The current sense amplifier has an operational amplifier circuit that senses the current flowing through the low-side power FET 402 at the Si node. The current is sensed by an operational amplifier circuit that includes an operational amplifier 408 and two input branches from the Si node, each input branch including a capacitor C1. The input capacitor C1 of the lower branch is connected to the non-inverting input of the operational amplifier on one side and to ground on the other side. The input capacitor C1 of the upper branch is connected to the inverting input of the operational amplifier 408 and is additionally connected to ground through a switch 404, or is connected to the sensing input Si through a switch 406. Switches 404, 404' and 406 (preferably implemented as GaN FET transistors) are driven by turn-on and turn-off timing signals for switching the low-side power FET 402.

[0032] The basic principle underlying the present invention is that since the current sensing in the present invention is integrated with the gate driver driving the low-side power FET 402, the turn-on and turn-off timing signals of the power FET 402 can be used to control the switches 404, 404' and 406 of the current sense amplifier. When the power FET 402 is turned off, current sensing on the power FET is unnecessary. Therefore, according to the present invention, the off time interval is used to reset the current sense amplifier to achieve offset cancellation. Utilizing the off time interval for this purpose is an essential feature of the present invention.

[0033] More specifically, in the operation of the low-side current sensing circuit 400, when the low-side power FET 402 is turned off, the switch 404 is closed, the amplifier is in the reset phase, and the operational amplifier offset is stored on the C1 and C2 capacitors. When the low-side power FET 402 is turned on, the switch 406 is closed and current sensing is performed. This is the amplification phase, where the operational amplifier offset is cancelled by the offset stored on the C1 and C2 capacitors. The operational amplifier output So is equal to -C1 / C2·Si+Vref.

[0034] Reference now Figure 4B-4D explain Figure 4A 4. Operation of a low-side current sense amplifier of FIG. 4, which shows the electrical connections of the components of the low-side sensing circuit 400, where the switch is opened / closed in two operating states (ie, current sensing off or on).

[0035] exist FIG. 4B to FIG. 4D , op amp 408 is modeled as an ideal op amp with an offset voltage V at the positive op amp input terminal. OS .

[0036] First reference Figure 4B, in the reset phase, when switches 404 and 404' are turned on and switch 406 is turned off (no current sensing), operational amplifier 408 is in unity gain feedback. Therefore, Va+ = Vref and Va- = Vref + V OS , where Va+ is the voltage at the positive input of the operational amplifier 408, and Va- is the voltage at the negative input of the operational amplifier 408. The input offset voltage V OS is stored on capacitors C1 and C2, and the output voltage at SO is equal to Vref + V OS When switch 404 is on, the output value is not important because the sense amplifier does not need to sense current during this time interval.

[0037] When switch 406 is turned on and switches 404 and 404' are turned off ( Figure 4C ), current sensing occurs and sense amplifier 408 must provide the correct output value. (Switch 404' is timed to be opened slightly before switch 404 to reduce the effects of clock feedthrough / charge injection when switches 404 and 404' are open).

[0038] If the input Si is at ground (0V) during the current sensing phase, the voltage across capacitors C1 and C2 is proportional to Figure 4B The voltage in the circuit connection remains the same. The output voltage at SO is equal to Va-minus the voltage across the top of capacitor C2, which is equal to (Vref + V OS )-V OS =Vref, which is the expected value for Si=0V (no current).

[0039] refer to Figure 4D , in the Figure 4C Under the same switching conditions (switch 406 is on, switches 404 and 404' are off), if Si is non-zero, current flows and the charge stored on the upper capacitor C1 changes by the amount Si×C1, and the charge flows into the top capacitor C1 and the top capacitor C2, as shown by the arrows. The same amount of charge that changed on capacitor C1 is transferred to C2, and the voltage on Vc2 changes by (Si×C1) / C2. Note that before switch 406 is turned on, the initial value of Vc2 is V OS .

[0040] Due to S O =Va--Vc2, so S O =(Vref+V OS )-(V OS +(Si×C1) / C2)=Vref-(Si×C1) / C2.

[0041] Therefore, as shown above, the low-side current sensing amplifier of the present invention advantageously eliminates the amplifier at the output S O The offset voltage V OS .

[0042] Note that for positive Si, the output S O is less than Vref, and for negative Si, the output S O In some cases, it may be more desirable for S to be greater than Vref for the positive input Si. O is greater than Vref, and for negative input Si, S may be more desirable O This can be achieved by flipping the switch arrangement of switches 504 and 506 connected between the input Si and the input capacitor C1 and the ground connection.

[0043] Low-Side Current Sensing Architecture with Capacitor Reset Gain

[0044] use Figure 4A One of the disadvantages of the offset cancellation circuit shown in is that the feedback gain of the operational amplifier during the reset phase (when switches 404 and 404' are turned on) is unity, which is different from the feedback gain C2 / (C1+C2) during the current sensing phase when switch 406 is turned on. This difference in feedback gain complicates the frequency compensation of the operational amplifier. To solve this problem, a capacitor reset gain circuit is provided in the second embodiment of the low-side current sensing amplifier of the present invention, as shown in FIG. Figure 5A 500. By using a capacitor reset gain circuit, the feedback gain of the two stages remains the same and is approximately equal to C2 / (C1+C2) when C2 is equal to C3. Note that Figure 4A C1a+C1b=C1 in the equation. C1b is used for Figure 5A In the circuit, when switch 506 is closed (where Si = 0V), if C1b is set to half of C2, the output voltage S O Can be set to Vref / 2.

[0045] Reference now Figure 5B and Figure 5C explain Figure 5A The operation of the low-side current sense amplifier, Figure 5B and Figure 5C The electrical connections of the components of the low-side sensing circuit 500 are shown, with the switch open / closed in two operating states (ie, current sensing off or on).

[0046] First reference Figure 5B , in the reset phase, when switches 504 and 504' are on and switch 506 is off (no current sensing), the bottom C3 and its associated switch ( Figure 5A) forms an equivalent (switched capacitor) resistance. Therefore, after a few clock cycles, the bottom C1 will be charged to Vref, so Va+ is equal to Vref in the steady state.

[0047] The operational amplifier 508 can be modeled as an ideal operational amplifier with an input offset voltage Vos.

[0048] Since the top C3 closes the op amp feedback loop, Va-=Va++Vos=Vref+V OS (Note that the term “capacitor reset” used in this article stems from the fact that the op amp reset is achieved using capacitor C3.) Therefore, the voltage across C1a and C1b is equal to Vref + V OS , the voltage across the top C2 is equal to V OS .

[0049] The voltage stored on the top C3 is the output voltage S of the previous clock phase (switch 506 closed). O Subtract Vref, as from the following Figure 5C and clearly visible in Figure 5D.

[0050] The output voltage S during this clock phase (when switch 504 is on / closed) O It is not critical because the high-side power FET is assumed to be off during this clock phase and there is no need to sense the power FET current.

[0051] Now go to Figure 5C , when switch 506 is on and switches 504 and 504' are off, current sensing occurs and the sense amplifier 408 must provide the correct output value. As the input voltage on Si changes, Va+ will change. The amount of change in Va+ can be calculated based on the voltage divider formed by the bottom C1 and C2 and is given as C1 / (C1+C2)×Si.

[0052] Therefore, Va+=C1 / (C1+C2)×Si+Vref, and due to the operational amplifier feedback loop, Va-=Va++V OS =C1 / (C1+C2)×Si+Vref+V OS .

[0053] Voltage change on C1a = C1 / (C1+C2)×Si+Vref+V OS -(Vref+V OS )=C1 / (C1+C2)×Si

[0054] Voltage change on C1b = [C1 / (C1+C2)×Si+Vref+V OS -Vref]-(Vref+VOS )=C1 / (C1+C2)×Si-Vref

[0055] The voltage changes on C1a and C1b above will result in charge changes on C1a and C1b. These charge changes will be provided from the top C2 (arrows show charge flow). Therefore, the charge change on the top C2 can be written as:

[0056] C2×[(S O -Va-)-(-V OS )]=C1a×[C1 / (C1+C2)×Si]+C1b×[(C1 / (C1+C2)×Si-Vref]

[0057] In the second current sensing stage, Va-=C1 / (C1+C2)×Si+Vref+V OS And C1=C1a+C1b into the above formula:

[0058] C2×[S O -C1 / (C1+C2)×Si-Vref]=C1×[C1 / (C1+C2)×Si]-C1b×

[0059] Vref

[0060] Therefore, S O =C1 / C2×Si+(1-C1b / C2)×Vref

[0061] If C1b is selected to be half of C2, then when Si = 0V, S O will be equal to half of Vref. Other values ​​are possible by choosing different C1b and C2.

[0062] As shown above, during the current sensing phase, the offset of the operational amplifier is cancelled. Figure 5A )'s current sense amplifier gain is given as C1 / C2.

[0063] The voltage Vc3 across C3 is equal to S O - Vref. (When switch 504 is turned on, Vc3 will remain the same during the next reset phase).

[0064] High-Side Current Sensing Architecture

[0065] The present invention also includes a current sense amplifier for sensing current flowing through the high-side FET of the half-bridge circuit.

[0066] Figure 6 A half-bridge integrated circuit design with a synchronous bootstrapped high-side gate driver circuit is shown. Figure 6The half-bridge IC design 600 includes a high-side power FET 602 and a low-side power FET 612 that are controlled to supply switching power at a SW node to a load 616 connected to an inductor 618 and a capacitor 620 in a buck converter topology.

[0067] The high-side power FET 602 is driven by a high-side gate driver 604, both of which are formed in an isolation well 606. The high-side gate driver 604 receives a high-side input signal from a level converter 608, which is controlled by a logic transistor and a power-on reset (POR) circuit 610, which is in turn controlled by a high-side input control signal "Hsin" and a low-side input control signal "LSin". The low-side power FET 612 is driven by a low-side gate driver 614, which receives a control signal from a logic transistor and a power-on reset (POR) circuit 610 based on the high-side signal "Hsin" and the low-side signal "LSin". The synchronous bootstrap circuit includes a synchronous bootstrap driver 622 and a synchronous bootstrap FET 624, which charges a synchronous bootstrap capacitor 626.

[0068] When the high-side power FET 602 is on (where HS' is logic high), the current flowing through the high-side power FET 602 is sensed by the voltage across the sense resistor Rs. When the high-side power FET 602 is off, HS' is logic low, no current sensing across Rs is required.

[0069] like Figure 6 As shown, the high-side current sense amplifier 630 is implemented in a separate isolation well 608 (well 2) that is different from the isolation well 606 (well 1) used for other high-side circuit systems, as described above. The supply voltage of the high-side current sense amplifier 630 is between V ddHA With V in between.

[0070] The power supply and clock generator 640 in the first isolation well 606 is used to provide the high-side current sense amplifier 630 with respect to V in The power supply voltage (V ddHA ) and clock signal HS. Fig. 6A The circuitry of the power supply and clock generator 640 is shown in detail, which includes, in addition to the synchronous bootstrap driver 622, an additional pair of synchronous bootstrap FETs 640 and 642, and an additional bootstrap capacitor 644.

[0071] The operation of the high-side current sensing circuit is as follows. When HS' is on, the synchronous bootstrap FET 624 is on, and SW is approximately equal to V inDuring this period, the output of the synchronous bootstrap driver 622 within the power and clock generator 640 will drive node GB above the high-side supply voltage V ddF Therefore, synchronous bootstrap FETs 640 and 642 are turned on, causing the in V ddHA Will charge to approximately V ddF and SW. (Note that V ddF - SW is approximately equal to V dd ). Produced at V ddHA With V in The high-side clock signal HS swings between 1 and 2, and this clock signal is synchronized with HS'.

[0072] It is possible to implement the high-side current sense amplifier 630 in two different ways.

[0073] Figure 7 A first embodiment of the high-side current sense amplifier of the present invention is shown, which uses an off-chip PMOS. The PMOS is off-chip because PFETs are not yet available in GaN processes, which is the preferred technology for implementing integrated circuits of the present invention.

[0074] exist Figure 7 In the high-side current sensing amplifier, the reference voltage Vref (reference Vin), together with the resistor R3, is used to sense the high-side current I HS =0 provides a non-zero voltage on the current sense amplifier output SO when the HS' and HS inputs are logic high. Therefore, for a negative high-side current I HS , the current sensing output SO can still be above ground.

[0075] Vref is also used to set the op amp's input common mode relative to V in Approximately equal to Vref.

[0076] When the HS input is logic low, the high-side power FET 602 is off and there is no need to sense I HS During this period, the operational amplifier 702 is reset so that its offset voltage will be stored on C1. (Note that HSb is the inverse logic signal of HS).

[0077] When HS is logic high, the high-side power FET 602 is turned on and the high-side current I HS During this time, the operational amplifier 702, together with all resistors, external PMOS FET 704 and Vref, is used to measure the high-side current I HS The output is generated at SO. During this period, the op amp offset is cancelled.

[0078] C3 is used to adjust the operational amplifier output voltage AO Performs level shifting to control the gate voltage of the external PFET 704, which is typically lower than V when the PFET 704 is an enhancement mode GaN FET. in Since the source of PFET 704 is approximately at V in , so due to the threshold voltage of PFET 704, the gate of PFET 704 must be lower than V in , PFET 704 can be turned on.

[0079] Now refer to Fig. 7A (Reset phase, when HS input is low) and Figure 7B (Current Sensing Phase, When HS Input is High) describes the operation of the high-side current sense amplifier 630.

[0080] During the reset phase, if Fig. 7A As shown, the top C2 behaves like a (switched capacitor) resistor, and the voltage across the top C2 is approximately equal to 0V in the steady state. Therefore, C2 charges Va+ to a value relative to V in = Vref, so that the input common-mode voltage of the operational amplifier 702 will be approximately V in The voltage across the top C1 is Vref.

[0081] Due to the op amp feedback loop associated with the bottom C2 and C1, Va- = Va++V OS =Vref+V OS (About V in ). Therefore, the voltage across the bottom C1 is Vref + V OS .

[0082] The voltage stored on the bottom C2 is the op amp output voltage A during the previous current sensing phase (HS is high). O Subtract Vr, such as from Figure 7B The use of C2 to reset the op amp 702 is intended to simplify the op amp frequency compensation by making the op amp feedback gain less than 1 and equal to C2 / (C1+C2). During this phase, the voltage V across C3 is C3 is charged to V ddHA -V in .

[0083] Since the source voltage and gate voltage of FET 404 are both approximately V in , so the source-gate voltage of FET 704 is less than the threshold voltage of FET 704. Therefore, FET 704 is turned off, and the current sense output SO is 0V.

[0084] During the current sensing phase, if Figure 7B As shown, the output of the operational amplifier is connected to PFET 704 through C3, and a feedback loop is created using the operational amplifier 702, Vref, R1, and R3. O Only in V ddHA With V in The voltage stored on C3 is approximately (V ddHA -V in )) will allow op amp 702 to control the gate of PFET 704 to be below V in .

[0085] The circuit now has a similar configuration to the conventional high-side current sensing circuit of Figure 3, with the addition of Vref and R3.

[0086] Due to the feedback loop, the source voltage of PFET 704 will be set equal to the power FET drain voltage (equal to V in ). Importantly, the op amp offset voltage Vos is cancelled by the offset voltage stored on the bottom C1. Therefore, the adverse effects due to amplification of the op amp offset are minimized. In addition, the voltage across the bottom C2 is equal to A O -Vr.

[0087] Due to the feedback loop, the voltage across R1 will be equal to the voltage across Rs, which is equal to I HS ×Rs=Vin'-Vin. Therefore, the current flowing through R1 is equal to the high-side current I HS ×Rs / R1.

[0088] Including the current from the voltage reference, the current flowing to the source of PFET 704 is equal to I HS ×Rs / R1+Vref / R3, therefore, the current sensing output SO=(I HS ×Rs / R1+Vref / R3)×R2.

[0089] High-Side Current Sense Amplifier Without PMOS

[0090] Figure 8 shows a high-side current sense amplifier 800, where Figure 7 The P-MOSFET 704 of FIG. 8 is replaced by a GaN NFET 804, allowing the high-side current sense amplifier to be fully integrated in GaN technology (GaN PFETs are not yet available). However, the output of the op amp 802 must control the gate of the NFET 804, which is close to ground, and the op amp 802 can only have a current sense amplifier at V ddHa With V inThus, C3 is provided for level shifting the op amp output swing to generate a control voltage for the gate of the GaN FET 804 (which is close to ground) during the current sensing phase.

[0091] In order to generate a control voltage close to ground during the current sensing phase, a ground referenced off state SO and VB generator 806 is provided. The circuitry of the off state SO and VB generator 806 is shown in FIG. Fig. 8A In the reset phase (below Figure 8B ), the off state SO and VB generator 806 generate a bias voltage VB, so that the voltage across C3 is charged to V in -VB. This voltage is used to level shift the op amp output swing to the gate of NFET 804 so that the gate voltage is equal to A O -(V in -VB), which is close to ground.

[0092] During the reset phase, NFET 804 is turned off, as shown in FIG. Figure 8B If a non-zero current sense output SO is desired during this phase, the off-state SO and VB generator 806 is also used to provide a non-zero SO.

[0093] For full integration, R1, R2 and R3 can be implemented on chip. Matching between these resistors can be achieved.

[0094] Note that C3 is required to be a high voltage (greater than Vin) capacitor and can be implemented as an integrated GaN FET by connecting the gate and source terminals of the GaN FET to the gate of NFET 804, where the drain terminal is another capacitor terminal.

[0095] Now refer to Figure 8B (Reset phase, when HS input is low) and Figure 8C (Current Sensing Phase, When HS Input is High) describes the operation of the high-side current sense amplifier 800.

[0096] During the reset phase, if Figure 8B As shown, there is no need to sense the high-side current I HS , the operational amplifier is connected with Fig. 7A The operational amplifier offset voltage V OS Stored on the bottom C1, C3 is charged between Vin and VB.

[0097] Although VB can be set to ground, VB is selected to be a gate-source voltage Vgs above ground, as determined by the off state SO and FET 808 in VB generator 806. The advantages of this will be discussed below with respect to Figure 8C (current sensing phase) becomes apparent in the discussion of FIG.

[0098] FET 812, FET 814 and R5 in the off state SO and VB generator 806 will generate a voltage on SO equal to the gate-source voltage (Vgs) of FET 812 during this phase (reset).

[0099] Since SO is equal to Vgs of FET 812, and gate voltage (VB) of FET 804 is equal to Vgs of FET 808, Vgs of FET 804 will be very small and less than the threshold voltage of FET 804. Therefore FET 804 will be off, and SO is determined by the off state SO and VB generator 806.

[0100] During the current sensing phase, if Figure 8C As shown, the operational amplifier output AO controls the voltage at the gate of FET 804 through C3. As a result, a feedback loop consisting of operational amplifier 814, Vref, FET 804, R1 and R3 is formed.

[0101] Due to this feedback loop, the drain voltage of FET 804 will be set equal to the power FET 602 drain voltage (equal to Vin). Importantly, the op amp offset voltage Vos is cancelled by the offset voltage stored on the bottom C1. Thus, the undesirable amplification of the op amp offset is minimized.

[0102] Due to this feedback loop, the voltage across R1 will be equal to the voltage across Rs, which is equal to I HS ×Rs=Vin'-Vin. Therefore, the current flowing through R1 is equal to I HS ×Rs / R1.

[0103] Including the current from the voltage reference, the current flowing to the drain of FET 804 is equal to I HS ×Rs / R1+Vref / R3, so the current sensing output SO=(I HS ×Rs / R1+Vref / R3)×R2.

[0104] Since AO can have a swing between VddHA and Vin, the current sense output SO can have a swing between VddHA -Vin+VB-VgsN and Vin-Vin+VB-VgsN, including the voltage drop VgsN across C3 and the Vgs of FET804. Note that VddHA-Vin is approximately equal to Vdd (paragraph

[0070] above). Then SO can swing between Vdd+VB-VgsN and VB-VgsN. Since SO cannot swing below ground, the actual swing on SO is between Vdd+VB-VgsN and ground (i.e., less than Vdd when VB=0V).

[0105] By setting VB to a Vgs (approximately equal to VgsN) instead of 0 V, the swing on SO becomes approximately between Vdd and ground. Thus, setting VB to a Vgs, instead of 0 V, allows the SO to have a swing of the full supply voltage (ie, Vdd).

[0106] High-Side Current Sense Amplifier with Sense FET

[0107] Fig. 9 The architecture of an alternative embodiment of the high-side current sense amplifier of the present invention is shown in which the high-side current through the high-side power FET 902 is sensed using FET 950 rather than a sense resistor.

[0108] Assume that the width-to-length ratio between the high-side FET 902 and the sense FET 950 is K:1, where K is a large number (eg, K=10,000).

[0109] If the high-side power FET 902 is matched with the sense FET 950 and their terminal voltages (gate voltage, drain voltage, and source voltage) are the same, the drain current H flowing through the high-side FET 902 is IS will be K times smaller than the drain current flowing through the high side FET 902 .

[0110] Reference now Fig.10 , the high-side current sense amplifier 930 is used to: (a) convert the current flowing through the high-side power FET 902 into a voltage output at SO; and (b) when the high-side FET 902 is turned on (where HS' is at logic high), keep the source voltage of the sense FET 950 the same as the voltage on the SW node.

[0111] For HS' at logic high, the switches connected to the high-side current sense amplifier 930 inputs A and B are switched to the current sense phase ( Fig. 10B ). For HS' at logic low, the switches connected to A and B are off and the high-side current sense amplifier 930 is in the reset phase ( Fig. 10A ).

[0112] The off state SO and VB generator 1006 and Fig. 8A The off state SO and VB generators 806 are shown identical and function as described with respect to Fig. 8A described.

[0113] The switches connected to A and B are shown as two FETs (HSb) controlled by HS'.

[0114] HS is referenced to Vin and is powered by the power and clock generator 940 ( Fig. 9 HSb is the inverse logic signal of HS.

[0115] As combined Figure 8 As described, C3 is introduced for level shifting the op amp output swing, thereby generating a control voltage to the gate of FET 1004 that is close to ground during the current sensing phase.

[0116] C3 needs to be a high voltage (greater than Vin) capacitor. Figure 8 As described, for full integration, C3 can be implemented as an integrated GaN FET by connecting its gate and source terminals to the gate of FET 1004, where the drain terminal is another capacitor terminal.

[0117] As combined Figure 7 As mentioned above, when the high-side current I HS When HS' and HS are logic high, the reference voltage Vref is used together with Rr to provide a non-zero voltage at the current sense amplifier output SO. Therefore, for negative I HS , SO can still be above ground. Vref is also used to set the input common mode of the op amp to approximately Vref relative to Vin.

[0118] Reference now Fig. 10A , during the reset phase, there is no need to sense I HS , and the operational amplifier is combined as Fig. 7A and Figure 8B The described is reset.

[0119] As mentioned before, in the stable phase, Va+ is equal to Vref relative to Vin, and Va- is equal to Vref+Vos relative to Vin. OS will be stored on the bottom C1.

[0120] C3 is charged to a voltage between Vin and VB. Although VB can be set to ground, VB is preferably selected to be one gate-source voltage Vgs above ground, as determined by the off state SO and FET 1008 of VB generator 1006. This has the advantage of combining Figure 8C Described below. Fig. 10B Also described.

[0121] During this phase, the FETs 1012, 1014 and R5 in the off state SO and VB generator will produce a voltage on SO equal to the Vgs of FET 1012.

[0122] Since SO is equal to Vgs of FET 1012, and the voltage at the gate of FET 1004 (VB) is equal to Vgs of FET 1008, Vgs of FET 1004 will be very small and less than the threshold voltage of FET 1004. Therefore, FET 1004 will be turned off, and SO is determined by the off state SO and VB generator 1006.

[0123] refer to Fig. 10B During the current sensing phase, the output AO of the operational amplifier 1002 controls GN through C3. As a result, a feedback loop consisting of the operational amplifier 1002, Vref, FET 1004 and Rr is formed. The off state SO and VB generator 1006 are turned off and will not affect SO.

[0124] Due to the feedback loop, the source voltage of the high side FET 950 at node C will be set equal to the source voltage of the power FET ( Fig. 9 and Fig.10 =The source voltage of FET 902 in the circuit is equal to the voltage at SW. Note that the op amp offset voltage Vos is cancelled by the offset voltage stored on the bottom C1. Therefore, the adverse effects caused by the amplification of the op amp offset are minimized. Since all terminal voltages of FETs 902 and 950 are matched, I HS Will be less than K times the drain current flowing through FET 902.

[0125] I HS Together with the current from the voltage reference (equal to Vref / Rr), it will flow through FET 1004 to Ro. Therefore, the output SO of the high-side current sense amplifier 1002 will be equal to I HS ×Ro+Vref / Rr×Ro.

[0126] As combined Figure 8C As described above, by setting VB to a Vgs (approximately equal to the gate-to-source voltage of FET 1004) instead of 0 V, the swing on SO becomes approximately between Vdd and ground. Therefore, setting VB to a Vgs instead of 0 V allows SO to have a swing of the full supply voltage (i.e., Vdd).

[0127] The integrated current sensing amplifier with offset cancellation of the present invention, in its various embodiments described above, has the following features and advantages:

[0128] 1. As in the present invention, the current sensing amplifier is integrated with the gate driver and the power FET, reducing off-chip components. Therefore, the integrated current sensing amplifier of the present invention reduces cost and PCB space.

[0129] 2. In GaN technology, due to the lack of GaN PFET, large V T Drift and big V T Mismatch, integrated current sensing amplifier is very difficult. The latter two factors lead to large amplifier offset voltage, which can have a significant adverse effect on the accuracy of the current sensed on the power FET. In order to reduce the amplifier offset, the current sensing circuit system of the present invention uses the power FET off time to store the offset on the capacitor. The stored offset is then used to eliminate the amplifier offset during the power FET on time (which is the time interval that current sensing is required).

[0130] 3. For high-side current sensing, an off-chip PFET can be used to transfer the sense current to a ground reference resistor. Alternatively and preferably, the present invention provides a high-side current sense amplifier that does not require a PFET and can therefore be implemented entirely in GaN technology.

[0131] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments should be considered merely illustrative and not restrictive in any sense. Therefore, the scope of the present invention is indicated by the appended claims rather than by the foregoing description. All changes falling within the meaning and equivalent scope of the claims should be included within the scope of the claims.

Claims

1. A current sensing amplifier for sensing a current flowing through a power FET, comprising: a current sensing circuit connected to a current sensing resistor connected in series with the power FET, wherein the current sensing circuit includes an operational amplifier having an input offset voltage, a plurality of switches, and a plurality of capacitors; The current sensing circuit is configured as follows: (i) storing the input offset voltage of the operational amplifier during a first phase when the power FET is turned off, and (ii) during a second phase when the power FET is turned on, sensing the current flowing through the power FET by measuring the voltage across the resistor, The stored input offset voltage of the operational amplifier is used to cancel the input offset voltage of the operational amplifier during the second stage when the power FET is turned on and the current is sensed.

2. The current sense amplifier of claim 1, wherein the power FET is a low-side power FET of a half-bridge circuit.

3. The current sense amplifier of claim 1, wherein the power FET is a high-side power FET of a half-bridge circuit.

4. The current sensing amplifier of claim 2 , wherein during the first phase, the current sensing circuit has a first feedback gain, and during the second phase, the current sensing circuit has a second feedback gain, and wherein the current sensing circuit includes a capacitor reset gain circuit for maintaining the first feedback gain equal to the second feedback gain.

5. The current sensing amplifier of claim 3 , further comprising a capacitor connected to the output of the operational amplifier, the capacitor being used to level-shift the output voltage of the operational amplifier to control the gate voltage of a FET connected to the output of the current sensing amplifier so that the gate voltage of the FET is lower than an input voltage and the output of the current sensing amplifier is referenced to ground.

6. The current sense amplifier of claim 5 implemented in an integrated circuit using GaN technology.

7. The current sense amplifier of claim 6 wherein the FET is a PMOSFET external to the integrated circuit.

8. The current sense amplifier of claim 6, wherein the FET is an enhancement mode GaN FET integrated in the integrated circuit.

9. The current sense amplifier of claim 5, wherein the current sense resistor is implemented by a FET.

10. The current sense amplifier of claim 5 implemented in an integrated circuit using GaN technology, wherein the integrated circuit includes a power supply and clock generator for generating a clock signal and a supply voltage to the current sense amplifier.

11. The current sense amplifier of claim 8 further comprising circuitry for generating a non-zero current sense output voltage during the first phase when the power FET is off and for generating a voltage for charging the capacitor.

12. An integrated circuit comprising a half-bridge circuit, the half-bridge circuit comprising a low-side power FET, a high-side power FET, and the current sensing amplifier of claim 1 for sensing a current flowing through the low-side FET or the high-side FET.

13. The integrated circuit of claim 12, implemented entirely in GaN technology.

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