Universal power FET driver IC architecture

Abstract

A gate driver circuit integrates a synchronous bootstrap circuit in an isolated well of an integrated circuit such that synchronous bootstrap capacitors connected to the synchronous bootstrap circuit (and to respective switching nodes of a power converter) can be floated with the respective switching nodes. Due to this feature, the voltage on one synchronous bootstrap capacitor may be used to charge the synchronous bootstrap capacitor of another (higher level) synchronous bootstrap circuit in the separate isolated wells connected to the different switching nodes. Therefore, the supply voltages of the synchronous bootstrap circuits in different isolated wells can be provided from a single ground reference supply Vdd.

Description

Background Art

[0001] Half-bridge integrated circuits typically use a high-side field effect transistor (FET) gate driver that implements a bootstrap circuit for providing an elevated voltage higher than the power supply voltage to the gate terminal of the high-side FET. Specifically, the bootstrap circuit utilizes a bootstrap capacitor that is charged during the low-side FET of the half-bridge is in the on state (when the SW terminal is shorted to ground) while the high-side FET is in the off state. When the low-side FET is turned off and the high-side FET is turned on, the voltage stored in the bootstrap capacitor will be applied to the gate terminal of the high-side FET. However, this architecture is not suitable for certain power converter topologies, such as multi-level converters, because the upper-level SW node in the multi-level converter is not switched to ground. If the SW node does not bring the low-side electrode of the bootstrap capacitor to ground, the bootstrap capacitor will not be fully charged, and the gate terminal of the high-side FET will not reach a voltage greater than the power supply voltage, thereby failing to put the high-side FET in the on state, thereby allowing the half-bridge circuit to operate normally. Therefore, a power FET driver that can be used in a multi-level power converter topology is needed.

[0002] FIG1 is a conventional half-bridge integrated circuit (IC) design with a synchronous bootstrap high-side gate driver circuit. The half-bridge IC design 100 of FIG1 includes a high-side FET 102 and a low-side FET 112 that are controlled to provide switching power at a SW node to a load 116 connected to an inductor 118 and a capacitor 120 in a buck converter topology.

[0003] The high-side FET 102 is driven by a high-side gate driver 104, both of which are formed in an isolation well 106. The high-side gate driver 104 receives a high-side input signal from a level shifter 108, which is controlled by a logic converter and a power-on reset (POR) circuit system 110, which is in turn controlled by a high-side input control signal "HSin" and a low-side input control signal "LSin". The low-side FET 112 is driven by a low-side gate driver 114, which receives a control signal from the logic converter and the POR circuit system 110 based on the high-side signal "HSin" and the low-side signal "LSin".

[0004] In the half-bridge IC circuit of FIG1 , the power supply voltage of the high-side circuit elements (including the level converter 108 and the high-side gate driver 104) is provided by a synchronous bootstrap circuit, which includes a bootstrap capacitor 122 and a bootstrap diode 112. When the high-side input signal “HSin” is at a logic level 0, the high-side FET 102 is turned off, and the low-side input signal “LSin” is at a logic level 1, the low-side FET 112 is turned on, the bootstrap capacitor 122 is connected to the power supply voltage V by the diode 124. dd Therefore, the SW node switches to ground, and the bootstrap capacitor 122 is charged through the diode 112 to obtain a voltage V dd minus the diode voltage drop across it. This again produces a voltage V ddF , which is higher than the voltage V at the SW node dd Subtract the diode voltage drop. When “HSin” is at logic level 1, V ddF Make sure that the gate-to-source voltage of the high-side FET 102 is high enough to turn on the transistor.

[0005] The half-bridge IC design 100 of FIG. 1 is not suitable for all power converter topologies. Specifically, the half-bridge design 100 cannot be used for multi-level power converters because the SW node is not always switched to ground in such topologies. Therefore, the synchronous bootstrap capacitor 122 cannot be connected by V dd fully charged, and the half-bridge IC design 100 may not function properly. In addition, charging the synchronous bootstrap capacitor 122 through the diode 112 reduces V ddF , which is due to the voltage drop associated with diode 112. To address the latter issue, in the half-bridge IC design of FIG. 2 , diode 124 ( FIG. 1 ) is replaced with a synchronous bootstrap FET 240, which is driven by a synchronous bootstrap driver 242, which is controlled by the logic converter and POR circuitry 210.

[0006] In the synchronous bootstrap circuit of FIG. 2 , the voltage drop associated with diode 112 of FIG. 1 is eliminated, so that V ddF -V SW ~V dd However, as with the circuit of FIG1, the synchronous bootstrap driver 242 must have a voltage greater than V dd The output logic 1 voltage of 100A is required to turn on the high-side FET 202. Therefore, like the half-bridge IC design 100 depicted in FIG. 1 , the half-bridge IC design 200 shown in FIG. 2 cannot be implemented in a multi-level power converter.

[0007] FIG3 is a circuit diagram showing a synchronous bootstrap driver 300 suitable for GaN technology. The synchronous bootstrap driver 300 disclosed in U.S. Patent No. 9,667,245 includes a FET 304 and a capacitor 306. When the low-side gate driver 314 is at a logic level 0 (0V), the capacitor 306 is charged to a value close to V dd -V th , where V th is the threshold voltage of FET 304. When the low-side gate driver 308 is at logic level 1 (V dd ), the synchronous bootstrap voltage V at the gate of the synchronous bootstrap FET 320 SB About 2V dd -V th Therefore, the gate of synchronous bootstrap FET 320 is connected to the gate-source voltage V dd -V th However, due to the threshold voltage V th can vary by relatively large amounts, so the gate-source voltage V dd -V th may not be sufficient to turn on the synchronous bootstrap FET 320 .

[0008] Therefore, there is a need to provide a power FET driver that can overcome the above-mentioned disadvantages of the prior art and can be universally implemented without the above-mentioned disadvantages. In particular, there is a need to provide a power FET driver IC that can be universally implemented to drive a power FET in any power FET driver topology. Summary of the invention

[0009] The present invention overcomes the above-mentioned disadvantages and achieves the above-mentioned objects by providing a power FET driver architecture that can be universally implemented in any power FET driver topology.

[0010] More specifically, as described herein, the present invention is a gate driver circuit that integrates a synchronous bootstrap circuit in an isolated well of an integrated circuit such that a synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to a corresponding switch node of a power converter) can be floated with the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrap capacitor can be used to charge a synchronous bootstrap capacitor of another (higher level) synchronous bootstrap circuit in a separate isolated well connected to a different switch node. Thus, the supply voltages of the synchronous bootstrap circuits in different isolated wells can all be derived from a single ground reference supply, V dd Thus, the present invention can be used to implement various power converter topologies, including multi-level converters.

[0011] Additional features and advantages of the present invention will be described in the following description, some of which will be apparent from the description or will be understood through the practice of the present invention. The features and advantages of the present invention may be realized and obtained by the means and combinations specifically indicated in the appended claims. These and other features of the present invention will become more apparent from the following description and the appended claims or will be understood through the practice of the present invention as described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Advantages and features of the present invention will become apparent when the following description of the preferred embodiments of the present invention is read in conjunction with the accompanying drawings, in which:

[0013] FIG1 is a conventional half-bridge buck converter with a synchronous bootstrap circuit;

[0014] FIG2 is a conventional half-bridge buck converter with synchronous bootstrap FETs;

[0015] Figure 3 shows a synchronous bootstrap driver suitable for GaN technology;

[0016] Figure 4 A general power FET driver circuit of the present invention is shown;

[0017] Figure 5 A buck converter implementation of the general power FET driver circuit of the present invention is shown;

[0018] Figure 6 yes Figure 5 The timing diagram of the circuit;

[0019] Figure 7 A three-level power converter IC using multiple universal power FET driver circuits of the present invention is shown;

[0020] Fig. 8A and Figure 8B yes Figure 7 The timing diagram of the circuit;

[0021] Fig. 9 The synchronous bootstrap driver of the present invention is shown incorporated in a cascade type topology;

[0022] Fig.10 Shows Fig. 9 a variation of the circuit of wherein two bootstrap capacitors and two FETs are incorporated; and

[0023] Fig.11 shows a wide switching range Fig.10 Variation of the circuit. DETAILED DESCRIPTION

[0024] It should be understood that the drawings and description of the present invention may have been simplified to illustrate only the elements relevant to a clear understanding of the present embodiments. Those of ordinary skill in the art will recognize that other elements may be desired and / or required in order to implement these embodiments. It should also be understood that the drawings included herein only provide schematic diagrams of the presently preferred embodiments of the present invention. Reference will now be made to the accompanying drawings, in which similar structures have the same reference numerals.

[0025] Figure 4 The basic architecture of the universal power FET driver IC of the present invention is shown. The universal power FET driver IC 400 includes the power FET gate driver circuit 401 of the present invention disposed in an isolation well, which is controlled by a logic converter and power-on reset circuit system 414, and a level converter 412 (whose receiver is disposed in the isolation well). The isolation well is formed by a known process and provides electrical isolation from other semiconductor circuit elements in the IC. The circuit elements of the gate driver of the present invention, namely the synchronous bootstrap FET 402, the power FET 404, the gate driver 406 for driving the power FET 404, the synchronous bootstrap gate driver 408 for driving the synchronous bootstrap FET 402, the NAND gate 410, and the receiver of the level converter 412, are all integrated in a single isolation well. In a preferred embodiment of the present invention, the synchronous bootstrap gate driver of the present invention is implemented using GaN technology.

[0026] In operation of the power FET driver IC of the present invention, the logic converter / power-on reset circuit system 414 receives the input control signal "in" and generates a corresponding control signal to the level converter 412. The level converter 412 generates a level-shifted logic 0 output or a level-shifted logic 1 output based on the input control signal "in". The logic 0 or logic 1 output of the level converter 412 is provided as an input to the logic gate 410 and the gate driver 406.

[0027] When the level shifter 412 generates a logic 1, FET 404 is turned on and V H Short circuit to V L .exist Figure 4 In the basic circuit shown, V L ground, so turning on FET 404 will pull V H Both inputs of NAND gate 410 also receive logic 1, causing NAND gate 410 to generate a logic 0, which is input to synchronous bootstrap gate driver 408, causing gate driver 408 to generate a logic 1 to the gate of FET 402. As a result, FET 402 is turned on, and synchronous bootstrap capacitor C SB From the power supply voltage V ddF Charge.

[0028] When the level shifter 412 generates a logic 0, FET 404 is turned off and V H With V L The two inputs of NAND gate 410 also receive logic 0, causing the NAND gate to generate a logic 1, which is input to synchronous bootstrap gate driver 408, which generates a logic 0 to the gate of FET 402. As a result, FET 402 is turned off and the current stored in synchronous bootstrap capacitor C SB The voltage V F Can be used to power similar gate drive circuits in different isolated wells, such as Figure 5 and Figure 7 shown. Figure 4 This feature of the circuit makes it widely usable in architectures suitable for implementing power converters with many different topologies, including multi-level converters.

[0029] NAND gate 410 is used to turn off synchronous bootstrap driver 408 in advance before power FET 404 turns off and delay turning on synchronous bootstrap driver 408 after power FET 404 turns on. The NAND gate thus prevents overcharging of the synchronous bootstrap capacitor during the dead time of the power converter.

[0030] Figure 5 is used Figure 4 Two general purpose power FET driver ICs and synchronous bootstrap capacitor C SB1 The low-side power FET driver integrated circuit 500a (bottom) includes a low-side power FET 504a and receives a low-side input control signal "LSin". The high-side power FET driver integrated circuit (top) includes a high-side power FET 504b and receives a high-side input control signal "HSin". The low-side synchronous gate driver circuit 501a (which includes a synchronous bootstrap FET 502a, a synchronous bootstrap gate driver 508a and a power FET 504a) is set in an isolation well 1 and is driven by a power supply voltage V dd The high-side synchronous gate driver circuit 501b (which includes the synchronous bootstrap FET 502b, the synchronous bootstrap gate driver 508b and the power FET 504b) is arranged in the isolation well 2 and is powered by the voltage V on the synchronous bootstrap capacitor. F1 powered instead of by V dd Therefore, the voltage stored on the synchronous bootstrap capacitor in the isolation well 2 is charged by the voltage stored on the synchronous bootstrap capacitor in the isolation well 1.

[0031] Figure 6 yes Figure 5In condition cl, when a logic 1 is provided as the low-side input signal "LSin" and a logic 0 is provided as the high-side input signal "HSin", both the synchronous bootstrap FET 502a and the low-side power FET 504a are turned on, and the synchronous bootstrap capacitor C SB1 Charge to V dd .

[0032] Under condition c2, the control input is switched to provide a logic 0 as the low-side input signal "LSin" and a logic 1 as the high-side input signal "HSin". The low-side synchronous bootstrap FET 502a and the low-side power FET 504a are both turned off, while the high-side synchronous bootstrap FET 502 and the high-side power FET 504b are both turned on, which increases V in Shorted to the switch node SW, thus driving the load. Bootstrap capacitor C SB1 The voltage on the F1 , including the input voltage V in and the stored supply voltage V dd The additive combination of , which powers the gate driver circuit 506b in the isolation well 2.

[0033] Condition c3 is basically the same as condition cl, with the synchronous bootstrap capacitor C SB1 Once again by V dd Recharge, and the cycle repeats.

[0034] Figure 7 A three-level buck power converter 700 is shown, which includes four Figure 4 The power FET driver circuit 400, three synchronous bootstrap capacitors C SB1 , C SB2 , C SB3 and capacitor C M .although Figure 7 Four power FET driver circuits 400 are depicted to form a three-level converter, but Figure 4 Any multiple N of the power FET driver circuit 400 depicted in FIG. Figure 7 The implementation shown is to form a (N-1) level shifter.

[0035] like Figure 7 As shown, the synchronous bootstrap capacitor C SB1 , C SB2 and C SB3 The voltage on the capacitor C provides a power supply voltage for the synchronous gate driver circuits 701b, 701c and 701d respectively arranged in the isolation wells 2, 3 and 4, and these synchronous gate driver circuits drive the corresponding power FETs 704b, 704c and 704d. MOne side of the capacitor C is connected to the drain of FET 704a and the source of FET 704b, and the other side is connected to the drain of FET 704c and the source of FET 704d. M In a three-level power converter, approximately V in / 2 three-level voltage level.

[0036] Fig. 8A and Figure 8B is a timing diagram showing Figure 7 The three bootstrap capacitors C in the three-level converter SB1 , C SB2 and C SB3 The charging and corresponding charging voltage V F1 、V F2 and V F3 and the switch node voltages SW1, SW2, and SW3, where the duty cycle is less than 50% ( Fig. 8A ) and duty cycle greater than 50% ( Figure 8B ).

[0037] exist Fig. 8A For the conditions in the first column, both in1 and in2 are on. Therefore, the outputs of drivers 708a and 708b are at logic 1. Therefore, C SB1 will be passed through FET 702a by V dd Charging, while C SB2 will pass through FET 702b by V F1 For the conditions in the second column, only in2 is on. Therefore, only the output of driver 708b is at logic 1. Therefore, C SB2 will pass through FET 702b by V F1 For the condition in the third column, both in1 and in2 are on, similar to the condition in the first column. Therefore, the outputs of drivers 708a and 708b are at logic 1. Therefore, C SB1 will be passed through FET 702a by V dd Charging, while C SB2 will pass through FET 702b by V F1 For the condition in the fourth column, in1 and in3 are on. Therefore, the outputs of drivers 708a and 708c are logic 1. As a result, C SB1 will be passed through FET 702a by V dd Charging, while C SB3 will pass through FET 702c by V F2 The conditions in the fifth column are essentially the same as those on the first column, and the cycle repeats.

[0038] exist Figure 8BFor the conditions in the first column, in3 is on. Therefore, the output of driver 708c is a logic 1. As a result, C SB3 will pass through FET 702c by V F2 For the condition in the second column, in2 is on. Therefore, the output of driver 708b is a logic 1. As a result, C SB2 will pass through FET 702b by V F1 For the condition in the second column, in3 is on, similar to the condition in the first column. Therefore, the output of driver 708c is a logic 1. As a result, C SB3 will pass through FET 702c by V F2 For the conditions in the fourth column, both in1 and in3 are on. Therefore, the outputs of drivers 708a and 708c are logic 1. As a result, C SB1 will be passed through FET 702a by V dd Charging, while C SB3 will pass through FET 702c by V F2 The conditions on the fifth column are essentially the same as those on the first column, and the cycle repeats.

[0039] Fig. 9 A cascade type active bootstrap topology 900 of a synchronous bootstrap driver circuit for a universal power FET driver of the present invention is shown. Fig. 9 The cascade type active bootstrap gate driver circuit 901 is connected to the capacitor C D Drives the gate of synchronous bootstrap FET 902. This circuit can be used for synchronous bootstrap gate driver 408 (in Figure 4 ), synchronous bootstrap gate drivers 508a and 508b (in Figure 5 ) and synchronous bootstrap gate drivers 708a, 708b, 708c and 708d (in Figure 7 middle).

[0040] Fig. 9 The cascade-type active bootstrap gate driver topology combines the active bootstrap gate driver circuit disclosed in U.S. Patent Application Publication No. 2023 / 0179203 and the cascade-type bootstrap gate driver circuit disclosed in U.S. Patent No. 10,790,811.

[0041] As described in detail in U.S. Patent No. 10,790,811, a cascaded bootstrap gate driver circuit (preferably implemented with GaN FET transistors) can quickly turn on the high-side power FET and reduce quiescent current consumption during the transistor off period. The initial bootstrap stage (left side) includes FET 903n, capacitor C Bnand resistor 906 (resistor 906 can reduce the quiescent current consumption during the transistor off period). B1 , C B2 ), the resistor 906 in the initial bootstrap stage is replaced by FETs (ie, FETs 905a, 905b).

[0042] In an active topology, as described in U.S. Patent Application Publication No. 2023 / 0179203, active charging FETs (903, 903a, 903b ... 903n) are used instead of diodes or diode-connected FETs in conventional bootstrap drivers to transfer the current stored in the first bootstrap capacitor C D The voltage on the high side (pull-up) FET 902 for turning on the driver is charged to the full supply voltage. The gate voltage of the active charging FET is provided by the bootstrap capacitor (C B1 , C B2 ...C Bn ) is bootstrapped to a voltage higher than the supply voltage. When the input is a logic 0 (low), the previous bootstrap capacitor is charged by the FETs (903a, 903b, 903n) connected to the supply voltage.

[0043] The operation of the active cascode-type bootstrap gate driver 900 will now be described.

[0044] When the input “in” is logic 1 (which is equal to V ddF -V L ), capacitor C D By FET M DI Charge to about V ddF -V L , because the gates of FET 903 and FETs 903a-903n are driven to approximately V by capacitor C1 ddF -V L Note that capacitor C1 is recharged by FET903 to approximately V ddF -V L , when the input "in" is logic 0, the voltage V DI Equal to about 2·(V ddF -V L ).

[0045] When the input "in" is a logic 0, the output of the cascaded bootstrap gate driver at the drain of FET 907a is a logic 1 (which is equal to approximately V ddF -V L ), and the gate voltage V SB About 2·(V ddF -V L). Therefore, the gate-source voltage V GS About V ddF -V L Therefore, the synchronous bootstrap FET 902 can F Drive to about V ddF .

[0046] Fig.10 shows a synchronous bootstrap driver circuit 1000, which is similar to Fig. 9 The synchronous bootstrap driver circuit 900 is modified to replace the bootstrap capacitor C B1 and C D Combined into a single bootstrap capacitor C MERGE , and merge FETs 903 and 903a into a single FET 1003. Fig. 9 The incorporation of the above capacitor and FET circuit is possible because V DI and V SB is roughly the same, since they both pass through the bootstrap capacitor C B1 and C D Driven by the same cascaded bootstrap driver output. Therefore, the synchronous bootstrap FET 1002 can be driven directly by the cascaded bootstrap driver as shown.

[0047] Fig.11 Shows Fig.10 An improvement of a combined synchronous bootstrap driver circuit having a wide switching range. Fig.11 The combined synchronous bootstrap driver circuit 1100 is similar to Fig.10 1000 , but the gate of the synchronous bootstrap FET 1102 is connected to the gate of the FET 1104.

[0048] In some cases, during the dead time period of the power converter, the switch node SW n may swing to a value greater than V L In this case, it may be necessary to turn off the synchronous bootstrap FET 1102 before the dead time period begins, and the gate terminal voltage V SB It may also be necessary to have a voltage close to V L The shutdown voltage is set to prevent the synchronous bootstrap capacitor C from being SBn By connecting the gate of synchronous bootstrap FET 1102 to the gate of FET 1104, the gate terminal voltage V SB The voltage swing will be between about 2·(V ddF -V L ) and will be 0V (referenced to VL ).therefore, Fig.11 The circuit minimizes the possibility of turning on the synchronous bootstrap FET 1102 during the dead time period.

[0049] In summary, the universal power FET driver IC of the present invention integrates a synchronous bootstrap circuit in the isolation well of the driver IC. The architecture of the present invention allows the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and the corresponding switch node connected to the power converter) to float using the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrap capacitor can be used to charge the synchronous bootstrap capacitor of another synchronous bootstrap circuit in an independent isolation well connected to a different switch node. Therefore, the power supply voltage of the synchronous bootstrap circuits in different isolation wells can all be provided from a single ground reference power supply. This allows the universal power FET driver IC architecture of the present invention to be used to implement various power converter topologies, including multi-level converters, in which the switch nodes of the power converter are not all switched to ground.

[0050] In order to reduce the voltage drop of the power supply voltage of the synchronous gate driver circuit in the isolation well, a cascade type active bootstrap driver topology may be used to drive the synchronous bootstrap FET.

[0051] The synchronous bootstrap driver of the present invention is particularly suitable for implementation in GaN technology using GaN FETs.

[0052] The present invention may be implemented in other specific forms without departing from its spirit or essential characteristics. The described embodiments should be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than the foregoing description. All changes in the equivalent meaning and scope of the claims should be included within their scope.

Claims

1. A gate driver integrated circuit comprising a synchronous bootstrap circuit, the synchronous bootstrap circuit comprising a synchronous bootstrap gate driver and a synchronous bootstrap FET driven by the synchronous bootstrap gate driver, wherein the synchronous bootstrap FET is configured to charge a synchronous bootstrap capacitor connected to the synchronous bootstrap circuit, and wherein the synchronous bootstrap circuit is integrated in an isolation well of the gate driver integrated circuit so that the synchronous bootstrap capacitor can be floated using a corresponding switch node of a power converter.

2. The gate driver integrated circuit of claim 1 , wherein the synchronous bootstrap gate driver is driven by a NAND gate in the isolation well, wherein the NAND gate receives: (i) an output of a gate driver for driving a power FET and (ii) a level shifter for level shifting an input logic signal.

3. The gate driver integrated circuit according to claim 1, implemented using GaN technology.

4. The gate driver integrated circuit of claim 2 further comprising a logic converter and a power-on reset (POR) circuit system, wherein the level converter receives an input signal from the logic converter and the POR circuit system and outputs the level-converted input signal to the synchronous bootstrap circuit. 5 . The gate driver integrated circuit of claim 1 , wherein the synchronous bootstrap circuit comprises a cascade type synchronous bootstrap gate driver circuit.

6. A power integrated circuit comprising a plurality of synchronous bootstrap circuits according to claim 1, wherein each of the plurality of synchronous bootstrap circuits is integrated in an independent isolation well, and wherein a voltage stored on a synchronous bootstrap capacitor connected to the synchronous bootstrap circuit in one isolation well charges another synchronous bootstrap capacitor connected to another synchronous bootstrap circuit in a different isolation well.

7. The power integrated circuit according to claim 6 comprises two synchronous bootstrap circuits according to claim 1 located in independent isolation wells, wherein one of the two synchronous bootstrap circuits is a low-side synchronous bootstrap circuit and the other of the two synchronous bootstrap circuits is a high-side synchronous bootstrap circuit, wherein the low-side synchronous bootstrap circuit receives a low-side signal for controlling a low-side power FET of a half-bridge circuit and the high-side synchronous bootstrap circuit receives a high-side signal for controlling a high-side power FET of the half-bridge circuit, and wherein a synchronous bootstrap capacitor connected to the corresponding switching nodes of the low-side synchronous bootstrap circuit and the power converter can be floated using the corresponding switching nodes so that the voltage stored on the synchronous bootstrap capacitor can be used to power the high-side synchronous bootstrap circuit.

8. The power integrated circuit according to claim 6 is implemented using GaN technology.

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