Timestamp at parallel interface of serDes coupling PHY with physical transmission medium

Abstract

One or more examples generally relate to timestamps at a parallel interface of SerDes for coupling a PHY with a physical transmission medium. In one example, an apparatus includes: a SerDes to couple a PHY to a physical transmission medium; a hardware timestamp logic component; a bit detector coupled to launch the hardware timestamp logic at least in part in response to observing the indicated bit at a parallel interface of the SerDes; and a logic circuit disposed at a portion of the PHY, the logic circuit coupled to receive the timestamp generated by the hardware timestamp logic component.

Description

[0001] Cross-references to related patent applications

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 367,286, filed on June 29, 2022, entitled “HIGH-ACCURACY ETHERNET PTP TIMESTAMP WITHOUTPATH ​​DATA DELAY MEASUREMENT,” under 35 U.S.C. §119(e), the contents and disclosure of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more examples generally relate to departure and arrival timestamping for Ethernet packets. One or more examples generally relate to departure and arrival timestamping at a serial / deserializer (SerDes) interface. Background Art

[0004] Packet arrival and departure times are used in various operational contexts, including but not limited to synchronizing time across a network. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or action, the most significant digit(s) in the drawing reference numbers refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram illustrating an apparatus for SerDes timestamping indicated bits according to one or more examples.

[0007] Figure 2 is a block diagram illustrating an apparatus for adding indicated bit positions to outgoing data according to one or more examples.

[0008] Figure 3 is a block diagram depicting an apparatus for adding indicated bit positions to incoming data according to one or more examples.

[0009] Figure 4 is a block diagram depicting an apparatus for changing an indication in incoming data from an arbitrary bit to a specific bit, according to one or more examples.

[0010] Figure 5 is a schematic block diagram of a system according to one or more examples.

[0011] Figure 6 is a flow diagram depicting a process for SerDes timestamping indicated bit positions according to one or more examples.

[0012] Figure 7 is a flow diagram depicting a process for adding indicated bit positions to outgoing data according to one or more examples.

[0013] Figure 8 is a flow diagram depicting a process for adding indicated bits to incoming data according to one or more examples.

[0014] Fig. 9 is a flow diagram depicting a process for generating a timestamp in response to observing an indicated arbitrary bit position, according to one or more examples.

[0015] Fig.10 is a flow diagram depicting a process for calculating an Rx adjustment value according to one or more examples.

[0016] Fig.11 is a flow diagram depicting a process for generating a timestamp in response to observing an indicated bit position, according to one or more examples.

[0017] Fig.12 is a diagram of example groupings including indicated bit positions according to one or more examples.

[0018] Fig.13 is a schematic diagram depicting an example Tx data path according to one or more examples.

[0019] Fig.14 is a schematic diagram depicting an example Rx data path according to one or more examples.

[0020] Fig.15 is a schematic diagram depicting an example Tx data path according to one or more examples.

[0021] Fig.16 is a schematic diagram depicting an example Rx data path according to one or more examples.

[0022] Fig.17 are block diagrams of circuit systems that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0024] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0025] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "such as," and "for example" means that the related description is illustrative, and while the scope of the present disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0026] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0027] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Components, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between the block definitions and the individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced by many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details do not need to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0028] Those of ordinary skill in the art will appreciate that any of a variety of different technologies and techniques may be used to represent information and signals. For clarity of presentation and description, some of the figures may illustrate signals as single signals. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0029] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer when the general purpose computer is configured to execute computing instructions (e.g., software code) associated with the examples disclosed herein.

[0030] Examples may be described in terms of processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operable actions as continuous processes, many of these actions may be performed in another order, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitates transferring a computer program from one location to another.

[0031] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a collection of elements may include one or more elements.

[0032] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on a particular parameter, attribute, or condition being substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0033] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The terms "on" and "connected" may be used interchangeably with the term "coupled" in this description and have the same meaning, unless otherwise expressly indicated or the context would otherwise indicate to one of ordinary skill in the art.

[0034] The 802.3 technical standard (and its derivative standards) currently being developed by the 802.3 Working Group of the Institute of Electrical and Electronics Engineers (IEEE) ("IEEE 802.3" or simply "802.3") "logically" provides for measuring the delay between the medium independent interface (MII) and the medium dependent interface (MDI).

[0035] MII is the interface (e.g., but not limited to, physical, logical, or both) between the physical layer (PHY) and the media access control (MAC) of the link layer, where the Ethernet byte stream is visible and packets are continuous. MDI is part of the physical medium dependent (PMD) sublayer of the PHY and is the physical connection (e.g., but not limited to, connectors, pins, electrical characteristics) of a device to the physical transmission medium.

[0036] As used herein, the term "latency" refers to, but is not limited to, the duration of data traveling between two reference planes (such as MII and MDI). In one or more examples, a given latency value may be a calculated approximation and therefore may not represent the exact actual duration of data traveling between the two reference planes. In one or more examples, latency may be expressed in time units (e.g., but not limited to, picoseconds (ps), nanoseconds (ns), microseconds (μs), milliseconds (ms)) or in bit times.

[0037] Due at least in part to complex PHY functionality, the delay between MII and MDI (in either direction) may vary, for example but not limited to, from bit to bit, from byte to byte, or from symbol to symbol. Examples of functions that introduce cyclic dynamic delays include, but are not limited to, including FEC parity bits or reordering symbols. Since the transmitted MII (Tx MII) stream is reconstructed as the received MII (Rx MII) at the other end of the transmission medium, the sum of the dynamic delays through the transmit physical layer (TxPHY) and the receive physical layer (Rx PHY) is constant. Take the FEC parity bits as an example: adding the FEC parity bits through the Tx PHY will delay the transmission of the bits that appear after the parity bits, that is, those bits will have a higher delay through the Tx PHY than the bits immediately before the parity bits are inserted. The Rx PHY will perform the inverse operation, removing those parity bits. Therefore, the bits immediately after the parity bits will incur lower latency through the Rx PHY than the bits immediately before the FEC parity bits. Therefore, the latency from the near-end Tx MII to the far-end Rx MII (the latency across the physical transmission medium) can be considered constant even though its components do not have constant latency. To this end, it is not sufficient to timestamp only the message timestamp point of the packet to the edge of the device (i.e., MDI) (as a non-limiting example, the message timestamp point is typically configurable, and is typically configured as the first bit after the start frame delimiter (SFD)), because this will cause time synchronization errors due to dynamic changes.

[0038] IEEE 802.3 specifies that for both transmit and receive data, timestamps will be generated at the MII and adjusted using a "constant" representing the path data delay to calculate the timestamp corresponding to the MDI reference plane ("MDI timestamp"). In the case of Tx PHY, the maximum dynamic MII to MDI delay is used. In the case of Rx PHY, the minimum dynamic MDI to MII delay is used (which also takes into account the media channel deviation). Therefore, in order to measure the transmit or receive data path delay between MII and MDI, the transmission time of a specific bit that causes the maximum (transmit) and minimum (receive) dynamic delay changes is observed. (Note that the bit that causes the maximum transmit dynamic delay must be the same as the bit that causes the minimum receive dynamic delay.) The specific bit can be any bit that reliably causes the maximum transmit delay (also called "Tx path data delay") or the minimum receive delay (also called "Rx path data delay"), as the case may be. The specific bits may vary with the PHY type (different rates and interfaces have different PHY capabilities and therefore different dynamic delays), such as but not limited to the first bit (or symbol) of a forward error correction (FEC) codeword or the first bit (or symbol) of a multi-lane distribution.

[0039] IEEE 802.3 specifies that MII is a constant bit rate interface. When an IEEE 802.3 device implements IEEE 1588, for Rx, the packet timestamp is the time when the message timestamp point of the packet crosses the Rx MII plane ("Rx MII packet timestamp") minus a constant "Rx path data delay" value corresponding to the minimum delay through the Rx PHY. For Tx, the packet timestamp is the time when the message timestamp point of the packet crosses the Tx MII plane ("Tx MII packet timestamp") plus a constant "Tx path data delay" value corresponding to the maximum delay through the Tx PHY.

[0040] In practice, it is difficult to directly measure MII timestamps (e.g., but not limited to, Rx MII packet timestamps, Tx MII packet timestamps). MII is a logical interface that may, but need not, physically exist, and it may be difficult to infer the timestamps at the MII equivalent interface. For example, instead of MII, the physical implementation of the device may use a wide interface, a time division multiplexing (TDM) interface, or an overclocked interface, but such interfaces are not necessarily constant bit rates. Therefore, it is difficult to determine (e.g., but not limited to, detect) when the message timestamp point of a packet crosses the MII. Since the Rx and Tx packet timestamps are calculated using the Rx MII and TxMII packet timestamps, this makes the Rx and Tx packet timestamps difficult to calculate.

[0041] Further, the delays for part or all of the circuit system for the PCS / FEC functional logic components and any optional implementation-specific logic components may or may not be deterministic. When the delays are not deterministic, it is difficult to track the delay of a particular bit and it is difficult to determine the minimum Rx path data delay and the maximum Tx path data delay. For example, many physical factors may affect the path delay measurement, such as clock skew on the device (clock distribution on the chip), data propagation delays (including the impact of source synchronous paths), clock domain crossings, and other structures such as FIFOs and gearboxes, all of which have dynamic delays that typically depend on non-deterministic startup conditions and process / voltage / temperature (PVT) conditions. Measuring path delays a priori by counting pipelines or measuring propagation delays in static timing analysis (STA) may result in larger timestamp uncertainty than the target.

[0042] Further, complete synchronization or distribution of the time of day between the two ends of the path data delay measurement is generally impossible or too costly to be practical. The calculation of any delay is the end time minus the start time. Therefore, due to having two measurements (the end time and the start time), and due to any difference in the wall clock time (according to the local time source) at those two measurement points, any such delay measurement will be inaccurate. Therefore, the calculation of the Rx Path Data Delay and the Tx Path Data Delay may cause additional errors due to the time difference at the two ends of any direct measurement.

[0043] In summary, obtaining accurate packet timestamps presents significant challenges, especially when strictly using the standard specified methods of obtaining MII packet timestamps and adjusting for path data delays. Because the MII is often not physically present for many implementations, the MII packet timestamps may be inaccurate. Because the PHY delay may be non-deterministic, the predetermined path data delay value may be inaccurate. Because the delay through the PHY is dynamically changing, and because of the difficulty in synchronizing clocks at both ends of the measurement and because of the fact that two time samples are required to calculate the delay, the measured path data delay value may be inaccurate.

[0044] To perform SerDes timestamping, the timestamping function at the SerDes should be initiated in response to detecting a predetermined bit in the incoming data or the outgoing data.

[0045] One or more examples generally involve adding an indication to incoming data or outgoing data, wherein the indication identifies a bit (or byte or symbol) in the data, i.e., an "indicated bit position". The indication marks the bit position of the outgoing data or the incoming data. The indicated bit position can be observed by a bit detector at a parallel interface of a SerDes, which triggers a hardware timestamp in response to detecting the indicated bit position to generate a SerDes timestamp.

[0046] Packet timestamp calculation using SerDes specific bit timestamp

[0047] Instead of measuring the path data delay and generating a timestamp when a message timestamp point crosses a MII that may or may not physically exist, the inventors of the present disclosure realized that it is easier to generate a timestamp near or within the device edge (i.e., the time when a particular bit representing the path data delay crosses a SerDes interface near the MDI) and calculate the packet timestamp based at least in part on that timestamp.

[0048] In the case of incoming data, the specific bit used to timestamp the crossing at the SerDes is referred to herein as the “Rx SerDes specific bit”, and the timestamp based on the specific bit is referred to as the “Rx SerDes specific bit timestamp”. In the case of outgoing data, the specific bit used to timestamp the crossing at the SerDes interface is referred to herein as the “TxSerDes specific bit”, and the timestamp based on the specific bit is referred to as the “Tx SerDes specific bit timestamp”.

[0049] In the case of incoming data, the point in the packet used to timestamp the crossing at the MII is referred to herein as the "message timestamp point", and the timestamp based on that point is referred to as the "packet timestamp". In the case of incoming data, the packet timestamp is referred to as the "Rx packet timestamp", and in the case of outgoing data, the packet timestamp is referred to as the "Tx packet timestamp".

[0050] Rx packet timestamp = Rx MII packet timestamp - Rx path data delay, and Tx packet timestamp = Tx MII packet timestamp + Tx path data delay.

[0051] The Rx packet timestamp and Tx packet timestamp represent the sum or difference, respectively, where the MII packet timestamp term cancels out in the calculation, as discussed below. Further, since the MII is logically a constant bit rate interface, the MII packet timestamp of bit x+n can be calculated as: (MII packet timestamp of bit x+n) = (MII packet timestamp of bit x) + (n*MII bit time), where the variables "x" and "n" are integers ≥ 1.

[0052] When the Rx SerDes specific bit timestamp and the Tx SerDes specific bit timestamp are available parameters, further equivalent formulas for calculating the Tx packet timestamp and the Rx packet timestamp can be derived.

[0053] Tx packet timestamp:

[0054] Tx packet timestamp = (Tx MII packet timestamp) + (Tx path data delay); (Formula 1).

[0055] Tx path data delay = (Tx SerDes specific bit timestamp) - (Tx MII specific bit timestamp) (Formula 2) wherein the Tx MII specific bit timestamp is the time when the Tx SerDes specific bit crosses the MII.

[0056] Tx packet timestamp = (Tx MII packet timestamp) + ((Tx SerDes specific bit timestamp) - (Tx MII specific bit timestamp)) (Formula 3).

[0057] Since Tx MII is a constant bit rate interface: Tx Packet Timestamp = (Tx MII Specific Bit Timestamp) + (TxMII Bit Distance) * (MII Bit Time) (Formula 4), where Tx MII Bit Distance is the distance (in bits) between the message timestamp point and the location where the Tx SerDes specific bit appears on the MII.

[0058] Tx packet timestamp = ((Tx MII specific bit timestamp) + (Tx MII bit distance) * (MII bit time)) + (Tx SerDes specific bit timestamp) - (Tx MII specific bit timestamp)) (Formula 5).

[0059] In Equation 5, the Tx MII specific bit timestamp parameters cancel out. Therefore, the Tx packet timestamp can be expressed as a function of the TxSerDes specific bit timestamp, the Tx MII bit distance, and the MII bit time as follows:

[0060] Tx packet timestamp = (Tx SerDes specific bit timestamp) + (Tx MII bit distance) * (MII bit time) (Formula 6).

[0061] Rx packet timestamp:

[0062] Rx Packet Timestamp = (Rx MII Packet Timestamp) - (Rx Path Data Delay) (Formula 7).

[0063] Rx path data delay = (Rx MII specific bit timestamp) - (Rx SerDes specific bit timestamp) (Formula 8) where the Rx MII specific bit timestamp is the time when the Rx SerDes specific bit crosses the MII.

[0064] Rx packet timestamp = Rx MII packet timestamp - ((Rx MII specific bit timestamp) - (RxSerDes specific bit timestamp)) (Formula 9).

[0065] Since Rx MII is a constant bit rate interface: Rx MII packet timestamp = Rx MII specific bit timestamp + (RxMII bit distance) * (MI1 bit time) (Formula 10) Where Rx MII bit distance is the distance between the message timestamp point and the RxSerDes specific bit (in bits).

[0066] Rx packet timestamp = ((Rx MII specific bit timestamp) + (Rx MII bit distance) * (MII bit time)) - ((Rx MII specific bit timestamp) - (Rx SerDes specific bit timestamp)) (Formula 11).

[0067] In Equation 11, the Rx MII specific bit timestamp parameters cancel out. Therefore, the Rx packet timestamp can be expressed as a function of the RxSerDes specific bit timestamp, the Rx MII bit distance, and the MII bit time as follows:

[0068] Rx Packet Timestamp = (Rx SerDes specific bit timestamp) + n*(MII bit time) (Equation 12), where n is the Rx MII bit distance from the specific bit to the message timestamp point of the packet.

[0069] The final equivalent expressions of the Tx packet timestamp and Rx packet timestamp above are all dependent on the SerDes specific bit timestamp. The Rx packet timestamp and Tx packet timestamp can be calculated. No direct measurement of the path data delay is used, and no MII timestamp is required. The Tx packet timestamp and Rx packet timestamp can be based on timestamps generated only at the edge of the device (e.g., SerDes).

[0070] Timestamp frequency or interval

[0071] The higher the frequency of SerDes timestamping, the faster timestamp errors can be detected, latency effects of process voltage / temperature changes corrected, and bit time inaccuracies mitigated, but not limited to. In fact, by periodically recalculating the SerDes bit-specific timestamps and resetting "n" to zero, the absolute timestamp error due to MII bit time inaccuracies is limited. To use an analogy, a watch can be synchronized to the exact time - Sunday noon. If the watch runs 0.01% fast, then by the next Sunday noon, the watch will be off by more than a minute. But if the watch is synchronized every day at noon, its time will never be off by more than 10 seconds. The more frequently the watch is synchronized, the smaller the time error due to frequency inaccuracies will be.

[0072] In order to obtain the values ​​of Tx SerDes specific bit timestamp and Rx SerDes specific bit timestamp, SerDes timestamping needs to be performed periodically for both single-channel channels and multi-channel channels (multi-channel will be discussed below). A specific bit may appear only once per FEC word or per multi-channel distribution, although other frequencies of occurrence are not beyond the scope of this disclosure. Since the timestamp formula uses the MII bit time, any inaccuracy in the value of the MII bit time will corrupt the timestamp the further the packet is from a specific MII bit: Timestamp Error = n*(MII Bit Time Error).

[0073] Specific bits

[0074] The location of the specific bit is used for Tx and Rx SerDes specific bit timestamping, as discussed below. The location of the specific bit should be indicated for the entire path between MII and SerDes (including through any PCS / FEC / PMA functions). Further, in the case of multiple channels, there should be an instance of this indication for each physical SerDes channel.

[0075] As a non-limiting example of Tx, a Tx SerDes specific bit is indicated at the Tx PCS and then carried along with the outgoing data on the Tx path of the PHY towards the SerDes where it is timestamped to generate a Tx SerDes specific bit timestamp. As a non-limiting example, when the FEC parity bits are inserted in the Tx PCS / FEC block, the bits immediately following the FEC parity bits have the maximum MII to MDI delay. Therefore, through the Tx PCS / FEC block, the specific bits and their positions on the MII can be determined.

[0076] As a non-limiting example at Rx, prior to frame processing at the PCS, it may be difficult or impossible to detect individual bits in the incoming data (including Rx SerDes specific bits) without complex circuitry that has its own latency that may make overall latency calculation difficult. With the Rx PCS / FEC block, a specific bit representing the Rx path data latency is determined. As a non-limiting example, for a channel with FEC, the bit immediately following the FEC parity bit has the minimum Rx path data latency. When the Rx PCS / FEC block performs frame processing and removes the FEC parity bits, a specific bit position in the data from the Rx SerDes and the corresponding bit position in the Rx MII are determined.

[0077] In one or more examples, for Rx SerDes specific bit timestamp marking, the position of an arbitrary bit (referred to herein as "Rx SerDes arbitrary bit") is indicated and timestamped at the SerDes to generate an RxSerDes arbitrary bit timestamp. The bit distance between the Rx SerDes arbitrary bit and the Rx SerDes specific bit ("arbitrary to specific SerDes bit distance") is calculated, and the timestamp of the Rx SerDes specific bit (Rx SerDes specific bit timestamp) is calculated, as discussed below.

[0078] As a non-limiting example of an Rx SerDes specific bit being a FEC codeword boundary: By detecting the FEC codeword boundary, the bit distance between any bit and the beginning of the FEC codeword can be measured (e.g., but not limited to, in units of bits or bit times). The Rx SerDes specific bit timestamp at the beginning of the FEC codeword (representing the Rx path data delay) depends on the Rx SerDes arbitrary bit timestamp and the time to the RxSerDes specific bit:

[0079] Rx SerDes specific bit timestamp = (Rx SerDes arbitrary bit timestamp) + (arbitrary to specific SerDes bit distance) * (SerDes bit time) (Formula 13).

[0080] By substituting Equation 13 into Equation 12, the Rx packet timestamp can be calculated based on the Rx SerDes arbitrary bit timestamp and the arbitrary to specific SerDes bit distance on the SerDes:

[0081] Rx Packet Timestamp = (Rx SerDes arbitrary bit timestamp) + (arbitrary to specific SerDes bit distance) * (SerDes bit time) + Rx MII bit distance * (MII bit time) (Formula 14).

[0082] Timestamping in multi-channel operations

[0083] "Multi-lane" refers to the use of multiple data paths ("lanes") to simultaneously transmit data over a physical transmission medium. As a non-limiting example, the use of multiple lanes allows for a higher overall data rate without increasing the data rates required for the respective lanes.

[0084] Deviations may occur across multiple physical lanes of a SerDes interface. Since the corresponding lanes are physically independent of the other lanes, the corresponding lanes may have different delays than other lanes on the device or across the physical medium. In this way, the corresponding lanes may leave (Tx) or arrive (Rx) in an interleaved manner. In order to calculate the Rx and Tx timestamps, the deviation, that is, the relative delay of each physical lane, is taken into account in order to properly model the path data delay. In other words, the maximum MII to MDI delay (Tx) and the minimum MDI to MII delay (Rx) will vary from lane to lane, so any SerDes timestamp marking of a specific bit position representing the path data delay needs to determine which lane is the last to leave (Tx) or the last to arrive (Rx).

[0085] For multi-lane channels, instead of labeling a single specific bit, the specific bit representing the path data delay can be mapped to a set of specific bits such that there is one specific bit per physical lane. Each set of specific bits (one specific bit per lane) is generated / determined such that in the presence of zero lane skew, the specific bits for all parallel lanes will all leave (Tx) or arrive (Rx) at the device boundary at the same time. Within the PHY circuitry, how the one-to-many specific bit conversion is performed depends on the specific PHY function and is therefore an implementation-specific detail.

[0086] In the Tx direction, in the presence of Tx channel skew, the last leaving channel representing the maximum MII to MDI delay is needed to calculate the Tx path data delay. For each SerDes channel, periodic specific bits are marked for SerDes timestamp marking. If there is zero channel skew, the marked bits of each channel will all arrive at the SerDes at exactly the same time, that is, with the same SerDes specific bit timestamp. But in the presence of channel skew, the indicated bit positions may arrive at the Tx SerDes staggered. The last leaving channel has the latest TxSerDes specific bit timestamp value.

[0087] Therefore, the expression for the Tx packet timestamp for a multi-channel interface is: Tx packet timestamp = last(Tx SerDes specific bit timestamp for each SerDes channel) + (Tx MII bit distance) * (MII bit time) (Formula 15), where "last" refers to the last channel left (i.e., the latest timestamp value among all channels, which is equivalent to the last specific bit that will appear at the SerDes), and n is the bit distance from the specific bit representing the Tx path data delay to the message timestamp point for the Tx packet.

[0088] For the Rx multi-channel channel, the deviation existing at the SerDes channel is the deviation of the medium. RxPHY performs a de-skew function to realign the channel and restore the MII channel. Since the Rx path data delay is the minimum MDI to MII delay, the last arriving channel is used for the Rx SerDes specific bit timestamp and is ultimately used to calculate the packet timestamp. In order to identify the last arriving channel, the single channel method is extended to multiple channels. For each SerDes channel, any bit is timestamped and marked, and the SerDes bit distance from any bit to the specific bit representing the Rx path data delay is calculated for each channel through the Rx PHY. Similar to the single-channel channel, the periodic "specific bit timestamp" of each channel is obtained by adjusting the periodic arbitrary bit timestamp by the following amount: the time distance to the Rx SerDes specific bit timestamp. Since the SerDes arbitrary bit is used on each channel, combined with the deviation between channels, it is necessary to carefully adjust to the common alignment set of specific bits (rather than the next set of common bits). To this end, the minimum interval of the arbitrary bit SerDes timestamp mark depends on the maximum possible channel deviation. Otherwise, it may not be aligned to the same set of Rx specific bits and the specific bit timestamp may be offset by the entire specific bit interval.

[0089] Therefore, the expression for the Rx packet timestamp for a multi-channel interface is:

[0090] Rx Packet Timestamp = last[(Rx SerDes arbitrary bit timestamp per SerDes lane) + ki*(SerDes bit time)] + n*(MII bit time) (Formula 16), where "last" refers to the last lane arrived at (i.e., the last "specific bit" that appears at the Rx SerDes calculated after the arbitrary to specific adjustment of each lane), ki is the arbitrary to specific SerDes bit distance of SerDes lane i (note that ki can be positive or negative so that the lanes are aligned to a common set of specific bits), and n is the Rx MII bit distance.

[0091] After the above arithmetic processing, the Tx packet timestamp and Rx packet timestamp:

[0092] Depends on the Rx SerDes specific bit timestamp (for the last arriving lane in case of multiple lanes) and the Tx SerDes specific bit timestamp (for the last departing lane in case of multiple lanes)

[0093] Rx SerDes specific bit timestamp can be expressed as Rx SerDes specific bit timestamp

[0094] =(Rx SerDes arbitrary bit timestamp) + (Rx adjustment value). Rx adjustment value = (arbitrary to specific SerDes bit distance) * (SerDes bit time)

[0095] The Tx MII bit distance and Rx MII bit distance between a specific timestamp bit and the packet message timestamp point

[0096] MII bit time and SerDes bit time

[0097] The following parameters are not required (or are optional) when calculating Tx packet timestamps or Rx packet timestamps:

[0098] Direct measurement of data delay in Tx or Rx paths

[0099] MII timestamp function (only SerDes timestamp function is used)

[0100] Time of day synchronization or distribution between SerDes and MII (only SerDes time of day is used)

[0101] The values ​​of MII bit time and SerDes bit time can be predetermined, or if more precise values ​​are needed, these values ​​can be measured at given intervals. Any distance to a specific SerDes bit, Tx MII bit distance, Rx MII bit distance, and Rx adjustment value can be calculated. It is worth noting that the above calculations can be performed without determining, measuring, or otherwise knowing the latency on the device.

[0102] One or more examples generally relate to logical timestamping and logical timestamping functionality at a SerDes provided at a physical layer.

[0103] The indicated bit position is timestamped at the parallel interface of the SerDes, rather than timestamping at the MII and adjusting the data path delay between the MII and the MDI. In the case of multiple channels, per-SerDes channel timestamping of the indicated bit position is performed. The SerDes timestamping of the indicated bit position is performed directly at the SerDes parallel interface. No attempt is made to measure, infer, or calculate the Rx path data delay or the Tx path data delay.

[0104] Using the bit position timestamp indicated by the SerDes, the SerDes specific bit timestamp can be derived, and the arrival / departure time of the packet at the MDI reference plane can be calculated based on the specific bit timestamp, the bit distance from the specific bit to the message timestamp point, and the SerDes bit time.

[0105] In multiple lanes, Rx skew across the medium can be corrected by timestamping relative to the last arriving lane, and Tx skew within the PHY can be corrected by timestamping relative to the last departing lane.

[0106] Since the annotated bit timestamps are generated relative to the edge of the device (ie, the parallel interface of the SerDes) (missing only the latency of the SerDes itself, which can be applied after the fact), no device latency is measured, inferred or calculated.

[0107] Figure 1 is a block diagram illustrating an apparatus 100 for SerDes timestamping indicated bit positions according to one or more examples.

[0108] The apparatus 100 includes a PHY portion 102, a SerDes 108 having a parallel interface 110, a bit position detector 112, and a timestamp logic circuit 114. The PHY portion 102 includes a logic circuit 104 and an adjustment value 106.

[0109] SerDes 108 is a pair of functional blocks, namely, a serializer and a deserializer. The serializer of SerDes 108 takes the parallel data on the input of the parallel interface 110, combines the parallel data, and outputs the data in a serial manner (one bit at a time) on a single data line or outputs portions of the data in a serial manner on multiple corresponding channels. The deserializer of SerDes 108 takes the serialized data stream on the input (a single data line or multiple channels), converts it into parallel data, and arranges the parallel data on the output of the parallel interface 110 as incoming data 126. The parallel interface 110 of SerDes 108 includes an input / output (I / O) for receiving and transmitting parallel data. The parallel interface 110 receives parallel outgoing data 128 from the PHY portion 102 and transmits parallel incoming data 126 to the PHY portion 102. In one or more examples, the SerDes 108 may or may not be co-located with the PHY portion 102 depending on specific operating conditions.

[0110] The bit position detector 112 receives the incoming data 126 or the outgoing data 128 from the parallel interface 110 of the SerDes 108 and detects the indicated bit position 116 (e.g., but not limited to, via data processing, pattern matching, or a combination thereof). In response to detecting the indicated bit position 116, the bit position detector 112 generates a trigger 118 to start the timestamp logic circuit 114 to generate a SerDes-specific bit timestamp 122. In one or more examples, the SerDes-specific bit timestamp 122 can be a hardware timestamp or a timestamp calculated at least in part based on a hardware timestamp. A hardware timestamp is a time stamp applied directly by a hardware device. A hardware timestamp is generally more accurate than a software timestamp (e.g., but not limited to, avoiding the delay and variability of a software timestamp). Further, compared to a software timestamp, a hardware timestamp enjoys greater flexibility in the location (i.e., physical location) where it can be applied. In one or more examples, the SerDes-specific bit timestamp 122 can be or include a Tx SerDes-specific bit timestamp or an Rx SerDes-specific bit timestamp.

[0111] PHY portion 102 is at least a portion of the physical layer of the device and may include circuitry for Tx and Rx PHY functions. PHY portion 102 is coupled to the MAC via a PHY / MAC interface or equivalent 120.

[0112] The logic circuit 104 is disposed at the PHY portion 102. The logic circuit 104 receives the SerDes specific bit timestamp 122 from the timestamp logic circuit 114 and generates a packet timestamp 124 based at least in part on the SerDes specific bit timestamp. The packet timestamp 124 can be an Rx packet timestamp or a Tx packet timestamp, as appropriate. In one or more examples, the logic circuit 104 can generate the packet timestamp 124 by combining the SerDes specific bit timestamp 122 with the adjustment value 106.

[0113] Generally speaking, the adjustment value 106 represents the MII distance (eg, but not limited to, in time) between the location of a SerDes specific bit (which represents the path data delay) and the message timestamp point of the incoming data or outgoing data to be timestamped.

[0114] In the case of Rx path data delay, the position of an arbitrary bit in the incoming data is initially used to generate the SerDes specific bit timestamp 122, so the SerDes specific bit timestamp 122 is the RxSerDes arbitrary bit timestamp. The Rx SerDes specific bit timestamp is calculated based at least in part on the bit distance between the position of the Rx SerDes arbitrary bit and the RxSerDes specific bit multiplied by the SerDes bit time. The logic circuit 104 can set the adjustment value 106 equal to the product of the arbitrary to specific SerDes bit distance multiplied by the SerDes bit time.

[0115] In one or more examples, it is determined which bit represents the Tx path data delay (eg, a specific bit), and its location on *both* the MII side and the SerDes side (referred to herein as a SerDes specific bit) is determined.

[0116] Figure 2 is a block diagram depicting an apparatus 200 for indicating a bit position of a particular bit in outgoing data according to one or more examples. As a non-limiting example, the apparatus 200 may be disposed in or adjacent to and coupled to the PHY portion 102 such that the apparatus receives a copy of the outgoing data.

[0117] The apparatus 200 includes a Tx timing signal generation circuit 206 and an optional PHY-side PHY-MAC logic component 210 .

[0118] The PHY-side PHY-MAC logic component 210 is a logic circuit that implements the PHY-side functions of a PHY / MAC interface or equivalent interface 120 (such as, but not limited to, a MII or MII equivalent interface).

[0119] Tx timing signal generation circuit 206 is a logic circuit (same or different from logic circuit 104) that receives outgoing data, detects that a bit in the outgoing data corresponds to a Tx SerDes specific bit, and adds an indication to the outgoing data to indicate the position of the Tx SerDes specific bit.

[0120] Here, the Tx timing signal generation circuit 206 receives the outgoing data 202 (or a copy thereof) including the specific bit 204, processes the outgoing data 202 (or a copy thereof) and indicates the position (indicated bit position 208) of the specific bit 204 in the outgoing data 202 based at least in part on the outgoing data (or a copy thereof).

[0121] In one or more examples, the Tx timing signal generation circuit 206 determines which particular bit represents Tx path data delay based on the Tx PHY function, processes the outgoing data 202 (or a copy thereof) and indicates the position (indicated bit position 208) of a particular bit 204 in the outgoing data 202 based at least in part on the outgoing data (or a copy thereof).

[0122] Here, the Tx timing signal generation circuit 206 receives the outgoing data 202 including the specific bit 204 directly from the PHY side PHY-MAC logic component 210, and the specific bit 204 is a bit visible at the PHY side PHY-MAC logic component 210. As a non-limiting example, the specific bit 204 can be a bit adjacent to a frame start delimiter (SFD) or an alignment mark or an FEC word. In one or more examples, the specific bit 204 can be a periodic bit, that is, a bit that is reliably present in the outgoing data 202 according to a consistent periodicity.

[0123] In one or more examples, the Tx timing signal generation circuit 206 adds an indication of the position of the specific bit 204 in the outgoing data 202 to indicate that the bit at the position (the specific bit 204 ) is being used as a Tx SerDes specific bit.

[0124] In one or more examples, the indication can be added to a portion of the outgoing data 202 adapted to hold out-of-band data, such as a vendor specific element or sideband bits. In one or more examples, the indication can be added to another data path or an auxiliary data path for carrying information about the outgoing data and its bits.

[0125] Figure 3is a block diagram depicting an apparatus 300 for indicating a bit position at incoming data according to one or more examples. As a non-limiting example, the apparatus 300 may be disposed at or adjacent to and coupled to the PHY portion 102 such that the apparatus receives a copy of the incoming data from a parallel interface of the SerDes.

[0126] The apparatus 300 includes an RX timing signal generation 302 and an optional SerDes parallel interface 308 .

[0127] The SerDes parallel interface 308 is such as Figure 1 The SerDes parallel interface 308 is an input / output interface in which data is exchanged in parallel between the SerDes 108 and a connected device or system (e.g., but not limited to, a processor, memory, other communication device, system bus). The SerDes parallel interface 308 may include, for example, one or more parallel data lines, control lines, and clock lines. The configuration of the SerDes parallel interface 308 will vary depending on the specific implementation and requirements of the SerDes 108.

[0128] RX timing signal generation 302 is a logic circuit that receives incoming data 306 (or a copy thereof) from SerDes parallel interface 308, processes incoming data 306 (or a copy thereof) and indicates the position of the bit being used as the Rx SerDes arbitrary bit in the incoming data 306 (such position is referred to herein as the "indicated arbitrary bit position"). The indication of the indicated arbitrary bit position 304 is provided with the incoming data 126.

[0129] An Rx SerDes arbitrary bit position 304 may be selected without regard to the content of the incoming data. In one or more examples, a particular bit position 304 may be a periodic bit, ie, a bit that is reliably present in the incoming data 306 according to a consistent periodicity.

[0130] The indicated arbitrary bit position 304 may be used to determine the position of an Rx SerDes specific bit, as discussed below.

[0131] Figure 4 is a block diagram illustrating an apparatus 400 for changing an indication in incoming data from an arbitrary bit position of an RxSerDes to a specific bit position of an Rx SerDes according to one or more examples.

[0132] The apparatus 400 includes an Rx signal timing adjustment circuit 402 .

[0133] The Rx signal timing adjustment circuit 402 is a logic circuit (with Figure 1 4. The Rx PHY 414 may include logic circuitry (the same or different logic circuitry as the PHY portion 102 of the Rx PHY 414) that receives incoming data 406 having a first indicated bit position 404 from the Rx PHY 414 and provides incoming data 408 to a second indicated bit position 410.

[0134] The first indicated bit position 404 is the position of an arbitrary bit of the Rx SerDes. The second indicated bit position 410 is the position of a specific bit of the Rx SerDes. Since the incoming data 406 is received at the Rx signal timing adjustment circuit 402 after frame processing, the Rx SerDes specific bit can be detected and the indication can be moved to indicate the position of the Rx SerDes specific bit. Here, "moving" the indication can include deleting the previous indication and adding a new indication of the position of the Rx SerDes specific bit. The Rx signal timing adjustment circuit 402 changes the indication in the incoming data 406 from the first indicated bit position 404 to the second indicated bit position 410.

[0135] The Rx SerDes arbitrary bit timestamp is associated with the position of the Rx SerDes arbitrary bit. Therefore, the Rx signal timing adjustment circuit 402 calculates the arbitrary to specific SerDes bit distance as the bit distance between the first indicated bit position 404 and the second indicated bit position 410.

[0136] The any-to-specific SerDes bit distance may be used by the Rx signal timing adjustment circuit 402 to calculate an Rx adjustment value 412 by multiplying the any-to-specific SerDes bit distance by the SerDes bit time, as discussed above. The Rx adjustment value 412e may be combined with the Rx SerDes any-bit timestamp to generate an Rx SerDes specific bit timestamp corresponding to the second indicated bit position 410 (i.e., the position of the Rx SerDes specific bit).

[0137] Figure 5 is a block diagram of a system 500 according to one or more examples. As discussed below, corresponding timing signals are provided at the Tx and Rx data paths to indicate when the bit position of a particular bit in the outgoing and incoming data crosses the parallel interface of the SerDes.

[0138] The system 500 includes an Ethernet PHY 502 and a physical transmission medium 536. The Ethernet PHY 502 and the physical transmission medium 536 are coupled via an MDI 534. The Ethernet PHY 502 includes a Tx timing generator 504, an Rx PHY 506, a Tx PHY 508, a SerDes 510, a parallel interface 512, an RX timing generator 516, a timestamp marker 518, an Rx timing adjuster 528, a packet timestamp marker logic 530, a packet timestamp 532, an MDI 534, and a physical transmission medium 536.

[0139] The Tx timing generator 504 is a logic circuit that receives a copy of the outgoing data from the Tx PCS block of the Tx PHY 508 and generates a Tx timing signal 514 to indicate the bit position of the bit in the outgoing data that is being used as a specific bit and when the bit position is present at the parallel interface 512 of the SerDes 510. In one or more examples, the Tx timing generator 504 determines the specific bit representing the Tx path data delay based on, but not limited to, a predetermined bit (such as, but not limited to, the first bit of an alignment marker of an FEC block word, a frame start delimiter (SFD)) or a state of the Tx PHY.

[0140] The RX timing generator 516 is a logic circuit that receives a copy of the incoming data from the parallel interface 512 of the SerDes 510 (after deserialization by the SerDes 510) and generates an Rx timing signal 520 to indicate the bit position of the bit in the incoming data that is being used as the temporary specific bit, as discussed above. In one or more examples, any bit in the incoming data can be selected as the temporary specific bit as long as its existence is maintained for the entire Rx PHY data path.

[0141] In one or more examples, the Tx timing signal 514 and the Rx timing signal 520 are metadata provided via another data path or an auxiliary data path, which is a data path that is different from the Tx PHY data path or the Rx PHY (for example, but not limited to, separate and distinct from the Tx PHY data path or the RxPHY), but exhibits the same timing as the TxPHY and RxPHY data paths and can be used to carry information about incoming data and outgoing data and specific portions and bits thereof.

[0142] The Tx PCS of Tx PHY 508 and the Rx PCS of Rx PHY 506 implement the functions of the Tx PCS sublayer and the Rx PCS sublayer of Ethernet PHY 502. The Tx PCS may be responsible for encoding, encryption, and forward error correction (FEC). The Rx PCS may be responsible for decoding, decryption, and forward error correction. As a non-limiting example of standardization, speed, security, or compatibility, encoding converts outgoing data into a form suitable for transmission on the physical transmission medium 536. Decoding reconstructs incoming data into its form before being encoded by the transmitter. Encryption and decryption involve: converting the data of the data stream into code to prevent unauthorized access to ensure security and privacy; and converting the code back into data. Forward error correction adds correction codes to the data stream that allow the receiver to detect and correct a limited number of errors without the need for retransmission.

[0143] Although in Figure 5 Only the PCS functional blocks (i.e., Tx PCS and Rx PCS) are depicted in FIG, but this is only to avoid Figure 5 Additional functionality may be implemented at the Tx PHY 508 and Rx PHY 506, such as but not limited to a PMA sublayer or a PMD sublayer, without exceeding the scope of the present disclosure.

[0144] The SerDes 510 performs bit-level serialization / deserialization if outgoing data and incoming data.

[0145] The timestamp marker 518 is a hardware timestamp marker that generates a timestamp in response to a specific event or signal. A timestamp is a value that represents a specific point in time. In one or more examples, the timestamp generated by the timestamp marker 518 can be provided separately or included in a log, record, or metadata, but is not limited thereto.

[0146] Here, the timestamp marker 518 performs timestamp marking when the bit position of the timestamp bit in the outgoing data (as indicated by the Tx timing signal 514) exists at the parallel interface 110 of the SerDes 510, and when the bit position of the temporary specific bit of the incoming data (as indicated by the Rx timing signal 520) exists at the parallel interface 110 of the SerDes 510. More specifically, the timestamp marker 518 generates a Tx SerDes specific bit timestamp 522 (which indicates when the specific bit in the outgoing data exists at the parallel interface 512 of the SerDes 510), and generates an Rx arbitrary timestamp 524 (which indicates when the temporary specific bit in the incoming data exists at the parallel interface 512 of the SerDes 510).

[0147] In one or more examples, the timestamp marker 518 includes: a time-of-day source for providing time information that can be included in the Tx SerDes specific bit timestamp 522 and the Rx arbitrary timestamp 524; and a signal detector for detecting the Tx timing signal 514 and the Rx timing signal 520. In one or more examples, the timestamp marker 518 and its time-of-day source are maintained at or near the parallel interface 512 of the SerDes 510, rather than being located deep in the device core or near the MII or MII equivalent interface 538.

[0148] The Rx timing adjuster 528 is a logic circuit that receives incoming data including indicated arbitrary bits after frame processing, detects the bit corresponding to the Rx SerDes specific bit, and changes the indication from the position of the arbitrary bit (the first indicated bit position) to the position of the Rx SerDes specific bit (the "second indicated bit position"). The Rx timing adjuster 528 calculates the bit distance between the arbitrary bit and the Rx SerDes 108 (the arbitrary to specific SerDes bit distance) and multiplies the bit distance by the SerDes bit time to generate an Rx adjustment value, which is combined with the Rx arbitrary timestamp 524 to generate the Rx SerDes specific bit timestamp 526 (i.e., the Rx SerDes specific bit timestamp).

[0149] The packet timestamp marking logic component 530 is a logic circuit that receives the SerDes specific bit timestamp (here, the Tx SerDes specific bit timestamp 522 ("Tx timestamp 522") and the Rx SerDes specific bit timestamp 526 ("Rx timestamp 526")) and calculates the packet timestamp 532 (here, the Rx packet timestamp and the Tx packet timestamp). In one or more examples, the packet timestamp marking logic component 530 calculates the Tx packet timestamp based on the following expression: Tx packet timestamp=last(Tx SerDes specific bit timestamp (per SerDes channel))+((TxMII bit distance)*(MII bit time)). In one or more examples, the packet timestamp marking logic component 530 calculates the Rx packet timestamp based on the following expression: Rx packet timestamp=last(RxSerDes specific bit timestamp (per SerDes channel))+(Rx MII bit distance)*(MII bit time)). The packet timestamp 532 calculated by the packet timestamp logic 530 is optionally output from the Ethernet PHY 502 via the MII or MII equivalent interface 538 .

[0150] In one or more examples, the values ​​of the SerDes bit time and the MII bit time can be pre-calculated (eg, but not limited to, during setup of a device including the system 500) and stored at the Rx timing adjuster 528 or the packet timestamping logic 530, respectively.

[0151] Figure 6 is a flow diagram depicting a process 600 for SerDes timestamping outgoing data or incoming indicated bit positions at a PHY according to one or more examples. As non-limiting examples, some or all of the operations of process 600 may be performed by apparatus 100 or system 500.

[0152] Although example process 600 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of process 600. In other examples, different components of an example device or system implementing process 600 may perform functions substantially simultaneously or in a particular order.

[0153] According to one or more examples, process 600 includes observing an indicated bit position at a parallel interface of a SerDes coupling a PHY with a physical transmission medium at operation 602. The indicated bit position may be the position of a bit in incoming data or outgoing data at the PHY. As discussed herein, the bit may be a Tx SerDes specific bit or an Rx SerDes arbitrary bit.

[0154] According to one or more examples, process 600 includes generating a timestamp at least in part in response to observing the indicated bit position at operation 604. The timestamp can be, but is not limited to, a TxSerDes specific bit timestamp, an RxSerDes any bit timestamp, an Rx SerDes any bit timestamp, or a packet timestamp.

[0155] According to one or more examples, process 600 includes providing the timestamp to an upstream or downstream user at operation 606. As a non-limiting example, the user may be a TimeSync client or user that performs higher layer processing. The user may be an upstream user in the case of Tx and a downstream user in the case of Rx.

[0156] Figure 7 is a flow diagram depicting a process 700 for adding indicated bit positions to outgoing data, according to one or more examples. As non-limiting examples, some or all of the operations of process 700 may be performed by device 100, device 200, or device system 500.

[0157] Although the example process 700 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 700. In other examples, different components of an example device or system implementing the process 700 may perform functions substantially simultaneously or in a particular order.

[0158] According to some examples, process 700 includes: at operation 702, detecting a specific bit of a PHY-MAC interface in outgoing data. The specific bit of the PHY-MAC interface may be a MII specific bit. The specific bit is a MII specific bit indicating Tx path data delay.

[0159] According to some examples, process 700 includes adding an indication of the position of the detected particular bit to the outgoing data at operation 704. The position of the detected particular bit is the indicated bit position.

[0160] Figure 8 is a flow diagram depicting a process 800 for adding indicated bit positions to incoming data, according to one or more examples. As non-limiting examples, some or all of the operations of process 800 may be performed by device 100, device 300, or device system 500.

[0161] Although the example process 800 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 800. In other examples, different components of an example device or system implementing the process 800 may perform functions substantially simultaneously or in a particular order.

[0162] According to some examples, process 800 includes, at operation 802 , selecting any bit in incoming data.

[0163] According to some examples, process 800 includes, at operation 804 , adding an indication to the incoming data that the arbitrary bit is an indicated bit.

[0164] Fig. 9 is a flow diagram depicting a process 900 for generating a timestamp in response to observing an indicated bit position, according to one or more examples. As non-limiting examples, some or all of the operations of process 900 may be performed by device 100, device 200, or system 500.

[0165] Although the example process 900 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 900. In other examples, different components of the example device or system implementing the process 900 may perform functions substantially simultaneously or in a particular order.

[0166] According to one or more examples, process 900 includes, at operation 902 , generating an Rx SerDes arbitrary bit timestamp in response to observing a position of an arbitrary bit in incoming data at a parallel interface of the SerDes.

[0167] According to one or more examples, process 900 includes, at operation 904 , combining the Rx SerDes arbitrary bit timestamp with the Rx adjustment value to obtain an Rx SerDes specific bit timestamp.

[0168] According to one or more examples, process 900 optionally includes, at operation 906 , generating a timestamp provided to an upstream or downstream user at least in part in response to the RxSerDes specific bit timestamp.

[0169] Fig.10 1 is a flow diagram depicting a process 1000 for calculating an Rx adjustment value according to one or more examples. As non-limiting examples, some or all of the operations of process 1000 may be performed by device 100, device 400, or system 500.

[0170] Although the example process 1000 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1000. In other examples, different components of an example device or system implementing the process 1000 may perform functions substantially simultaneously or in a particular order.

[0171] According to one or more examples, process 1000 includes, at operation 1002 , calculating a bit distance between an arbitrary bit and a location of a specific bit of an Rx SerDes.

[0172] According to one or more examples, process 1000 includes, at operation 1004 , calculating an Rx adjustment value in response at least in part to the calculated bit distance and a bit rate of the SerDes.

[0173] Fig.11is a flow diagram depicting a process 1100 for generating a timestamp in response to observing an indicated bit position in outgoing data, according to one or more examples. As non-limiting examples, some or all of the operations of process 1100 may be performed by device 100, device 300, or system 500.

[0174] Although the example process 1100 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1100. In other examples, different components of an example device or system implementing the process 1100 may perform functions substantially simultaneously or in a particular order.

[0175] According to one or more examples, process 1100 includes receiving a SerDes specific bit timestamp at operation 1102. In one or more examples, the SerDes specific bit timestamp may be an Rx SerDes specific bit timestamp or a Tx SerDes specific bit timestamp.

[0176] According to one or more examples, process 1100 includes, at operation 1104, combining the SerDes specific bit timestamp with an adjustment value. The adjustment value represents the duration between the time when the SerDes specific bit crosses the PHY-MAC interface and the time when the message timestamp point of the packet crosses the PHY-MAC interface. The PHY-MAC interface may be a MII or MII equivalent interface. The packet timestamp represents when the message timestamp point crosses the PHY-MAC interface. The adjustment value may be predetermined or calculated as the distance (in bits) between the message timestamp point and the SerDes specific bit multiplied by the PH-MAC interface bit time (e.g., but not limited to, the MII or MII equivalent bit time).

[0177] According to some examples, process 1100 includes, at operation 1106 , providing the packet timestamp as a timestamp provided to a user.

[0178] Fig.12 is a schematic diagram of an example packet 1200 including indicated bit positions of SerDes specific bits.

[0179] The timestamp of packet 1200 is calculated as:

[0180] Packet timestamp = ((SerDes specific bit timestamp) + (n i ))*(MII bit time), where “n i” is the MII bit distance between a particular bit and the message timestamp point of packet i. Examples of distances to various example message timestamp points are depicted, represented as distances n0, n1, n2, and n3. The location of the message timestamp points may differ based at least in part on the particular operating context (as a non-limiting example, which standard is being used).

[0181] Fig.13 is a schematic diagram depicting an example Tx data path 1300 according to one or more examples.

[0182] Depicted is a representation of data flows for a Tx MII (which may be a physical MII or MII equivalent interface) and a single lane SerDes interface (such as, but not limited to, present at corresponding first-in first-out buffer(s)).

[0183] The Tx MII data stream includes a Tx SerDes specific bit 1302a and a message timestamp point 1304. The distance between the Tx SerDes specific bit 1302a and the message timestamp point 1304 is the distance "n". The channel data stream from the Tx PHY includes the TxSerDes specific bit 1302a, another instance of the specific bit 1302b, and added bits 1306a to 1306h. These added bits are added by the Tx PHY function and do not exist at the MII, so they cannot represent the Tx path data delay.

[0184] The logic in the Tx PHY determines a specific bit (here, Tx SerDes specific bit 1302a) representing the Tx path data delay (i.e., Tx SerDes specific bit 1302a), where the specific bit falls on the SerDes lane and the Tx MII. The regularly occurring bits used as the specific bits are marked on each lane (here, a single lane) toward the Tx SerDes (i.e., indicating the position).

[0185] The selection of a particular bit position is based at least in part on the functionality of the Tx PHY. As a non-limiting example, if the Tx PHY inserts FEC parity bits (light pink), then the particular bits representing the path data delay will fall directly after the FEC parity bits.

[0186] Fig.14 is a schematic diagram depicting an example Rx data path 1400 according to one or more examples.

[0187] Depicted is a representation of a data stream for an Rx MII (which may be a physical MII or MII equivalent interface) and a single-lane SerDes interface (such as, but not limited to, present at corresponding one or more first-in, first-out buffers (FIFOs)). The Rx MII data stream includes a specific bit 1402a and a message timestamp point 1406. The single-lane data stream from the Rx PHY includes the specific bit 1402a, another instance of the specific bit 1402b, an arbitrary bit 1404, and bits to be removed 1408a to 1408g. Bits to be removed 1408a to 1408g are bits that will be removed by the function of the Rx PHY and therefore cannot represent the Rx path data delay because they are not present at the Rx MII.

[0188] The distance "n" is the Rx MII bit distance, ie, the distance between the Rx MII specific bit (Rx SerDes specific bit) and the message timestamp point of the packet.

[0189] “k” is the SerDes lane bit distance between any noted bit and the specific bit representing the Rx path data delay.

[0190] The logic in the Rx PHY determines the specific bit (SerDes specific bit 1402) representing the Rx path data delay, where the specific bit falls on the SerDes lane and the corresponding Rx MII bit. The logic in the Rx PHY measures the bit distance between any marked bit (blue) from the RxSerDes and the specific bit representing the Rx path data delay.

[0191] Fig.15 is a schematic diagram depicting an example Tx path 1500 according to one or more examples.

[0192] Depicted is a representation of data flows (such as, but not limited to, present at corresponding FIFO(s)) for four lanes of a Tx MII (which may be a physical MII or MII equivalent interface) and a SerDes interface.

[0193] The distance "n" is the MII bit distance, ie, the distance between the Tx MII specific bit 1502 (Tx SerDes specific bit) and the message timestamp point 1504 of the packet.

[0194] The logic in the Tx PHY determines the location of the specific bits representing the Tx path data delay on the Tx MII, the corresponding per-lane Tx SerDes specific bits 1506a, 1506b, 1506c, and 1506d (indicated by padding in the cells), and where they fall on the SerDes lanes. The location of these bits is indicated on each lane towards the Tx SerDes. The added bits are indicated by Fig.15 Depicted but not labeled again.

[0195] Fig.16 is a schematic diagram depicting an example Rx path 1600 according to one or more examples.

[0196] Depicted is a representation of data flows (such as, but not limited to, present at corresponding FIFOs) for four lanes of the Rx MII (which may be a physical MII or MII equivalent interface) and a SerDes interface.

[0197] The distance "n" is the MII bit distance, ie, the distance between the Rx MII specific bit 1602 (Tx SerDes specific bit) and the message timestamp point 1604 of the packet.

[0198] The logic in the Rx PHY determines the per-lane Rx SerDes specific bits 1606a, 1606b, 1606c, and 1606d (indicated in red) that represent the Rx path data delay. Determine where this bit falls on the RxMII (after frame processing and de-skew). The logic in the Rx PHY calculates the bit distance between the per-lane Rx SerDes arbitrary bits 1608a, 1608b, 1608c, and 1608d from the Rx SerDes and the per-lane Rx SerDes specific bits 1606a, 1606b, 1606c, and 1606d that represent the Rx path data delay.

[0199] ″k i ″ is the distance from any bit to a specific SerDes bit per SerDes lane i, ie, the bit distance between any bit of RxSerDes and a specific bit of Rx SerDes representing the path data delay, where “i” is an integer greater than or equal to 0 for representing the corresponding SerDes lane.

[0200] The bits to be removed are given by Fig.16 Depicted but not labeled again.

[0201] Fig.171700 is a block diagram of a circuit system 1700 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit system 1700 includes one or more processors 1702 (sometimes referred to herein as "processors 1702") that are operably coupled to one or more data storage devices 1704 (sometimes referred to herein as "storage devices 1704"). The storage devices 1704 include machine executable code 1706 stored thereon, and the processor 1702 includes logic circuits 1708. The machine executable code 1706 information describes functional elements that can be implemented by (e.g., executed by) the logic circuits 1708. The logic circuits 1708 are adapted to implement (e.g., execute) the functional elements described by the machine executable code 1706. When executing the functional elements described by the machine executable code 1706, the circuit system 1700 should be regarded as dedicated hardware for performing the functional elements disclosed herein. In some examples, processor 1702 may execute the functional elements described by machine executable code 1706 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0202] When implemented by logic circuitry 1708 of processor 1702, machine executable code 1706 adapts processor 1702 to perform operations of the examples disclosed herein. As non-limiting examples, machine executable code 1706 may adapt processor 1702 to perform some or all operations of one or more of process 600, process 700, process 800, process 900, process 1000, and process 1100.

[0203] Likewise, as a non-limiting example, the machine executable code 1706 may adapt the processor 1702 to perform some or all of the features, functions, or operations disclosed herein for one or more of the device 100, the device 200, the device 300, the device 400, or the system 500. More specifically, the features, functions, or operations disclosed herein are for one or more of the following: Figure 1 The PHY portion 102, logic circuit 104, adjustment value 106, SerDes 108, parallel interface 110, bit position detector 112, time stamp logic circuit 114 or indicated bit position 116; Figure 2 Tx timing signal generating circuit 206; Figure 3 RX timing signal generation 302 and optional SerDes parallel interface 308; Figure 4 Rx signal timing adjustment circuit 402 and optional Rx PHY 414; or Figure 5Ethernet PHY 502, Tx timing generator 504, Rx PHY 506, Tx PHY 508, SerDes510, parallel interface 512, Tx timing signal 514, Rx timing generator 516, timestamp marker 518, Tx SerDes specific bit timestamp 522, Rx arbitrary timestamp 524, packet timestamp marking logic component 530, MII or MII equivalent interface 538, MDI 534 or physical transmission medium 536.

[0204] Processor 1702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor executes a functional element corresponding to a machine executable code 1706 (e.g., software code, firmware code, hardware description) associated with an example of the present disclosure, the general-purpose computer is considered a special-purpose computer. It should be noted that a general-purpose processor (which may also be referred to as a host processor or simply a host in this article) may be a microprocessor, but in an alternative, processor 1702 may include any conventional processor, controller, microcontroller, or state machine. Processor 1702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0205] In some examples, storage device 1704 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., but not limited to flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM)). In some examples, processor 1702 and storage device 1704 may be implemented as a single device (e.g., but not limited to semiconductor device product, system on chip (SOC)). In some examples, processor 1702 and storage device 1704 may be implemented as independent devices.

[0206] In some examples, machine executable code 1706 may include computer readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer readable instructions may be stored by storage device 1704, directly accessed by processor 1702, and executed by processor 1702 using at least logic circuit 1708. Likewise, as a non-limiting example, the computer readable instructions may be stored on storage device 1704, transferred to a memory device (not shown) for execution, and executed by processor 1702 using at least logic circuit 1708. Thus, in some examples, Tx PHY 508 includes logic circuit 1708 that can be electrically configured.

[0207] In some examples, machine executable code 1706 may describe hardware (e.g., circuitry) to be implemented in logic circuit 1708 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). As non-limiting examples, Verilog, SystemVerilog, or a very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0208] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations to be performed by the hardware logic circuits (e.g., but not limited to gates, flip-flops, registers) of the logic circuit 1708 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic component, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 1706 may include HDL, RTL, GL description, mask-level description, other hardware descriptions, or any combination thereof.

[0209] In examples where the machine executable code 1706 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1704) implements the hardware description described by the machine executable code 1706. As a non-limiting example, the processor 1702 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1708 may be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit 1708. Likewise, as a non-limiting example, the logic circuit 1708 may include hard-wired logic components manufactured by a manufacturing system (not shown, but including the storage device 1704) according to the hardware description of the machine executable code 1706.

[0210] Regardless of whether the machine executable code 1706 includes computer readable instructions or a hardware description, the logic circuit 1708 is adapted to perform the functional elements described by the machine executable code 1706 when implementing the functional elements of the machine executable code 1706. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0211] The terms used in this disclosure, especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “including” should be interpreted as “including but not limited to,” etc.).

[0212] Additionally, if a specific number of introduced claim recitations is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that a claim recitation introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim recitation to an example containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an" (e.g., "a" and / or "an" may be interpreted to mean "at least one" or "one or more"); the same is true when a definite article is used to introduce a claim recitation.

[0213] In addition, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the unmodified recitation "two recitations" means at least two recitations, or two or more recitations, in the absence of other modifiers). Moreover, in those cases where a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such construction is generally intended to include only A, only B, only C, both A and B, both A and C, both B and C, or all three of A, B, and C, etc. As used herein, "each" refers to some or the whole, and "each" refers to the whole.

[0214] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0215] Additional non-limiting examples include:

[0216] Embodiment 1: A method, comprising: observing an indicated bit position at a parallel interface of a SerDes coupling a PHY to a physical transmission medium; generating a timestamp at least in part in response to observing the indicated bit position; and providing the timestamp to a user.

[0217] Embodiment 2: The method according to embodiment 1, the method comprising: detecting a specific bit representing Tx path data delay; and generating an indication of a position of the detected specific bit.

[0218] Embodiment 3: The method according to any one of Embodiments 1 and 2, wherein detecting the specific bit indicating the Tx path data delay comprises: detecting the specific bit indicating the Tx path data delay in outgoing data.

[0219] Embodiment 4: The method according to any one of embodiments 1 to 3, wherein generating the indication of the position of the detected specific bit includes: generating the indication of the position of the detected specific bit using outgoing data.

[0220] Embodiment 5: A method according to any one of embodiments 1 to 4, wherein generating the timestamp at least partially in response to observing the indicated bit position includes: obtaining a SerDes-specific bit timestamp at least partially in response to observing the indicated bit position at the parallel interface of the SerDes; combining the SerDes-specific bit timestamp with an adjustment value to obtain a packet timestamp; and providing the packet timestamp as the timestamp provided to the user.

[0221] Embodiment 6: The method according to any one of embodiments 1 to 5, wherein the adjustment value represents the duration between the time when the SerDes specific bit crosses the PHY-MAC interface and the time when the message timestamp point of the packet crosses the PHY-MAC interface.

[0222] Embodiment 7: A method according to any one of embodiments 1 to 6, wherein obtaining the SerDes specific bit timestamp at least partially in response to an indicated bit position observed at the parallel interface of the SerDes includes: generating an Rx SerDes arbitrary bit timestamp in response to an indicated position of an arbitrary bit in the incoming data observed at the parallel interface of the SerDes; and combining the Rx SerDes arbitrary bit timestamp with an Rx adjustment value to obtain an RxSerDes specific bit timestamp.

[0223] Embodiment 8: According to the method described in any one of Embodiments 1 to 7, the method comprises: calculating the bit distance between the indicated bit position of the arbitrary bit and the bit position of a specific bit of the Rx SerDes; and calculating the Rx adjustment value at least partially in response to the calculated bit distance and the bit rate of the SerDes.

[0224] Embodiment 9: A method according to any one of embodiments 1 to 8, wherein generating the SerDes specific bit timestamp at least partially in response to an indicated bit position observed at the parallel interface of the SerDes includes: generating a Tx SerDes specific bit timestamp at least partially in response to an indicated bit position of outgoing data observed at the parallel interface of the SerDes.

[0225] Embodiment 10: The method according to any one of embodiments 1 to 9, wherein the user is a TimeSync client.

[0226] Embodiment 11: A device comprising: a SerDes, the SerDes being used to couple a PHY to a physical transmission medium; a timestamp logic circuit; a bit detector, the bit detector being coupled to initiate the timestamp logic circuit at least in part in response to observing an indicated bit position at a parallel interface of the SerDes; and a logic circuit, the logic circuit being disposed at a portion of the PHY, the logic circuit being coupled to receive a timestamp generated by the timestamp logic circuit and to generate a packet timestamp based at least in part on the timestamp.

[0227] Embodiment 12: The apparatus of embodiment 11, comprising a Tx timing signal generating circuit for: detecting a bit in outgoing data visible at a PHY-MAC interface; and using the outgoing data to generate an indication that the detected bit is the indicated bit.

[0228] Embodiment 13: The apparatus according to any one of embodiments 11 and 12, the apparatus comprising an Rx timing signal generating circuit, the Rx timing signal generating circuit being used to: observe any bit in incoming data; and generate an indication of a bit position of the any bit using the incoming data.

[0229] Embodiment 14: An apparatus according to any one of embodiments 11 to 13, wherein the timestamp logic circuit is used to: change the hardware timestamp at least partially in response to an Rx adjustment value, wherein the Rx adjustment value represents the duration between the time when any bit crosses the parallel interface of the SerDes and the time when a specific bit of the SerDes crosses the parallel interface of the SerDes.

[0230] Embodiment 15: The apparatus according to any one of embodiments 11 to 14, wherein the timestamp logic circuit is used to: remove the indication of the bit position of the arbitrary bit and generate the indication of the bit position of the SerDes specific bit.

[0231] Embodiment 16: A device according to any one of embodiments 11 to 15, wherein the logic circuit is used to: calculate the bit distance between the indicated bit position of the arbitrary bit and the bit position of a specific SerDes bit to obtain an arbitrary to specific SerDes bit distance; and calculate the Rx adjustment value at least partially in response to the arbitrary to specific SerDes bit distance and the SerDes bit time.

[0232] Embodiment 17: The apparatus of any one of Embodiments 11 to 16, wherein the SerDes is provided at a physical medium attachment sublayer of the PHY.

[0233] Embodiment 18: The apparatus according to any one of embodiments 11 to 17, comprising a local time source.

[0234] Embodiment 19: The apparatus of any one of Embodiments 11 to 18, wherein the timestamp logic circuit comprises a hardware timestamp marker.

[0235] Embodiment 20: A system comprising: a SerDes interface; a timestamp logic circuit, the timestamp logic circuit being used to generate a timestamp; a bit position detector, the bit position detector being used to: observe an indicated bit position at a parallel interface of the SerDes; and start the timestamp logic circuit; and a logic circuit, the logic circuit being used to receive the timestamp generated by the timestamp logic circuit and to generate a packet timestamp based at least in part on the timestamp.

[0236] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Instead, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. In addition, features from one example may be combined with features of another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A method, comprising: observing the indicated bit position at a parallel interface of a SerDes coupling the PHY to a physical transmission medium; generating a timestamp responsive at least in part to observing a bit position of the indication; as well as The timestamp is provided to the user.

2. The method according to claim 1, comprising: Detecting specific bits that represent Tx path data delay; as well as An indication of the position of the particular bit detected is generated.

3. The method according to claim 2, wherein detecting the specific bit representing the Tx path data delay comprises: The specific bit representing the Tx path data delay is detected in the outgoing data.

4. The method of claim 2, wherein generating the indication of the position of the detected specific bit comprises: The indication of the position of the detected particular bit is generated using outgoing data.

5. The method of claim 1 , wherein generating the timestamp at least in part in response to observing the indicated bit position comprises: obtaining a SerDes specific bit timestamp at least in part in response to observing the indicated bit position at the parallel interface of the SerDes; combining the SerDes specific bit timestamp with an adjustment value to obtain a packet timestamp; as well as The packet timestamp is provided as the timestamp provided to the user.

6. The method of claim 5, wherein the adjustment value represents a duration between a time when the SerDes specific bit crosses a PHY-MAC interface and a time when a message timestamp point of the packet crosses the PHY-MAC interface.

7. The method of claim 5, wherein obtaining the SerDes-specific bit timestamp in response, at least in part, to observing the indicated bit position at the parallel interface of the SerDes comprises: generating an Rx SerDes arbitrary bit timestamp in response to a location at which an indication of an arbitrary bit in incoming data is observed at the parallel interface of the SerDes; and The Rx SerDes arbitrary bit timestamp is combined with the Rx adjustment value to obtain the Rx SerDes specific bit timestamp.

8. The method according to claim 7, comprising: Calculating a bit distance between the indicated bit position of the arbitrary bit and the bit position of an Rx SerDes specific bit; as well as The Rx adjustment value is calculated at least in part in response to the calculated bit distance and a bit rate of the SerDes.

9. The method of claim 8, wherein generating the SerDes-specific bit timestamp at least in part in response to observing the indicated bit position at the parallel interface of the SerDes comprises: A Tx SerDes specific bit timestamp is generated at least in part in response to observing the indicated bit position of outgoing data at the parallel interface of the SerDes.

10. The method according to claim 7, comprising: selecting an arbitrary bit in said incoming data; as well as An indication of the position of any detected bits is generated using the incoming data. The method of claim 1 , wherein the user is a TimeSync client.

12. A device, comprising: SerDes, the SerDes is used to couple the PHY to a physical transmission medium; timestamp logic circuit; a bit detector coupled to enable the timestamp logic circuit in response, at least in part, to observing an indicated bit position at a parallel interface of the SerDes; and A logic circuit is disposed at a portion of the PHY, the logic circuit being coupled to receive the timestamp generated by the timestamp logic circuit and to generate a packet timestamp based at least in part on the timestamp.

13. The device according to claim 12, comprising a Tx timing signal generating circuit, wherein the Tx timing signal generating circuit is used to: detecting bits in outgoing data visible at the PHY-MAC interface; and An indication that the detected bit is the indicated bit is generated using the outgoing data.

14. The device according to claim 12, comprising an Rx timing signal generating circuit, wherein the Rx timing signal generating circuit is configured to: observe any bit in the incoming data; and An indication of a bit position of the arbitrary bit is generated using the incoming data.

15. The apparatus of claim 12, wherein the timestamp logic circuit is configured to: The hardware timestamp is altered at least in part in response to an Rx adjustment value, wherein the Rx adjustment value represents a duration between a time when an arbitrary bit crosses the parallel interface of the SerDes and a time when a particular bit of a SerDes crosses the parallel interface of the SerDes.

16. The apparatus of claim 15, wherein the timestamp logic circuit is configured to: The indication of the bit position of the arbitrary bit is removed and the indication of the bit position of the SerDes specific bit is generated.

17. The apparatus of claim 15, wherein the logic circuit is configured to: Calculating a bit distance between the indicated bit position of the arbitrary bit and a bit position of a SerDes specific bit to obtain an arbitrary to specific SerDes bit distance; and The Rx adjustment value is calculated at least in part in response to the arbitrary to-specific SerDes bit distance and a SerDes bit time.

18. The apparatus of claim 12, wherein the SerDes is provided at a physical medium attachment sublayer of the PHY.

19. The apparatus of claim 12, comprising a local time source.

20. The apparatus of claim 12, wherein the timestamp logic circuit comprises a hardware timestamp marker.

21. A system, comprising: SerDes interface; A timestamp logic circuit, wherein the timestamp logic circuit is used to generate a timestamp; a bit position detector, the bit position detector being used to: observe the indicated bit position at the parallel interface of the SerDes; and starting the timestamp logic circuit; and Logic circuitry is configured to receive the timestamp generated by the timestamp logic circuitry and generate a packet timestamp based at least in part on the timestamp.

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