A precision test platform for delay calculation

Abstract

This invention discloses a precision testing platform for delay calculation, comprising a test data acquisition module for decomposing each timing path of an integrated circuit into multiple independent stages; a test database for storing the computational information required for each stage in a standardized format; a test data modification and file generation module for modifying the stored stage data according to test requirements and reconstructing the modified data into a design file that conforms to the requirements of specific EDA tools; and a test execution and evaluation module for executing the target test software and benchmark third-party software, parsing the results, and performing comparative analysis. This invention addresses the complexity of computational precision evaluation and the difficulty of verifying individual modules in large-scale ASIC designs. By providing a standardized and modular testing environment, it significantly improves the development efficiency and accuracy of VLSI design EDA tools, while also providing an automated process for comparison with third-party software tools.

Description

Technical Field

[0001] The present invention belongs to the technical field of testing EDA tools for IC-side verification, and in particular relates to a precision testing platform for delay calculation. Background Art

[0002] An integrated circuit is a microelectronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) on a small semiconductor substrate. In an integrated circuit, a timing path is the path for a signal to propagate from one timing element to another. When a signal propagates on each timing path, it has its own specific delay. The static timing analysis tool (STA) calculates and checks the delay on each path to verify whether the signal can be correctly propagated within the specified time, ensuring the correctness and reliability of the IC design.

[0003] For circuit designs with tens of millions of gates, timing simulation analysis is very time-consuming, while the STA tool can perform complete circuit analysis and testing more efficiently. As the complexity of modern integrated circuits and the requirements for performance continue to increase, the requirements for delay calculation accuracy in the STA tool are also gradually increasing. Currently, there are the following problems:

[0004] 1. In complex IC circuit design, it is difficult to compare accuracy due to error transmission:

[0005] In integrated circuit (IC) design, each timing path usually contains thousands of stages (in delay calculation, a timing path is divided into multiple stages, i.e. gate-level signal units, and then the delay of each stage is calculated in sequence along the timing path). The output result (jump time) of the previous stage will be used as the input of the next stage, so the calculation accuracy of the jump time of each stage will affect the input of the subsequent stage. Therefore, the error of the final delay result comes from two aspects: the calculation algorithm itself and the cumulative transmission of the error.

[0006] 2. Isolate and verify a single delay calculation function:

[0007] The difficulty in isolating and verifying the delay calculation of a single stage lies in the fact that, in addition to the delay algorithm itself, other factors such as other functions of the static timing analysis (STA) tool or differences in processing the same data may also affect the results of the delay calculation. For example, for multi-input logic gates, the STA tool will merge the internal calculation results, resulting in inconsistencies between the internal data actually used and the final results. In the STA tool, it is usually difficult to directly eliminate these factors.

[0008] 3. The input data of the stage delay calculation lacks a standardized format:

[0009] The input data of stage delay calculation lacks a standardized format. The large amount of input data required for delay calculation is usually stored in text form and processed internally in the STA environment. Therefore, it has no index mechanism and requires full-text search. It is difficult to represent multiple data. With the iteration of versions, the parsing of files requires additional code implementation and verification, which is inefficient and has other limitations.

[0010] 4. Lack of interoperability and comparative fairness between computing and third-party software tools:

[0011] Different STA tools may use different delay models or priorities for processing data, resulting in inconsistent results and increasing the difficulty of comparison and verification.

[0012] Therefore, further improvements are made to the above problems. Summary of the invention

[0013] The main purpose of the present invention is to provide an accuracy testing platform for delay calculation, which solves the complexity of calculation accuracy evaluation and the difficulty of individual module verification in large-scale ASIC design. By providing a standardized and modular testing environment, the present invention significantly improves the development efficiency and accuracy of VLSI design EDA tools, and at the same time provides an automated process for comparison with third-party software tools.

[0014] To achieve the above objectives, the present invention provides an accuracy test platform for delay calculation, comprising: a test data acquisition module, a test database, a test data modification and file generation module, and a test operation and evaluation module, wherein:

[0015] The test data acquisition module is used to decompose each timing path of the integrated circuit into multiple independent stages;

[0016] The test database is used to store the information required for calculation of each stage in a standardized format;

[0017] The test data modification and file generation module is used to modify the stored stage data according to the test requirements, and reconstruct the modified data into design files and data files that meet the requirements of specific EDA tools;

[0018] The test operation and evaluation module is used to execute the target test software (target EDA tool) and the benchmark third-party software, analyze the results and perform comparative analysis.

[0019] As a further preferred technical solution of the above technical solution, the test data acquisition module is specifically implemented as follows:

[0020] Decomposing the timing path, decomposing each timing path of the integrated circuit into multiple stages, each stage including a single-input single-output logic gate and a wire connected thereto for connecting one or more loads;

[0021] Perform logic gate processing to split a multi-input logic gate into multiple equivalent single-input single-output logic gates. Specifically, when extracting the information of the multi-input logic gate in the standard cell library, split the information of the cell timing arc to ensure that each single-input single-output logic gate is consistent with the original multi-input logic gate in timing behavior, while keeping the subsequent wire structure unchanged to ensure the integrity of the signal flow path;

[0022] Perform stage data export and standardization, define a unified data structure or file format, and create standardized fields and attributes for each type of data to ensure data consistency and interoperability as well as indexing capabilities.

[0023] As a further preferred technical solution of the above technical solution, in stage data export and standardization:

[0024] Parasitic parameters are processed. The parasitic parameters on the wire include resistance and capacitance. The default structure of the wire is a tree structure, that is, a wire has a unique input and one or more end nodes. There is a capacitor connected to the ground on each node, and no resistor is connected to the ground. There is only one resistor connected between the nodes, and there is no capacitor between any two non-ground nodes. Based on the above structure, 4 arrays are used to represent the RC tree structure; first, the RC tree structure is traversed from the driver end, and each node is numbered. The values ​​of the traversed resistors and capacitors will be saved in the resistor array and the capacitor array in turn. In order to represent the structure of the tree, the link array is used to store the resistor parent node, and the end node array is used to store the number of the end node;

[0025] Standard cell library information extraction, extracting the timing arc data set used for timing calculation. The timing arc represents the timing relationship between the input and output of the logic gate, including delay, transition time and polarity. The timing arc modeling is divided into nonlinear delay model, composite current source model and effective current source model. The delay table in the nonlinear delay model of the logic gate timing arc is parsed, the transition time is fixed as the vertical axis, the output load is fixed as the horizontal axis, and then the delay table in the two-dimensional is stored in the form of rows. For a single-input single-output logic gate, there are one or more timing arcs from each input to the output, or a multi-input logic gate may have multiple inputs. After parsing the standard cell library, the timing arc data from each input port to the output port is extracted, and the numbers of the stages using this timing arc are matched to each other. In the test reconstruction stage, a separate single-input single-output logic gate is created for each timing arc.

[0026] Stage timing constraints: the input transition time of each stage is the output transition time of the previous stage. The timing constraints are recorded after the path is split.

[0027] As a further preferred technical solution of the above technical solution, the test database stores and manages the extracted and standardized data, stores and maintains all relevant stage data, and the test database includes the currently processed stage data, historical stage data and randomly generated data, thereby fully supporting testing and analysis requirements.

[0028] As a further preferred technical solution of the above technical solution, for the test data modification and file generation module, the original data is converted into a format that meets the requirements of specific third-party software (if the original data is not modified, the reconstructed design will retain the original timing characteristics; if the original data is modified, some timing behaviors (such as signal delay, jump time) may change), wherein:

[0029] Generate a parasitic parameter file that conforms to a specific format. From the above-saved RC tree structure, restore the tree structure and generate the required file format. First, determine the output format: First, determine the format of the target file. Second, write the file header. Third, traverse the data structure, starting from the root node, and traverse the entire RC tree structure. Fourth, write the formatted data. During the traversal process, convert the data into the specific syntax required by the target format.

[0030] Reconstruct the netlist information so that each stage exists as an independent entity;

[0031] Create standard cell library files that meet the requirements of various EDA tools. When reconstructing logic gates, process the timing arc from each input port to the output port separately. In the data extraction stage, after parsing the original lib, copy the stored timing information to the new single-input single-output logic gate, retaining the original timing characteristics, that is, using the same input jump time, the reconstructed total delay and output jump time match the original logic gate. After reconstructing the logic gate, it is necessary to create a standard cell library that meets the requirements of various EDA tools. The file contains not only the reconstructed logic cell data, but also the necessary metadata and annotations.

[0032] Create timing constraints for the input port of each stage. Timing constraints are used to specify the time relationship of signals in digital circuits and are set at the input and output ports of the module. In the reconstructed design, it is necessary to define the expected signal transition time for the input port of each stage. The format of the created timing constraints depends on the requirements of various EDA tools based on the output characteristics of the previous stage in the original design and the calculated threshold. Create constraints for each input port of each stage.

[0033] As a further preferred technical solution of the above technical solution, for the test operation and evaluation module, the results of the third-party software are compared with the results of the target test software in stages, and the evaluation conclusion of the algorithm is obtained through in-depth statistical analysis, wherein:

[0034] Data collection and organization: Data collection uses automated scripts. For the comparison object, after the test, the output results are parsed from the location and naming rules of the determined log file. During the parsing, the results of each test case are identified and extracted, including the delay of logic gates and wires, the output jump time of logic gates, and the jump time of wire outputs. For the target test software, there are two ways. The first is to directly collect the output results when calculating the timing path through the API provided in the EDA software. The second way is suitable for the calculation code to be developed in the form of an independent library, providing a special API interface to directly pass in the data required by the calculation stage. After the calculation, the results are stored through the interface.

[0035] Result Evaluation,When evaluating computational algorithms with third-party software,,key indicators include the error percentage of timing,analysis results, running time, and resource usage. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a structural schematic diagram of the present invention.

[0037] Figure 2 It is a schematic diagram of logic gate processing of the present invention.

[0038] Figure 3 It is a schematic diagram of parasitic parameter processing of the present invention.

[0039] Figure 4 It is a schematic diagram of stage timing constraints of the present invention.

[0040] Figure 5 It is a schematic diagram of the netlist reconstruction of the present invention. DETAILED DESCRIPTION

[0041] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0042] In the preferred embodiments of the present invention, those skilled in the art should note that the integrated circuits, third-party software, etc. involved in the present invention may be regarded as prior art.

[0043] Preferred embodiments.

[0044] like Figure 1-5 As shown, the present invention discloses an accuracy test platform for delay calculation, including: a test data acquisition module, a test database, a test data modification and file generation module and a test operation and evaluation module, wherein:

[0045] The test data acquisition module is used to decompose each timing path of an integrated circuit (IC) into multiple independent stages;

[0046] The test database is used to store the information required for calculation of each stage in a standardized format;

[0047] The test data modification and file generation module is used to modify the stored stage data according to the test requirements, and reconstruct the modified data into design files and data files that meet the requirements of specific EDA tools (in order to better analyze and evaluate with the analysis results of third-party software in the test operation and evaluation module);

[0048] The test operation and evaluation module is used to execute the target test software and the benchmark third-party software, analyze the results and perform comparative analysis.

[0049] Specifically, the test data collection module is implemented as follows:

[0050] Perform timing path decomposition, decomposing each timing path of the integrated circuit into multiple stages, each stage contains a single-input single-output (SISO) logic gate and a wire connected to it for connecting one or more loads (therefore, multi-input logic gates need to be further decomposed, and the delay of a stage is the delay of the logic gate plus the delay of the signal passing through the wire);

[0051] Perform logic gate processing, such as Figure 2 As shown, a multi-input logic gate is split into multiple equivalent single-input single-output (SISO) logic gates. Specifically, when extracting the information of the multi-input logic gate in the standard cell library, the information of the cell arc is split to ensure that each single-input single-output logic gate is consistent with the original multi-input logic gate in timing behavior, while keeping the subsequent wire structure unchanged to ensure the integrity of the signal flow path;

[0052] Perform stage data export and standardization, define a unified data structure or file format, and create standardized fields and attributes for each type of data to ensure data consistency and interoperability as well as indexing capabilities.

[0053] More specifically, in stage data export and standardization:

[0054] Perform parasitic parameter processing, such as Figure 3 As shown, the parasitic parameters on the wire include resistance and capacitance. The default structure of the wire is a tree structure, that is, a wire has a unique input and one or more end nodes. Each node has a capacitor connected to ground and no resistor is connected to ground. There is one and only one resistor connected between the nodes. There is no capacitor between any two non-ground nodes. Based on the above structure, four arrays (resistance array, capacitance array, link array and end node array) are used to represent the RC tree structure; first, the RC tree structure is traversed from the driving end, and each node is numbered. The values ​​of the traversed resistance and capacitance will be saved in the resistance array and the capacitance array in turn. In order to represent the structure of the tree, the link array is used to store the parent node of the resistance (the link array is used to store the number of the parent node of the resistance (located at a higher level of the tree, closer to the root node)), (the number of the node closer to the driving end) The end node array is used to store the number of the end node;

[0055] Standard cell library information extraction, extracting the timing arc data set for timing calculation. The timing arc represents the timing relationship between the input and output of the logic gate, including delay (the time required for the input change to propagate to the output), slew time (i.e., the time required for the signal to switch from low to high or from high to low), and polarity (the relationship between the direction conversion of the input and output signals); timing arc modeling is divided into nonlinear delay model (NLDM), composite current source (CCS) model, and effective current source model (ECSM) (the models contained in the standard cell library are different, and the timing arc may be generated by different models). (Taking the nonlinear delay model as an example) the delay table in the nonlinear delay model of the logic gate timing arc is decoded. Analysis (for example, for NLDM, it uses the input parameters: transition time and output load, and uses a two-dimensional lookup table to find the output delay and output transition time respectively) to fix the transition time as the vertical axis and the output load (load capacitance value) as the horizontal axis, and then store the delay time in the two-dimensional table in the form of rows; for a single-input single-output logic gate, there are one or more timing arcs from each input to the output, or a multi-input logic gate may have multiple input terminals. After parsing the standard cell library, the timing arc data from each input port to the output port is extracted, and the numbers of the stages using this timing arc are matched to each other. In the test reconstruction stage, a separate single-input single-output logic gate is created for each timing arc;

[0056] Stage timing constraints, the input jump time of each stage is the output jump time of the previous stage. The timing constraints are recorded after the path is split (the input information of the stage will be lost. In order to restore the original stage calculation, these timing constraints need to be recorded, such as Figure 4(Sa, Sb, Si) in it). Furthermore, the test database stores and manages the extracted and standardized data, stores (for example, in json format) and maintains all relevant stage data. The test database includes the currently processed stage data, historical stage data and randomly generated data, so as to fully support the test and analysis requirements (the structural design of the database takes into account the complexity of the data and the iteration of the development process. First, the data entry of each stage contains multiple fields, such as the stage end unique end ID, logic gate type, wire parameters, timing constraints, etc. In order to improve the efficiency of data retrieval, an index structure is used in the database. The main indexes include stage identifiers, logic gate types, processes used in the original design, etc. This indexing strategy can quickly locate a specific stage or a set of stages that meet specific conditions in a large amount of data. Secondly, for the historical stage end data, a version control mechanism is implemented. Each time the standardized format is modified or updated, a new version record and interface are generated, while ensuring compatibility with the old version of the data. The randomly generated data is used in the test database to test various extreme cases and boundary conditions. The random data generator is based on a predefined parameter range and distribution model to ensure that the generated data can cover various possible scenarios);

[0057] An index structure for fast retrieval, including stage identifiers, logic gate types, and the process used in the original design; a version control mechanism for tracking performance changes over versions and ensuring the validity of old versions after iterations; randomly generated data for testing various extreme situations and boundary conditions.

[0058] Furthermore, for the test data modification and file generation module, the original data is converted into a format that meets the requirements of specific third-party software (if the original data is not modified, the reconstructed design will retain the original timing characteristics; if the original data is modified, some timing behaviors (such as signal delay and jump time) may change), where:

[0059] Generate a parasitic parameter file that conforms to a specific format, restore the tree structure from the above-mentioned saved RC tree structure, and generate the required file format; first determine the output format: first, it is necessary to determine the format of the target file (such as SPEF, SPICE, etc., each format has its specific syntax and structure requirements); second, write the file header (write the necessary file header information according to the requirements of the target format. For example, the SPEF file requires version information, design name, and units of electronic components, etc.); third, traverse the data structure, starting from the root node, traverse the entire RC tree structure (a. Establish nodes by traversing the capacitor array; b. Traverse the resistor array and the link array at the same time, and process the connection between nodes (resistors are edges); c. Traverse the end node array and mark the end node); fourth, write formatted data. During the traversal process, convert the data into the specific syntax required by the target format (for example, for SPEF, it may be necessary to generate *D_NET, *CONN, *CAP, *RES, etc. statements; for SPICE, it may be necessary to generate description lines for resistors (R) and capacitors (C));

[0060] Reconstruct the netlist information so that each stage exists as an independent entity;

[0061] In IC design, netlist information represents the connection relationship between logic gates. Here, stage-based netlist reconstruction is used. The following is a detailed explanation of this method:

[0062] 1. Basic concepts:

[0063] Split the entire IC design into multiple independent stages, each stage contains a single-input and single-output logic gate and a network line (net) connected to it;

[0064] Each stage is described separately, and its connection information with other stages is not retained. The input of the stage is replaced by the input port of the netlist module, and all the logic gates of the next stage connected by the net will be replaced by the output port;

[0065] These stages exist as an independent entity in the reconstructed netlist, and each stage is a path, thus eliminating the error propagation caused by the path.

[0066] 2. Reconstructed netlist structure. Taking the previous example, in the original design, the port definition consists of two input ports and one output port, and the internal logic consists of two logic gate units forming a path. After reconstruction, Figure 5 As shown, this timing path is decomposed into three logic gates, each of which is directly connected to the input port and output port of the module. The internal logic of the module consists of three timing paths.

[0067] Create standard cell library files that meet the requirements of various EDA tools. When reconstructing the logic gate, process the timing arc from each input port to the output port separately. In the data extraction stage, after parsing the original lib, copy the stored timing information to the new single-input single-output logic gate, retaining the original timing characteristics, that is, using the same input jump time, the reconstructed total delay and output jump time match the original logic gate. After reconstructing the logic gate, it is necessary to create a standard cell library that meets the requirements of various EDA tools. The file contains not only the reconstructed logic cell data, but also the necessary metadata and annotations (such as units, delay calculation level thresholds, and rising and falling edge judgment thresholds, etc., to restore the parameters used for calculation);

[0068] Create timing constraints for the input port of each stage. Timing constraints are used to specify the time relationship of signals in digital circuits and are set at the input and output ports of the module. In the reconstructed design, (in order to restore the stage calculation in the original design) it is necessary to define the expected signal jump time for the input port of each stage. Based on the output characteristics of the previous stage in the original design and the calculated threshold, the format of the created timing constraints depends on the requirements of various EDA tools. Create constraints for each input port of each stage.

[0069] Furthermore, for the test run and evaluation module, the results of the third-party software are compared with the results of the target test software (own algorithm software) in stages, and the evaluation conclusions of the algorithm are obtained through in-depth statistical analysis, among which:

[0070] Data collection and organization: Data collection uses automated scripts. For the comparison object, after the test, the output results are parsed from the location and naming rules of the log file. During the parsing, the results of each test case (stage) are identified and extracted, including the delay of logic gates and wires, the output jump time of logic gates, and the jump time of wire outputs. For the target test software, there are two ways. The first is to directly collect the output results when calculating the timing path through the API provided in the EDA software (in order to facilitate the comparison of results, the data is converted and standardized to create a unified data structure, such as JSON or CSV format, containing key fields such as logic gate jump time, wire jump time, wire delay, gate delay, and marked by the stage end ID for easy query. The data is stored in the database to facilitate repeated comparisons during the iteration process); the second method is applicable when the calculation code is developed in the form of an independent library, providing a special API interface to directly input the data required by the calculation stage (that is, the standardized data in the test database). After the calculation, the result is stored through the interface (that is, there are two algorithms for extracting the results of the test algorithm. The first is in the API of the test data acquisition module, and an interface for extracting data is also provided. When the stage is decomposed, the calculation results can be provided at the same time; the second method is applicable when the delay calculation algorithm is developed in the form of an independent library, providing an interface API, directly inputting the data in the above stage calculation, and the calculated result is output through the interface and marked with the stage number, and stored in the form of pure data);

[0071] Result evaluation, when evaluating the calculation algorithm with third-party software, key indicators include the error percentage of timing analysis results, running time and resource usage (CPU memory usage) (accuracy is one of the most basic indicators, and it is necessary to compare the results of each stage in detail, calculate the average error and standard deviation, and evaluate the accuracy of the overall algorithm. It is also possible to extract specific analysis of stages other than the maximum / minimum error and standard deviation to locate the specific stage of the problem, providing precise direction for subsequent optimization).

[0072] The main process of the present invention is to decompose the calculation: decompose the complex IC design into independent stages to achieve independent testing, storage and reconstruction of individual units;

[0073] Standardized storage: Use a standard format to store the information required for calculation at each stage, ensuring data consistency and accessibility, as well as consistency with the original data after restoration;

[0074] API interface and cross-platform compatibility: Access is provided through standardized API, which facilitates seamless integration with various software tools. At the same time, data comparison and result verification with third-party software are supported;

[0075] Flexible data source: With the support of standardized storage, comprehensive testing can be carried out using pre-generated databases, existing designs, or randomly generated data on the end according to test requirements;

[0076] Generate test report: Automatically evaluate the calculation accuracy of delay and slew time, generate detailed statistical reports, and provide in-depth performance analysis and accuracy comparison.

[0077] The advantages of the present invention are:

[0078] 1. Formatting text data to achieve scalability

[0079] By converting all complex text information into standardized data formats, unnecessary operations and terminal information are reduced during the development process. In the future, more software interfaces and plug-ins can be provided as the demand increases. Format independence allows us to easily convert from one format to another. We can also flexibly support multiple output formats by simply implementing the corresponding output logic for each terminal format.

[0080] 2. Simplify complex problems

[0081] Decomposing a timing path into a set of path units and decomposing a multi-input logic gate into multiple single-input logic gate terminals ensures that the purest delay calculation results can be obtained, thereby improving the accuracy and controllability of the analysis.

[0082] It is worth mentioning that the technical features such as integrated circuits and third-party software involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected according to the conventional selection in the field, and should not be regarded as the inventive point of the patent of this invention. The patent of this invention will not be further elaborated.

[0083] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A precision test platform for delay calculation, characterized in that: include: A test data acquisition module is used to decompose each timing path of the integrated circuit into multiple independent stages; The specific implementation of the test data acquisition module is as follows: Decomposing the timing path, decomposing each timing path of the integrated circuit into multiple stages, each stage including a single-input single-output logic gate and a wire connected thereto for connecting one or more loads; Perform logic gate processing to split a multi-input logic gate into multiple equivalent single-input single-output logic gates; Export and standardize stage data, define a unified data structure or file format, and create standardized fields and attributes for each type of data to ensure data consistency and interoperability as well as indexing capabilities; In stage data export and standardization: Parasitic parameters are processed. The parasitic parameters on the wire include resistance and capacitance. The default structure of the wire is a tree structure, that is, a wire has a unique input and one or more end nodes. There is a capacitor connected to ground on each node, and no resistor is connected to ground. There is only one resistor connected between the nodes, and there is no capacitor between any two non-ground nodes. Based on the above structure, 4 arrays are used to represent the RC tree structure; first, the RC tree structure is traversed from the driver end, and each node is numbered. The values ​​of the traversed resistors and capacitors will be saved in the resistor array and the capacitor array in turn. In order to represent the structure of the tree, the link array is used to store the parent node of the resistor, and the end node array is used to store the number of the end node; Standard cell library information extraction: extracting the timing arc data set used for timing calculation. The timing arc represents the timing relationship between the input and output of the logic gate, including delay, transition time, and polarity. Timing arc modeling is divided into nonlinear delay model, composite current source model and effective current source model. The delay table in the nonlinear delay model of the logic gate timing arc is parsed, the jump time is fixed as the vertical axis, the output load is fixed as the horizontal axis, and then the delay table in the two-dimensional is stored in the form of rows; for a single-input single-output logic gate, there are one or more timing arcs from each input to output, or a multi-input logic gate may have multiple input terminals. After parsing the standard cell library, the timing arc data from each input port to the output port is extracted, and the numbers of the stages using this timing arc are matched to each other. In the test reconstruction stage, a separate single-input single-output logic gate is created for each timing arc; Stage timing constraints: the input transition time of each stage is the output transition time of the previous stage. The timing constraints are recorded after the path is split; The test database is used to store the information required for calculations at each stage in a standardized format; The test data modification and file generation module is used to modify the stored stage data according to the test requirements and reconstruct the modified data into design files and data files that meet the requirements of specific EDA tools; The test run and evaluation module is used to execute the target EDA tool and benchmark third-party software, analyze the results and perform comparative analysis.

2. The accuracy test platform for delay calculation according to claim 1, characterized in that: The specific implementation of logic gate processing is to split the information of the unit timing arc when extracting the information of the multi-input logic gate in the standard unit library, ensuring that each single-input and single-output logic gate is consistent with the original multi-input logic gate in timing behavior, while keeping the subsequent wire structure unchanged to ensure the integrity of the signal flow path.

3. The accuracy test platform for delay calculation according to claim 2, characterized in that: The test database stores and manages the extracted and standardized data, and stores and maintains all relevant stage data. The test database includes the currently processed stage data, historical stage data, and randomly generated data, thereby fully supporting testing and analysis requirements.

4. The accuracy test platform for delay calculation according to claim 3, characterized in that: For the test data modification and file generation module, the raw data is converted into a format that meets the requirements of specific third-party software, including: Generate a parasitic parameter file that conforms to a specific format. From the above-saved RC tree structure, restore the tree structure and generate the required file format. First, determine the output format: First, determine the format of the target file. Second, write the file header. Third, traverse the data structure, starting from the root node, and traverse the entire RC tree structure. Fourth, write the formatted data. During the traversal process, convert the data into the specific syntax required by the target format. Reconstruct the netlist information so that each stage exists as an independent entity; Create standard cell library files that meet the requirements of various EDA tools. When reconstructing logic gates, process the timing arc from each input port to the output port separately. In the data extraction stage, after parsing the original lib, copy the stored timing information to the new single-input single-output logic gate, retaining the original timing characteristics, that is, using the same input jump time, the reconstructed total delay and output jump time match the original logic gate. After reconstructing the logic gate, it is necessary to create a standard cell library that meets the requirements of various EDA tools. The file contains not only the reconstructed logic cell data, but also the necessary metadata and annotations. Create timing constraints for the input port of each stage. Timing constraints are used to specify the time relationship of signals in digital circuits and are set at the input and output ports of the module. In the reconstructed design, it is necessary to define the expected signal transition time for the input port of each stage. The format of the created timing constraints depends on the requirements of various EDA tools based on the output characteristics of the previous stage in the original design and the calculated threshold. Create constraints for each input port of each stage.

5. The accuracy test platform for delay calculation according to claim 4, characterized in that: For the test run and evaluation module, the results of the third-party software are compared with the results of the target test software in stages, and the evaluation conclusions of the algorithm are obtained through in-depth statistical analysis, including: Data collection and organization: Data collection uses automated scripts. For the comparison object, after the test, the output results are parsed from the location and naming rules of the log file. During the parsing, the results of each test case are identified and extracted, including the delay of logic gates and wires, the output jump time of logic gates, and the jump time of wire outputs. For the target test software, there are two ways. The first is to directly collect the output results when calculating the timing path through the API provided in the EDA software. The second method is suitable for the calculation code to be developed in the form of an independent library, providing a special API interface to directly pass in the data required for the calculation stage. After the calculation, the results are stored through the interface. Result Evaluation,When evaluating computational algorithms with third-party software,,key indicators include the error percentage of timing,analysis results, running time, and resource usage.

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