An over-current protection circuit applied to a low voltage input LDO

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to an overcurrent protection circuit applied to a low-voltage input LDO, which comprises: a current sampling circuit, an operational amplifier circuit and a current comparison circuit; the current sampling circuit is used for sampling an LDO load current and converting the LDO load current into a voltage signal; the operational amplifier circuit is used for ensuring the accuracy of sampling and outputting a comparison signal; and the current comparison circuit is used for converting the comparison signal output by the operational amplifier circuit into a current signal and comparing the current signal with a reference current source to limit the current of an output power tube when the output of the LDO overflows. The circuit output tube and the sampling tube are at the same potential at each port during sampling, have the characteristics of accurate sampling and easy design, and have a certain universality in circuit design.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, and in particular relates to an overcurrent protection circuit applied to a low-voltage input LDO. Background Art

[0002] Overcurrent protection circuits are a common submodule in low-dropout linear regulator (LDO) chips. When a high-power NMOS transistor serves as the LDO's output transistor, it can easily break down and burn out if a current overload or output short circuit occurs. Therefore, LDOs require overcurrent protection to limit the current flowing through the output transistor, protecting both the LDO chip and the downstream load.

[0003] There are two common problems with the design of overcurrent protection circuits for LDOs. First, current sampling is not accurate enough, and the sampling circuit has a certain degree of offset, resulting in large differences in the LDO current limit under different application conditions. Second, sampling and processing the output current signal usually requires additional comparators, reference modules, and other modules. In addition, to meet the low voltage difference requirements, an additional internal power supply is usually required. The large circuit scale leads to high chip costs. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention provides an overcurrent protection circuit applied to a low voltage input LDO, characterized in that it includes: a current sampling circuit, an operational amplifier circuit and a current comparison circuit;

[0005] The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal;

[0006] The operational amplifier circuit is used to ensure sampling accuracy and output a comparison signal;

[0007] The current comparison circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with a reference current source, so as to limit the current of the output power tube when the output of the LDO is overcurrent.

[0008] Beneficial effects of the present invention:

[0009] (1) The output tube and the sampling tube of the circuit of the present invention are at the same potential when sampling, and the current sampling accuracy is high;

[0010] (2) The circuit of the present invention has a dual power supply structure, and the power supply voltage required for operation is low;

[0011] (3) The circuit of the present invention requires less external bias, has a simple structure and is low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a circuit principle diagram of the present invention;

[0013] Figure 2 This is a simulation diagram of the waveform of key nodes of the circuit changing with load current under the 0.35um BCD process of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0015] like Figure 1 As shown, an embodiment of the present invention provides an overcurrent protection circuit applied to a low-voltage input LDO, characterized in that it includes: a current sampling circuit, an operational amplifier circuit and a current comparison circuit;

[0016] The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal;

[0017] The operational amplifier circuit is used to ensure sampling accuracy and output a comparison signal;

[0018] The current comparator circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with the reference current source, thereby limiting the current of the output power tube when the output of the LDO is overcurrent.

[0019] The current sampling circuit includes an operational amplifier A0, resistors R1-R2, and NMOS transistors N1-N3. These components form the basic structure of an LDO. The positive input of operational amplifier A0 is connected to the reference voltage VREF, while the output is connected to the gates of output power transistor N1 and sampling transistor N2, designated VG. N1's drain is connected to the first power supply VIN, and its source is connected to one end of resistor R1, serving as the LDO output port LDOOUT (VP). The other end of R1 is connected to one end of R2 and to the negative input of A0. The other end of R2 is grounded to GND. The drain of sampling transistor N2 is connected to the first power supply VIN, while its source is connected to the drain of N3 (VM). The source of N3 is grounded to GND.

[0020] An operational amplifier circuit includes PMOS transistors P1-P10, NMOS transistors N4-N8, bias current sources IBIAS1-IBIAS2, and a bias voltage source VBIAS1. The sources of P1, P2, P3, and P4 are connected to a first power supply VIN, and the drain of P1 is connected to IBIAS1 and connected to the gates of P1, P2, P3, and P4 to form a current mirror structure.

[0021] The sources of P5 and P6 are connected to the second power supply VCP, the drain of P5 is connected to IBIAS2 and connected to the gates of P5 and P6 to form a current mirror structure; the drain of P6 is connected to the source of P7 and P8; the drain of P2 is connected to the source of P9 and P10; the gates of P7 and P10 are connected to VM and connected to the drain of N4; the gates of P8 and P9 are connected to VP; the drain of P3 is connected to the drain of N5 and is connected to the gates of N7 and N8; the drain of P4 is connected to the drain of N6 The drain of P7 and P10 is connected to the source of N5 and the drain of N7, and the drain of P8 and P9 is connected to the source of N6 and the drain of N8; the source of N7 and N8 is grounded to GND; P7-P10 and N4-N8 together constitute a folded common-source common-gate structure.

[0022] The current comparison circuit includes PMOS transistors P11-P12, NMOS transistors N9-N13, a reference current source IREF, and a bias voltage source VBIAS2. The drain of N9 is connected to a first power supply VIN; the gates of N9 and N10 are connected to the bias voltage source VBIAS2; the source of N9 is connected to the gate of N11 and to VO; the sources of P11 and P12 are connected to the first power supply VIN, and the gates of P11 and P12 are connected to the drain of P11 and the drain of N10; the source of N10 is connected to the drain of N11 and to the reference current source VREF; the source of N11 is grounded GND; the drain of P12 is connected to the drain of N12, the gate of N12, and the gate of N13; the sources of N12 and N13 are grounded GND; and the drain of N13 is connected to VG in the current sampling circuit.

[0023] The principles of the present invention are as follows:

[0024] In the current sampling circuit of the present invention, the basic structure of the LDO is represented by an operational amplifier A0, resistors R1-R2, and an NMOS transistor N1, where N1 is the output power transistor of the LDO. Ignoring the offset in the circuit, the operational amplifier circuit of the subsequent stage clamps the VP and VM points to the same voltage, that is, it can be considered that VP = VM in the normal working state of the LDO without overcurrent. Assuming that the width-to-length ratio of N1 and N2 is N1:N2 = m:1 (m is a first positive integer), the load current of the LDO is I load , we can get the current of sampling tube N2 at this time:

[0025]

[0026] Among them, I N2 is the current flowing through the sampling tube N2.

[0027] Since the gate, source, and drain voltages of the sampling tube N2 and the power tube N1 are the same in this structure, N2 can perform accurate current sampling.

[0028] In the operational amplifier circuit of the present invention, P7, P8, P9, and P10 form a dual-input structure, where the gates of P7 and P10 serve as the positive input terminal VM of the operational amplifier, and the gates of P8 and P9 serve as the negative input terminal VP of the operational amplifier. The operational amplifier is powered by two power sources: a first power supply VIN and a second power supply VCP. The first power supply VIN is typically the chip's power supply, and the second power supply VCP is typically an internal power supply generated by the chip's internal charge pump. LDOs with NMOS output power transistors typically have an internal charge pump module, making the circuit somewhat versatile. IBIAS1 and IBIAS2 provide bias currents for the dual inputs, respectively. When the circuit operates at a higher power supply, the dual-input structure formed by P7, P8, P9, and P10 operates simultaneously. When the circuit operates at a lower power supply, VCP > VIN, and VIN is insufficient to provide a sufficient voltage difference for P9 and P10. VCP then powers the input terminal formed by P7 and P8, and the operational amplifier circuit switches to single-input mode and continues operation. P7, P8, P9, P10, N5, N6, N7, and N8 form the op amp's folded cascode structure, providing high gain while increasing the op amp's swing, ensuring normal operation at low power supplies (VIN). The gates of N4, N5, and N6 are driven by a suitable bias voltage (VBIAS1). N4's function is to generate a suitable voltage at the drain, or the op amp's positive input terminal (VP), before the LDO's output is established or when the LDO is unloaded. This improves the speed and accuracy of overcurrent detection after the LDO load is established.

[0029] The working principle of the operational amplifier circuit is as follows: When the load current I load When the gate voltage VG of N1 and N2 increases, the current I N2 As the voltage increases, the source voltage VM of N2 tends to rise. VP, the output terminal of the LDO, is assumed to remain constant despite changes in the LDO load. Therefore, an increase in VM causes the drain voltages of P7 and P10 to decrease, while the drain voltages of P8 and P9 increase, leading to an increase in the op amp's output voltage, VO. This increase in VO feeds back to the N3 transistor in the current sampling circuit, increasing its conduction level and causing VM to decrease, thus achieving the op amp's clamping effect on VP and VM.

[0030] In the current comparison circuit of the present invention, the bias voltage VBIAS2 provides a bias for the gates of N9 and N10, turning on N9 before the output VO of the operational amplifier is established, so that VO has an initial voltage, thereby improving the establishment speed and detection accuracy of overcurrent detection. N10 works as a switch tube. IREF is the maximum I REF When the LDO is in a non-overcurrent state, the output VO of the operational amplifier is low, N11 is turned on and operates in the saturation region, and the current flowing through N11 can be obtained as:

[0031]

[0032] Among them, I N11 is the current flowing through N11, μ n is the electron mobility, C ox is the oxide layer capacitance, W N11 is the channel width of N11, L N11 is the channel length of N11, V GSN11 is the gate-source voltage of N11, V TH is the threshold voltage of the MOS tube, and VO is the voltage at the VO point.

[0033] From formula (2), we can know that as the voltage of the operational amplifier output VO increases, the current flowing through N11 will increase accordingly. When VO continues to rise until it exceeds the maximum current I REF When the reference current source IREF is insufficient to provide sufficient current to N11, N10 turns on and P11 continues to provide additional current to N11. At this time, the current of P11 is copied to N13 by the current mirror structure composed of P11, P12, N12, and N13, causing it to have a tendency to flow through the current, thereby pulling the VG point to a low level, thereby limiting the output current of the LDO output power tube N1 and realizing the overcurrent protection function.

[0034] In the current sampling circuit, the N3 tube works in the saturation region, and its current can be obtained as:

[0035]

[0036] Among them, I N3 is the current flowing through N3, I N2 is the current flowing through N2, W N3 is the channel width of N3, L N3 is the channel length of N3, V GSN3 is the gate-source voltage of N3;

[0037] Assume that the width-to-length ratio of N3 and N11 is N3:N11=n:1 (n is the second positive integer), that is:

[0038]

[0039] Combining formulas (2), (3), and (4), we can get the current I of N11: N11 for:

[0040]

[0041] And it is assumed that when the current of N11 is equal to I REF When is the detection flip threshold of the overcurrent protection circuit, that is:

[0042] I N11 =I REF (6)

[0043] Combining formulas (1), (3), (5), and (6), we can get the output current limit of LDO I LIM for:

[0044] I LIM =m·n·I REF (7)

[0045] From formula (7), it can be obtained that the output current limit value of the overcurrent protection circuit of the present invention for the LDO is only related to the width-to-length ratio of N1, N2 and N3, N11. It has the characteristics of accurate sampling and easy design, and has certain versatility in circuit design.

[0046] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. An overcurrent protection circuit for a low voltage input LDO, characterized in that: include: Current sampling circuit, operational amplifier circuit and current comparison circuit; The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal; The operational amplifier circuit is used to ensure sampling accuracy and output a comparison signal; The current comparison circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with the reference current source, thereby limiting the current of the output power tube when the output of the LDO is overcurrent; The operational amplifier circuit includes: PMOS transistors P1-P10, NMOS transistors N4-N8, bias current sources IBIAS1-IBIAS2, and a bias voltage source VBIAS1; The sources of the PMOS transistors P1, P2, P3, and P4 are connected to the first power supply VIN, the current sampling circuit, and the current comparison circuit; The drain of the PMOS transistor P1 is connected to the bias current source IBIAS1 and is connected to the gates of the PMOS transistors P1, P2, P3, and P4 to form a current mirror structure; The sources of the PMOS transistors P5 and P6 are connected to the second power supply VCP, the drain of the PMOS transistor P5 is connected to the bias current source IBIAS2 and is connected to the gates of the PMOS transistors P5 and P6 to form a current mirror structure; The drain of the PMOS transistor P6 is connected to the sources of the PMOS transistors P7 and P8; The drain of the PMOS transistor P2 is connected to the sources of the PMOS transistors P9 and P10; The gates of the PMOS tubes P7, P8, P9, and P10 are connected to a current sampling circuit; The gates of the PMOS transistors P7 and P10 are connected to the drain of the NMOS transistor N4; The drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, and is also connected to the gates of the NMOS transistors N7 and N8; The drain of the PMOS transistor P4 is connected to the drain of the NMOS transistor N6, and is also connected to the current sampling circuit and the current comparison circuit, which is named VO. The gates of NMOS transistors N4, N5, and N6 are connected to the bias voltage source VBIAS1; The source of the NMOS tube N4 is grounded to GND, a current sampling circuit and a current comparison circuit; The drains of the PMOS transistors P7 and P10 are connected to the source of the NMOS transistor N5 and to the drain of the NMOS transistor N7; The drains of the PMOS transistors P8 and P9 are connected to the source of the NMOS transistor N6 and to the drain of the NMOS transistor N8; The source electrodes of the NMOS tubes N7 and N8 are grounded to GND, a current sampling circuit and a current comparison circuit; The PMOS transistors P7-P10 and the NMOS transistors N4-N8 together form a folded cascode structure.

2. The overcurrent protection circuit for low voltage input LDO according to claim 1, characterized in that: The current sampling circuit includes: an operational amplifier A0, resistors R1-R2, and NMOS tubes N1-N3; The positive input of operational amplifier A0 is connected to the reference voltage VREF, and the output is connected to the gates of NMOS transistors N1 and N2, which is named VG. The drain of the NMOS transistor N1 is connected to the first power supply VIN, and the source is connected to one end of the resistor R1, serving as the output port LDOOUT of the LDO, which is named VP. The other end of the resistor R1 is connected to one end of the resistor R2 and to the negative input terminal of the operational amplifier A0; the other end of the resistor R2 is grounded GND; The drain of the NMOS transistor N2 is connected to the first power supply VIN, and the source is connected to the drain of the NMOS transistor N3, which is named VM; The source of the NMOS tube N3 is grounded GND and is connected to the operational amplifier circuit and the current comparison circuit; The gate of the NMOS tube N3 is connected to a current comparison circuit; The drains of NMOS tubes N1 and N2 are also connected to the operational amplifier circuit and the current comparison circuit; VP, VM, and GND are connected to the operational amplifier circuit.

3. The overcurrent protection circuit for low voltage input LDO according to claim 2, characterized in that: The operational amplifier A0, resistors R1-R2, and NMOS transistor N1 constitute the basic circuit structure of the LDO.

4. The overcurrent protection circuit for low voltage input LDO according to claim 1, characterized in that: The current comparison circuit includes PMOS transistors P11-P12, NMOS transistors N9-N13, a reference current source IREF, and a bias voltage source VBIAS2; The drain of the NMOS tube N9 is connected to the first power supply VIN, the current sampling circuit and the operational amplifier circuit; The gates of NMOS transistors N9 and N10 are connected and connected to the bias voltage source VBIAS2; The source of the NMOS transistor N9 is connected to the gate of the NMOS transistor N11 and is also connected to the current sampling circuit and the operational amplifier circuit; The sources of the PMOS transistors P11 and P12 are connected to the first power supply VIN, the current sampling circuit and the operational amplifier circuit, and the gates of the PMOS transistors P11 and P12 are connected to the drain of the PMOS transistor P11 and the drain of the NMOS transistor N10; The source of the NMOS transistor N10 is connected to the drain of N11 and is also connected to the reference current source VREF; The source of the NMOS tube N11 is grounded GND, the current sampling circuit and the operational amplifier circuit; The drain of the PMOS transistor P12 is connected to the drain of the NMOS transistor N12, the gate of N12, and the gate of N13; The source electrodes of the NMOS tubes N12 and N13 are grounded to GND, a current sampling circuit, and an operational amplifier circuit; The drain of the NMOS tube N13 is connected to the current sampling circuit.

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