Power supply device

Abstract

The invention discloses a power supply device, and belongs to the technical field of terminals. The power supply device comprises a circuit board which comprises a first conductor layer, a first dielectric layer and a second conductor layer, the first conductor layer, the first dielectric layer and the second conductor layer are stacked in sequence, and the dielectric constant of the first dielectric layer is larger than or equal to a preset threshold value; the chip is arranged on the circuit board, a grounding pin of the chip is electrically connected with the first conductor layer, and a power supply pin of the chip is electrically connected with the second conductor layer; and the power supply module is arranged on the circuit board and is electrically connected with the second conductor layer.

Description

Technical Field

[0001] The present application belongs to the field of terminal technology, and specifically relates to a power supply device. Background Art

[0002] As the operating frequency of the system on chip (SOC) of electronic devices (such as mobile phones) gradually increases and the computing scenarios become more complicated, the SOC has increasingly higher requirements for the response of the power supply, which is specifically manifested in power supply characteristics such as power ripple and power supply response speed when the SOC is working.

[0003] In the related art, a large number of filter capacitors are added on the back of the SOC on the motherboard to improve the above power supply characteristics. However, when the above solution is adopted, a large number of filter capacitors need to occupy a large motherboard layout area, thereby limiting the flexibility of the layout of other components on the motherboard, thereby reducing the flexibility of the overall machine structure design. Summary of the invention

[0004] The present application aims to provide a power supply device that can improve the flexibility of the overall structural design.

[0005] An embodiment of the present application discloses a power supply device, comprising: a circuit board, comprising a first conductor layer, a first dielectric layer, and a second conductor layer, wherein the first conductor layer, the first dielectric layer, and the second conductor layer are stacked in sequence, wherein a dielectric constant of the first dielectric layer is greater than or equal to a preset threshold; a chip, arranged on the circuit board, a ground pin of the chip being electrically connected to the first conductor layer, and a power pin of the chip being electrically connected to the second conductor layer; and a power supply module, arranged on the circuit board, and electrically connected to the second conductor layer.

[0006] An embodiment of the present application provides a power supply device, which includes a circuit board, a chip and a power supply module. The circuit board includes a first conductor layer, a first dielectric layer with a dielectric constant greater than or equal to a preset threshold, and a second conductor layer stacked in sequence, which is equivalent to forming a flat capacitor that can meet the needs of filtering scenarios. The chip is arranged on the circuit board, the ground pin of the chip is electrically connected to the first conductor layer, the power pin of the chip is electrically connected to the second conductor layer, and the power supply module is arranged on the circuit board, and the power supply module is electrically connected to the second conductor layer, so as to filter the power provided by the power supply module and improve the power supply characteristics of the chip when working. In addition, there is no need to set a large number of capacitor elements on the circuit board, which saves the layout area of ​​the circuit board, thereby improving the flexibility of the overall structure design.

[0007] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a power supply device disclosed in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a PCB capacitor disclosed in an embodiment of the present application; Figure 3 It is a structural schematic diagram of a power supply device of the related technology; Figure 4A For Figure 3 The corresponding schematic diagram on the back of the circuit board; Figure 4B For Figure 1 The corresponding schematic diagram on the back of the circuit board; Figure 5A For Figure 3 Schematic diagram of the corresponding filtering chain; Figure 5B For Figure 1 Schematic diagram of the corresponding filtering chain; Figure 6 This is a schematic diagram of the structure of the first circuit board disclosed in the embodiment of the present application; Figure 7 A schematic diagram of the structure of a second circuit board disclosed in an embodiment of the present application; Figure 8 This is a schematic diagram of the structure of a third circuit board disclosed in an embodiment of the present application; Fig. 9 This is a schematic diagram of the structure of a fourth circuit board disclosed in an embodiment of the present application; Fig. 10A This is a schematic diagram of the structure of the fifth circuit board disclosed in the embodiment of the present application; Fig. 10B This is a schematic diagram of the structure of the sixth circuit board disclosed in the embodiment of the present application; Fig. 10C This is a schematic diagram of the structure of the seventh circuit board disclosed in the embodiment of the present application. DETAILED DESCRIPTION

[0009] Embodiments of the present invention will be described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0010] The term "first" or "second" in the specification and claims of the present application may include one or more of the features explicitly or implicitly. In the description of the present invention, unless otherwise specified, "plurality" means two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects connected before and after are in an "or" relationship.

[0011] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0012] like Figure 1 As shown, an embodiment of the present application discloses a power supply device, which includes: a circuit board 100, including a first conductor layer 110, a first dielectric layer 120 and a second conductor layer 130, wherein the first conductor layer 110, the first dielectric layer 120 and the second conductor layer 130 are stacked in sequence, wherein the dielectric constant of the first dielectric layer 120 is greater than or equal to a preset threshold; a chip 200, arranged on the circuit board 100, a ground pin 210 of the chip 200 is electrically connected to the first conductor layer 110, and a power pin 220 of the chip 200 is electrically connected to the second conductor layer 130; a power supply module 300, arranged on the circuit board 100, and electrically connected to the second conductor layer 130.

[0013] like Figure 1 and Figure 2 As shown, the present application forms a flat capacitor that can meet the needs of filtering scenarios by stacking a first conductor layer 110, a first dielectric layer 120 having a dielectric constant greater than or equal to a preset threshold, and a second conductor layer 130 in sequence. Moreover, since the circuit board 100 in the present application includes the first conductor layer 110, the first dielectric layer 120 and the second conductor layer 130 stacked in sequence, the characteristics of the capacitor can be realized inside the circuit board 100.

[0014] The present application filters the power provided by the power supply module 300 by electrically connecting the ground pin 210 of the chip 200 to the first conductor layer 110, electrically connecting the power pin 220 of the chip 200 to the second conductor layer 130, and electrically connecting the power supply module 300 to the second conductor layer 130, thereby improving the power supply characteristics of the chip 200 when working, and there is no need to set a large number of capacitor elements 400 on the circuit board 100, saving the layout area of ​​the circuit board 100, thereby improving the flexibility of the overall structural design.

[0015] For example, the circuit board 100 in the present application may be a printed circuit board (PCB), and correspondingly, the combined structure of the first conductor layer 110, the first dielectric layer 120 and the second conductor layer 130 stacked in sequence may be called a PCB capacitor. It should be noted that the present application does not impose any specific restrictions on the plane shape of the PCB capacitor, which may be circular, square, rectangular, elliptical, or irregular. For example, the plane shape of the PCB capacitor may be as follows: Figure 2 Trapezoid shown.

[0016] The capacitance value of the PCB capacitor is C=Dk*K*S / d, where Dk is the relative dielectric constant of the first dielectric layer 120, K is a constant, the value of K is related to the formulation process of the dielectric material of the first dielectric layer 120, S is the overlapping area of ​​the first conductor layer 110 and the second conductor layer 130, and d is the thickness of the first dielectric layer 120. The capacitance value of the PCB capacitor can be increased by adjusting the thickness of the first dielectric layer 120. The smaller the thickness of the first dielectric layer 120, the greater the capacitance value of the PCB capacitor. In the present application, the capacitance value of the PCB capacitor can be linearly increased by reducing the thickness of the first dielectric layer 120, thereby improving the filtering effect of the PCB capacitor and increasing the number of replaceable capacitor elements 400.

[0017] It should be noted that the first conductor layer 110 and the second conductor layer 130 in the present application may be conductor layers of the circuit board itself, or may be conductor layers newly added on the basis of the original circuit board, and the present application does not impose any specific restrictions on this.

[0018] The embodiment of the present application provides a power supply device, which includes a circuit board 100, a chip 200 and a power supply module 300. The circuit board 100 includes a first conductor layer 110, a first dielectric layer 120 with a dielectric constant greater than or equal to a preset threshold, and a second conductor layer 130 stacked in sequence, which is equivalent to forming a flat capacitor that can meet the needs of filtering scenarios. The chip 200 is arranged on the circuit board 100, and the ground pin 210 of the chip 200 is electrically connected to the first conductor layer 110. The power pin 220 of the chip 200 is electrically connected to the second conductor layer 130. The power supply module 300 is arranged on the circuit board 100, and the power supply module 300 is electrically connected to the second conductor layer 130, so as to filter the power provided by the power supply module 300 and improve the power supply characteristics of the chip 200 when working. In addition, there is no need to set a large number of capacitor elements 400 on the circuit board 100, which saves the layout area of ​​the circuit board 100, thereby improving the flexibility of the overall structural design.

[0019] Furthermore, since the capacitor element 400 is removed in this solution, it is not affected by the parasitic inductance characteristics and capacitance tolerance of the capacitor element 400, and the filtering effect can be effectively improved.

[0020] When a solution of adding a large number of capacitor elements 400 to the back of the circuit board 100 to improve the power supply characteristics of the chip 200 during operation is adopted in the related art, the structure is as follows: Figure 3 As shown, the back side of the circuit board 100 is as shown in FIG. Figure 4A As shown, when the present application solution is adopted, the back side of the circuit board 100 is as shown in FIG. Figure 4B As shown, the solution of the present application can filter the power provided by the power supply module 300, improve the power supply characteristics of the chip 200 when it is working, and there is no need to set a large number of capacitor elements 400 on the circuit board 100, thereby saving the layout area of ​​the circuit board 100, thereby improving the flexibility of the overall structural design.

[0021] Furthermore, when the solution of the related art is adopted, the filter link of the chip 200 and the power supply module 300 is as follows: Figure 5A As shown, in the solution of the present application, the filter link of the chip 200 and the power supply module 300 is as follows Figure 5B As shown, compared with the solutions of the related technology, the loop size of the filter link of the present application is greatly shortened, which can reduce the inductance value of the filter loop, thereby improving the response speed and power ripple of the power supply module 300 when the chip 200 works, thereby improving the power supply characteristics.

[0022] In this application, if Figure 1 As shown, the first conductor layer 110, the first dielectric layer 120 and the second conductor layer 130 may at least partially overlap. That is, the first conductor layer 110, the first dielectric layer 120 and the second conductor layer 130 may partially overlap or completely overlap, that is, the circuit board 100 may partially use PCB capacitors, or the PCB capacitors may also cover the entire circuit board 100, which may be specifically set according to actual needs.

[0023] In the embodiments of the present application, Figure 6 As shown, the first dielectric layer 120 may include a first dielectric region 121 and a second dielectric region 122, the first conductor layer 110, the first dielectric region 121 and the second conductor layer 130 partially overlap, the first conductor layer 110, the second dielectric region 122 and the second conductor layer 130 partially overlap, and the dielectric constant of the first dielectric region 121 is greater than or equal to the preset threshold. In other words, a dielectric material with a dielectric constant greater than or equal to the preset threshold is used in a local area of ​​the first dielectric layer 120, and ordinary dielectric materials are used in other areas of the first dielectric layer 120, thereby reducing the amount of dielectric material with a dielectric constant greater than or equal to the preset threshold, saving costs.

[0024] It should be noted that the present application does not specifically limit dielectric materials having a dielectric constant greater than or equal to a preset threshold value, and any organic material, inorganic material, organic and inorganic hybrid material, etc. that can achieve high capacitance values ​​as long as the conditions are met are acceptable.

[0025] In one implementation, Figure 7 As shown, the first projection and the second projection may overlap, wherein the first projection is the projection of the chip 200 in the target direction, and the second projection is the projection of the first dielectric region 121 in the target direction, and the target direction is a direction perpendicular to the circuit board 100. That is, in the direction perpendicular to the circuit board 100, the projection of the chip 200 and the projection of the first dielectric region 121 may overlap, that is, the PCB capacitor is located directly below the chip 200. In this case, the distance from the chip 200 to the PCB capacitor can be effectively shortened, thereby improving the filtering effect.

[0026] In one implementation, Figure 8 As shown, the first projection and the second projection may partially overlap, wherein the first projection is the projection of the chip 200 in the target direction, and the second projection is the projection of the first medium area 121 in the target direction, and the target direction is a direction perpendicular to the circuit board 100. That is, in the direction perpendicular to the circuit board 100, the projection of the chip 200 and the projection of the first medium area 121 may partially overlap.

[0027] In one implementation, Fig. 9 As shown, the first projection and the second projection may be staggered, wherein the first projection is the projection of the chip 200 in the target direction, and the second projection is the projection of the first medium area 121 in the target direction, and the target direction is a direction perpendicular to the circuit board 100. That is, in the direction perpendicular to the circuit board 100, the projection of the chip 200 and the projection of the first medium area 121 may be staggered.

[0028] In the embodiments of the present application, Figure 1 As shown, the first conductor layer 110 is arranged close to the target surface, wherein the target surface is the surface of the circuit board 100 on which the chip 200 is arranged. By arranging the first conductor layer 110 close to the target surface, the distance between the chip 200 and the PCB capacitor can be further shortened, thereby improving the filtering effect.

[0029] For example, Figure 1As shown, taking the circuit board 100 including 12 conductor layers, the first conductor layer 110 and the second conductor layer 130 being the conductor layers of the circuit board itself as an example, since the chip is arranged on the first conductor layer of the circuit board 100, and there are dense chip pads on the first conductor layer, the first conductor layer cannot be made into a very large plane, and then the second conductor layer of the circuit board is used as the first conductor layer 110 mentioned above, and the third conductor layer of the circuit board is used as the second conductor layer 130 mentioned above, so as to shorten the distance between the chip and the PCB capacitor and improve the filtering effect. In addition, the third conductor layer of the circuit board can be used as the first conductor layer 110 mentioned above, and the fourth conductor layer of the circuit board can be used as the second conductor layer 130 mentioned above, or the fourth conductor layer of the circuit board can be used as the first conductor layer 110 mentioned above, and the fifth conductor layer of the circuit board can be used as the second conductor layer 130 mentioned above, or the fifth conductor layer of the circuit board can be used as the first conductor layer 110 mentioned above, and the sixth conductor layer of the circuit board can be used as the second conductor layer 130 mentioned above, or the third conductor layer of the circuit board can be used as the first conductor layer 110 mentioned above, and the fifth conductor layer of the circuit board can be used as the second conductor layer 130 mentioned above, that is, the first conductor layer 110 and the second conductor layer 130 can be any two conductor layers in the circuit board. When the first conductor layer 110 and the second conductor layer 130 are two non-adjacent conductor layers in the circuit board, the thickness of the first dielectric layer 120 is relatively large.

[0030] In one implementation, Fig. 10A As shown, the circuit board 100 may also include a third conductor layer 140, a second dielectric layer 150 and a fourth conductor layer 160, the first conductor layer 110 and the third conductor layer 140 are symmetrically arranged relative to the central layer of the circuit board 100 in the target direction, the first dielectric layer 120 and the second dielectric layer 150 are symmetrically arranged relative to the central layer in the target direction, and the second conductor layer 130 and the fourth conductor layer 160 are symmetrically arranged relative to the central layer in the target direction, wherein the target direction is a direction perpendicular to the circuit board 100. Since the circuit board 100 of this solution is a symmetrical structure, it can be easily processed and save processing costs. It should be noted that the central layer of the circuit board 100 is the layer in the middle position of all the layers of the circuit board 100 in the direction perpendicular to the circuit board 100.

[0031] When processing the circuit board 100 of the present application, the following can be made first: Fig. 10BThe inner layer circuit board 170 shown in FIG. 1 is then manufactured into a first conductor layer 110, a first dielectric layer 120, a second conductor layer 130, a third conductor layer 140, a second dielectric layer 150 and a fourth conductor layer 160. The first conductor layer 110, the first dielectric layer 120, the second conductor layer 130, the third conductor layer 140, the second dielectric layer 150 and the fourth conductor layer 160 are sequentially combined with the inner layer circuit board 170 through a lamination process to obtain a circuit board as shown in FIG. Fig. 10C Finally, the outermost dielectric layer 180 and the outermost conductor layer 190 are made to obtain the structure shown in FIG. Fig. 10A The circuit board 100 is shown.

[0032] In one implementation, Figure 1 As shown, the ground pin 210 of the chip 200 is electrically connected to the first conductor layer 110, and the power pin 220 of the chip 200 is electrically connected to the second conductor layer 130, which may include: the ground pin 210 of the functional module 230 of the chip 200 is electrically connected to the first conductor layer 110, and the power pin 220 of the functional module 230 is electrically connected to the second conductor layer 130. In other words, filtering of the functional module 230 on the chip 200 is achieved through the PCB capacitor.

[0033] In the present application, the circuit board 100 may be provided with a plurality of PCB capacitors, and the number of the PCB capacitors may correspond to the number of the power supply modules 300 , or the number of the PCB capacitors may be determined according to the power supply network of the power supply module 300 .

[0034] In one implementation, the chip 200 and the power supply module 300 may be disposed on the same surface of the circuit board 100 .

[0035] In another implementation, the chip 200 and the power supply module 300 may be disposed on different surfaces of the circuit board 100 to shorten a power supply path from the power supply module 300 to the chip 200 .

[0036] It should be noted that the chip 200 in this application can be a SOC, a short-range wireless connection (Wireless Fidelity, WIFI) chip, a radio frequency processor chip, etc., and this application does not make specific restrictions on this. In addition, the power supply device disclosed in this application can be used not only for consumer electronic products such as mobile phones, but also for telecommunications / medical / automotive / aviation equipment, chip / module carrier scenarios.

[0037] Taking the chip 200 as a mobile phone SOC as an example, the preset threshold mentioned above can be 9, that is, the dielectric constant of the first dielectric layer 120 is greater than or equal to 9. For example, the high-frequency noise of the power supply module of the SOC requires a capacitance value of nF for the corresponding filter capacitor, the dielectric thickness limit of the mobile phone circuit board is about 8um, and the common mobile phone CPU size is about 16*16mm, so the area limit S≤10*10=100mm 2 , based on C=1nF=1000pF, d=8um=0.000008m, S=100mm 2 =0.0001m 2 , K takes the vacuum dielectric constant of 8.86pF / m, and calculates Dk=9.029345372≈9.03. Therefore, taking the chip as a mobile phone SOC as an example, the dielectric constant of the first dielectric layer can be greater than or equal to 9.

[0038] It should be noted that the present application does not impose any specific limitation on the value of the preset threshold, which can be set according to actual needs.

[0039] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0040] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A power supply device, characterized in that: include: A circuit board, comprising a first conductor layer, a first dielectric layer, and a second conductor layer, wherein the first conductor layer, the first dielectric layer, and the second conductor layer are stacked in sequence, wherein the dielectric constant of the first dielectric layer is greater than or equal to a preset threshold; A chip is arranged on the circuit board, a ground pin of the chip is electrically connected to the first conductor layer, and a power pin of the chip is electrically connected to the second conductor layer; The power supply module is arranged on the circuit board and is electrically connected to the second conductor layer.

2. The power supply device according to claim 1, characterized in that: The first conductor layer, the first dielectric layer and the second conductor layer at least partially overlap.

3. The power supply device according to claim 1, characterized in that: The first dielectric layer includes a first dielectric area and a second dielectric area, the first conductor layer, the first dielectric area and the second conductor layer partially overlap, the first conductor layer, the second dielectric area and the second conductor layer partially overlap, and the dielectric constant of the first dielectric area is greater than or equal to the preset threshold.

4. The power supply device according to claim 3, characterized in that: The first projection coincides with the second projection, wherein the first projection is a projection of the chip in a target direction, and the second projection is a projection of the first medium area in the target direction, and the target direction is a direction perpendicular to the circuit board.

5. The power supply device according to claim 3, characterized in that: The first projection partially overlaps with the second projection, wherein the first projection is a projection of the chip in a target direction, and the second projection is a projection of the first medium area in the target direction, and the target direction is a direction perpendicular to the circuit board.

6. The power supply device according to claim 3, characterized in that: The first projection is staggered with the second projection, wherein the first projection is a projection of the chip in a target direction, and the second projection is a projection of the first medium area in the target direction, and the target direction is a direction perpendicular to the circuit board.

7. The power supply device according to claim 1, characterized in that: The first conductor layer is disposed close to a target surface, wherein the target surface is a surface of the circuit board on which the chip is disposed.

8. The power supply device according to claim 1, characterized in that: The circuit board also includes a third conductor layer, a second dielectric layer and a fourth conductor layer, the first conductor layer and the third conductor layer are symmetrically arranged relative to the central layer of the circuit board in a target direction, the first dielectric layer and the second dielectric layer are symmetrically arranged relative to the central layer in the target direction, and the second conductor layer and the fourth conductor layer are symmetrically arranged relative to the central layer in the target direction, wherein the target direction is a direction perpendicular to the circuit board.

9. The power supply device according to claim 1, characterized in that: The ground pin of the chip is electrically connected to the first conductor layer, and the power pin of the chip is electrically connected to the second conductor layer, including: A ground pin of a functional module of the chip is electrically connected to the first conductor layer, and a power pin of the functional module is electrically connected to the second conductor layer.

10. The power supply device according to claim 1, characterized in that: The chip and the power supply module are arranged on different surfaces of the circuit board.

11. The power supply device according to claim 1, characterized in that: The chip and the power supply module are arranged on the same surface of the circuit board.

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