Solid state drive, operating method of solid state drive, storage system, and data center

Abstract

Embodiments of the present application disclose a solid state disk, an operating method of the solid state disk, a storage system and a data center. The solid state disk comprises a flash memory module, a dynamic random access memory module and a controller. The dynamic random access memory module comprises a first storage area, the first storage area stores first data and a check code of the first data, and a code length of the first data is greater than an interface width of the dynamic random access memory module. The operating method of the solid state disk comprises: reading, by the controller, the first data and the check code of the first data from the first storage area of the dynamic random access memory module, and the code length of the first data is greater than the interface width of the dynamic random access memory module. The code length of the first data is greater than the interface width of the dynamic random access memory module, the overall code length of the check code is reduced, and the use efficiency of the interface width of the dynamic random access memory module is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more specifically, to a solid-state drive, a method for operating a solid-state drive, a storage system, and a data center. Background Technology

[0002] Solid-state drives (SSDs), also known as solid-state drives, offer numerous advantages over hard disk drives (HDDs). For example, they provide greater data security; shaking an SSD during use does not damage the stored data, and sudden power outages will not result in data loss. Therefore, SSDs are widely used in various working environments, such as enterprise servers with high reliability requirements and personal storage devices.

[0003] Solid-state drives (SSDs) typically consist of flash memory, a controller, and dynamic random access memory (DRAM). Flash memory is a non-volatile storage medium used for data storage. It can store data without power, but its read / write speed is slower than the data transfer speed between the host and the SSD. Therefore, DRAM is used as a cache. Data received by the SSD from the host is first cached in DRAM before being written from DRAM to flash memory. To achieve higher sequential write bandwidth, higher random operations per second (IOPS), and better system QoS, increasingly wider cache interface widths are required. Currently, increasing the cache interface width and frequency is generally used to meet system bandwidth access requirements. For example, the cache interface width is increased from 32 bits to 64 bits. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a solid-state drive controller, a solid-state drive operation method, a storage system, and a data center, which can improve the utilization rate of cache interface width.

[0005] One aspect of this invention provides a solid-state drive (SSD), comprising: a flash memory module; a dynamic random access memory (DRAM) module; and a controller. The DRAM module includes a first storage area storing first data and a checksum of the first data, wherein the code length of the first data is greater than the interface width of the DRAM module.

[0006] Another aspect of the present invention provides a method for operating a solid-state drive, the solid-state drive including a flash memory module, a DRAM module and a controller, the method including: the controller reading first data and a check code of the first data from a first storage area of ​​the DRAM module, the code length of the first data being greater than the interface width of the DRAM module.

[0007] Another aspect of the present invention provides a storage system including the solid-state drive described above.

[0008] Another aspect of the present invention provides a data center including the storage system described above.

[0009] According to the solid-state drive and its operation method provided in the embodiments of the present invention, when the first data in the first storage area of ​​the DRAM module is encoded with a check code, the first data is set with a code length greater than the interface width of the DRAM module as the granularity, which reduces the number of check bits per unit byte of data, improves the interface width utilization efficiency of the DRAM module, and thus improves the bandwidth utilization of the DRAM module. Attached Figure Description

[0010] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a schematic block diagram of a solid-state drive according to an embodiment of the present invention;

[0012] Figure 2 This is a schematic block diagram of a flash memory cell according to an embodiment of the present invention;

[0013] Figure 3 This is a schematic block diagram of a DRAM module according to an embodiment of the present invention;

[0014] Figure 4 This is a schematic block diagram of a DRAM cell according to an embodiment of the present invention;

[0015] Figure 5 This is a schematic diagram of the partitioning of the DRAM module according to an embodiment of the present invention;

[0016] Figure 6 This illustrates data transmission between a solid-state drive controller and a DRAM module in related technologies;

[0017] Figure 7 The data transmission between the solid-state drive controller and the DRAM module in an embodiment of the present invention is illustrated. Detailed Implementation

[0018] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0019] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0020] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0021] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0022] Figure 1 This is a schematic block diagram of a solid-state drive (SSD). SSDs can store data under the control of a host device (such as a smartphone, desktop computer, game console, television, tablet computer, or in-vehicle infotainment system). Figure 1 As shown, a solid-state drive (SSD) includes: a flash memory module, a controller, a dynamic random access memory (DRAM) module, and an interface. SSDs can use any of the following packages: Point-of-Package (POP), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-on-Package (WFP), and Wafer-on-Shipment (WSP).

[0023] The interface is used to manage communication between the solid-state drive (SSD) and the host. Communication includes read operations (Read IO) for reading data from the SSD and write operations (Write IO) for writing data to the SSD. The SSD can communicate with the host via at least one of the following communication protocols: Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Non-Volatile Memory Host Controller Interface Specification (NVMe), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), PCI, PCIe, Gen 3.0, and PCIe Gen.

[0024] Flash memory is a non-volatile random access storage medium that can store data without a power supply. Flash memory modules are connected to a controller via a bus. A flash memory module consists of multiple flash memory cells (also called flash memory chips). A flash memory cell consists of an array of memory cells, addressed via word lines and bit lines. A memory cell is, for example, a floating-gate transistor, which includes a floating gate, a control gate, a substrate, and a tunneling dielectric layer between the substrate and the floating gate. By controlling the voltage of the substrate and the voltage of the control gate, charges in the substrate tunnel into the floating gate, or vice versa. The amount of charge in the floating gate determines the threshold voltage of the floating-gate transistor. The information stored in the floating-gate transistor is determined based on the range of its threshold voltage. A floating-gate transistor can store 1 bit of binary data (Single-Level Cell, SLC), 2 bits of binary data (Multi-Level Cell, MLC), 3 bits of binary data (Trinary-Level Cell, TLC), or 4 bits of binary data (Quad-Level Cell, QLC). Flash memory modules are, for example, NAND flash memory, and flash memory cells are NAND chips. Figure 2 This is a schematic block diagram of a flash memory cell according to an embodiment of the present invention. Figure 2 As shown, each flash memory cell comprises multiple blocks, each block comprises multiple pages, and each page comprises multiple storage units. NAND flash memory performs write and read operations on a page-by-page basis and erase operations on a block-by-block basis. Before performing a write operation, the block must be erased. The target data for the host's read and write operations is stored in the flash memory.

[0025] DRAM is a volatile memory medium. A DRAM memory cell consists of transistors and capacitors. Each memory cell stores one bit of data. For example, when a capacitor stores charge, the memory cell stores a "1"; when the capacitor does not store charge, the memory cell stores a "0". A DRAM module is, for example, Double Data Rate Synchronous DRAM (DDR SDRAM). DDR means that input / output (I / O) operations can be performed on both the rising and falling edges of the clock signal to transfer data.

[0026] DRAM has a faster read / write speed than flash memory, thus acting as a cache between the flash memory module and the host, improving the SSD's responsiveness to the host. When the host writes data to the SSD, the SSD's interface receives the data, which is cached in the DRAM module. The controller then reads the data from the DRAM module and writes it to the target address in the flash memory module. When the host reads data from the SSD, the controller reads the data from the target address in the flash memory module, caches the data in the DRAM module, and the cached data in the DRAM module is then sent to the host through the interface.

[0027] The interface width of a DRAM module refers to the number of bits of data input or output to the DRAM module during each read or write operation. For example, if the DRAM module outputs 32 bits of data simultaneously on the rising edge of the clock signal, then the interface width of the DRAM module is 32 bits. The interface width of a DRAM module is equal to the number of data I / O ports of the DRAM module. DRAM modules also include address signal ports, etc.

[0028] Figure 3 This is a schematic block diagram of a DRAM module according to an embodiment of the present invention. A data bus, address signal lines, and instruction signal lines are provided between the DRAM module and the controller. Figure 3 As shown, the DRAM module comprises n DRAM cells (also known as DRAM chips), where n is a positive integer, such as 4, 8, or 16. Each DRAM cell has, for example, 8 data I / O ports, capable of simultaneously inputting / outputting 8 bits of data. Correspondingly, the interface width of the DRAM module is 8*n, allowing simultaneous input / output of 8*n bits of data. It can be understood that the number of data I / O ports for a DRAM cell can also be other values, such as 4 or 16.

[0029] Figure 4 This is a schematic block diagram of a DRAM cell according to an embodiment of the present invention. Figure 4 As shown, a DRAM cell comprises m banks, where m is a positive integer, such as 4, 8, or 16. Each bank includes multiple memory cell arrays, and the memory cells are addressed via word lines and bit lines. The number of data bits that can be simultaneously input / output in each bank is equal to the number of data I / O ports in the DRAM cell. For example, if a DRAM cell has 8 data I / O ports and a bank includes an array of 8 memory cells, it can output 8 bits of data simultaneously. The m banks are interleaved for read and write operations.

[0030] The bank performs read operations based on row and column addresses, selecting the target row in the memory cell array. Simultaneously, it reads data from the memory cells at the intersections of the target row and multiple consecutive columns, storing this data in the bank's buffer. In other words, it reads data from the target row and multiple memory cells located in consecutive columns at the same time. The buffer is, for example, Static Random Access Memory (SRAM). The number of consecutive columns is called the burst length. That is, at any given time, burst length bits of data are read from the memory cell array into the buffer. Burst lengths are, for example, 2, 4, 8, 16, etc.

[0031] The controller, also known as the master chip or master controller, is the manager of the solid-state drive (SSD). It consists of a processor that executes firmware code and some hardware acceleration modules. The controller can perform functions such as a software middleware layer (flash translation layer), wear leveling management, flash bad block management, garbage collection, and checksum encoding. These functions can be implemented through software, hardware, or a combination of both. The controller requires system data to operate, which is stored in its read-only memory (ROM). Because DRAM has a faster access speed, system data is transferred from ROM to the DRAM module when the SSD is powered on.

[0032] The controller comprises functional modules 1-N, a DDR physical layer circuit (DDR PHY), and a DDR controller circuit (DDRController). The controller accesses and manages the DRAM through the DDR physical layer circuit and the DDR controller circuit. Functional modules 1-N are used to execute functions such as software middleware, wear leveling, bad block management, garbage collection, and checksum encoding.

[0033] Some of the nouns or terms used in the description of the embodiments of the present invention are to be interpreted as follows.

[0034] The Flash Physical Address (FPA), also known as the Physical Block Address (PBA), is used to identify the storage location of data in the flash memory chip and generally includes information such as Die, Plane, Block, and Page.

[0035] Logical Block Address (LBA) is a common mechanism used in computer data storage devices to represent the location of data.

[0036] The global mapping table (L2P) is a global mapping table between the LBA index and the PBA of the flash memory. The global mapping table is stored in the controller's read-only memory. When the solid-state drive is powered on, the global mapping table is transferred from the read-only memory to the DRAM module.

[0037] Error correction coding (ECC) is an algorithm used to detect and correct errors that occur during data transmission or storage. ECC can improve data reliability and integrity, preventing data corruption or loss. ECC can use various coding algorithms, such as BCH (Bose Chaudhuri Hocquenghem) codes, Reed-solomon codes, and Low Density Parity Check Code (LDPC).

[0038] As described above, the I / O operations of the DRAM module can be performed once on the rising edge and once on the falling edge of each clock cycle. Therefore, data transmission between the DRAM module and the controller is performed once on the rising edge and once on the falling edge of each clock cycle. The number of data bits transmitted each time is A*n (i.e., the interface width of the DRAM module), where n is the number of DRAM cells involved in the transmission, and A is the number of data I / O ports of the DRAM cells. In each data transmission, the data of the DRAM cell comes from one Bank within the DRAM cell.

[0039] Figure 6 This illustrates the method for setting the checksum of data in a DRAM module, as well as the data transmission between the solid-state drive controller and the DRAM module, in related technologies. For example... Figure 6 As shown, the DRAM module includes five DRAM cells: DRAM0 to DRAM4. Each DRAM cell can output 8 bits of data simultaneously; therefore, the interface width of the DRAM module is 40 bits. DRAM cells DRAM0 to DRAM3 store the data, while DRAM4 stores the corresponding checksum. The numbers 1-n on the left side of the DRAM module represent the data transmission sequence numbers, i.e., from the first data transmission to the nth data transmission. Data transmission is illustrated using the controller retrieving data from the DRAM module as an example. Figure 6 As shown, for each data transmission, the controller reads 32 bits of data and the corresponding ECC checksum from the DRAM module. That is, a set of checksum bits is set for every 32 bits of data in the DRAM module. Figure 6 The method shown in the diagram sets the checksum. Eight bits of the 40-bit interface width of the DRAM module are used to transmit the ECC checksum. The interface width utilization rate is 80%, which is relatively low.

[0040] According to the solid-state drive and its operation method provided in embodiments of the present invention, the data in the DRAM module is set with a checksum with a code length greater than the interface width of the DRAM module. The DRAM module includes a first storage area, which stores first data and a checksum for the first data. The code length (i.e., the number of bits of the first data) of the first data is greater than the interface width of the DRAM module. For example, if the interface width of the DRAM module is 40 bits, a set of check bits (i.e., checksum) is set for every 152 bytes of the first data; the first data is 152 bytes, and the checksum is 8 bytes. As another example, if the interface width of the DRAM module is 40 bits, a set of check bits is set for every 308 bytes of the first data; the first data is 308 bytes, and the checksum is 12 bytes.

[0041] According to the check code algorithm, a check code (with Z bits) is set for X bits of data. The larger X is, the smaller Z / (X+Z) is. That is, the larger the proportion of the data bits in the total number of bits, the fewer the check bits per byte of data.

[0042] The first storage area can be a portion or all of the storage area of ​​the DRAM module. That is, all data in the DRAM module is set with checksums in the manner described above, or data in a portion of the storage area of ​​the DRAM module is set with checksums in the manner described above.

[0043] Figure 7 This illustration shows the method for setting the checksum of data in the DRAM module in an embodiment of the present invention, as well as the data transmission between the solid-state drive controller and the DRAM module. Figure 7 In the illustrated embodiment, the DRAM module includes five DRAM cells: DRAM0 to DRAM4. Each DRAM cell can simultaneously input / output 8 bits of data. The interface width of the DRAM module is 40 bits. The number of DRAM cells in the DRAM module is not limited and can also be 4, 8, 16, etc.

[0044] DRAM cells DRAM0 through DRAM4 can store both data and a checksum. Each DRAM cell stores a portion of the first data and a portion of the checksum for that first data. For example... Figure 7 As shown, the first data is 152 bytes, the checksum is 8 bytes, 31 bytes of the first data and 1 byte of the checksum are stored in DRAM0, 31 bytes of the first data and 1 byte of the checksum are stored in DRAM1, 30 bytes of the first data and 2 bytes of the checksum are stored in DRAM2, 30 bytes of the first data and 2 bytes of the checksum are stored in DRAM3, and 30 bytes of the first data and 2 bytes of the checksum are stored in DRAM4.

[0045] The numbers 1-N on the left side of the DRAM module represent the data transmission sequence number. For example... Figure 7 As shown, from the first data transmission to the 30th data transmission, 150 bytes of the first data are transmitted from the DRAM module to the controller. In the 31st data transmission, 2 bytes of the first data are transmitted from the DRAM module to the controller, and 3 bytes of the checksum are transmitted from the DRAM module to the controller. In the 32nd data transmission, 5 bytes of the checksum are transmitted from the DRAM module to the controller. That is, through 32 data transmissions, the controller receives 152 bytes of the first data and 8 bytes of the checksum from the DRAM module.

[0046] The total number of bits for the first data and its checksum is an integer multiple of the DRAM module's interface bandwidth, which is greater than or equal to 2. The controller receives the first data and its checksum through multiple data transmissions.

[0047] In this embodiment of the invention, the check code can be BCH, RS, or LDPC code, etc. The controller selects the type of check code for the first data according to the reliability requirements of the first data.

[0048] by Figure 6 The shown checksum setting method involves the controller obtaining 4*32 bytes of data and 32 bytes of checksum from the DRAM module through 32 data transmissions. Each 4 bytes of data is corrected using a 1-byte checksum. Figure 7 The illustrated checksum setting method involves 32 data transmissions, during which the controller obtains 152 bytes of data and 8 bytes of checksum from the DRAM module. The 152 bytes of data are then processed as a whole using the 8 bytes of checksum for error correction. The DRAM module's interface width utilization rate is 95%. Therefore, the checksum setting method of this application improves the utilization rate of the DRAM module's interface width.

[0049] The above embodiment uses the DRAM module outputting data to the controller as an example. The above-mentioned method of setting the checksum is also used in the process of writing data to the DRAM module. The writing process is controlled by the controller, and the checksum is generated by the controller, which can also improve the utilization rate of the DRAM module's interface width.

[0050] In some embodiments, the first data is data received by the solid-state drive (SSD) from the host and cached in the DRAM module. The host transmits data to the SSD and sends an instruction to store the first data at a target address in the flash memory module. The first data is received through the SSD's interface. The controller generates a checksum for the first data, and the first data and the checksum are cached as a single data unit in the first storage area of ​​the DRAM module. The code length of the first data is greater than the interface width of the DRAM module.

[0051] In some embodiments, the first data is data cached from the flash memory module to the DRAM module during garbage collection. Due to the write-before-erase characteristic of NAND flash memory, invalid pages containing expired file data will be generated in the NAND flash memory after a large number of write update operations. When the number of writable free pages in the NAND flash memory falls below a threshold, the solid-state drive controller will perform a garbage collection operation, i.e., erase the flash memory block containing a large number of invalid pages. Before erasing the flash memory block, the data in the valid pages of the flash memory block needs to be migrated to the DRAM module, and then subsequently written to the erased flash memory block or other flash memory blocks.

[0052] In some embodiments, the total number of bits in the data unit consisting of the first data and its checksum is M times the interface width of the DRAM module, where M is a positive integer greater than or equal to 2.

[0053] In some embodiments, the total number of bits in a data unit consisting of the first data and its checksum is S times the Burst length, where S is a positive integer greater than or equal to 2.

[0054] In some embodiments, the DRAM module further includes a second storage area that stores second data and a checksum for the second data, wherein the code length of the first data and the code length of the second data are different. For example, for the first data in the first storage area, a set of checksum bits is set every X bits, and for the second data in the second storage area, a set of checksum bits is set every Y bits, where X and Y are different. X, for example, is greater than Y.

[0055] Data in the DRAM module typically falls into three categories: business data, system data required for controller operation (such as program space accessed by the controller's CPU core or data managed by the CPU), and mapping tables (including but not limited to global mapping tables and entries involved in FTL management). Business data includes data cached in the DRAM module during host read / write operations on the SSD, and data cached in the DRAM module during garbage collection operations. Business data is normally stored in the flash memory module, but cached in the DRAM module during SSD read / write operations and garbage collection operations. According to embodiments of this application, different types of data use different checksum setting methods. For example, business data is the first data in this application, with a set of checksum bits set for every X bits of the first data, where X is greater than the interface width of the DRAM module. System data and the mapping table are the second data, with a set of checksum bits set for every Y bits of the second data, where X is greater than Y. For example, the system data and the mapping table use... Figure 6 The checksum setting shown is such that the controller reads data and the corresponding checksum from the DRAM module each time, and the sum of the lengths of the data and the corresponding checksum is equal to the interface width of the DRAM module.

[0056] Figure 5 This is a schematic diagram of the partitioning of a DRAM module according to an embodiment of the present invention. The DRAM module is divided into a first storage area 11, a second storage area 12, and a third storage area 13. The first storage area 11 is used to store first data (i.e., business data). One of the second storage area 12 and the third storage area 13 is used to store system data, and the other is used to store a mapping table.

[0057] In some embodiments, the second storage area 12 and the third storage area 13 can be a single storage area, i.e., the system data and the mapping table are set with check codes at the same code length granularity.

[0058] like Figure 3 As shown, in the same I / O operation of the DRAM module, data comes from multiple DRAM cells. Therefore, as Figure 5 As shown, the first storage region 11 includes a portion of DRAM cell 1, a portion of DRAM cell 2, ..., a portion of DRAM cell n. The second storage region 12 and the third storage region 13 are similar and will not be described further.

[0059] According to embodiments of the present invention, the data code length originally cached in the DRAM module is increased, and a reasonable parity bit length is used (to meet DRAM reliability), thereby improving the bandwidth utilization when accessing the DRAM module. This effectively improves the bandwidth access efficiency of the entire solid-state drive's DRAM module, reduces system power consumption, and lowers the overall system cost.

[0060] This invention also provides a storage system. The storage system includes the solid-state drive described in the above embodiments. The storage system is deployed, for example, in a data center.

[0061] This invention also provides a data center, including the aforementioned storage system. This data center is used, for example, to provide cloud services. The data center also includes servers. A data center is a large-scale collaborative network of specific devices used to transmit, accelerate, display, compute, and store data information on network infrastructure. Examples of data centers include financial data centers, enterprise data centers, and internet cloud data centers.

[0062] The above-mentioned products can perform the methods provided in the embodiments of the present invention, and have the corresponding functional modules and beneficial effects of performing the methods. For technical details not described in detail in this embodiment, please refer to the methods provided in the embodiments of the present invention.

[0063] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solid-state drive, comprising: Flash memory module; Dynamic Random Access Memory (DRAM) module; as well as Controller; The DRAM module includes a first storage area that stores first data and a checksum of the first data. The first data is service data, and the code length of the first data is greater than the interface width of the DRAM module. The total number of bits of the data unit composed of the first data and the corresponding checksum is an integer multiple of the interface width of the DRAM module.

2. The solid-state drive according to claim 1, wherein, The first data is data received from the host and cached in the DRAM module.

3. The solid-state drive according to claim 1, wherein, The first data is data cached in the DRAM module from the flash memory module during the garbage collection operation.

4. The solid-state drive according to claim 1, wherein, The DRAM module includes multiple DRAM units, each DRAM unit includes multiple banks, and each DRAM unit stores a portion of the first data and a portion of the checksum of the first data.

5. The solid-state drive according to any one of claims 1-4, wherein, The DRAM module further includes a second storage area, which stores second data and a check code for the second data, wherein the code length of the first data and the code length of the second data are different.

6. The solid-state drive according to claim 5, wherein, The second data is the global mapping table and / or the system data of the controller.

7. A method for operating a solid-state drive (SSD), the SSD comprising a flash memory module, a dynamic random access memory (DRAM) module, and a controller, the method comprising: The controller reads first data and a checksum of the first data from the first storage area of ​​the DRAM module. The first data is service data, and the code length of the first data is greater than the interface width of the dynamic random access memory. The total number of bits of the data unit composed of the first data and the corresponding checksum is an integer multiple of the interface width of the DRAM module.

8. The operating method according to claim 7, wherein, The first data is data received from the host and cached in the DRAM module.

9. The operating method according to claim 7, wherein, The first data is data cached in the DRAM module from the flash memory module during the garbage collection operation.

10. The operating method according to claim 7, wherein, The DRAM module includes multiple DRAM units, each DRAM unit includes multiple banks, and each DRAM unit stores a portion of the first data and a portion of the checksum of the first data.

11. The operating method according to any one of claims 7-10, further comprising: The controller reads second data and the check code of the second data from the second storage area of ​​the DRAM module. The code length of the first data and the code length of the second data are different.

12. The operating method according to claim 11, wherein, The second data is the global mapping table and / or the system data of the controller.

13. A storage system, comprising: The solid-state drive according to any one of claims 1-6.

14. A data center, comprising: The storage system according to claim 13.

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